8da6aca2ec
Support Alder Lake N (fam 6 exmodel 11 model 14) as Haswell
2023-07-16 22:15:15 +02:00
f249ccb741
Fix spr sbgemm error
2023-05-19 10:48:18 +08:00
ac650225c1
Fix x86 detection error
2023-04-13 00:08:27 +08:00
280b6d57d1
Add more Intel Raptor Lake CPUIDs
2023-03-28 00:55:23 +02:00
1865b15240
Add fallbacks to RaptorLake entry
2022-11-09 10:31:30 +01:00
e27ad3a6cc
add raptor lake ids
2022-10-28 11:45:43 -04:00
2d0ad89b0d
Support Zhaoxin/Centaur kh40000 as ZEN
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Signed-off-by: JonasZhou <JonasZhou@zhaoxin.com>
2022-03-10 15:08:38 +08:00
f7e8f9ec57
Support AVX512-enabled AlderLake
2022-02-07 00:00:15 +01:00
9809931eb4
clean up unused variables and unreachable statements
2021-12-21 18:53:55 +01:00
faae86fba2
Add CPUIDs for Alder Lake and some other recent Intel cpus
2021-11-04 20:35:41 +01:00
ead476025d
auto-detect for Intel i7-11800H
2021-10-27 14:16:37 +08:00
3dc6052c7e
initial support for Sapphire Rapids platform
2021-10-12 01:30:40 -07:00
0fca36c8c3
Add cpu detection support for Zhaoxin processors
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Signed-off-by: JonasZhou <JonasZhou@zhaoxin.com>
2021-07-12 13:43:45 +08:00
4f4e286bf6
Fix copy-paste error in LIBCORE assignment for Tiger Lake
2021-07-10 18:20:40 +02:00
da623ae838
Add vendor string Shanghai as the successor to Centaur
2021-07-08 18:26:23 +02:00
0d8d261dd4
Recognize newer Zhaoxin/Centaur cpus as Nehalem
2021-07-08 12:20:19 +02:00
26e87ac517
Support Intel Ice Lake SP as Cooper Lake
2021-05-14 20:39:55 +02:00
ae53e3e233
Recognize Intel Tiger Lake as SkylakeX
2021-02-11 20:16:27 +01:00
0f7776af0b
Add Intel Rocket Lake
2020-12-14 22:30:36 +01:00
1f564d729b
fix avx2 detection
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reword commits to make it clearer
2020-10-31 10:00:48 -04:00
e740c4873d
Enable COOPERLAKE build target
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Enable new build target platform -- COOPERLAKE. This target platform
supports all the SKYLAKEX supported ISAs + avx512bf16. So all the
SKYLAKEX specific kernels/drivers and related code are now extended
to be also active on COOPERLAKE. Besides, new BF16 related kernels
are active under this target.
2020-08-13 06:18:00 +08:00
200f5c44cc
Add AMD Renoir models and preliminary support for ZEN3 as ZEN2
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also remap erroneous family 16 entry to BOBCAT and reclaim erroneous family 25 "Barcelona" for Zen3
2020-07-28 13:45:23 +00:00
83f4746825
Add support for Comet Lake H and S
2020-06-27 14:41:24 +02:00
2f9c10810c
Also set CPUTYPE in get_cpuname()
2020-06-25 15:53:56 -04:00
2a91452bdd
Add cpu detection support for comet lake U
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Comet Lake U CPUs have family: 6, model: 6, extended family: 0, and
extended model: 10 were not being correctly detected by GETARCH during
openblas builds and would show CORE=UNKNOWN and LIBCORE=unknown. This
commit adds the necessary information to cpuid_x86 to detect extended
family 10 model 6 and return the proper core information. It's
essentially just a skylake cpu, not skylake x, so I just took the used
the same return fields as skylake.
2020-06-25 11:32:09 -04:00
303bdb673b
Fix coretype detection for Intel extended models 6 and 7
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affecting Goldmont, Cannon Lake, Ice Lake autodetection
2020-02-10 19:17:32 +01:00
e9437eebd2
Restore Goldmont ID and improve QEMU support
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#2283 had inadvertently removed Goldmont+, and cpuid was reporting a mix of Core2 and Pentium2 for some QEMU configurations
2019-10-24 18:45:27 +02:00
e8a2aed2b9
Support QEMU cpu calling itself 64bit AMD Athlon as well
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Some QEMU instances pretend to be "AuthenticAMD" with the same family 6/model 6 even when running on an Intel host
(could be related to qemu or libvirt version and/or kvm availability). Also fix the define to depend on __x86_64__ set by the
compiler, the defines using __64BIT__ will only work for getarch_2nd.
2019-10-09 18:24:13 +02:00
f262031685
Support QEMU virtual cpu as CORE2
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qemu itself claims it is a 64bit P6, which does not exist in the wild.
2019-10-08 22:30:02 +02:00
6d8595351c
Add Intel Goldmont Plus CPUID
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fixes #2227
2019-08-19 14:19:21 +02:00
b1393c7a97
Add Intel Denverton
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for #2048
2019-03-12 16:03:56 +01:00
83b5c6b92d
Fix compilation with NO_AVX=1 set
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fixes #1974
2019-01-20 12:18:53 +01:00
29dc72889f
Add support for Hygon Dhyana
2019-01-16 14:25:19 +08:00
00401489c2
Fix missing braces in support_avx()
2019-01-14 22:38:32 +01:00
68eb3146ce
Add xcr0 (os support) check
2019-01-05 18:07:14 +01:00
0afaae4b23
Query AVX2 and AVX512VL capability in x86 cpu detection
2019-01-05 16:58:56 +01:00
211120c508
Fix typo in UNKNOWN core name
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Should be of no consequence, right?
2018-12-27 23:09:21 +01:00
64ca44873b
Fix detection of Ryzen2 (missing CORE_ZEN)
2018-10-28 18:36:55 +01:00
3f73e8b8cf
Add cpuid for AMD Ryzen 2
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for #1664
2018-07-03 21:01:35 +02:00
2d8cc7193a
Support upcoming Intel Cannon Lake CPUs as Skylake X ( #1621 )
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* Support upcoming Cannon Lake as Skylake X
2018-06-17 23:38:14 +02:00
dc9fe05ab5
Update cpuid_x86.c
2018-06-04 17:10:19 +02:00
5a92b311e0
Separate Skylake X from Skylake
2018-06-03 23:29:07 +02:00
99c7bba8e4
Initial support for SkylakeX / AVX512
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This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server)
target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set,
which brings 2 basic things:
1) 512 bit wide SIMD (2x width of AVX2)
2) 32 SIMD registers (2x the number on AVX2)
This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel
to AVX512VL; more will follow later but this patch aims to get the infrastructure
in place for this "later".
Full performance tuning has not been done yet; with more registers and wider SIMD
it's in theory possible to retune the kernels but even without that there's an
interesting enough performance increase (30-40% range) with just this change.
2018-06-03 07:58:52 +00:00
aece65ea29
Fix coretype detection for Bay Trail Atom
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My earlier PR #982 appears to have been incomplete in this regard - fixes #1285
2017-08-27 13:06:54 +02:00
00774b1105
Add dummy implementation of cpuid_count for the CPUIDEMU case
2017-07-12 21:56:23 +02:00
6497aae57c
Use cpuid 4 with subleafs to query L1 cache size on Intel processors
2017-07-12 20:43:09 +02:00
9c884986ad
Add an extra familiy/model combination used by AMD Steamrolller (Godavari).
2017-04-19 19:15:47 +02:00
b4071d0d16
Autodetect AMD A8-6410 as BARCELONA
2017-04-03 17:07:27 +10:00
c9ff735da6
Add ZEN support (tested for auto-detected static backend)
2017-03-19 15:32:50 +01:00
688267edf3
Fix core detection for Kaby Lake without AVX (G4560)
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Should fix #1109 )
2017-03-02 17:36:16 +01:00
Martin Kroeker
Honglin Zhu
linouxis9
Guillaume Horel
JonasZhou
Neutron3529
Wangyang Guo
Chen, Guobing
Matthew Treinish
caiyu
TiborGY
Arjan van de Ven
Gian-Carlo Pascutto
Johannes Buchner
Denis Steckelmacher