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4 Commits

Author SHA1 Message Date
Xianyi Zhang 77b7020d69 changed prefetch order. 2011-01-29 03:03:34 +08:00
Xianyi Zhang e003b811ab load x & y contiguously in axpy. 2011-01-28 11:18:50 +08:00
Xianyi Zhang ebe2da8474 Modified aligned size. Added additional prefetch instruction because of cache line is 32 bytes in Loongson 3A. 2011-01-27 23:07:06 +08:00
Xianyi Zhang c0b5992fab added axpy kernel with prefetch for Loongson3A. To-Do: tuning prefetch distance & instruction order. 2011-01-26 22:34:33 +08:00