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23 Commits

Author SHA1 Message Date
Arjan van de Ven 99c7bba8e4 Initial support for SkylakeX / AVX512 
This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server)
target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set,
which brings 2 basic things:
1) 512 bit wide SIMD (2x width of AVX2)
2) 32 SIMD registers (2x the number on AVX2)

This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel
to AVX512VL; more will follow later but this patch aims to get the infrastructure
in place for this "later".

Full performance tuning has not been done yet; with more registers and wider SIMD
it's in theory possible to retune the kernels but even without that there's an
interesting enough performance increase (30-40% range) with just this change.
 2018-06-03 07:58:52 +00:00
Martin Kroeker 73cc321190
Add MIPS 1004K target 2018-05-02 20:27:56 +02:00
Shivraj Patil e3d844b062 Added mips I6500 core 
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
 2017-09-22 11:57:43 +05:30
Sébastien Villemot 7543e578a4 Add support for TARGET=ZARCH_GENERIC and TARGET=Z13 2017-09-19 12:16:42 +02:00
Denis Steckelmacher c9ff735da6 Add ZEN support (tested for auto-detected static backend) 2017-03-19 15:32:50 +01:00
Ashwin Sekhar T K 4b55fae337 ARM64: Add Cavium THUNDERX2T99 Target 2017-01-11 11:18:40 +05:30
Andrew Pinski fb200c7245 ARM64: Add Cavium THUNDERX Target 2017-01-10 15:01:37 +05:30
Ashwin Sekhar T K 4713e7c47f ARM64: Add the VULCAN Target 2017-01-10 15:01:17 +05:30
Shivraj Patil beb1d076a4 Added MSA optimization for GEMV_N, GEMV_T, ASUM, DOT functions 
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
 2016-07-15 18:38:25 +05:30
Shivraj Patil 2c3dfe2bf3 MIPS P5600(32 bit) and I6400(64 bit) cores support added. 
Seperated mips and mips64 files.
Configurations support for mips 32 bit.

Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
 2016-04-22 14:03:18 +05:30
Ashwin Sekhar T K f2f8a0fe8b Adding arm64 target CORTEXA57 
Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
 2015-11-09 14:15:50 +05:30
Fábio Perez b8d64a856a Add POWER7/POWER8 as targets 2015-08-05 11:02:39 -03:00
Zhang Xianyi 51ff17d46e Add AMD Excavator target. 2015-05-13 16:16:30 -05:00
Zhang Xianyi c674fa32be Add ARM targets. 2015-03-24 12:17:04 -05:00
Werner Saar 4319769b79 added target processor STEAMROLLER 2014-12-28 20:16:46 +08:00
Zhang Xianyi 70d1ba09b2 Update the doc for target list. 2014-09-17 14:29:21 +08:00
Eliot Eshelman 9912dbbcf9 Add HASWELL to TargetList.txt 
The Intel "Haswell" architecture is missing from the list of build targets.
 2014-09-16 18:26:45 -04:00
Explorer09 309f90e563 TargetList.txt: minor re-ordering 2013-03-17 23:03:05 +08:00
Zhang Xianyi bfaaa975e6 Added BULLDOZER target. So far it uses barcelona kernels. 2012-12-07 00:53:31 +08:00
Zhang Xianyi d3b67d0bd8 Refs #113. Fixed the typo BOBCATE -> BOBCAT 2012-05-31 22:40:15 +08:00
Zhang Xianyi d6cab3f37e Refs #113. Support AMD Bobcate using Barcelona kernel codes. Replace 3DNow! with MMX. 2012-05-31 18:17:45 +08:00
Xianyi Zhang 19a48b82cf Init Sandybridge codes based on Nehalem. 2012-03-30 20:01:03 +08:00
Xianyi Zhang b8d93812f0 Added docs for make TARGET=your_cpu_target. 2011-04-22 22:07:46 +08:00