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7452 Commits

Author SHA1 Message Date
Xianyi Zhang b206fc7075 Fixed #28. Convert the result to double precision in the end of dsdot kernel. 2011-05-13 02:34:30 +08:00
Xianyi Zhang 1d60510959 Added the unit testcase for dsdot. 2011-05-13 02:19:55 +08:00
Xianyi Zhang 03272a606d Added the unit test for drotmg. 2011-05-13 01:21:39 +08:00
Xianyi Zhang 0dc9eca36f Merge branch 'hotfix-readme_about_branches' into develop 2011-05-12 19:06:31 +08:00
Xianyi Zhang 8cc628a953 Merge branch 'hotfix-readme_about_branches' 2011-05-12 19:06:02 +08:00
Xianyi Zhang bbc517292a Added the spec of git branches about this project. 2011-05-12 19:05:20 +08:00
traz 29dce62b8f Finish dtrsm_kernel_Rx.S on Loongson3A. 2011-05-11 10:44:23 +00:00
Xianyi Zhang fa8e4fd879 Fixed #26 the wrong result of rotmg. Used fabs() instead of abs(). 2011-05-11 01:12:32 +08:00
traz 432c309f63 Finish dtrsm_kernel_Lx.S on Loongson3A. 2011-05-10 12:48:43 +00:00
traz d2f351d819 Modify dtrsm compiler options 2011-05-09 17:31:58 +00:00
traz 5a991b7149 Fixed #24 drmm error on Loongson3A 2011-05-09 17:28:20 +00:00
Xianyi Zhang 417b8ec792 Added openblas_set_num_threads for Fortran. 2011-05-06 17:03:35 +08:00
Xianyi Zhang 7dcf4eeee7 Fixed #23. Fixed a bug of f_check script about generating link flags. 2011-05-04 13:03:10 +08:00
Xianyi Zhang 1acf5ace29 Fixed a bug when detecting Intel CPU. 2011-05-03 17:19:36 +08:00
traits fcf9b82f14 Fixed a build bug with NO_LAPACK=1 and SANNITY_CHECK=1. 2011-05-03 14:42:11 +08:00
Xianyi Zhang 2aab238c61 Fixed #16. Print the user-friendly message when detecting CPU failed. 2011-04-22 22:14:06 +08:00
Xianyi Zhang b8d93812f0 Added docs for make TARGET=your_cpu_target. 2011-04-22 22:07:46 +08:00
Xianyi Zhang ff6ae89d3e Fixed #19. Provided an error msg when the arch is not supported. 2011-04-22 20:21:42 +08:00
Xianyi Zhang 0a45e5495f Fixed #21. Added extern C to support C++. Thank Tasio for the patch. 2011-04-20 13:41:38 +08:00
traz 9320933520 Completely dtrmm function. 2011-04-17 20:26:49 +00:00
traz 921caefa56 Increased handling trmm part, no edge handling. Test size(M and N) must be a multiple of 4 . 2011-04-15 21:56:25 +00:00
traz ecd4c1f3d9 Modify prefetching C. 2011-04-11 22:46:36 +00:00
traz ab9e4ce351 Adjust kc size from 112 to 116 . 2011-04-11 22:17:57 +00:00
Xianyi Zhang 921e040b15 Changed default page size to 16KB on Loongson 3A. 2011-04-11 21:46:48 +00:00
Xianyi Zhang 00ef0cd434 Supported goto_set_num_threads & openblas_set_num_threads functions when USE_OPENMP=1. 2011-04-07 14:52:35 +08:00
Xianyi Zhang 989c6f8b06 Fixed #14 the SEGFAULT bug on 64 cores. On SMP server, the number of CPUs or cores should be less than or equal to 64. 2011-04-07 14:48:10 +08:00
Xianyi Zhang 552f31dbbd Fixed #13. Fixed blasint undefined bug in <cblas.h> file. 2011-04-07 14:48:10 +08:00
Xianyi Zhang 5452ba3850 Updated the developing version to v0.1 alpha2. 2011-04-07 14:48:10 +08:00
Xianyi Zhang 54745902b8 Init Changelog file for next release version(v0.1alpha2). 2011-04-07 14:48:10 +08:00
traz 1aa9a298e1 Change BLOCK SIZE of LOONGSON3A TARGET. 2011-04-06 10:39:31 +00:00
traz 782205a693 Add dgemm compiler Options in KERNEL.LOONGSON3A. 2011-04-06 10:38:34 +00:00
traz ac494c0d04 New kernel in LOONGSON3A. 2011-04-06 10:36:44 +00:00
Xianyi Zhang 85f99d4769 Fixed #14 the SEGFAULT bug on 64 cores. On SMP server, the number of CPUs or cores should be less than or equal to 64. 2011-03-28 10:58:39 +08:00
Xianyi Zhang 5e7f29b19e Fixed #13. Fixed blasint undefined bug in <cblas.h> file. 2011-03-25 01:17:27 +08:00
Xianyi Zhang 141091f528 Merge branch 'master' of github.com:xianyi/OpenBLAS into x86 2011-03-22 14:16:18 +08:00
Xianyi Zhang e4bb6f2482 Fixed the detecting bug on Intel Core i5. Thank ggl329 for the patch. 2011-03-22 14:09:47 +08:00
Xianyi Zhang 0edcdd470e Updated the developing version to v0.1 alpha2. 2011-03-20 23:35:31 +08:00
Xianyi Zhang d672491122 Init Changelog file for next release version(v0.1alpha2). 2011-03-20 23:30:09 +08:00
Xianyi Zhang 972062903c OpenBLAS 0.1 alpha version 1. 2011-03-20 22:44:57 +08:00
Xianyi Zhang d9aa359e69 Merge remote branch 'origin/loongson3a' into x86 2011-03-20 21:57:58 +08:00
Xianyi Zhang 04769bdf54 Merge remote branch 'origin/loongson3a' into x86 2011-03-20 21:57:09 +08:00
Xianyi Zhang 6f058487ab Detect Intel Core Clarkdale & Arrandale 2011-03-20 21:56:40 +08:00
Xianyi Zhang f405b5bcc5 Fixed the bug about Loongson3A gsLQC1 & gsSQC1 instructions in daxpy kernel. Now daxpy is correct. 2011-03-18 23:05:56 +00:00
Xianyi Zhang 2b8643e0de Merge branch 'loongson3a' of github.com:xianyi/OpenBLAS into loongson3a 2011-03-18 01:20:15 +00:00
Xianyi Zhang c84f8be453 Supported detecting new kernel(2.6.36) & new Loongson3A03 CPU. 2011-03-18 01:10:58 +00:00
Wang Qian d5cffd506a Modified the default kernel makefile in MIPS64 arch. 2011-03-07 11:23:12 +00:00
Xianyi Zhang 5838f12995 Support unalign address in daxpy on loongson3a simd.. 2011-03-05 10:17:10 +08:00
Xianyi Zhang 5444a3f8f7 Unroll to 16 in daxpy on loongson3a. 2011-03-04 17:50:17 +08:00
Xianyi Zhang 88cbfcc5b5 Merge commit 'origin/x86' into loongson3a 2011-03-04 14:11:52 +00:00
Xianyi Zhang ce78abe37e Merge branch 'x86' of github.com:xianyi/OpenBLAS into x86 2011-03-04 11:53:04 +08:00