Martin Kroeker
|
cdbe0f0235
|
Add MIPS implementation of ?sum
as trivial copy of ?asum with the fabs calls removed
|
2019-03-30 22:20:14 +01:00 |
|
Martin Kroeker
|
941ad280a8
|
Fix typo in MIPS P5600 complex ASUM code selection
|
2018-04-25 22:50:10 +02:00 |
Shivraj Patil
|
a4d97d980f
|
Added rot functions.
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
|
2017-01-17 12:15:07 +05:30 |
kaustubh
|
1480f3df71
|
Add msa optimization for AXPY, COPY, SCALE, SWAP
Signed-off-by: kaustubh <kaustubh.raste@imgtec.com>
|
2017-01-09 18:27:23 +05:30 |
|
kaustubh
|
88afb3bc94
|
Add msa optimization for AXPY, COPY, SCALE, SWAP
Signed-off-by: kaustubh <kaustubh.raste@imgtec.com>
|
2017-01-09 18:22:09 +05:30 |
|
Shivraj Patil
|
9687437928
|
MIPS n32 ABI and build time mips simd support check
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
|
2016-08-10 17:44:22 +05:30 |
|
Shivraj Patil
|
d1c6469283
|
MIPS n32 ABI support, MSA support detection and rename ARCH, ARCHFLAGS
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
|
2016-08-08 11:58:01 +05:30 |
|
Shivraj Patil
|
beb1d076a4
|
Added MSA optimization for GEMV_N, GEMV_T, ASUM, DOT functions
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
|
2016-07-15 18:38:25 +05:30 |
|
Shivraj Patil
|
57df7956ee
|
Added CGEMM, ZGEMM, STRMM, DTRMM, CTRMM, ZTRMM. Updated macros in SGEMM, DGEMM, STRMM.
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
|
2016-06-28 17:51:10 +05:30 |
|
Kaustubh Raste
|
ad9f317870
|
STRSM optimization for MIPS P5600 and I6400 using MSA
Signed-off-by: Kaustubh Raste <kaustubh.raste@imgtec.com>
|
2016-05-20 10:59:03 +05:30 |
|
Shivraj Patil
|
c4ba40e308
|
SGEMM optimization for MIPS P5600 and I6400 using MSA. Unrolled k loop in DGEMM kernel function
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
|
2016-05-19 11:04:42 +05:30 |
|
Kaustubh Raste
|
edb5980c13
|
DTRSM optimization for MIPS P5600 and I6400 using MSA
Signed-off-by: Kaustubh Raste <kaustubh.raste@imgtec.com>
|
2016-05-09 15:15:26 +05:30 |
|
Shivraj Patil
|
b7b3d8ec8e
|
DGEMM optimization for MIPS P5600 and I6400 using MSA
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
|
2016-05-03 14:42:26 +05:30 |
|
Shivraj Patil
|
2c3dfe2bf3
|
MIPS P5600(32 bit) and I6400(64 bit) cores support added.
Seperated mips and mips64 files.
Configurations support for mips 32 bit.
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
|
2016-04-22 14:03:18 +05:30 |