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37 Commits

Author SHA1 Message Date
Martin Kroeker
cdbe0f0235 Add MIPS implementation of ?sum 
as trivial copy of ?asum with the fabs calls removed
 2019-03-30 22:20:14 +01:00
Martin Kroeker
86a824c97f Fix wrong comparison that made IMIN identical to IMAX 
as reported by aarnez in #1990
 2019-01-31 15:27:21 +01:00
Martin Kroeker
8dd3515fa2 Merge pull request #1565 from martin-frbg/mipstypo 
Remove extraneous brace from previous commit of mips dsdot fix
 2018-05-17 20:22:58 +02:00
Martin Kroeker
95f7f0229c Remove extraneous brace from previous commit 2018-05-17 18:43:59 +02:00
Martin Kroeker
893b535540 Use correct data type for initializers of v2f64, v4f32 
Fixes #1561
 2018-05-15 14:42:12 +02:00
Martin Kroeker
9d5098dbc9 Add MIPS 1004K target (Mediatek MT7621 SOC) 2018-05-02 20:20:44 +02:00
Martin Kroeker
954f1832de Merge pull request #1540 from martin-frbg/mips32-zasum 
Fix typo in MIPS P5600 complex ASUM code selection
 2018-04-25 23:23:00 +02:00
Martin Kroeker
941ad280a8 Fix typo in MIPS P5600 complex ASUM code selection 2018-04-25 22:50:10 +02:00
Martin Kroeker
0fe434598b Fix precision of mips dsdot 2018-04-10 23:30:59 +02:00
Andrew
13e137fbc9 Initialize uninitialized variables (cppcheck) 2018-01-12 22:33:41 +01:00
Shivraj Patil
a4d97d980f Added rot functions. 
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
 2017-01-17 12:15:07 +05:30
kaustubh
1480f3df71 Add msa optimization for AXPY, COPY, SCALE, SWAP 
Signed-off-by: kaustubh <kaustubh.raste@imgtec.com>
 2017-01-09 18:27:23 +05:30
kaustubh
88afb3bc94 Add msa optimization for AXPY, COPY, SCALE, SWAP 
Signed-off-by: kaustubh <kaustubh.raste@imgtec.com>
 2017-01-09 18:22:09 +05:30
Shivraj Patil
a9bf8a781a Added prefetch to CGEMV and ZGEMV. 
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
 2016-12-27 11:33:51 +05:30
kaustubh
5f93aa5f87 Updated data prefetch in TRSM, ASUM, DOT functions 
Signed-off-by: kaustubh <kaustubh.raste@imgtec.com>
 2016-12-14 14:05:11 +05:30
kaustubh
9db451acd0 Updated data prefetch in TRSM, ASUM, DOT functions 
Signed-off-by: kaustubh <kaustubh.raste@imgtec.com>
 2016-12-13 14:02:14 +05:30
kaustubh
3eaff85191 Updated data prefetch in TRSM, ASUM, DOT functions 
Signed-off-by: kaustubh <kaustubh.raste@imgtec.com>
 2016-12-13 11:41:17 +05:30
kaustubh
00abce3b93 Add data prefetch in DOT and ASUM functions 
Signed-off-by: kaustubh <kaustubh.raste@imgtec.com>
 2016-11-22 11:21:03 +05:30
kaustubh
f3419e634c SGEMM, DGEMM, CGEMM, ZGEMM functions data prefetch 
Signed-off-by: kaustubh <kaustubh.raste@imgtec.com>
 2016-10-17 18:29:38 +05:30
kaustubh
90e2321ac3 STRSM, DTRSM functions data prefetch 
Signed-off-by: kaustubh <kaustubh.raste@imgtec.com>
 2016-10-14 16:41:28 +05:30
Martin Kroeker
91610f3835 Update zdot_msa.c 2016-10-05 18:59:09 +02:00
Martin Kroeker
6e22ecf102 Update zdot.c 2016-10-05 18:58:03 +02:00
Martin Kroeker
3178e4fea0 Remove explicit include of complex.h 2016-09-29 23:41:43 +02:00
Martin Kroeker
95c245ddb0 Remove explicit include of complex.h 2016-09-29 23:40:36 +02:00
Shivraj Patil
54747fe24a DGEMM function split and data prefech 
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
 2016-09-22 17:25:46 +05:30
Shivraj Patil
9687437928 MIPS n32 ABI and build time mips simd support check 
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
 2016-08-10 17:44:22 +05:30
Shivraj Patil
d1c6469283 MIPS n32 ABI support, MSA support detection and rename ARCH, ARCHFLAGS 
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
 2016-08-08 11:58:01 +05:30
Shivraj Patil
beb1d076a4 Added MSA optimization for GEMV_N, GEMV_T, ASUM, DOT functions 
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
 2016-07-15 18:38:25 +05:30
Shivraj Patil
57df7956ee Added CGEMM, ZGEMM, STRMM, DTRMM, CTRMM, ZTRMM. Updated macros in SGEMM, DGEMM, STRMM. 
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
 2016-06-28 17:51:10 +05:30
Kaustubh Raste
011431b9d7 STRSM optimized for MSA 
Signed-off-by: Kaustubh Raste <kaustubh.raste@imgtec.com>
 2016-05-31 10:17:23 +05:30
Kaustubh Raste
c8a7860eb3 STRSM optimized 
Signed-off-by: Kaustubh Raste <kaustubh.raste@imgtec.com>
 2016-05-30 21:17:00 +05:30
Kaustubh Raste
ad9f317870 STRSM optimization for MIPS P5600 and I6400 using MSA 
Signed-off-by: Kaustubh Raste <kaustubh.raste@imgtec.com>
 2016-05-20 10:59:03 +05:30
Shivraj Patil
c4ba40e308 SGEMM optimization for MIPS P5600 and I6400 using MSA. Unrolled k loop in DGEMM kernel function 
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
 2016-05-19 11:04:42 +05:30
Kaustubh Raste
d7cbc7ac13 DTRSM bug fix for MIPS P5600 and I6400 
Signed-off-by: Kaustubh Raste <kaustubh.raste@imgtec.com>
 2016-05-17 15:48:02 +05:30
Kaustubh Raste
edb5980c13 DTRSM optimization for MIPS P5600 and I6400 using MSA 
Signed-off-by: Kaustubh Raste <kaustubh.raste@imgtec.com>
 2016-05-09 15:15:26 +05:30
Shivraj Patil
b7b3d8ec8e DGEMM optimization for MIPS P5600 and I6400 using MSA 
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
 2016-05-03 14:42:26 +05:30
Shivraj Patil
2c3dfe2bf3 MIPS P5600(32 bit) and I6400(64 bit) cores support added. 
Seperated mips and mips64 files.
Configurations support for mips 32 bit.

Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
 2016-04-22 14:03:18 +05:30