098672b51b
add trsm_kernel_LT_sve
2022-01-09 20:11:47 +01:00
be7e55880c
sve trsm_kernel_LN
2022-01-09 19:40:04 +01:00
f33543d029
combine zchemm into single file
2022-01-05 14:42:37 +01:00
39ab219704
sve copy functions for cgemm chemm zsymm
2022-01-05 09:12:22 +01:00
18102ae8c3
add cgemm ctrmm sve kernels
2022-01-05 09:09:18 +01:00
87537b8c55
modify sve zgemmcopy kernels
2022-01-05 09:07:28 +01:00
d30157d891
update configuration of kernels for A64FX and ARMV8SVE
2022-01-05 09:00:54 +01:00
2e2c02b762
fix sve ztrmm kernel
2022-01-04 14:42:07 +01:00
68c414d3a6
ztrmm sve copy functions
2022-01-04 14:40:59 +01:00
ce329ab686
add sve zhemm copy routines
2022-01-03 15:56:05 +01:00
0140373802
add sve ztrmm
2022-01-02 19:15:33 +01:00
f7b6912868
ztrmm sve copy kernels
2021-12-30 21:00:16 +01:00
40b14e4957
fix zgemm kernel
2021-12-29 11:42:04 +01:00
6ec4aab875
zgemm sve copy routines
2021-12-26 17:05:46 +01:00
878064f394
sve zgemm kernel
2021-12-26 08:44:05 +01:00
683a7548bf
added macros for sve zgemm kernels
2021-12-25 11:46:41 +01:00
e3c9947c0f
prepare kernel for sve zgemm
2021-12-21 11:19:27 +01:00
b610d2de37
optimize cgemm on ARM cortex A53 & cortex A55
2021-12-12 17:22:52 +08:00
a8f62a347b
fix UNROLL_MN and add to targets for SVE
2021-12-11 16:37:23 +01:00
a1fea1fe2a
sgemm v2x8 SVE kernel
2021-12-05 18:47:29 +01:00
abe1ce3434
strmm sve v1x8 kernel
2021-12-05 14:03:08 +01:00
0de36f7b5c
trmm sve copy fucntions for single precision
2021-11-29 21:25:05 +01:00
86ae89bf33
add sgemm kernel and copy functions for sgemm and ssymm
2021-11-28 18:12:47 +01:00
454edd741c
Merge pull request #3425 from binebrank/arm_sve_dgemm
...
Add dgemm kernel for arm64 SVE
2021-11-26 16:14:55 +01:00
5c1cd5e0c2
MOD: add comments to a53 zgemm kernel
2021-11-25 22:48:48 +08:00
9f59b19fcd
MOD: optimize zgemm on cortex-A53/cortex-A55
2021-11-24 21:51:45 +08:00
531a28b6a0
removed unused code (compiler warnings)
2021-11-22 10:12:34 +01:00
9b9cb90bb1
modify Makefile for SVE copy
2021-11-22 09:54:20 +01:00
b58d4f31ab
some clean-up & commentary
2021-11-21 14:56:27 +01:00
e6ed4be02e
symm SVE copy rutines
2021-11-20 16:35:29 +01:00
302f22693a
MOD: optimize normal DGEMM on ARMV8 cortex-A53 & cortex-A55
2021-11-18 21:14:43 +08:00
3c7eed0e53
add remaining trmm copy rutines for SVE
2021-11-14 16:00:10 +01:00
7d996b1c36
dtrmm_utcopy sve function
2021-11-13 18:48:53 +01:00
ab7917910d
add v2x8 kernel + fix sve dtrmm
2021-11-07 20:37:51 +01:00
7093372e32
add ARMV8SVE target
2021-11-01 22:53:21 +01:00
a8fbdbac34
fix sve dgemm kernel + sve dtrmm
2021-10-31 10:24:25 +01:00
746b4f0f17
added SVE ncopy and tcopy
2021-10-30 12:11:44 +02:00
1a10d3e09d
add sve dgemm prototype
2021-10-27 16:37:18 +02:00
22bf5c27ba
Add basic support for the Fujitsu A64FX ( #3415 )
...
* Add initial support for Fujitsu A64FX as generic ARMV8
2021-10-18 15:00:19 +02:00
8c20ca345a
Use Neoverse's current mix of ThunderX2 kernels for Vortex as well
2021-10-06 11:06:43 +02:00
90cc944625
Move alphaI to x22 to leave x18 unused (reserved on OSX)
2021-09-17 09:53:18 +02:00
590fbff06e
move alpha to x19/x20 to leave x18 unused for OSX
2021-09-17 09:42:17 +02:00
380940271b
Move temp to x21 to leave x18 unused (reserved on OSX)
2021-09-17 09:28:19 +02:00
7d75177446
Move temp to x21 to leave x18 unused (reserved on OSX)
2021-09-17 09:24:11 +02:00
0a4ac4b585
Use x21 for I to leave x18 unused (reserved on OSX)
2021-09-17 09:19:51 +02:00
7d4a221579
Remove unused TEMP2 and reshuffle to leave x18 unused (reserved on OSX)
2021-09-17 09:18:25 +02:00
39ef0880ae
copy conf
2021-06-19 21:49:58 +02:00
9d292d37b2
arm64: add the missing d9 register to the clobber list
...
Refs. numpy/numpy#18422
Signed-off-by: Gilles Gouaillardet <gilles@rist.or.jp>
2021-06-14 17:01:28 +09:00
d2bda3b56a
Remove Unnecessary/Erroneous Reads In sgemm_tcopy_16.S COPY1x8 Macro
...
There appears to have been some code leak when copying from the COPY2x8
macro above where we're reading 8 bytes into d4-d7 directly after
reading 4 bytes into s4-s7. These 32 bytes in d4-7 are unused and can
possibly overrun the boundary of allocated memory -- Valgrind detected
this which is what dragged my attention to it for a 128,1 copy.
Additionally, there is no need to update the addresses stored in A0-A7
as the only possible paths after running this macro will overwrite A0-7
if looping to the next 8 rows, or overwrite A0-3 if moving to 4 rows --
in which case A4-7 are unused.
2021-03-31 15:44:25 -04:00
b716c0ef01
Add workaround for NVIDIA HPC
2021-01-12 16:51:35 +01:00
Bine Brank
Jia-Chen
Martin Kroeker
User User-User
Gilles Gouaillardet
CodesWithWolves