4 Commits

Author	SHA1	Message	Date
sh-zheng	18d7afe69d	Add rvv support for zsymv and active rvv support for zhemv	2023-05-20 01:19:44 +08:00
Heller Zheng	63cf4d0166	add riscv level3 C,Z kernel functions.	2023-02-01 19:13:44 -08:00
Heller Zheng	5d0d1c5551	Remove redundant files	2022-11-15 18:22:21 -08:00
Heller Zheng	bef47917bd	Initial version for riscv sifive x280	2022-11-15 00:06:25 -08:00