Commit Graph

11 Commits

Author SHA1 Message Date
Martin Kroeker 2a203eedd3
Make HAVE_MSA describe cpu capability, NO_MSA software/env 2023-01-02 22:23:17 +01:00
Jiaxun Yang a50b29c540 Provide a fallback MIPS64_GENERIC target
It is really dangerous to fallback to Loongson core on other
MIPS64 processors.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2022-08-12 13:13:28 +01:00
yuanhecai 2db0b2e445 Fixed MSA enabled optimization on Loongson-3A4000 2021-12-23 20:29:42 +08:00
Martin Kroeker f3b51ec608
move brace inside the ifdef block 2021-12-16 09:37:58 +01:00
Martin Kroeker d6194d6a0c
get MSA capability from feature flags 2021-11-13 23:25:34 +01:00
gxw 4b548857d6 Add msa support for loongson
1. Using core loongson3r3 and loongson3r4 for loongson
2. Add DYNAMIC_ARCH for loongson

Change-Id: I1c6b54dbeca3a0cc31d1222af36a7e9bd6ab54c1
2020-12-09 10:28:46 +08:00
Martin Kroeker 0b2bb5696a
Change ifdef linux to __linux for C11 compatibility 2020-09-30 22:47:25 +02:00
TiborGY 7cbc2c37d6
Update cpuid_mips64.c 2018-12-28 14:36:39 +01:00
Shivraj Patil e3d844b062 Added mips I6500 core
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2017-09-22 11:57:43 +05:30
Shivraj Patil beb1d076a4 Added MSA optimization for GEMV_N, GEMV_T, ASUM, DOT functions
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-07-15 18:38:25 +05:30
Shivraj Patil 2c3dfe2bf3 MIPS P5600(32 bit) and I6400(64 bit) cores support added.
Seperated mips and mips64 files.
Configurations support for mips 32 bit.

Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 14:03:18 +05:30