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Merge pull request #1178 from jcowgill/mips-fixes 

MIPS threading fixes
This commit is contained in:
Martin Kroeker 2017-05-06 17:20:10 +02:00 committed by GitHub
parent 6464d1723a de7875ca5d
commit fd4e68128e
2 changed files with 4 additions and 31 deletions
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9
common_mips.h
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@ -33,8 +33,8 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifndef COMMON_MIPS
#define COMMON_MIPS
#define MB
#define WMB
#define MB __sync_synchronize()
#define WMB __sync_synchronize()
#define INLINE inline
@ -42,11 +42,6 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifndef ASSEMBLER
static void INLINE blas_lock(volatile unsigned long *address){
}
#define BLAS_LOCK_DEFINED
static inline unsigned int rpcc(void){
unsigned long ret;

26
common_mips64.h
View File

@ -71,35 +71,13 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifndef COMMON_MIPS64
#define COMMON_MIPS64
#define MB
#define WMB
#define MB __sync_synchronize()
#define WMB __sync_synchronize()
#define INLINE inline
#ifndef ASSEMBLER
static void INLINE blas_lock(volatile unsigned long *address){
long int ret, val = 1;
do {
while (*address) {YIELDING;};
__asm__ __volatile__(
"1: ll %0, %3\n"
" ori %2, %0, 1\n"
" sc %2, %1\n"
" beqz %2, 1b\n"
" andi %2, %0, 1\n"
" sync\n"
: "=&r" (val), "=m" (address), "=&r" (ret)
: "m" (address)
: "memory");
} while (ret);
}
#define BLAS_LOCK_DEFINED
static inline unsigned int rpcc(void){
unsigned long ret;