Add ARMV8SVE to AArch64 Dynamic Dispatch
In order to enable support for future cores which have similar tunings (in this case I'm doing this for the Arm(R) Neoverse(TM) V2 core), this generically detects SVE support and enables it. This should better manage the size and complexity of dynamic dispatch rather than just copy pasting the same parameters. To make `ARMV8SVE` more representive of the common 128-bit SVE case, I've split it and similar parameters from A64FX which has the wider 512-bit SVE.
This commit is contained in:
Chris Sidebottom
parent
7976deff80
commit
f971ef55f2
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@ -668,6 +668,7 @@ DYNAMIC_CORE += NEOVERSEN1
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ifneq ($(NO_SVE), 1)
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DYNAMIC_CORE += NEOVERSEV1
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DYNAMIC_CORE += NEOVERSEN2
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DYNAMIC_CORE += ARMV8SVE
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endif
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DYNAMIC_CORE += CORTEXA55
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DYNAMIC_CORE += FALKOR
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@ -46,7 +46,7 @@ if (DYNAMIC_ARCH)
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if (ARM64)
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set(DYNAMIC_CORE ARMV8 CORTEXA53 CORTEXA55 CORTEXA57 CORTEXA72 CORTEXA73 FALKOR THUNDERX THUNDERX2T99 TSV110 EMAG8180 NEOVERSEN1 THUNDERX3T110)
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if (${CMAKE_C_COMPILER_VERSION} VERSION_GREATER 9.99)
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set(DYNAMIC_CORE ${DYNAMIC_CORE} NEOVERSEV1 NEOVERSEN2)
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set(DYNAMIC_CORE ${DYNAMIC_CORE} NEOVERSEV1 NEOVERSEN2 ARMV8SVE)
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endif ()
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if (DYNAMIC_LIST)
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set(DYNAMIC_CORE ARMV8 ${DYNAMIC_LIST})
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@ -1,5 +1,6 @@
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/*********************************************************************/
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/* Copyright 2009, 2010 The University of Texas at Austin. */
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/* Copyright 2023 The OpenBLAS Project */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or */
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@ -109,6 +110,11 @@ extern gotoblas_t gotoblas_NEOVERSEN2;
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#else
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#define gotoblas_NEOVERSEN2 gotoblas_ARMV8
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#endif
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#ifdef DYN_ARMV8SVE
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extern gotoblas_t gotoblas_ARMV8SVE;
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#else
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#define gotoblas_ARMV8SVE gotoblas_ARMV8
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#endif
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#ifdef DYN_CORTEX_A55
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extern gotoblas_t gotoblas_CORTEXA55;
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#else
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@ -128,9 +134,11 @@ extern gotoblas_t gotoblas_NEOVERSEN1;
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#ifndef NO_SVE
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extern gotoblas_t gotoblas_NEOVERSEV1;
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extern gotoblas_t gotoblas_NEOVERSEN2;
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extern gotoblas_t gotoblas_ARMV8SVE;
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#else
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#define gotoblas_NEOVERSEV1 gotoblas_ARMV8
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#define gotoblas_NEOVERSEN2 gotoblas_ARMV8
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#define gotoblas_ARMV8SVE gotoblas_ARMV8
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#endif
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extern gotoblas_t gotoblas_THUNDERX3T110;
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extern gotoblas_t gotoblas_CORTEXA55;
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@ -140,7 +148,7 @@ extern void openblas_warning(int verbose, const char * msg);
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#define FALLBACK_VERBOSE 1
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#define NEOVERSEN1_FALLBACK "OpenBLAS : Your OS does not support SVE instructions. OpenBLAS is using Neoverse N1 kernels as a fallback, which may give poorer performance.\n"
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#define NUM_CORETYPES 13
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#define NUM_CORETYPES 16
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/*
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* In case asm/hwcap.h is outdated on the build system, make sure
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@ -173,6 +181,7 @@ static char *corename[] = {
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"neoversen2",
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"thunderx3t110",
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"cortexa55",
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"armv8sve",
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"unknown"
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};
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@ -192,6 +201,7 @@ char *gotoblas_corename(void) {
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if (gotoblas == &gotoblas_NEOVERSEN2) return corename[12];
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if (gotoblas == &gotoblas_THUNDERX3T110) return corename[13];
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if (gotoblas == &gotoblas_CORTEXA55) return corename[14];
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if (gotoblas == &gotoblas_ARMV8SVE) return corename[15];
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return corename[NUM_CORETYPES];
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}
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@ -226,6 +236,7 @@ static gotoblas_t *force_coretype(char *coretype) {
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case 12: return (&gotoblas_NEOVERSEN2);
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case 13: return (&gotoblas_THUNDERX3T110);
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case 14: return (&gotoblas_CORTEXA55);
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case 15: return (&gotoblas_ARMV8SVE);
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}
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snprintf(message, 128, "Core not found: %s\n", coretype);
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openblas_warning(1, message);
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@ -345,6 +356,12 @@ static gotoblas_t *get_coretype(void) {
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snprintf(coremsg, 128, "Unknown CPU model - implementer %x part %x\n",implementer,part);
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openblas_warning(1, coremsg);
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}
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#ifndef NO_SVE
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if ((getauxval(AT_HWCAP) & HWCAP_SVE)) {
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return &gotoblas_ARMV8SVE;
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}
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#endif
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return NULL;
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#endif
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}
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41
param.h
41
param.h
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@ -3371,7 +3371,7 @@ is a big desktop or server with abundant cache rather than a phone or embedded d
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#define CGEMM_DEFAULT_R 4096
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#define ZGEMM_DEFAULT_R 4096
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#elif defined(NEOVERSEV1)
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#elif defined(NEOVERSEV1) // 256-bit SVE
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#if defined(XDOUBLE) || defined(DOUBLE)
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#define SWITCH_RATIO 8
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@ -3449,7 +3449,7 @@ is a big desktop or server with abundant cache rather than a phone or embedded d
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#define CGEMM_DEFAULT_R 4096
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#define ZGEMM_DEFAULT_R 4096
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#elif defined(ARMV8SVE) || defined(A64FX) || defined(ARMV9) || defined(CORTEXA510)|| defined(CORTEXA710) || defined(CORTEXX2)
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#elif defined(A64FX) // 512-bit SVE
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/* When all BLAS3 routines are implemeted with SVE, SGEMM_DEFAULT_UNROLL_M should be "sve_vl".
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Until then, just keep it different than DGEMM_DEFAULT_UNROLL_N to keep copy routines in both directions seperated. */
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@ -3490,6 +3490,43 @@ Until then, just keep it different than DGEMM_DEFAULT_UNROLL_N to keep copy rout
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#define CGEMM_DEFAULT_R 4096
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#define ZGEMM_DEFAULT_R 4096
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#elif defined(ARMV8SVE) || defined(ARMV9) || defined(CORTEXA510)|| defined(CORTEXA710) || defined(CORTEXX2) // 128-bit SVE
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#if defined(XDOUBLE) || defined(DOUBLE)
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#define SWITCH_RATIO 8
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#else
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#define SWITCH_RATIO 16
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#endif
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#define SGEMM_DEFAULT_UNROLL_M 4 // Actually 1VL (8) but kept seperate to keep copies seperate
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#define SGEMM_DEFAULT_UNROLL_N 8
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#define DGEMM_DEFAULT_UNROLL_M 4
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#define DGEMM_DEFAULT_UNROLL_N 8
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#define CGEMM_DEFAULT_UNROLL_M 2
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#define CGEMM_DEFAULT_UNROLL_N 4
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#define CGEMM_DEFAULT_UNROLL_MN 16
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#define ZGEMM_DEFAULT_UNROLL_M 2
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#define ZGEMM_DEFAULT_UNROLL_N 4
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#define ZGEMM_DEFAULT_UNROLL_MN 16
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#define SGEMM_DEFAULT_P 128
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#define DGEMM_DEFAULT_P 160
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#define CGEMM_DEFAULT_P 128
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#define ZGEMM_DEFAULT_P 128
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#define SGEMM_DEFAULT_Q 352
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#define DGEMM_DEFAULT_Q 128
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#define CGEMM_DEFAULT_Q 224
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#define ZGEMM_DEFAULT_Q 112
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#define SGEMM_DEFAULT_R 4096
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#define DGEMM_DEFAULT_R 4096
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#define CGEMM_DEFAULT_R 4096
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#define ZGEMM_DEFAULT_R 4096
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#else /* Other/undetected ARMv8 cores */
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#define SGEMM_DEFAULT_UNROLL_M 16
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