[RISC-V] Add RISC-V Vector 128-bit target

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Current RVV x280 target depends on vlen=512-bits for Level 3 operations.
Commit adds generic target that supports vlen=128-bits.
New target uses the same scalable kernels as x280 for Level 1&2 operations, and autogenerated kernels for Level 3 operations.
Functional correctness of Level 3 operations tested on vlen=128-bits using QEMU v8.1.1 for ctests and BLAS-Tester.

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This commit is contained in:

Octavian Maghiar

2023-12-04 11:02:18 +00:00

parent 62f0f506ec

commit e4586e81b8

15 changed files with 6863 additions and 2 deletions

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kernel/riscv64/ctrmm_kernel_8x4_zvl128b.c Normal file

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