From de7875ca5df77306c5f7216959d3c15d82a0a259 Mon Sep 17 00:00:00 2001
From: James Cowgill <james410@cowgill.org.uk>
Date: Thu, 4 May 2017 14:35:36 +0100
Subject: [PATCH] mips: remove incorrect blas_lock implementations

MIPS 32-bit currently has an empty blas_lock implementation which is
worse than nothing at all. MIPS 64-bit does has a blas_lock
implementation but is broken. Remove them and fallback to the generic
version in common.h which should do the right thing on MIPS.
---
 common_mips.h   |  5 -----
 common_mips64.h | 22 ----------------------
 2 files changed, 27 deletions(-)

diff --git a/common_mips.h b/common_mips.h
index bb579d166..35bff5083 100644
--- a/common_mips.h
+++ b/common_mips.h
@@ -42,11 +42,6 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef ASSEMBLER
 
-static void INLINE blas_lock(volatile unsigned long *address){
-
-}
-#define BLAS_LOCK_DEFINED
-
 static inline unsigned int rpcc(void){
   unsigned long ret;
 
diff --git a/common_mips64.h b/common_mips64.h
index 21e706ca3..93bc7e519 100644
--- a/common_mips64.h
+++ b/common_mips64.h
@@ -78,28 +78,6 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef ASSEMBLER
 
-static void INLINE blas_lock(volatile unsigned long *address){
-
-  long int ret, val = 1;
-
-  do {
-    while (*address) {YIELDING;};
-
-    __asm__ __volatile__(
-			 "1:	ll	%0, %3\n"
-			 "	ori	%2, %0, 1\n"
-			 "	sc	%2, %1\n"
-			 "	beqz	%2, 1b\n"
-			 "	 andi	%2, %0, 1\n"
-			 "	sync\n"
-			 : "=&r" (val), "=m" (address), "=&r" (ret)
-			 : "m" (address)
-			 : "memory");
-
-  } while (ret);
-}
-#define BLAS_LOCK_DEFINED
-
 static inline unsigned int rpcc(void){
   unsigned long ret;