LoongArch64: using getauxval to do runtime check

Using the getauxval instruction can prevent errors
caused by hardware supporting vector instructions
while the kernel does not support them
This commit is contained in:
gxw 2023-06-30 16:31:47 +08:00
parent d46772e037
commit db9a42f8c3
1 changed files with 6 additions and 12 deletions

View File

@ -32,6 +32,7 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**********************************************************************************/ **********************************************************************************/
#include <stdint.h> #include <stdint.h>
#include <sys/auxv.h>
/* If LASX extension instructions supported, /* If LASX extension instructions supported,
* using core LOONGSON3R5 * using core LOONGSON3R5
@ -46,9 +47,8 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define CPU_LOONGSON3R5 1 #define CPU_LOONGSON3R5 1
#define CPU_LOONGSON2K1000 2 #define CPU_LOONGSON2K1000 2
#define LOONGARCH_CFG2 0x02 #define LA_HWCAP_LSX (1<<4)
#define LOONGARCH_LASX 1<<7 #define LA_HWCAP_LASX (1<<5)
#define LOONGARCH_LSX 1<<6
static char *cpuname[] = { static char *cpuname[] = {
"LOONGSONGENERIC", "LOONGSONGENERIC",
@ -64,17 +64,11 @@ static char *cpuname_lower[] = {
int detect(void) { int detect(void) {
#ifdef __linux #ifdef __linux
uint32_t reg = 0; int flag = (int)getauxval(AT_HWCAP);
__asm__ volatile ( if (flag & LA_HWCAP_LASX)
"cpucfg %0, %1 \n\t"
: "+&r"(reg)
: "r"(LOONGARCH_CFG2)
);
if (reg & LOONGARCH_LASX)
return CPU_LOONGSON3R5; return CPU_LOONGSON3R5;
else if (reg & LOONGARCH_LSX) else if (flag & LA_HWCAP_LSX)
return CPU_LOONGSON2K1000; return CPU_LOONGSON2K1000;
else else
return CPU_GENERIC; return CPU_GENERIC;