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Enable thread affinity on Loongson 3B. Fixed the bug of reading cycle counter. 

In Loongson 3A and 3B, the CPU core increases the counter in every 2 cycles by default.
This commit is contained in:
Xianyi Zhang 2011-11-11 17:49:41 +00:00
parent 0884f6b78d
commit d1baf14a64
2 changed files with 23 additions and 7 deletions
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2
Makefile.system
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@ -591,9 +591,11 @@ endif
ifneq ($(ARCH), x86_64) ifneq ($(ARCH), x86_64)
ifneq ($(ARCH), x86) ifneq ($(ARCH), x86)
ifneq ($(CORE), LOONGSON3B)
NO_AFFINITY = 1 NO_AFFINITY = 1
endif endif
endif endif
endif
ifdef NO_AFFINITY ifdef NO_AFFINITY
CCOMMON_OPT += -DNO_AFFINITY CCOMMON_OPT += -DNO_AFFINITY

28
common_mips64.h
View File

@ -101,13 +101,15 @@ static void INLINE blas_lock(volatile unsigned long *address){
static inline unsigned int rpcc(void){ static inline unsigned int rpcc(void){
unsigned long ret; unsigned long ret;
#if defined(LOONGSON3A) #if defined(LOONGSON3A) || defined(LOONGSON3B)
unsigned long long tmp; // unsigned long long tmp;
__asm__ __volatile__("dmfc0 %0, $25, 1": "=r"(tmp):: "memory"); //__asm__ __volatile__("dmfc0 %0, $25, 1": "=r"(tmp):: "memory");
ret=tmp; //ret=tmp;
#elif defined(LOONGSON3B) __asm__ __volatile__(".set push \n"
//Temp Implementation. ".set mips32r2\n"
return 1; "rdhwr %0, $2\n"
".set pop": "=r"(ret):: "memory");
#else #else
__asm__ __volatile__(".set push \n" __asm__ __volatile__(".set push \n"
".set mips32r2\n" ".set mips32r2\n"
@ -117,6 +119,18 @@ static inline unsigned int rpcc(void){
return ret; return ret;
} }
//#if defined(LOONGSON3A) || defined(LOONGSON3B)
static inline int WhereAmI(void){
int ret=0;
__asm__ __volatile__(".set push \n"
".set mips32r2\n"
"rdhwr %0, $0\n"
".set pop": "=r"(ret):: "memory");
return ret;
}
//#endif
static inline int blas_quickdivide(blasint x, blasint y){ static inline int blas_quickdivide(blasint x, blasint y){
return x / y; return x / y;
} }