Separate implementations of AMAX and IAMAX on arm
As noted in #1912 and comment on #1942, the combined implementation happens to "do the right thing" on hardfp, but cannot return both value and index on softfp where they would have to share the return register
This commit is contained in:
Martin Kroeker
GitHub
parent
ff1bfe7b16
commit
c70496b108
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@ -1,20 +1,20 @@
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include $(KERNELDIR)/KERNEL.ARMV5
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SAMAXKERNEL = iamax_vfp.S
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DAMAXKERNEL = iamax_vfp.S
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CAMAXKERNEL = iamax_vfp.S
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ZAMAXKERNEL = iamax_vfp.S
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SAMAXKERNEL = amax_vfp.S
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DAMAXKERNEL = amax_vfp.S
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CAMAXKERNEL = amax_vfp.S
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ZAMAXKERNEL = amax_vfp.S
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SAMINKERNEL = iamax_vfp.S
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DAMINKERNEL = iamax_vfp.S
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CAMINKERNEL = iamax_vfp.S
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ZAMINKERNEL = iamax_vfp.S
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SAMINKERNEL = amax_vfp.S
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DAMINKERNEL = amax_vfp.S
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CAMINKERNEL = amax_vfp.S
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ZAMINKERNEL = amax_vfp.S
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SMAXKERNEL = iamax_vfp.S
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DMAXKERNEL = iamax_vfp.S
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SMAXKERNEL = amax_vfp.S
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DMAXKERNEL = amax_vfp.S
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SMINKERNEL = iamax_vfp.S
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DMINKERNEL = iamax_vfp.S
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SMINKERNEL = amax_vfp.S
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DMINKERNEL = amax_vfp.S
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ISAMAXKERNEL = iamax_vfp.S
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IDAMAXKERNEL = iamax_vfp.S
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@ -0,0 +1,441 @@
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/***************************************************************************
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Copyright (c) 2013, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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/**************************************************************************************
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* 2013/11/14 Saar
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* BLASTEST : OK
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* CTEST : OK
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* TEST : OK
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*
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**************************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define STACKSIZE 256
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#define N r0
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#define X r1
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#define INC_X r2
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#define I r12
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#define X_PRE 512
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/**************************************************************************************
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* Macro definitions
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**************************************************************************************/
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#if defined(USE_ABS)
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#if defined(DOUBLE)
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#define VABS(x0,x1) vabs.f64 x0, x1
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#else
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#define VABS(x0,x1) vabs.f32 x0, x1
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#endif
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#else
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#define VABS(x0,x1) nop
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#endif
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/*****************************************************************************************/
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#if defined(USE_MIN)
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#define MOVCOND movlt
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#if defined(DOUBLE)
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#define VMOVCOND vmovlt.f64
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#else
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#define VMOVCOND vmovlt.f32
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#endif
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#else
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#define MOVCOND movgt
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#if defined(DOUBLE)
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#define VMOVCOND vmovgt.f64
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#else
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#define VMOVCOND vmovgt.f32
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#endif
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#endif
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/*****************************************************************************************/
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#if !defined(COMPLEX)
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#if defined(DOUBLE)
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.macro INIT_F
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vldmia.f64 X!, { d0 }
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VABS( d0, d0 )
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.endm
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.macro KERNEL_F1
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vldmia.f64 X!, { d4 }
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VABS( d4, d4 )
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vcmpe.f64 d4, d0
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vmrs APSR_nzcv, fpscr
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VMOVCOND d0, d4
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.endm
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.macro INIT_S
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vldmia.f64 X, { d0 }
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VABS( d0, d0 )
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add X, X, INC_X
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.endm
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.macro KERNEL_S1
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vldmia.f64 X, { d4 }
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VABS( d4, d4 )
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vcmpe.f64 d4, d0
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vmrs APSR_nzcv, fpscr
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VMOVCOND d0, d4
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add X, X, INC_X
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.endm
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#else
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.macro INIT_F
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vldmia.f32 X!, { s0 }
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VABS( s0, s0 )
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.endm
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.macro KERNEL_F1
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vldmia.f32 X!, { s4 }
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VABS( s4, s4 )
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vcmpe.f32 s4, s0
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vmrs APSR_nzcv, fpscr
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VMOVCOND s0, s4
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.endm
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.macro INIT_S
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vldmia.f32 X, { s0 }
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VABS( s0, s0 )
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add X, X, INC_X
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.endm
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.macro KERNEL_S1
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vldmia.f32 X, { s4 }
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VABS( s4, s4 )
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vcmpe.f32 s4, s0
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vmrs APSR_nzcv, fpscr
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VMOVCOND s0, s4
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add X, X, INC_X
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.endm
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#endif
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#else
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#if defined(DOUBLE)
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.macro INIT_F
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vldmia.f64 X!, { d0 -d1 }
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vabs.f64 d0, d0
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vabs.f64 d1, d1
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vadd.f64 d0 , d0, d1
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.endm
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.macro KERNEL_F1
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vldmia.f64 X!, { d4 - d5 }
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vabs.f64 d4, d4
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vabs.f64 d5, d5
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vadd.f64 d4 , d4, d5
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vcmpe.f64 d4, d0
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vmrs APSR_nzcv, fpscr
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VMOVCOND d0, d4
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.endm
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.macro INIT_S
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vldmia.f64 X, { d0 -d1 }
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vabs.f64 d0, d0
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vabs.f64 d1, d1
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vadd.f64 d0 , d0, d1
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add X, X, INC_X
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.endm
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.macro KERNEL_S1
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vldmia.f64 X, { d4 - d5 }
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vabs.f64 d4, d4
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vabs.f64 d5, d5
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vadd.f64 d4 , d4, d5
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vcmpe.f64 d4, d0
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vmrs APSR_nzcv, fpscr
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VMOVCOND d0, d4
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add X, X, INC_X
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.endm
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#else
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.macro INIT_F
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vldmia.f32 X!, { s0 -s1 }
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vabs.f32 s0, s0
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vabs.f32 s1, s1
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vadd.f32 s0 , s0, s1
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.endm
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.macro KERNEL_F1
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vldmia.f32 X!, { s4 - s5 }
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vabs.f32 s4, s4
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vabs.f32 s5, s5
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vadd.f32 s4 , s4, s5
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vcmpe.f32 s4, s0
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vmrs APSR_nzcv, fpscr
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VMOVCOND s0, s4
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.endm
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.macro INIT_S
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vldmia.f32 X, { s0 -s1 }
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vabs.f32 s0, s0
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vabs.f32 s1, s1
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vadd.f32 s0 , s0, s1
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add X, X, INC_X
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.endm
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.macro KERNEL_S1
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vldmia.f32 X, { s4 - s5 }
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vabs.f32 s4, s4
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vabs.f32 s5, s5
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vadd.f32 s4 , s4, s5
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vcmpe.f32 s4, s0
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vmrs APSR_nzcv, fpscr
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VMOVCOND s0, s4
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add X, X, INC_X
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.endm
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#endif
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#endif
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/**************************************************************************************
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* End of macro definitions
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**************************************************************************************/
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PROLOGUE
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.align 5
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movs r12, #0 // clear floating point register
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vmov s0, r12
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#if defined(DOUBLE)
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vcvt.f64.f32 d0, s0
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#endif
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cmp N, #0
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ble amax_kernel_L999
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cmp INC_X, #0
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beq amax_kernel_L999
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cmp INC_X, #1
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bne amax_kernel_S_BEGIN
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amax_kernel_F_BEGIN:
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INIT_F
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subs N, N , #1
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ble amax_kernel_L999
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asrs I, N, #2 // I = N / 4
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ble amax_kernel_F1
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.align 5
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amax_kernel_F4:
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pld [ X, #X_PRE ]
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KERNEL_F1
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KERNEL_F1
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#if defined(COMPLEX) && defined(DOUBLE)
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pld [ X, #X_PRE ]
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#endif
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KERNEL_F1
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KERNEL_F1
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subs I, I, #1
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ble amax_kernel_F1
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#if defined(COMPLEX) || defined(DOUBLE)
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pld [ X, #X_PRE ]
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#endif
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KERNEL_F1
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KERNEL_F1
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#if defined(COMPLEX) && defined(DOUBLE)
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pld [ X, #X_PRE ]
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#endif
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KERNEL_F1
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KERNEL_F1
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subs I, I, #1
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bne amax_kernel_F4
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amax_kernel_F1:
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ands I, N, #3
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ble amax_kernel_L999
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amax_kernel_F10:
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KERNEL_F1
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subs I, I, #1
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bne amax_kernel_F10
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b amax_kernel_L999
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amax_kernel_S_BEGIN:
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#if defined(COMPLEX)
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#if defined(DOUBLE)
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lsl INC_X, INC_X, #4 // INC_X * SIZE * 2
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#else
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lsl INC_X, INC_X, #3 // INC_X * SIZE * 2
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#endif
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#else
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#if defined(DOUBLE)
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lsl INC_X, INC_X, #3 // INC_X * SIZE
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#else
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lsl INC_X, INC_X, #2 // INC_X * SIZE
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#endif
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#endif
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INIT_S
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subs N, N , #1
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ble amax_kernel_L999
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asrs I, N, #2 // I = N / 4
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ble amax_kernel_S1
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.align 5
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amax_kernel_S4:
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KERNEL_S1
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KERNEL_S1
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KERNEL_S1
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KERNEL_S1
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subs I, I, #1
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bne amax_kernel_S4
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amax_kernel_S1:
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ands I, N, #3
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ble amax_kernel_L999
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amax_kernel_S10:
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KERNEL_S1
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subs I, I, #1
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bne amax_kernel_S10
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amax_kernel_L999:
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#if !defined(__ARM_PCS_VFP)
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vmov r0, s0
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#endif
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bx lr
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EPILOGUE
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