loongarch64: Refine amax,amin,max,min optimization.
This commit is contained in:
Shiyou Yin
229
kernel/loongarch64/max_lasx.S
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229
kernel/loongarch64/max_lasx.S
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/***************************************************************************
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Copyright (c) 2023, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define N $r4
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#define X $r5
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#define INCX $r6
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#define I $r12
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#define TEMP $r13
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#define VM0 $xr0
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#define VM1 $xr1
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#define VM2 $xr2
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#define VX0 $xr3
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#define VX1 $xr4
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#define VX2 $xr5
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#define VX3 $xr6
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#define t1 $r14
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#define t2 $r15
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#define t3 $r16
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#define t4 $r17
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PROLOGUE
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#ifdef F_INTERFACE
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LDINT N, 0(N)
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LDINT INCX, 0(INCX)
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#endif
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bge $r0, N, .L999
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bge $r0, INCX, .L999
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li.d TEMP, 1
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slli.d TEMP, TEMP, BASE_SHIFT
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slli.d INCX, INCX, BASE_SHIFT
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#ifdef DOUBLE
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xvldrepl.d VM0, X, 0
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#else
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xvldrepl.w VM0, X, 0
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#endif
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bne INCX, TEMP, .L20
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srai.d I, N, 4
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bge $r0, I, .L11
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.align 3
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.L10:
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#ifdef DOUBLE
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xvld VX0, X, 0
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xvld VX1, X, 32
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xvld VX2, X, 64
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xvld VX3, X, 96
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addi.d I, I, -1
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addi.d X, X, 128
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XVFMAX VM1, VX0, VX1
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XVFMAX VM2, VX2, VX3
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XVFMAX VM0, VM0, VM1
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XVFMAX VM0, VM0, VM2
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#else
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xvld VX0, X, 0
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xvld VX1, X, 32
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addi.d I, I, -1
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addi.d X, X, 64
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XVFMAX VM1, VX0, VX1
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XVFMAX VM0, VM0, VM1
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#endif
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blt $r0, I, .L10
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#ifdef DOUBLE
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xvrepl128vei.d VX0, VM0, 0
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xvrepl128vei.d VX1, VM0, 1
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XVFMAX VM0, VX0, VX1
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#else
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xvrepl128vei.w VX0, VM0, 0
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xvrepl128vei.w VX1, VM0, 1
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xvrepl128vei.w VX2, VM0, 2
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xvrepl128vei.w VX3, VM0, 3
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XVFMAX VM1, VX0, VX1
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XVFMAX VM2, VX2, VX3
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XVFMAX VM0, VM1, VM2
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#endif
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xvpermi.q VM1, VM0, 0x1
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XVFMAX VM0, VM0, VM1
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.align 3
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.L11:
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andi I, N, 0x0f
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bge $r0, I, .L13
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.align 3
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.L12: /* 0 < N < 16 */
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LD $f1, X, 0
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addi.d I, I, -1
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addi.d X, X, SIZE
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FMAX $f0, $f0, $f1
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bnez I, .L12
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.align 3
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.L13:
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jirl $r0, $r1, 0x0
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.align 3
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.L20: // INCX!=1
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srai.d I, N, 3
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bge $r0, I, .L23
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.align 3
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.L21:
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#ifdef DOUBLE
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ld.d t1, X, 0
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add.d X, X, INCX
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ld.d t2, X, 0
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add.d X, X, INCX
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ld.d t3, X, 0
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add.d X, X, INCX
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ld.d t4, X, 0
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add.d X, X, INCX
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xvinsgr2vr.d VX0, t1, 0
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xvinsgr2vr.d VX0, t2, 1
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xvinsgr2vr.d VX0, t3, 2
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xvinsgr2vr.d VX0, t4, 3
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ld.d t1, X, 0
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add.d X, X, INCX
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ld.d t2, X, 0
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add.d X, X, INCX
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ld.d t3, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t4, X, 0 * SIZE
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add.d X, X, INCX
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xvinsgr2vr.d VX1, t1, 0
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xvinsgr2vr.d VX1, t2, 1
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xvinsgr2vr.d VX1, t3, 2
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xvinsgr2vr.d VX1, t4, 3
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xvfmaxa.d VM1, VX0, VX1
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xvfmaxa.d VM0, VM0, VM1
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#else
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ld.w t1, X, 0
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add.d X, X, INCX
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ld.w t2, X, 0
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add.d X, X, INCX
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ld.w t3, X, 0
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add.d X, X, INCX
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ld.w t4, X, 0
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add.d X, X, INCX
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xvinsgr2vr.w VM1, t1, 0
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xvinsgr2vr.w VM1, t2, 1
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xvinsgr2vr.w VM1, t3, 2
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xvinsgr2vr.w VM1, t4, 3
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ld.w t1, X, 0
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add.d X, X, INCX
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ld.w t2, X, 0
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add.d X, X, INCX
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ld.w t3, X, 0
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add.d X, X, INCX
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ld.w t4, X, 0
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add.d X, X, INCX
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xvinsgr2vr.w VM1, t1, 4
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xvinsgr2vr.w VM1, t2, 5
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xvinsgr2vr.w VM1, t3, 6
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xvinsgr2vr.w VM1, t4, 7
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xvfmaxa.s VM0, VM0, VM1
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#endif
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addi.d I, I, -1
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blt $r0, I, .L21
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.align 3
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.L22:
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#ifdef DOUBLE
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xvrepl128vei.d VX0, VM0, 0
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xvrepl128vei.d VX1, VM0, 1
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XVFMAX VM0, VX0, VX1
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#else
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xvrepl128vei.w VX0, VM0, 0
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xvrepl128vei.w VX1, VM0, 1
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xvrepl128vei.w VX2, VM0, 2
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xvrepl128vei.w VX3, VM0, 3
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XVFMAX VM1, VX0, VX1
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XVFMAX VM2, VX2, VX3
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XVFMAX VM0, VM1, VM2
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#endif
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xvpermi.q VM1, VM0, 1
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XVFMAX VM0, VM0, VM1
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.align 3
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.L23: //INCX!=1 and N<8
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andi I, N, 7
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bge $r0, I, .L999
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.align 3
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.L24: /* 0 < N < 8 */
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LD $f1, X, 0
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addi.d I, I, -1
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add.d X, X, INCX
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FMAX $f0, $f0, $f1
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bnez I, .L24
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.align 3
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.L999:
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jirl $r0, $r1, 0x0
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EPILOGUE
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