From 86720778efe90391862c64f03fd5876fd302efaf Mon Sep 17 00:00:00 2001 From: Martin Kroeker Date: Fri, 18 Oct 2024 14:14:43 +0200 Subject: [PATCH 1/2] write HAVE_SVE to config where applicable --- cpuid_arm64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cpuid_arm64.c b/cpuid_arm64.c index 2cfa96ea6..77d5e286b 100644 --- a/cpuid_arm64.c +++ b/cpuid_arm64.c @@ -401,6 +401,7 @@ void get_cpuconfig(void) break; case CPU_NEOVERSEV1: + printf("#define HAVE_SVE 1\n"); case CPU_CORTEXA76: printf("#define %s\n", cpuname[d]); printf("#define L1_CODE_SIZE 65536\n"); @@ -432,6 +433,7 @@ void get_cpuconfig(void) break; case CPU_NEOVERSEV2: printf("#define ARMV9\n"); + printf("#define HAVE_SVE 1\n"); printf("#define %s\n", cpuname[d]); printf("#define L1_CODE_SIZE 65536\n"); printf("#define L1_CODE_LINESIZE 64\n"); @@ -452,6 +454,7 @@ void get_cpuconfig(void) case CPU_CORTEXX1: case CPU_CORTEXX2: printf("#define ARMV9\n"); + printf("#define HAVE_SVE 1\n"); printf("#define %s\n", cpuname[d]); printf("#define L1_CODE_SIZE 65536\n"); printf("#define L1_CODE_LINESIZE 64\n"); @@ -568,6 +571,7 @@ void get_cpuconfig(void) break; case CPU_A64FX: printf("#define A64FX\n"); + printf("#define HAVE_SVE 1\n"); printf("#define L1_CODE_SIZE 65535\n"); printf("#define L1_DATA_SIZE 65535\n"); printf("#define L1_DATA_LINESIZE 256\n"); From c4bb4e74fc5ce7987d32cb0eb8c9dfedc4ecd7ae Mon Sep 17 00:00:00 2001 From: Martin Kroeker Date: Fri, 18 Oct 2024 14:50:55 +0200 Subject: [PATCH 2/2] NeoverseN2 has SVE too --- cpuid_arm64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cpuid_arm64.c b/cpuid_arm64.c index 77d5e286b..5d25d2ff6 100644 --- a/cpuid_arm64.c +++ b/cpuid_arm64.c @@ -430,6 +430,7 @@ void get_cpuconfig(void) printf("#define L2_ASSOCIATIVE 8\n"); printf("#define DTB_DEFAULT_ENTRIES 48\n"); printf("#define DTB_SIZE 4096\n"); + printf("#define HAVE_SVE 1\n"); break; case CPU_NEOVERSEV2: printf("#define ARMV9\n");