THUNDERX2T99: Add threaded SNRM2 Implementation
This commit is contained in:
Ashwin Sekhar T K
parent
cde3aee08b
commit
907e286eb6
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@ -1,6 +1,10 @@
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include $(KERNELDIR)/KERNEL.CORTEXA57
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ifndef SMP
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SNRM2KERNEL = snrm2_thunderx2t99.S
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else
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SNRM2KERNEL = nrm2_thunderx2t99_threaded.c
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endif
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CNRM2KERNEL = cnrm2_thunderx2t99.S
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DAXPYKERNEL = daxpy_thunderx2t99.S
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@ -0,0 +1,249 @@
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/***************************************************************************
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Copyright (c) 2017, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#include "common.h"
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#include <arm_neon.h>
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extern int blas_level1_thread_with_return_value(int mode, BLASLONG m, BLASLONG n,
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BLASLONG k, void *alpha, void *a, BLASLONG lda, void *b, BLASLONG ldb,
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void *c, BLASLONG ldc, int (*function)(), int nthreads);
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#if !defined(DOUBLE)
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#define N "x0" /* vector length */
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#define X "x1" /* X vector address */
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#define INC_X "x2" /* X stride */
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#define I "x5" /* loop variable */
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#define TMPF "s16"
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#define TMPFD "d17"
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#define SSQD "d0"
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#define KERNEL_F1 \
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"ldr "TMPF", ["X"], #4 \n" \
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"fcvt "TMPFD", "TMPF" \n" \
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"fmadd "SSQD", "TMPFD", "TMPFD", "SSQD"\n"
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#define KERNEL_F32 \
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"ldur q16, ["X"] \n" \
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"ldur q18, ["X", #16] \n" \
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"ldur q20, ["X", #32] \n" \
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"ldur q22, ["X", #48] \n" \
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"ldur q24, ["X", #64] \n" \
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"ldur q26, ["X", #80] \n" \
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"ldur q28, ["X", #96] \n" \
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"ldur q30, ["X", #112] \n" \
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"add "X", "X", #128 \n" \
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"fcvtl2 v17.2d, v16.4s \n" \
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"fcvtl v16.2d, v16.2s \n" \
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"fcvtl2 v19.2d, v18.4s \n" \
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"fcvtl v18.2d, v18.2s \n" \
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"fcvtl2 v21.2d, v20.4s \n" \
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"fcvtl v20.2d, v20.2s \n" \
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"fcvtl2 v23.2d, v22.4s \n" \
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"fcvtl v22.2d, v22.2s \n" \
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"fcvtl2 v25.2d, v24.4s \n" \
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"fcvtl v24.2d, v24.2s \n" \
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"fcvtl2 v27.2d, v26.4s \n" \
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"fcvtl v26.2d, v26.2s \n" \
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"fcvtl2 v29.2d, v28.4s \n" \
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"fcvtl v28.2d, v28.2s \n" \
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"fcvtl2 v31.2d, v30.4s \n" \
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"fcvtl v30.2d, v30.2s \n" \
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"fmla v0.2d, v16.2d, v16.2d \n" \
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"fmla v1.2d, v17.2d, v17.2d \n" \
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"fmla v2.2d, v18.2d, v18.2d \n" \
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"fmla v3.2d, v19.2d, v19.2d \n" \
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"fmla v4.2d, v20.2d, v20.2d \n" \
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"fmla v5.2d, v21.2d, v21.2d \n" \
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"fmla v6.2d, v22.2d, v22.2d \n" \
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"fmla v7.2d, v23.2d, v23.2d \n" \
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"fmla v0.2d, v24.2d, v24.2d \n" \
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"fmla v1.2d, v25.2d, v25.2d \n" \
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"fmla v2.2d, v26.2d, v26.2d \n" \
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"fmla v3.2d, v27.2d, v27.2d \n" \
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"fmla v4.2d, v28.2d, v28.2d \n" \
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"fmla v5.2d, v29.2d, v29.2d \n" \
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"fmla v6.2d, v30.2d, v30.2d \n" \
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"fmla v7.2d, v31.2d, v31.2d \n" \
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"prfm PLDL1KEEP, ["X", #1024] \n" \
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"prfm PLDL1KEEP, ["X", #1024+64] \n"
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#define KERNEL_F32_FINALIZE \
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"fadd v0.2d, v0.2d, v1.2d \n" \
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"fadd v2.2d, v2.2d, v3.2d \n" \
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"fadd v4.2d, v4.2d, v5.2d \n" \
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"fadd v6.2d, v6.2d, v7.2d \n" \
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"fadd v0.2d, v0.2d, v2.2d \n" \
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"fadd v4.2d, v4.2d, v6.2d \n" \
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"fadd v0.2d, v0.2d, v4.2d \n" \
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"faddp "SSQD", v0.2d \n"
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#define KERNEL_S1 \
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"ldr "TMPF", ["X"] \n" \
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"add "X", "X", "INC_X" \n" \
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"fcvt "TMPFD", "TMPF" \n" \
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"fmadd "SSQD", "TMPFD", "TMPFD", "SSQD"\n"
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static double nrm2_compute(BLASLONG n, FLOAT *x, BLASLONG inc_x)
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{
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double ret = 0.0 ;
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if (n <= 0) return ret;
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__asm__ __volatile__ (
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" mov "N", %[N_] \n"
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" mov "X", %[X_] \n"
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" mov "INC_X", %[INCX_] \n"
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" fmov "SSQD", xzr \n"
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" fmov d1, xzr \n"
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" fmov d2, xzr \n"
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" fmov d3, xzr \n"
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" fmov d4, xzr \n"
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" fmov d5, xzr \n"
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" fmov d6, xzr \n"
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" fmov d7, xzr \n"
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" cmp "N", xzr \n"
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" ble 8f //nrm2_kernel_L999 \n"
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" cmp "INC_X", xzr \n"
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" ble 8f //nrm2_kernel_L999 \n"
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" cmp "INC_X", #1 \n"
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" bne 5f // nrm2_kernel_S_BEGIN \n"
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"1: //nrm2_kernel_F_BEGIN: \n"
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" asr "I", "N", #6 \n"
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" cmp "I", xzr \n"
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" beq 5f // nrm2_kernel_S_BEGIN \n"
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" .align 5 \n"
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"2: //nrm2_kernel_F64: \n"
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" "KERNEL_F32" \n"
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" "KERNEL_F32" \n"
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" subs "I", "I", #1 \n"
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" bne 2b //nrm2_kernel_F64 \n"
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" "KERNEL_F32_FINALIZE" \n"
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"3: // nrm2_kernel_F1: \n"
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" ands "I", "N", #63 \n"
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" ble 8f //nrm2_kernel_L999 \n"
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"4: // nrm2_kernel_F10: \n"
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" "KERNEL_F1" \n"
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" subs "I", "I", #1 \n"
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" bne 4b //nrm2_kernel_F10 \n"
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" b 8f //nrm2_kernel_L999 \n"
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"5: // nrm2_kernel_S_BEGIN: \n"
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" lsl "INC_X", "INC_X", #2 \n"
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" asr "I", "N", #2 \n"
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" cmp "I", xzr \n"
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" ble 6f //nrm2_kernel_S1 \n"
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"4: //nrm2_kernel_S4: \n"
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" "KERNEL_S1" \n"
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" "KERNEL_S1" \n"
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" "KERNEL_S1" \n"
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" "KERNEL_S1" \n"
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" subs "I", "I", #1 \n"
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" bne 4b //nrm2_kernel_S4 \n"
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"6: //nrm2_kernel_S1: \n"
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" ands "I", "N", #3 \n"
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" ble 8f //nrm2_kernel_L999 \n"
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"7: //nrm2_kernel_S10: \n"
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" "KERNEL_S1" \n"
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" subs "I", "I", #1 \n"
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" bne 7b //nrm2_kernel_S10 \n"
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"8: //nrm2_kernel_L999: \n"
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" fmov %[RET_], "SSQD" \n"
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: [RET_] "=r" (ret) //%0
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: [N_] "r" (n), //%1
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[X_] "r" (x), //%2
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[INCX_] "r" (inc_x) //%3
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: "cc",
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"memory",
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"x0", "x1", "x2", "x3", "x4", "x5",
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"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7"
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);
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return ret;
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}
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#else //!defined(DOUBLE)
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#endif
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static int nrm2_thread_function(BLASLONG n, BLASLONG dummy0,
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BLASLONG dummy1, FLOAT dummy2, FLOAT *x, BLASLONG inc_x, FLOAT *dummy3,
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BLASLONG dummy4, FLOAT *result, BLASLONG dummy5)
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{
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*(double *)result = nrm2_compute(n, x, inc_x);
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return 0;
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}
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FLOAT CNAME(BLASLONG n, FLOAT *x, BLASLONG inc_x)
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{
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int nthreads;
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FLOAT nrm2 = 0.0;
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double nrm2_double = 0.0;
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FLOAT dummy_alpha;
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if (n <= 0 || inc_x <= 0) return 0.0;
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if (n == 1) return fabs(x[0]);
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nthreads = num_cpu_avail(1);
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if (n <= 10000)
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nthreads = 1;
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if (nthreads == 1) {
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nrm2_double = nrm2_compute(n, x, inc_x);
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} else {
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int mode, i;
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char result[MAX_CPU_NUMBER * sizeof(double) * 2];
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double *ptr;
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mode = BLAS_SINGLE | BLAS_REAL;
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blas_level1_thread_with_return_value(mode, n, 0, 0, &dummy_alpha,
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x, inc_x, NULL, 0, result, 0,
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( void *)nrm2_thread_function, nthreads);
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ptr = (double *)result;
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for (i = 0; i < nthreads; i++) {
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nrm2_double = nrm2_double + (*ptr) * (*ptr);
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ptr = (double *)(((char *)ptr) + sizeof(double) * 2);
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}
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}
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nrm2 = sqrt(nrm2_double);
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return nrm2;
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}
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