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Add more x86_64 target definitions for cross-compiling

This commit is contained in:
Martin Kroeker 2022-08-04 19:18:32 +02:00 committed by GitHub
parent 096ae6f2bd
commit 3784b3d45c
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 680 additions and 0 deletions
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680
cmake/prebuild.cmake
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@ -131,6 +131,8 @@ if (DEFINED CORE AND CMAKE_CROSSCOMPILING AND NOT (${HOST_OS} STREQUAL "WINDOWSS
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSSE3 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 8)
set(SGEMM_UNROLL_N 4)
set(DGEMM_UNROLL_M 4)
@ -143,6 +145,684 @@ if (DEFINED CORE AND CMAKE_CROSSCOMPILING AND NOT (${HOST_OS} STREQUAL "WINDOWSS
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "ATOM")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t24576\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t524288\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t64\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_CMOV\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define HAVE_SSSE3\n"
"#define SLOCAL_BUFFER_SIZE\t16384\n"
"#define DLOCAL_BUFFER_SIZE\t8192\n"
"#define CLOCAL_BUFFER_SIZE\t16384\n"
"#define ZLOCAL_BUFFER_SIZE\t8192\n")
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSSE3 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 8)
set(SGEMM_UNROLL_N 4)
set(DGEMM_UNROLL_M 4)
set(DGEMM_UNROLL_N 2)
set(CGEMM_UNROLL_M 4)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 2)
set(ZGEMM_UNROLL_N 1)
set(CGEMM3M_UNROLL_M 8)
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "PRESCOTT")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t16384\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t1048576\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t64\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_CMOV\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define SLOCAL_BUFFER_SIZE\t8192\n"
"#define DLOCAL_BUFFER_SIZE\t8192\n"
"#define CLOCAL_BUFFER_SIZE\t8192\n"
"#define ZLOCAL_BUFFER_SIZE\t8192\n")
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 8)
set(SGEMM_UNROLL_N 4)
set(DGEMM_UNROLL_M 4)
set(DGEMM_UNROLL_N 4)
set(CGEMM_UNROLL_M 4)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 2)
set(ZGEMM_UNROLL_N 2)
set(CGEMM3M_UNROLL_M 8)
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "NEHALEM")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t32768\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t262144\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t64\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_CMOV\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define HAVE_SSSE3\n"
"#define HAVE_SSE4_1\n"
"#define HAVE_SSE4_2\n"
"#define SLOCAL_BUFFER_SIZE\t65535\n"
"#define DLOCAL_BUFFER_SIZE\t32768\n"
"#define CLOCAL_BUFFER_SIZE\t65536\n"
"#define ZLOCAL_BUFFER_SIZE\t32768\n")
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSSE3 1)
set(HAVE_SSE4_1 1)
set(HAVE_SSE4_2 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 4)
set(SGEMM_UNROLL_N 8)
set(DGEMM_UNROLL_M 2)
set(DGEMM_UNROLL_N 8)
set(CGEMM_UNROLL_M 2)
set(CGEMM_UNROLL_N 4)
set(ZGEMM_UNROLL_M 1)
set(ZGEMM_UNROLL_N 4)
set(CGEMM3M_UNROLL_M 4)
set(CGEMM3M_UNROLL_N 8)
set(ZGEMM3M_UNROLL_M 2)
set(ZGEMM3M_UNROLL_N 8)
elseif ("${TCORE}" STREQUAL "SANDYBRIDGE")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t32768\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t262144\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t64\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_CMOV\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define HAVE_SSSE3\n"
"#define HAVE_SSE4_1\n"
"#define HAVE_SSE4_2\n"
"#define HAVE_AVX\n"
"#define SLOCAL_BUFFER_SIZE\t24576\n"
"#define DLOCAL_BUFFER_SIZE\t16384\n"
"#define CLOCAL_BUFFER_SIZE\t32768\n"
"#define ZLOCAL_BUFFER_SIZE\t24576\n")
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSSE3 1)
set(HAVE_SSE4_1 1)
set(HAVE_SSE4_2 1)
set(HAVE_AVX 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 16)
set(SGEMM_UNROLL_N 4)
set(DGEMM_UNROLL_M 8)
set(DGEMM_UNROLL_N 4)
set(CGEMM_UNROLL_M 8)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 1)
set(ZGEMM_UNROLL_N 4)
set(CGEMM3M_UNROLL_M 4)
set(CGEMM3M_UNROLL_N 8)
set(ZGEMM3M_UNROLL_M 2)
set(ZGEMM3M_UNROLL_N 8)
elseif ("${TCORE}" STREQUAL "HASWELL")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t32768\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t262144\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t64\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_CMOV\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define HAVE_SSSE3\n"
"#define HAVE_SSE4_1\n"
"#define HAVE_SSE4_2\n"
"#define HAVE_AVX\n"
"#define HAVE_AVX2\n"
"#define HAVE_FMA3\n"
"#define SLOCAL_BUFFER_SIZE\t20480\n"
"#define DLOCAL_BUFFER_SIZE\t32768\n"
"#define CLOCAL_BUFFER_SIZE\t16384\n"
"#define ZLOCAL_BUFFER_SIZE\t12288\n")
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSSE3 1)
set(HAVE_SSE4_1 1)
set(HAVE_SSE4_2 1)
set(HAVE_AVX 1)
set(HAVE_AVX2 1)
set(HAVE_FMA3 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 8)
set(SGEMM_UNROLL_N 4)
set(DGEMM_UNROLL_M 4)
set(DGEMM_UNROLL_N 8)
set(CGEMM_UNROLL_M 8)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 4)
set(ZGEMM_UNROLL_N 2)
set(CGEMM3M_UNROLL_M 8)
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "SKYLAKEX")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t32768\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t262144\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t64\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_CMOV\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define HAVE_SSSE3\n"
"#define HAVE_SSE4_1\n"
"#define HAVE_SSE4_2\n"
"#define HAVE_AVX\n"
"#define HAVE_AVX2\n"
"#define HAVE_FMA3\n"
"#define HAVE_AVX512VL\n"
"#define SLOCAL_BUFFER_SIZE\t28672\n"
"#define DLOCAL_BUFFER_SIZE\t12288\n"
"#define CLOCAL_BUFFER_SIZE\t12288\n"
"#define ZLOCAL_BUFFER_SIZE\t8192\n")
set(HAVE_CMOV 1)
set(HAVE_MMX 1)
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSSE3 1)
set(HAVE_SSE4_1 1)
set(HAVE_SSE4_2 1)
set(HAVE_AVX 1)
set(HAVE_AVX2 1)
set(HAVE_FMA3 1)
set(HAVE_AVX512VL 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 16)
set(SGEMM_UNROLL_N 4)
set(DGEMM_UNROLL_M 16)
set(DGEMM_UNROLL_N 2)
set(CGEMM_UNROLL_M 8)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 4)
set(ZGEMM_UNROLL_N 2)
set(CGEMM3M_UNROLL_M 8)
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "COOPERLAKE")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t32768\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t262144\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t64\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_CMOV\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define HAVE_SSSE3\n"
"#define HAVE_SSE4_1\n"
"#define HAVE_SSE4_2\n"
"#define HAVE_AVX\n"
"#define HAVE_AVX2\n"
"#define HAVE_FMA3\n"
"#define HAVE_AVX512VL\n"
"#define HAVE_AVX512BF16\n"
"#define SLOCAL_BUFFER_SIZE\t20480\n"
"#define DLOCAL_BUFFER_SIZE\t12288\n"
"#define CLOCAL_BUFFER_SIZE\t12288\n"
"#define ZLOCAL_BUFFER_SIZE\t8192\n")
set(HAVE_CMOV 1)
set(HAVE_MMX 1)
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSSE3 1)
set(HAVE_SSE4_1 1)
set(HAVE_SSE4_2 1)
set(HAVE_AVX 1)
set(HAVE_AVX2 1)
set(HAVE_FMA3 1)
set(HAVE_AVX512VL 1)
set(HAVE_AVX512BF16 1)
set(SBGEMM_UNROLL_M 16)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 16)
set(SGEMM_UNROLL_N 4)
set(DGEMM_UNROLL_M 16)
set(DGEMM_UNROLL_N 2)
set(CGEMM_UNROLL_M 8)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 4)
set(ZGEMM_UNROLL_N 2)
set(CGEMM3M_UNROLL_M 8)
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "SAPPHIRERAPIDS")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t32768\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t262144\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t64\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_CMOV\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define HAVE_SSSE3\n"
"#define HAVE_SSE4_1\n"
"#define HAVE_SSE4_2\n"
"#define HAVE_AVX\n"
"#define HAVE_AVX2\n"
"#define HAVE_FMA3\n"
"#define HAVE_AVX512VL\n"
"#define HAVE_AVX512BF16\n"
"#define SLOCAL_BUFFER_SIZE\t20480\n"
"#define DLOCAL_BUFFER_SIZE\t12288\n"
"#define CLOCAL_BUFFER_SIZE\t12288\n"
"#define ZLOCAL_BUFFER_SIZE\t8192\n")
set(HAVE_CMOV 1)
set(HAVE_MMX 1)
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSSE3 1)
set(HAVE_SSE4_1 1)
set(HAVE_SSE4_2 1)
set(HAVE_AVX 1)
set(HAVE_AVX2 1)
set(HAVE_FMA3 1)
set(HAVE_AVX512VL 1)
set(HAVE_AVX512BF16 1)
set(SBGEMM_UNROLL_M 32)
set(SBGEMM_UNROLL_N 16)
set(SGEMM_UNROLL_M 16)
set(SGEMM_UNROLL_N 4)
set(DGEMM_UNROLL_M 16)
set(DGEMM_UNROLL_N 2)
set(CGEMM_UNROLL_M 8)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 4)
set(ZGEMM_UNROLL_N 2)
set(CGEMM3M_UNROLL_M 8)
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "OPTERON")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t65536\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t1048576\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t32\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_3DNOW\n"
"#define HAVE_3DNOWEX\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define SLOCAL_BUFFER_SIZE\t15360\n"
"#define DLOCAL_BUFFER_SIZE\t15360\n"
"#define CLOCAL_BUFFER_SIZE\t15360\n"
"#define ZLOCAL_BUFFER_SIZE\t15360\n")
set(HAVE_3DNOW 1)
set(HAVE_3DNOWEX 1)
set(HAVE_MMX 1)
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 8)
set(SGEMM_UNROLL_N 4)
set(DGEMM_UNROLL_M 4)
set(DGEMM_UNROLL_N 4)
set(CGEMM_UNROLL_M 4)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 2)
set(ZGEMM_UNROLL_N 2)
set(CGEMM3M_UNROLL_M 8)
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "BARCELONA")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t32768\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t524288\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t64\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define HAVE_SSE4A\n"
"#define HAVE_MISALIGNSSE\n"
"#define HAVE_128BITFPU\n"
"#define HAVE_FASTMOVU\n"
"#define SLOCAL_BUFFER_SIZE\t14336\n"
"#define DLOCAL_BUFFER_SIZE\t14336\n"
"#define CLOCAL_BUFFER_SIZE\t14336\n"
"#define ZLOCAL_BUFFER_SIZE\t14336\n")
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSE4A 1)
set(HAVE_MISALIGNSSE 1)
set(HAVE_128BITFPU 1)
set(HAVE_FASTMOVU 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 8)
set(SGEMM_UNROLL_N 4)
set(DGEMM_UNROLL_M 4)
set(DGEMM_UNROLL_N 4)
set(CGEMM_UNROLL_M 4)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 2)
set(ZGEMM_UNROLL_N 2)
set(CGEMM3M_UNROLL_M 8)
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "BULLDOZER")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t49152\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t1024000\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t32\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define HAVE_SSE4A\n"
"#define HAVE_AVX\n"
"#define HAVE_MISALIGNSSE\n"
"#define HAVE_128BITFPU\n"
"#define HAVE_FASTMOVU\n"
"#define SLOCAL_BUFFER_SIZE\t5376\n"
"#define DLOCAL_BUFFER_SIZE\t5376\n"
"#define CLOCAL_BUFFER_SIZE\t14336\n"
"#define ZLOCAL_BUFFER_SIZE\t14336\n")
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSE4A 1)
set(HAVE_AVX 1)
set(HAVE_MISALIGNSSE 1)
set(HAVE_128BITFPU 1)
set(HAVE_FASTMOVU 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 16)
set(SGEMM_UNROLL_N 2)
set(DGEMM_UNROLL_M 8)
set(DGEMM_UNROLL_N 2)
set(CGEMM_UNROLL_M 2)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 2)
set(ZGEMM_UNROLL_N 2)
set(CGEMM3M_UNROLL_M 8)
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "PILEDRIVER")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t16384\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t2097152\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t64\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define HAVE_SSE4_1\n"
"#define HAVE_SSE4_2\n"
"#define HAVE_SSE4A\n"
"#define HAVE_AVX\n"
"#define HAVE_MISALIGNSSE\n"
"#define HAVE_128BITFPU\n"
"#define HAVE_FASTMOVU\n"
"#define HAVE_CFLUSH\n"
"#define HAVE_FMA3\n"
"#define SLOCAL_BUFFER_SIZE\t6144\n"
"#define DLOCAL_BUFFER_SIZE\t5376\n"
"#define CLOCAL_BUFFER_SIZE\t10752\n"
"#define ZLOCAL_BUFFER_SIZE\t10752\n")
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSE4_1 1)
set(HAVE_SSE4_2 1)
set(HAVE_SSE4A 1)
set(HAVE_AVX 1)
set(HAVE_FMA3 1)
set(HAVE_MISALIGNSSE 1)
set(HAVE_128BITFPU 1)
set(HAVE_FASTMOVU 1)
set(HAVE_CFLUSH 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 16)
set(SGEMM_UNROLL_N 2)
set(DGEMM_UNROLL_M 8)
set(DGEMM_UNROLL_N 2)
set(CGEMM_UNROLL_M 4)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 2)
set(ZGEMM_UNROLL_N 2)
set(CGEMM3M_UNROLL_M 8)
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "STEAMROLLER")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t16384\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t2097152\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t64\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define HAVE_SSE4_1\n"
"#define HAVE_SSE4_2\n"
"#define HAVE_SSE4A\n"
"#define HAVE_AVX\n"
"#define HAVE_MISALIGNSSE\n"
"#define HAVE_128BITFPU\n"
"#define HAVE_FASTMOVU\n"
"#define HAVE_CFLUSH\n"
"#define HAVE_FMA3\n"
"#define SLOCAL_BUFFER_SIZE\t6144\n"
"#define DLOCAL_BUFFER_SIZE\t5120\n"
"#define CLOCAL_BUFFER_SIZE\t10240\n"
"#define ZLOCAL_BUFFER_SIZE\t10240\n")
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSE4_1 1)
set(HAVE_SSE4_2 1)
set(HAVE_SSE4A 1)
set(HAVE_AVX 1)
set(HAVE_FMA3 1)
set(HAVE_MISALIGNSSE 1)
set(HAVE_128BITFPU 1)
set(HAVE_FASTMOVU 1)
set(HAVE_CFLUSH 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 16)
set(SGEMM_UNROLL_N 2)
set(DGEMM_UNROLL_M 8)
set(DGEMM_UNROLL_N 2)
set(CGEMM_UNROLL_M 4)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 2)
set(ZGEMM_UNROLL_N 2)
set(CGEMM3M_UNROLL_M 8)
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "EXCAVATOR")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t16384\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t2097152\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t64\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define HAVE_SSE4_1\n"
"#define HAVE_SSE4_2\n"
"#define HAVE_SSE4A\n"
"#define HAVE_AVX\n"
"#define HAVE_MISALIGNSSE\n"
"#define HAVE_128BITFPU\n"
"#define HAVE_FASTMOVU\n"
"#define HAVE_CFLUSH\n"
"#define HAVE_FMA3\n"
"#define SLOCAL_BUFFER_SIZE\t6144\n"
"#define DLOCAL_BUFFER_SIZE\t5120\n"
"#define CLOCAL_BUFFER_SIZE\t10240\n"
"#define ZLOCAL_BUFFER_SIZE\t10240\n")
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSE4_1 1)
set(HAVE_SSE4_2 1)
set(HAVE_SSE4A 1)
set(HAVE_AVX 1)
set(HAVE_FMA3 1)
set(HAVE_MISALIGNSSE 1)
set(HAVE_128BITFPU 1)
set(HAVE_FASTMOVU 1)
set(HAVE_CFLUSH 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 16)
set(SGEMM_UNROLL_N 2)
set(DGEMM_UNROLL_M 8)
set(DGEMM_UNROLL_N 2)
set(CGEMM_UNROLL_M 4)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 2)
set(ZGEMM_UNROLL_N 2)
set(CGEMM3M_UNROLL_M 8)
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "ZEN")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t32768\n"
"#define L1_DATA_LINESIZE\t64\n"
"#define L2_SIZE\t524288\n"
"#define L2_LINESIZE\t64\n"
"#define DTB_DEFAULT_ENTRIES\t64\n"
"#define DTB_SIZE\t4096\n"
"#define HAVE_MMX\n"
"#define HAVE_SSE\n"
"#define HAVE_SSE2\n"
"#define HAVE_SSE3\n"
"#define HAVE_SSE4_1\n"
"#define HAVE_SSE4_2\n"
"#define HAVE_SSE4A\n"
"#define HAVE_MISALIGNSSE\n"
"#define HAVE_128BITFPU\n"
"#define HAVE_FASTMOVU\n"
"#define HAVE_CFLUSH\n"
"#define HAVE_AVX\n"
"#define HAVE_AVX2\n"
"#define HAVE_FMA3\n"
"#define SLOCAL_BUFFER_SIZE\t20480\n"
"#define DLOCAL_BUFFER_SIZE\t32768\n"
"#define CLOCAL_BUFFER_SIZE\t16384\n"
"#define ZLOCAL_BUFFER_SIZE\t12288\n")
set(HAVE_SSE 1)
set(HAVE_SSE2 1)
set(HAVE_SSE3 1)
set(HAVE_SSE4_1 1)
set(HAVE_SSE4_2 1)
set(HAVE_AVX 1)
set(HAVE_AVX2 1)
set(HAVE_FMA3 1)
set(HAVE_SSE4A 1)
set(HAVE_MISALIGNSSE 1)
set(HAVE_128BITFPU 1)
set(HAVE_FASTMOVU 1)
set(HAVE_CFLUSH 1)
set(SBGEMM_UNROLL_M 8)
set(SBGEMM_UNROLL_N 4)
set(SGEMM_UNROLL_M 8)
set(SGEMM_UNROLL_N 4)
set(DGEMM_UNROLL_M 4)
set(DGEMM_UNROLL_N 8)
set(CGEMM_UNROLL_M 8)
set(CGEMM_UNROLL_N 2)
set(ZGEMM_UNROLL_M 4)
set(ZGEMM_UNROLL_N 2)
set(CGEMM3M_UNROLL_M 8)
set(CGEMM3M_UNROLL_N 4)
set(ZGEMM3M_UNROLL_M 4)
set(ZGEMM3M_UNROLL_N 4)
elseif ("${TCORE}" STREQUAL "ARMV7")
file(APPEND ${TARGET_CONF_TEMP}
"#define L1_DATA_SIZE\t65536\n"