temporarily(?) disable the alpha=0 branch as it does not handle INF,NAN
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@ -84,8 +84,9 @@
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cmpwi cr0, N, 0
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blelr- cr0
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fcmpu cr0, FZERO, ALPHA
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bne- cr0, LL(A1I1)
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// fcmpu cr0, FZERO, ALPHA
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// bne- cr0, LL(A1I1)
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b LL(A1I1)
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cmpwi cr0, INCX, SIZE
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bne- cr0, LL(A0IN)
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