Replace with ARM64 intrinsics
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1bb7993a97
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@ -35,9 +35,9 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifdef C_MSVC
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#ifdef C_MSVC
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#include <intrin.h>
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#include <intrin.h>
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#define MB do {} while (0)
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#define MB __dmb(_ARM64_BARRIER_ISH)
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#define WMB do {} while (0)
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#define WMB __dmb(_ARM64_BARRIER_ISHST)
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#define RMB
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#define RMB __dmb(_ARM64_BARRIER_ISHLD)
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#else
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#else
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#define MB __asm__ __volatile__ ("dmb ish" : : : "memory")
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#define MB __asm__ __volatile__ ("dmb ish" : : : "memory")
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#define WMB __asm__ __volatile__ ("dmb ishst" : : : "memory")
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#define WMB __asm__ __volatile__ ("dmb ishst" : : : "memory")
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@ -92,7 +92,12 @@ static void __inline blas_lock(volatile BLASULONG *address){
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#if !defined(OS_DARWIN) && !defined (OS_ANDROID)
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#if !defined(OS_DARWIN) && !defined (OS_ANDROID)
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static __inline BLASULONG rpcc(void){
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static __inline BLASULONG rpcc(void){
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#ifdef C_MSVC
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#ifdef C_MSVC
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return __rdtsc();
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const int64_t pmccntr_el0 = (((3 & 1) << 14) | // op0
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((3 & 7) << 11) | // op1
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((9 & 15) << 7) | // crn
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((13 & 15) << 3) | // crm
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((0 & 7) << 0)); // op2
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return _ReadStatusReg(pmccntr_el0);
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#else
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#else
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BLASULONG ret = 0;
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BLASULONG ret = 0;
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blasint shift;
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blasint shift;
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