loongarch64: Refine imin optimization.
This commit is contained in:
zhoupeng
Shiyou Yin
parent
8be2654193
commit
116aee7527
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@ -22,8 +22,8 @@ DMINKERNEL = min_lsx.S
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ISMAXKERNEL = imax_lsx.S
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IDMAXKERNEL = imax_lsx.S
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ISMINKERNEL = ismin_lsx.S
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IDMINKERNEL = idmin_lsx.S
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ISMINKERNEL = imin_lsx.S
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IDMINKERNEL = imin_lsx.S
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ISAMAXKERNEL = isamax_lsx.S
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IDAMAXKERNEL = idamax_lsx.S
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@ -22,8 +22,8 @@ DMINKERNEL = min_lsx.S
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ISMAXKERNEL = imax_lasx.S
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IDMAXKERNEL = imax_lasx.S
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ISMINKERNEL = ismin_lasx.S
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IDMINKERNEL = idmin_lasx.S
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ISMINKERNEL = imin_lasx.S
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IDMINKERNEL = imin_lasx.S
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ISAMAXKERNEL = isamax_lasx.S
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IDAMAXKERNEL = idamax_lasx.S
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@ -1,272 +0,0 @@
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#define ASSEMBLER
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#include "common.h"
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#define N $r4
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#define X $r5
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#define INCX $r6
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#define I $r12
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#define t1 $r13
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#define t2 $r15
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#define t3 $r18
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#define t4 $r16
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#define i0 $r17
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#define i1 $r14
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#define TEMP $r19
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#define x1 $xr9
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#define x2 $xr10
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#define x3 $xr11
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#define x4 $xr12
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#define VX0 $xr13
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#define VX1 $xr14
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#define VM0 $xr15
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#define VM1 $xr16
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#define VINC4 $xr17
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#define VINC8 $xr18
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#define VI0 $xr20
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#define VI1 $xr21
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#define VI2 $xr22
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#define VI3 $xr8
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#define VI4 $xr19
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#define VT0 $xr23
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PROLOGUE
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li.d i0, 0
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bge $r0, N, .L999
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bge $r0, INCX, .L999
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li.d TEMP, 1
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slli.d TEMP, TEMP, BASE_SHIFT
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slli.d INCX, INCX, BASE_SHIFT
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bne INCX, TEMP, .L20
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xvld VM0, X, 0
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addi.d i0, i0, 1
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srai.d I, N, 3
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bge $r0, I, .L21
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slli.d i0, i0, 2 //4
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xvreplgr2vr.d VINC4, i0
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slli.d i0, i0, 1 //8
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xvreplgr2vr.d VINC8, i0
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addi.d i0, i0, -15
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xvinsgr2vr.d VI1, i0, 0 //initialize the index value for vectorization
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addi.d i0, i0, 1
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xvinsgr2vr.d VI1, i0, 1
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addi.d i0, i0, 1
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xvinsgr2vr.d VI1, i0, 2
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addi.d i0, i0, 1
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xvinsgr2vr.d VI1, i0, 3
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addi.d i0, i0, 5
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xvinsgr2vr.d VI0, i0, 0 //1
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addi.d i0, i0, 1
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xvinsgr2vr.d VI0, i0, 1 //2
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addi.d i0, i0, 1
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xvinsgr2vr.d VI0, i0, 2 //3
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addi.d i0, i0, 1
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xvinsgr2vr.d VI0, i0, 3 //4
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.align 3
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.L10:
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xvld VX0, X, 0 * SIZE
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xvadd.d VI1, VI1, VINC8
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xvld VX1, X, 4 * SIZE
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xvadd.d VI2, VI1, VINC4
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xvfcmp.clt.d VT0, VX1, VX0
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addi.d I, I, -1
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xvbitsel.v VM1, VX0, VX1, VT0
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xvbitsel.v VI2, VI1, VI2, VT0
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xvfcmp.clt.d VT0, VM1, VM0
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addi.d X, X, 8 * SIZE
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xvbitsel.v VM0, VM0, VM1, VT0
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xvbitsel.v VI0, VI0, VI2, VT0
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blt $r0, I, .L10
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.align 3
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.L15:
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xvpickve.d VI1, VI0, 0
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xvpickve.d VI2, VI0, 1
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xvpickve.d VI3, VI0, 2
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xvpickve.d VI4, VI0, 3
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xvpickve.d x1, VM0, 0
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xvpickve.d x2, VM0, 1
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xvpickve.d x3, VM0, 2
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xvpickve.d x4, VM0, 3
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xvfcmp.clt.d VT0, x2, x1
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xvbitsel.v VM1, x1, x2, VT0
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xvbitsel.v VINC4, VI1, VI2, VT0
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xvfcmp.clt.d VT0, x4, x3
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xvbitsel.v VM0, x3, x4, VT0
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xvbitsel.v VINC8, VI3, VI4, VT0
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xvfcmp.clt.d VT0, VM1, VM0
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xvbitsel.v VM0, VM0, VM1, VT0
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xvbitsel.v VI0, VINC8, VINC4, VT0
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li.d TEMP, 1 //处理尾数相等时取最小序号
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movgr2fr.d $f17, TEMP
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ffint.d.l $f17, $f17
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xvfcmp.ceq.d VT0, VM0, x1
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fcmp.ceq.d $fcc0, $f23, $f17
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bceqz $fcc0, .L26
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xvfcmp.clt.d VT0, VI1, VI0
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xvbitsel.v VI0, VI0, VI1, VT0
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b .L26
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.align 3
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.L20: // INCX!=1
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move TEMP, X
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addi.d i0, i0, 1
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ld.d t1, TEMP, 0 * SIZE
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add.d TEMP, TEMP, INCX
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xvinsgr2vr.d VM0, t1, 0
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srai.d I, N, 3
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bge $r0, I, .L21
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ld.d t2, TEMP, 0 * SIZE
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add.d TEMP, TEMP, INCX
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ld.d t3, TEMP, 0 * SIZE
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add.d TEMP, TEMP, INCX
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ld.d t4, TEMP, 0 * SIZE
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add.d TEMP, TEMP, INCX
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xvinsgr2vr.d VM0, t2, 1
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xvinsgr2vr.d VM0, t3, 2
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xvinsgr2vr.d VM0, t4, 3
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slli.d i0, i0, 2 //4
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xvreplgr2vr.d VINC4, i0
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slli.d i0, i0, 1 //8
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xvreplgr2vr.d VINC8, i0
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addi.d i0, i0, -15
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xvinsgr2vr.d VI1, i0, 0 //initialize the index value for vectorization
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addi.d i0, i0, 1
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xvinsgr2vr.d VI1, i0, 1
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addi.d i0, i0, 1
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xvinsgr2vr.d VI1, i0, 2
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addi.d i0, i0, 1
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xvinsgr2vr.d VI1, i0, 3
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addi.d i0, i0, 5
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xvinsgr2vr.d VI0, i0, 0 //1
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addi.d i0, i0, 1
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xvinsgr2vr.d VI0, i0, 1 //2
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addi.d i0, i0, 1
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xvinsgr2vr.d VI0, i0, 2 //3
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addi.d i0, i0, 1
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xvinsgr2vr.d VI0, i0, 3 //4
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.align 3
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.L24:
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ld.d t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t2, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t3, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t4, X, 0 * SIZE
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add.d X, X, INCX
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xvinsgr2vr.d VX0, t1, 0
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xvinsgr2vr.d VX0, t2, 1
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xvinsgr2vr.d VX0, t3, 2
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xvinsgr2vr.d VX0, t4, 3
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xvadd.d VI1, VI1, VINC8
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ld.d t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t2, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t3, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t4, X, 0 * SIZE
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add.d X, X, INCX
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xvinsgr2vr.d VX1, t1, 0
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xvinsgr2vr.d VX1, t2, 1
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xvinsgr2vr.d VX1, t3, 2
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xvinsgr2vr.d VX1, t4, 3
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xvadd.d VI2, VI1, VINC4
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xvfcmp.clt.d VT0, VX1, VX0
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addi.d I, I, -1
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xvbitsel.v VM1, VX0, VX1, VT0
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xvbitsel.v VI2, VI1, VI2, VT0
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xvfcmp.clt.d VT0, VM1, VM0
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xvbitsel.v VM0, VM0, VM1, VT0
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xvbitsel.v VI0, VI0, VI2, VT0
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blt $r0, I, .L24
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.align 3
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.L25:
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xvpickve.d VI1, VI0, 0
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xvpickve.d VI2, VI0, 1
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xvpickve.d VI3, VI0, 2
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xvpickve.d VI4, VI0, 3
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xvpickve.d x1, VM0, 0
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xvpickve.d x2, VM0, 1
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xvpickve.d x3, VM0, 2
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xvpickve.d x4, VM0, 3
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xvfcmp.clt.d VT0, x2, x1
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xvbitsel.v VM1, x1, x2, VT0
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xvbitsel.v VINC4, VI1, VI2, VT0
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xvfcmp.clt.d VT0, x4, x3
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xvbitsel.v VM0, x3, x4, VT0
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xvbitsel.v VINC8, VI3, VI4, VT0
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xvfcmp.clt.d VT0, VM1, VM0
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xvbitsel.v VM0, VM0, VM1, VT0
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xvbitsel.v VI0, VINC8, VINC4, VT0
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li.d TEMP, 1 //处理尾数相等时取最小序号
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movgr2fr.d $f17, TEMP
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ffint.d.l $f17, $f17
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xvfcmp.ceq.d VT0, VM0, x1
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fcmp.ceq.d $fcc0, $f23, $f17
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bceqz $fcc0, .L26
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xvfcmp.clt.d VT0, VI1, VI0
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xvbitsel.v VI0, VI0, VI1, VT0
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.align 3
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.L26:
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xvfcmp.ceq.d VT0, VM0, x2
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fcmp.ceq.d $fcc0, $f23, $f17
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bceqz $fcc0, .L27
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xvfcmp.clt.d VT0, VI2, VI0
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xvbitsel.v VI0, VI0, VI2, VT0
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.align 3
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.L27:
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xvfcmp.ceq.d VT0, VM0, x3
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fcmp.ceq.d $fcc0, $f23, $f17
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bceqz $fcc0, .L28
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xvfcmp.clt.d VT0, VI3, VI0
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xvbitsel.v VI0, VI0, VI3, VT0
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.align 3
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.L28:
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xvfcmp.ceq.d VT0, VM0, x4
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fcmp.ceq.d $fcc0, $f23, $f17
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bceqz $fcc0, .L29
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xvfcmp.clt.d VT0, VI4, VI0
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xvbitsel.v VI0, VI0, VI4, VT0
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.align 3
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.L29:
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movfr2gr.d i0, $f20
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.align 3
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.L21: //N<8
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andi I, N, 7
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bge $r0, I, .L999
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srai.d i1, N, 3
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slli.d i1, i1, 3
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addi.d i1, i1, 1 //current index
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movgr2fr.d $f21, i1
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movgr2fr.d $f20, i0
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.align 3
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.L22:
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fld.d $f9, X, 0
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addi.d I, I, -1
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fcmp.clt.d $fcc0, $f9, $f15
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add.d X, X, INCX
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fsel $f15, $f15, $f9, $fcc0
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fsel $f20, $f20, $f21, $fcc0
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addi.d i1, i1, 1
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movgr2fr.d $f21, i1
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blt $r0, I, .L22
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movfr2gr.d i0, $f20
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.align 3
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.L999:
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move $r4, $r17
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jirl $r0, $r1, 0x0
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.align 3
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EPILOGUE
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@ -1,225 +0,0 @@
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#define ASSEMBLER
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#include "common.h"
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#define N $r4
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#define X $r5
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#define INCX $r6
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#define I $r12
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#define t1 $r13
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#define t2 $r15
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#define t3 $r18
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#define t4 $r16
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#define i0 $r17
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#define i1 $r14
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#define TEMP $r19
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#define x1 $vr9
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#define x2 $vr10
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#define x3 $vr11
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#define x4 $vr12
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#define VX0 $vr13
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#define VX1 $vr14
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#define VM0 $vr15
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#define VM1 $vr16
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#define VINC2 $vr17
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#define VINC4 $vr18
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#define VI0 $vr20
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#define VI1 $vr21
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#define VI2 $vr22
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#define VI3 $vr8
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#define VI4 $vr19
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#define VT0 $vr23
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PROLOGUE
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li.d i0, 0
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bge $r0, N, .L999
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bge $r0, INCX, .L999
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li.d TEMP, 1
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slli.d TEMP, TEMP, BASE_SHIFT
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slli.d INCX, INCX, BASE_SHIFT
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bne INCX, TEMP, .L20
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vld VM0, X, 0
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addi.d i0, i0, 1
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srai.d I, N, 3
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bge $r0, I, .L21
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slli.d i0, i0, 1 //2
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vreplgr2vr.d VINC2, i0
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slli.d i0, i0, 1 //4
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vreplgr2vr.d VINC4, i0
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addi.d i0, i0, -7
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vinsgr2vr.d VI1, i0, 0 //initialize the index value for vectorization
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addi.d i0, i0, 1
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vinsgr2vr.d VI1, i0, 1
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addi.d i0, i0, 3
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vinsgr2vr.d VI0, i0, 0 //1
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addi.d i0, i0, 1
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vinsgr2vr.d VI0, i0, 1 //2
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.align 3
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.L10:
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vld VX0, X, 0 * SIZE
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vadd.d VI1, VI1, VINC4
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vld VX1, X, 2 * SIZE
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vadd.d VI2, VI1, VINC2
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vfcmp.clt.d VT0, VX1, VX0
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vbitsel.v x1, VX0, VX1, VT0
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vbitsel.v x2, VI1, VI2, VT0
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vld VX0, X, 4 * SIZE
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vadd.d VI1, VI2, VINC2
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vld VX1, X, 6 * SIZE
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vadd.d VI2, VI1, VINC2
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vfcmp.clt.d VT0, VX1, VX0
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addi.d I, I, -1
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vbitsel.v x3, VX0, VX1, VT0
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vbitsel.v x4, VI1, VI2, VT0
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vfcmp.clt.d VT0, x3, x1
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addi.d X, X, 8 * SIZE
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vbitsel.v x1, x1, x3, VT0
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vbitsel.v x2, x2, x4, VT0
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vfcmp.clt.d VT0, x1, VM0
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vbitsel.v VM0, VM0, x1, VT0
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vbitsel.v VI0, VI0, x2, VT0
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blt $r0, I, .L10
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.align 3
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.L15:
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vreplvei.d VI1, VI0, 0
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vreplvei.d VI2, VI0, 1
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vreplvei.d x1, VM0, 0
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vreplvei.d x2, VM0, 1
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li.d TEMP, 1 //处理尾数相等时取最小序号
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movgr2fr.d $f17, TEMP
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ffint.d.l $f17, $f17
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vfcmp.ceq.d VT0, x2, x1
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fcmp.ceq.d $fcc0, $f23, $f17
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bceqz $fcc0, .L26
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vfcmp.clt.d VT0, VI1, VI0
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vbitsel.v VI0, VI0, VI1, VT0
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b .L27
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.align 3
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.L20: // INCX!=1
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move TEMP, X
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addi.d i0, i0, 1
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ld.d t1, TEMP, 0 * SIZE
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add.d TEMP, TEMP, INCX
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vinsgr2vr.d VM0, t1, 0
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srai.d I, N, 3
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bge $r0, I, .L21
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ld.d t2, TEMP, 0 * SIZE
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add.d TEMP, TEMP, INCX
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vinsgr2vr.d VM0, t2, 1
|
||||
slli.d i0, i0, 1 //2
|
||||
vreplgr2vr.d VINC2, i0
|
||||
slli.d i0, i0, 1 //4
|
||||
vreplgr2vr.d VINC4, i0
|
||||
addi.d i0, i0, -7
|
||||
vinsgr2vr.d VI1, i0, 0 //initialize the index value for vectorization
|
||||
addi.d i0, i0, 1
|
||||
vinsgr2vr.d VI1, i0, 1
|
||||
addi.d i0, i0, 3
|
||||
vinsgr2vr.d VI0, i0, 0 //1
|
||||
addi.d i0, i0, 1
|
||||
vinsgr2vr.d VI0, i0, 1 //2
|
||||
.align 3
|
||||
|
||||
.L24:
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX0, t1, 0
|
||||
vinsgr2vr.d VX0, t2, 1
|
||||
vadd.d VI1, VI1, VINC4
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX1, t1, 0
|
||||
vinsgr2vr.d VX1, t2, 1
|
||||
vadd.d VI2, VI1, VINC2
|
||||
vfcmp.clt.d VT0, VX1, VX0
|
||||
vbitsel.v x1, VX0, VX1, VT0
|
||||
vbitsel.v x2, VI1, VI2, VT0
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX0, t1, 0
|
||||
vinsgr2vr.d VX0, t2, 1
|
||||
vadd.d VI1, VI2, VINC2
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX1, t1, 0
|
||||
vinsgr2vr.d VX1, t2, 1
|
||||
vadd.d VI2, VI1, VINC2
|
||||
vfcmp.clt.d VT0, VX1, VX0
|
||||
vbitsel.v x3, VX0, VX1, VT0
|
||||
vbitsel.v x4, VI1, VI2, VT0
|
||||
vfcmp.clt.d VT0, x3, x1
|
||||
vbitsel.v x1, x1, x3, VT0
|
||||
vbitsel.v x2, x2, x4, VT0
|
||||
vfcmp.clt.d VT0, x1, VM0
|
||||
addi.d I, I, -1
|
||||
vbitsel.v VM0, VM0, x1, VT0
|
||||
vbitsel.v VI0, VI0, x2, VT0
|
||||
blt $r0, I, .L24
|
||||
.align 3
|
||||
|
||||
.L25:
|
||||
vreplvei.d VI1, VI0, 0
|
||||
vreplvei.d VI2, VI0, 1
|
||||
vreplvei.d x1, VM0, 0
|
||||
vreplvei.d x2, VM0, 1
|
||||
li.d TEMP, 1 //处理尾数相等时取最小序号
|
||||
movgr2fr.d $f17, TEMP
|
||||
ffint.d.l $f17, $f17
|
||||
vfcmp.ceq.d VT0, x2, x1
|
||||
fcmp.ceq.d $fcc0, $f23, $f17
|
||||
bceqz $fcc0, .L26
|
||||
vfcmp.clt.d VT0, VI1, VI0
|
||||
vbitsel.v VI0, VI0, VI1, VT0
|
||||
b .L27
|
||||
.align 3
|
||||
|
||||
.L26:
|
||||
vfcmp.clt.d VT0, x2, x1
|
||||
vbitsel.v VM0, x1, x2, VT0
|
||||
vbitsel.v VI0, VI1, VI2, VT0
|
||||
.align 3
|
||||
|
||||
.L27:
|
||||
movfr2gr.d i0, $f20
|
||||
.align 3
|
||||
|
||||
.L21: //N<8
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
srai.d i1, N, 3
|
||||
slli.d i1, i1, 3
|
||||
addi.d i1, i1, 1 //current index
|
||||
movgr2fr.d $f21, i1
|
||||
movgr2fr.d $f20, i0
|
||||
.align 3
|
||||
|
||||
.L22:
|
||||
fld.d $f9, X, 0
|
||||
addi.d I, I, -1
|
||||
fcmp.clt.d $fcc0, $f9, $f15
|
||||
add.d X, X, INCX
|
||||
fsel $f15, $f15, $f9, $fcc0
|
||||
fsel $f20, $f20, $f21, $fcc0
|
||||
addi.d i1, i1, 1
|
||||
movgr2fr.d $f21, i1
|
||||
blt $r0, I, .L22
|
||||
movfr2gr.d i0, $f20
|
||||
.align 3
|
||||
|
||||
.L999:
|
||||
move $r4, $r17
|
||||
jirl $r0, $r1, 0x0
|
||||
.align 3
|
||||
|
||||
EPILOGUE
|
||||
|
|
@ -1,3 +1,30 @@
|
|||
/***************************************************************************
|
||||
Copyright (c) 2023, The OpenBLAS Project
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
3. Neither the name of the OpenBLAS project nor the names of
|
||||
its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
|
||||
USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*****************************************************************************/
|
||||
|
||||
#define ASSEMBLER
|
||||
|
||||
#include "common.h"
|
||||
|
|
@ -39,6 +66,31 @@
|
|||
slli.d INCX, INCX, BASE_SHIFT
|
||||
bne INCX, TEMP, .L20
|
||||
xvld VM0, X, 0
|
||||
#ifdef DOUBLE
|
||||
addi.d i0, i0, 1
|
||||
srai.d I, N, 3
|
||||
bge $r0, I, .L21
|
||||
slli.d i0, i0, 2 //4
|
||||
xvreplgr2vr.d VINC4, i0
|
||||
slli.d i0, i0, 1 //8
|
||||
xvreplgr2vr.d VINC8, i0
|
||||
addi.d i0, i0, -15
|
||||
xvinsgr2vr.d VI1, i0, 0 //initialize the index value for vectorization
|
||||
addi.d i0, i0, 1
|
||||
xvinsgr2vr.d VI1, i0, 1
|
||||
addi.d i0, i0, 1
|
||||
xvinsgr2vr.d VI1, i0, 2
|
||||
addi.d i0, i0, 1
|
||||
xvinsgr2vr.d VI1, i0, 3
|
||||
addi.d i0, i0, 5
|
||||
xvinsgr2vr.d VI0, i0, 0 //1
|
||||
addi.d i0, i0, 1
|
||||
xvinsgr2vr.d VI0, i0, 1 //2
|
||||
addi.d i0, i0, 1
|
||||
xvinsgr2vr.d VI0, i0, 2 //3
|
||||
addi.d i0, i0, 1
|
||||
xvinsgr2vr.d VI0, i0, 3 //4
|
||||
#else
|
||||
addi.w i0, i0, 1
|
||||
srai.d I, N, 3
|
||||
bge $r0, I, .L21
|
||||
|
|
@ -76,20 +128,45 @@
|
|||
xvinsgr2vr.w VI0, i0, 6 //7
|
||||
addi.w i0, i0, 1
|
||||
xvinsgr2vr.w VI0, i0, 7 //8
|
||||
#endif
|
||||
.align 3
|
||||
|
||||
.L10:
|
||||
xvld VX0, X, 0 * SIZE
|
||||
#ifdef DOUBLE
|
||||
xvadd.d VI1, VI1, VINC8
|
||||
xvld VX1, X, 4 * SIZE
|
||||
xvadd.d VI2, VI1, VINC4
|
||||
XVCMPLT VT0, VX1, VX0
|
||||
addi.d I, I, -1
|
||||
xvbitsel.v VM1, VX0, VX1, VT0
|
||||
xvbitsel.v VI2, VI1, VI2, VT0
|
||||
XVCMPLT VT0, VM1, VM0
|
||||
addi.d X, X, 8 * SIZE
|
||||
xvbitsel.v VM0, VM0, VM1, VT0
|
||||
xvbitsel.v VI0, VI0, VI2, VT0
|
||||
#else
|
||||
xvadd.w VI1, VI1, VINC8
|
||||
xvfcmp.clt.s VT0, VX0, VM0
|
||||
XVCMPLT VT0, VX0, VM0
|
||||
addi.d I, I, -1
|
||||
xvbitsel.v VM0, VM0, VX0, VT0
|
||||
xvbitsel.v VI0, VI0, VI1, VT0
|
||||
addi.d X, X, 8 * SIZE
|
||||
#endif
|
||||
blt $r0, I, .L10
|
||||
.align 3
|
||||
|
||||
.L15:
|
||||
#ifdef DOUBLE
|
||||
xvpickve.d VI1, VI0, 0
|
||||
xvpickve.d VI2, VI0, 1
|
||||
xvpickve.d VI3, VI0, 2
|
||||
xvpickve.d VI4, VI0, 3
|
||||
xvpickve.d x1, VM0, 0
|
||||
xvpickve.d x2, VM0, 1
|
||||
xvpickve.d x3, VM0, 2
|
||||
xvpickve.d x4, VM0, 3
|
||||
#else
|
||||
xvxor.v VX0, VX0, VX0
|
||||
xvor.v VX0, VI0, VX0
|
||||
xvxor.v VX1, VX1, VX1
|
||||
|
|
@ -98,32 +175,67 @@
|
|||
xvpickve.w VI2, VI0, 1
|
||||
xvpickve.w VI3, VI0, 2
|
||||
xvpickve.w VI4, VI0, 3
|
||||
xvpickve.w x1, VM0, 0
|
||||
xvpickve.w x2, VM0, 1
|
||||
xvpickve.w x3, VM0, 2
|
||||
xvpickve.w x4, VM0, 3
|
||||
xvfcmp.clt.s VT0, x2, x1
|
||||
xvpickve.w x1, VM0, 0
|
||||
xvpickve.w x2, VM0, 1
|
||||
xvpickve.w x3, VM0, 2
|
||||
xvpickve.w x4, VM0, 3
|
||||
#endif
|
||||
XVCMPLT VT0, x2, x1
|
||||
xvbitsel.v VM1, x1, x2, VT0
|
||||
xvbitsel.v VINC4, VI1, VI2, VT0
|
||||
xvfcmp.clt.s VT0, x4, x3
|
||||
XVCMPLT VT0, x4, x3
|
||||
xvbitsel.v VM0, x3, x4, VT0
|
||||
xvbitsel.v VINC8, VI3, VI4, VT0
|
||||
xvfcmp.clt.s VT0, VM1, VM0
|
||||
XVCMPLT VT0, VM1, VM0
|
||||
xvbitsel.v VM0, VM0, VM1, VT0
|
||||
xvbitsel.v VI0, VINC8, VINC4, VT0
|
||||
li.d TEMP, 1 //处理尾数相等时取最小序号
|
||||
movgr2fr.w $f17, TEMP
|
||||
ffint.s.w $f17, $f17
|
||||
xvfcmp.ceq.s VT0, x1, VM0
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
fcmp.ceq.d $fcc0, $f15, $f9
|
||||
bceqz $fcc0, .L26
|
||||
xvfcmp.clt.s VT0, VI1, VI0
|
||||
XVCMPLT VT0, VI1, VI0
|
||||
xvbitsel.v VI0, VI0, VI1, VT0
|
||||
b .L26
|
||||
.align 3
|
||||
|
||||
.L20: // INCX!=1
|
||||
move TEMP, X
|
||||
#ifdef DOUBLE
|
||||
addi.d i0, i0, 1
|
||||
ld.d t1, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
xvinsgr2vr.d VM0, t1, 0
|
||||
srai.d I, N, 3
|
||||
bge $r0, I, .L21
|
||||
ld.d t2, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
ld.d t3, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
ld.d t4, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
xvinsgr2vr.d VM0, t1, 0
|
||||
xvinsgr2vr.d VM0, t2, 1
|
||||
xvinsgr2vr.d VM0, t3, 2
|
||||
xvinsgr2vr.d VM0, t4, 3
|
||||
slli.d i0, i0, 2 //4
|
||||
xvreplgr2vr.d VINC4, i0
|
||||
slli.d i0, i0, 1 //8
|
||||
xvreplgr2vr.d VINC8, i0
|
||||
addi.d i0, i0, -15
|
||||
xvinsgr2vr.d VI1, i0, 0 //initialize the index value for vectorization
|
||||
addi.d i0, i0, 1
|
||||
xvinsgr2vr.d VI1, i0, 1
|
||||
addi.d i0, i0, 1
|
||||
xvinsgr2vr.d VI1, i0, 2
|
||||
addi.d i0, i0, 1
|
||||
xvinsgr2vr.d VI1, i0, 3
|
||||
addi.d i0, i0, 5
|
||||
xvinsgr2vr.d VI0, i0, 0 //1
|
||||
addi.d i0, i0, 1
|
||||
xvinsgr2vr.d VI0, i0, 1 //2
|
||||
addi.d i0, i0, 1
|
||||
xvinsgr2vr.d VI0, i0, 2 //3
|
||||
addi.d i0, i0, 1
|
||||
xvinsgr2vr.d VI0, i0, 3 //4
|
||||
#else
|
||||
addi.w i0, i0, 1
|
||||
ld.w t1, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
|
|
@ -185,9 +297,46 @@
|
|||
xvinsgr2vr.w VI0, i0, 6 //7
|
||||
addi.w i0, i0, 1
|
||||
xvinsgr2vr.w VI0, i0, 7 //8
|
||||
#endif
|
||||
.align 3
|
||||
|
||||
.L24:
|
||||
#ifdef DOUBLE
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.d VX0, t1, 0
|
||||
xvinsgr2vr.d VX0, t2, 1
|
||||
xvinsgr2vr.d VX0, t3, 2
|
||||
xvinsgr2vr.d VX0, t4, 3
|
||||
xvadd.d VI1, VI1, VINC8
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.d VX1, t1, 0
|
||||
xvinsgr2vr.d VX1, t2, 1
|
||||
xvinsgr2vr.d VX1, t3, 2
|
||||
xvinsgr2vr.d VX1, t4, 3
|
||||
xvadd.d VI1, VI1, VINC8
|
||||
xvadd.d VI2, VI1, VINC4
|
||||
XVCMPLT VT0, VX1, VX0
|
||||
addi.d I, I, -1
|
||||
xvbitsel.v VM1, VX0, VX1, VT0
|
||||
xvbitsel.v VI2, VI1, VI2, VT0
|
||||
XVCMPLT VT0, VM1, VM0
|
||||
xvbitsel.v VM0, VM0, VM1, VT0
|
||||
xvbitsel.v VI0, VI0, VI2, VT0
|
||||
#else
|
||||
ld.w t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t2, X, 0 * SIZE
|
||||
|
|
@ -213,73 +362,83 @@
|
|||
xvinsgr2vr.w VX0, t3, 6
|
||||
xvinsgr2vr.w VX0, t4, 7
|
||||
xvadd.w VI1, VI1, VINC8
|
||||
xvfcmp.clt.s VT0, VX0, VM0
|
||||
XVCMPLT VT0, VX0, VM0
|
||||
addi.d I, I, -1
|
||||
xvbitsel.v VM0, VM0, VX0, VT0
|
||||
xvbitsel.v VI0, VI0, VI1, VT0
|
||||
#endif
|
||||
blt $r0, I, .L24
|
||||
.align 3
|
||||
|
||||
.L25:
|
||||
#ifdef DOUBLE
|
||||
xvpickve.d VI1, VI0, 0
|
||||
xvpickve.d VI2, VI0, 1
|
||||
xvpickve.d VI3, VI0, 2
|
||||
xvpickve.d VI4, VI0, 3
|
||||
xvpickve.d x1, VM0, 0
|
||||
xvpickve.d x2, VM0, 1
|
||||
xvpickve.d x3, VM0, 2
|
||||
xvpickve.d x4, VM0, 3
|
||||
#else
|
||||
xvxor.v VX0, VX0, VX0
|
||||
xvor.v VX0, VI0, VX0
|
||||
xvor.v VX0, VI0, VX0
|
||||
xvxor.v VX1, VX1, VX1
|
||||
xvor.v VX1, VM0, VX1
|
||||
xvor.v VX1, VM0, VX1
|
||||
xvpickve.w VI1, VI0, 0
|
||||
xvpickve.w VI2, VI0, 1
|
||||
xvpickve.w VI3, VI0, 2
|
||||
xvpickve.w VI4, VI0, 3
|
||||
xvpickve.w x1, VM0, 0
|
||||
xvpickve.w x2, VM0, 1
|
||||
xvpickve.w x3, VM0, 2
|
||||
xvpickve.w x4, VM0, 3
|
||||
xvfcmp.clt.s VT0, x2, x1
|
||||
xvpickve.w x1, VM0, 0
|
||||
xvpickve.w x2, VM0, 1
|
||||
xvpickve.w x3, VM0, 2
|
||||
xvpickve.w x4, VM0, 3
|
||||
#endif
|
||||
XVCMPLT VT0, x2, x1
|
||||
xvbitsel.v VM1, x1, x2, VT0
|
||||
xvbitsel.v VINC4, VI1, VI2, VT0
|
||||
xvfcmp.clt.s VT0, x4, x3
|
||||
XVCMPLT VT0, x4, x3
|
||||
xvbitsel.v VM0, x3, x4, VT0
|
||||
xvbitsel.v VINC8, VI3, VI4, VT0
|
||||
xvfcmp.clt.s VT0, VM1, VM0
|
||||
XVCMPLT VT0, VM1, VM0
|
||||
xvbitsel.v VM0, VM0, VM1, VT0
|
||||
xvbitsel.v VI0, VINC8, VINC4, VT0
|
||||
li.d TEMP, 1 //处理尾数相等时取最小序号
|
||||
movgr2fr.w $f17, TEMP
|
||||
ffint.s.w $f17, $f17
|
||||
xvfcmp.ceq.s VT0, VM0, x1
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
fcmp.ceq.d $fcc0, $f15, $f9
|
||||
bceqz $fcc0, .L26
|
||||
xvfcmp.clt.s VT0, VI1, VI0
|
||||
XVCMPLT VT0, VI1, VI0
|
||||
xvbitsel.v VI0, VI0, VI1, VT0
|
||||
.align 3
|
||||
|
||||
.L26:
|
||||
xvfcmp.ceq.s VT0, VM0, x2
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
fcmp.ceq.d $fcc0, $f15, $f10
|
||||
bceqz $fcc0, .L27
|
||||
xvfcmp.clt.s VT0, VI2, VI0
|
||||
XVCMPLT VT0, VI2, VI0
|
||||
xvbitsel.v VI0, VI0, VI2, VT0
|
||||
.align 3
|
||||
|
||||
.L27:
|
||||
xvfcmp.ceq.s VT0, VM0, x3
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
fcmp.ceq.d $fcc0, $f15, $f11
|
||||
bceqz $fcc0, .L28
|
||||
xvfcmp.clt.s VT0, VI3, VI0
|
||||
XVCMPLT VT0, VI3, VI0
|
||||
xvbitsel.v VI0, VI0, VI3, VT0
|
||||
.align 3
|
||||
|
||||
.L28:
|
||||
xvfcmp.ceq.s VT0, VM0, x4
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
fcmp.ceq.d $fcc0, $f15, $f12
|
||||
bceqz $fcc0, .L29
|
||||
xvfcmp.clt.s VT0, VI4, VI0
|
||||
XVCMPLT VT0, VI4, VI0
|
||||
xvbitsel.v VI0, VI0, VI4, VT0
|
||||
.align 3
|
||||
|
||||
.L29:
|
||||
#ifdef DOUBLE
|
||||
MTG i0, $f20
|
||||
#else
|
||||
fmov.s $f16, $f20
|
||||
#endif
|
||||
.align 3
|
||||
|
||||
#ifndef DOUBLE
|
||||
.L252:
|
||||
xvxor.v VI0, VI0, VI0
|
||||
xvor.v VI0, VI0, VX0
|
||||
|
|
@ -294,13 +453,13 @@
|
|||
xvpickve.w x2, VM0, 5
|
||||
xvpickve.w x3, VM0, 6
|
||||
xvpickve.w x4, VM0, 7
|
||||
xvfcmp.clt.s VT0, x2, x1
|
||||
XVCMPLT VT0, x2, x1
|
||||
xvbitsel.v x1, x1, x2, VT0
|
||||
xvbitsel.v VINC4, VI1, VI2, VT0
|
||||
xvfcmp.clt.s VT0, x4, x3
|
||||
XVCMPLT VT0, x4, x3
|
||||
xvbitsel.v VM0, x3, x4, VT0
|
||||
xvbitsel.v VINC8, VI3, VI4, VT0
|
||||
xvfcmp.clt.s VT0, x1, VM0
|
||||
XVCMPLT VT0, x1, VM0
|
||||
xvbitsel.v VM0, VM0, x1, VT0
|
||||
xvbitsel.v VI0, VINC8, VINC4, VT0
|
||||
li.d TEMP, 1 //处理尾数相等时取最小序号
|
||||
|
|
@ -309,7 +468,7 @@
|
|||
xvfcmp.ceq.s VT0, VM0, x1
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
bceqz $fcc0, .L262
|
||||
xvfcmp.clt.s VT0, VI1, VI0
|
||||
XVCMPLT VT0, VI1, VI0
|
||||
xvbitsel.v VI0, VI0, VI1, VT0
|
||||
.align 3
|
||||
|
||||
|
|
@ -317,7 +476,7 @@
|
|||
xvfcmp.ceq.s VT0, VM0, x2
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
bceqz $fcc0, .L272
|
||||
xvfcmp.clt.s VT0, VI2, VI0
|
||||
XVCMPLT VT0, VI2, VI0
|
||||
xvbitsel.v VI0, VI0, VI2, VT0
|
||||
.align 3
|
||||
|
||||
|
|
@ -325,7 +484,7 @@
|
|||
xvfcmp.ceq.s VT0, VM0, x3
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
bceqz $fcc0, .L282
|
||||
xvfcmp.clt.s VT0, VI3, VI0
|
||||
XVCMPLT VT0, VI3, VI0
|
||||
xvbitsel.v VI0, VI0, VI3, VT0
|
||||
.align 3
|
||||
|
||||
|
|
@ -333,17 +492,18 @@
|
|||
xvfcmp.ceq.s VT0, VM0, x4
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
bceqz $fcc0, .L292
|
||||
xvfcmp.clt.s VT0, VI4, VI0
|
||||
XVCMPLT VT0, VI4, VI0
|
||||
xvbitsel.v VI0, VI0, VI4, VT0
|
||||
.align 3
|
||||
|
||||
.L292:
|
||||
fcmp.clt.s $fcc0, $f13, $f15
|
||||
CMPLT $fcc0, $f13, $f15
|
||||
fsel $f15, $f15, $f13, $fcc0
|
||||
fsel $f20, $f20, $f16, $fcc0
|
||||
movfr2gr.s i0, $f20
|
||||
MTG i0, $f20
|
||||
#endif
|
||||
|
||||
.L21: //N<8
|
||||
.L21: //N<8
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
srai.d i1, N, 3
|
||||
|
|
@ -356,14 +516,14 @@
|
|||
.L22:
|
||||
fld.d $f9, X, 0
|
||||
addi.d I, I, -1
|
||||
fcmp.clt.s $fcc0, $f9, $f15
|
||||
CMPLT $fcc0, $f9, $f15
|
||||
add.d X, X, INCX
|
||||
fsel $f15, $f15, $f9, $fcc0
|
||||
fsel $f20, $f20, $f21, $fcc0
|
||||
addi.d i1, i1, 1
|
||||
movgr2fr.d $f21, i1
|
||||
add.d X, X, INCX
|
||||
blt $r0, I, .L22
|
||||
movfr2gr.s i0, $f20
|
||||
MTG i0, $f20
|
||||
.align 3
|
||||
|
||||
.L999:
|
||||
|
|
@ -371,4 +531,4 @@
|
|||
jirl $r0, $r1, 0x0
|
||||
.align 3
|
||||
|
||||
EPILOGUE
|
||||
EPILOGUE
|
||||
|
|
@ -0,0 +1,428 @@
|
|||
/***************************************************************************
|
||||
Copyright (c) 2023, The OpenBLAS Project
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
3. Neither the name of the OpenBLAS project nor the names of
|
||||
its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
|
||||
USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*****************************************************************************/
|
||||
|
||||
#define ASSEMBLER
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define N $r4
|
||||
#define X $r5
|
||||
#define INCX $r6
|
||||
#define I $r12
|
||||
#define t1 $r13
|
||||
#define t2 $r15
|
||||
#define t3 $r18
|
||||
#define t4 $r16
|
||||
#define i0 $r17
|
||||
#define i1 $r14
|
||||
#define TEMP $r19
|
||||
#define x1 $vr9
|
||||
#define x2 $vr10
|
||||
#define x3 $vr11
|
||||
#define x4 $vr12
|
||||
#define VX0 $vr13
|
||||
#define VX1 $vr14
|
||||
#define VM0 $vr15
|
||||
#define VM1 $vr16
|
||||
#define VI0 $vr20
|
||||
#define VI1 $vr21
|
||||
#define VI2 $vr22
|
||||
#define VI3 $vr8
|
||||
#define VI4 $vr19
|
||||
#define VT0 $vr23
|
||||
|
||||
PROLOGUE
|
||||
li.d i0, 0
|
||||
bge $r0, N, .L999
|
||||
bge $r0, INCX, .L999
|
||||
li.d TEMP, 1
|
||||
slli.d TEMP, TEMP, BASE_SHIFT
|
||||
slli.d INCX, INCX, BASE_SHIFT
|
||||
bne INCX, TEMP, .L20
|
||||
vld VM0, X, 0
|
||||
#ifdef DOUBLE
|
||||
addi.d i0, i0, 1
|
||||
srai.d I, N, 3
|
||||
bge $r0, I, .L21
|
||||
slli.d i0, i0, 1 //2
|
||||
vreplgr2vr.d $vr17, i0
|
||||
slli.d i0, i0, 1 //4
|
||||
vreplgr2vr.d $vr18, i0
|
||||
addi.d i0, i0, -7
|
||||
vinsgr2vr.d VI1, i0, 0 //initialize the index value for vectorization
|
||||
addi.d i0, i0, 1
|
||||
vinsgr2vr.d VI1, i0, 1
|
||||
addi.d i0, i0, 3
|
||||
vinsgr2vr.d VI0, i0, 0 //1
|
||||
addi.d i0, i0, 1
|
||||
vinsgr2vr.d VI0, i0, 1 //2
|
||||
#else
|
||||
addi.w i0, i0, 1
|
||||
srai.d I, N, 3
|
||||
bge $r0, I, .L21
|
||||
slli.w i0, i0, 2 //4
|
||||
vreplgr2vr.w $vr17, i0
|
||||
slli.w i0, i0, 1 //8
|
||||
vreplgr2vr.w $vr18, i0
|
||||
addi.w i0, i0, -15
|
||||
vinsgr2vr.w VI1, i0, 0 //initialize the index value for vectorization
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI1, i0, 1
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI1, i0, 2
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI1, i0, 3
|
||||
addi.w i0, i0, 5
|
||||
vinsgr2vr.w VI0, i0, 0 //1
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI0, i0, 1 //2
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI0, i0, 2 //3
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI0, i0, 3 //4
|
||||
#endif
|
||||
.align 3
|
||||
|
||||
.L10:
|
||||
vld VX0, X, 0 * SIZE
|
||||
#ifdef DOUBLE
|
||||
vadd.d VI1, VI1, $vr18
|
||||
vld VX1, X, 2 * SIZE
|
||||
vadd.d VI2, VI1, $vr17
|
||||
VCMPLT VT0, VX1, VX0
|
||||
vbitsel.v x1, VX0, VX1, VT0
|
||||
vbitsel.v x2, VI1, VI2, VT0
|
||||
vld VX0, X, 4 * SIZE
|
||||
vadd.d VI1, VI2, $vr17
|
||||
vld VX1, X, 6 * SIZE
|
||||
vadd.d VI2, VI1, $vr17
|
||||
VCMPLT VT0, VX1, VX0
|
||||
addi.d I, I, -1
|
||||
vbitsel.v x3, VX0, VX1, VT0
|
||||
vbitsel.v x4, VI1, VI2, VT0
|
||||
VCMPLT VT0, x3, x1
|
||||
addi.d X, X, 8 * SIZE
|
||||
vbitsel.v x1, x1, x3, VT0
|
||||
vbitsel.v x2, x2, x4, VT0
|
||||
VCMPLT VT0, x1, VM0
|
||||
vbitsel.v VM0, VM0, x1, VT0
|
||||
vbitsel.v VI0, VI0, x2, VT0
|
||||
#else
|
||||
vadd.w VI1, VI1, $vr18
|
||||
vld VX1, X, 4 * SIZE
|
||||
vadd.w VI2, VI1, $vr17
|
||||
VCMPLT VT0, VX1, VX0
|
||||
addi.d I, I, -1
|
||||
vbitsel.v VM1, VX0, VX1, VT0
|
||||
vbitsel.v VI2, VI1, VI2, VT0
|
||||
VCMPLT VT0, VM1, VM0
|
||||
addi.d X, X, 8 * SIZE
|
||||
vbitsel.v VM0, VM0, VM1, VT0
|
||||
vbitsel.v VI0, VI0, VI2, VT0
|
||||
#endif
|
||||
blt $r0, I, .L10
|
||||
.align 3
|
||||
|
||||
.L15:
|
||||
#ifdef DOUBLE
|
||||
vreplvei.d VI1, VI0, 0
|
||||
vreplvei.d VI2, VI0, 1
|
||||
vreplvei.d x1, VM0, 0
|
||||
vreplvei.d x2, VM0, 1
|
||||
fcmp.ceq.d $fcc0, $f10, $f9
|
||||
bceqz $fcc0, .L26
|
||||
VCMPLT VT0, VI1, VI2
|
||||
vbitsel.v VI0, VI2, VI1, VT0
|
||||
b .L27
|
||||
#else
|
||||
vreplvei.w VI1, VI0, 0
|
||||
vreplvei.w VI2, VI0, 1
|
||||
vreplvei.w VI3, VI0, 2
|
||||
vreplvei.w VI4, VI0, 3
|
||||
vreplvei.w x1, VM0, 0
|
||||
vreplvei.w x2, VM0, 1
|
||||
vreplvei.w x3, VM0, 2
|
||||
vreplvei.w x4, VM0, 3
|
||||
VCMPLT VT0, x2, x1
|
||||
vbitsel.v VM1, x1, x2, VT0
|
||||
vbitsel.v $vr17, VI1, VI2, VT0
|
||||
VCMPLT VT0, x4, x3
|
||||
vbitsel.v VM0, x3, x4, VT0
|
||||
vbitsel.v $vr18, VI3, VI4, VT0
|
||||
VCMPLT VT0, VM1, VM0
|
||||
vbitsel.v VM0, VM0, VM1, VT0
|
||||
vbitsel.v VI0, $vr18, $vr17, VT0
|
||||
fcmp.ceq.d $fcc0, $f15, $f9
|
||||
bceqz $fcc0, .L26
|
||||
VCMPLT VT0, VI1, VI0
|
||||
vbitsel.v VI0, VI0, VI1, VT0
|
||||
b .L26
|
||||
#endif
|
||||
.align 3
|
||||
|
||||
.L20: // INCX!=1
|
||||
move TEMP, X
|
||||
#ifdef DOUBLE
|
||||
addi.d i0, i0, 1
|
||||
ld.d t1, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
vinsgr2vr.d VM0, t1, 0
|
||||
srai.d I, N, 3
|
||||
bge $r0, I, .L21
|
||||
ld.d t2, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
vinsgr2vr.d VM0, t2, 1
|
||||
slli.d i0, i0, 1 //2
|
||||
vreplgr2vr.d $vr17, i0
|
||||
slli.d i0, i0, 1 //4
|
||||
vreplgr2vr.d $vr18, i0
|
||||
addi.d i0, i0, -7
|
||||
vinsgr2vr.d VI1, i0, 0 //initialize the index value for vectorization
|
||||
addi.d i0, i0, 1
|
||||
vinsgr2vr.d VI1, i0, 1
|
||||
addi.d i0, i0, 3
|
||||
vinsgr2vr.d VI0, i0, 0 //1
|
||||
addi.d i0, i0, 1
|
||||
vinsgr2vr.d VI0, i0, 1 //2
|
||||
#else
|
||||
addi.w i0, i0, 1
|
||||
ld.w t1, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
vinsgr2vr.w VM0, t1, 0
|
||||
srai.d I, N, 3
|
||||
bge $r0, I, .L21
|
||||
ld.w t2, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
ld.w t3, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
ld.w t4, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
vinsgr2vr.w VM0, t2, 1
|
||||
vinsgr2vr.w VM0, t3, 2
|
||||
vinsgr2vr.w VM0, t4, 3
|
||||
slli.w i0, i0, 2 //4
|
||||
vreplgr2vr.w $vr17, i0
|
||||
slli.w i0, i0, 1 //8
|
||||
vreplgr2vr.w $vr18, i0
|
||||
addi.w i0, i0, -15
|
||||
vinsgr2vr.w VI1, i0, 0 //initialize the index value for vectorization
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI1, i0, 1
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI1, i0, 2
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI1, i0, 3
|
||||
addi.w i0, i0, 5
|
||||
vinsgr2vr.w VI0, i0, 0 //1
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI0, i0, 1 //2
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI0, i0, 2 //3
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI0, i0, 3 //4
|
||||
#endif
|
||||
.align 3
|
||||
|
||||
.L24:
|
||||
#ifdef DOUBLE
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX0, t1, 0
|
||||
vinsgr2vr.d VX0, t2, 1
|
||||
vadd.d VI1, VI1, $vr18
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX1, t1, 0
|
||||
vinsgr2vr.d VX1, t2, 1
|
||||
vadd.d VI2, VI1, $vr17
|
||||
VCMPLT VT0, VX1, VX0
|
||||
vbitsel.v x1, VX0, VX1, VT0
|
||||
vbitsel.v x2, VI1, VI2, VT0
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX0, t1, 0
|
||||
vinsgr2vr.d VX0, t2, 1
|
||||
vadd.d VI1, VI2, $vr17
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX1, t1, 0
|
||||
vinsgr2vr.d VX1, t2, 1
|
||||
vadd.d VI2, VI1, $vr17
|
||||
VCMPLT VT0, VX1, VX0
|
||||
vbitsel.v x3, VX0, VX1, VT0
|
||||
vbitsel.v x4, VI1, VI2, VT0
|
||||
VCMPLT VT0, x3, x1
|
||||
vbitsel.v x1, x1, x3, VT0
|
||||
vbitsel.v x2, x2, x4, VT0
|
||||
VCMPLT VT0, x1, VM0
|
||||
addi.d I, I, -1
|
||||
vbitsel.v VM0, VM0, x1, VT0
|
||||
vbitsel.v VI0, VI0, x2, VT0
|
||||
#else
|
||||
ld.w t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.w VX0, t1, 0
|
||||
vinsgr2vr.w VX0, t2, 1
|
||||
vinsgr2vr.w VX0, t3, 2
|
||||
vinsgr2vr.w VX0, t4, 3
|
||||
vadd.w VI1, VI1, $vr18
|
||||
ld.w t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.w VX1, t1, 0
|
||||
vinsgr2vr.w VX1, t2, 1
|
||||
vinsgr2vr.w VX1, t3, 2
|
||||
vinsgr2vr.w VX1, t4, 3
|
||||
vadd.w VI2, VI1, $vr17
|
||||
VCMPLT VT0, VX1, VX0
|
||||
addi.d I, I, -1
|
||||
vbitsel.v VM1, VX0, VX1, VT0
|
||||
vbitsel.v VI2, VI1, VI2, VT0
|
||||
VCMPLT VT0, VM1, VM0
|
||||
vbitsel.v VM0, VM0, VM1, VT0
|
||||
vbitsel.v VI0, VI0, VI2, VT0
|
||||
#endif
|
||||
blt $r0, I, .L24
|
||||
.align 3
|
||||
|
||||
.L25:
|
||||
#ifdef DOUBLE
|
||||
vreplvei.d VI1, VI0, 0
|
||||
vreplvei.d VI2, VI0, 1
|
||||
vreplvei.d x1, VM0, 0
|
||||
vreplvei.d x2, VM0, 1
|
||||
fcmp.ceq.d $fcc0, $f10, $f9
|
||||
bceqz $fcc0, .L26
|
||||
VCMPLT VT0, VI1, VI2
|
||||
vbitsel.v VI0, VI2, VI1, VT0
|
||||
b .L27
|
||||
#else
|
||||
vreplvei.w VI1, VI0, 0
|
||||
vreplvei.w VI2, VI0, 1
|
||||
vreplvei.w VI3, VI0, 2
|
||||
vreplvei.w VI4, VI0, 3
|
||||
vreplvei.w x1, VM0, 0
|
||||
vreplvei.w x2, VM0, 1
|
||||
vreplvei.w x3, VM0, 2
|
||||
vreplvei.w x4, VM0, 3
|
||||
VCMPLT VT0, x2, x1
|
||||
vbitsel.v VM1, x1, x2, VT0
|
||||
vbitsel.v $vr17, VI1, VI2, VT0
|
||||
VCMPLT VT0, x4, x3
|
||||
vbitsel.v VM0, x3, x4, VT0
|
||||
vbitsel.v $vr18, VI3, VI4, VT0
|
||||
VCMPLT VT0, VM1, VM0
|
||||
vbitsel.v VM0, VM0, VM1, VT0
|
||||
vbitsel.v VI0, $vr18, $vr17, VT0
|
||||
fcmp.ceq.d $fcc0, $f15, $f9
|
||||
bceqz $fcc0, .L26
|
||||
VCMPLT VT0, VI1, VI0
|
||||
vbitsel.v VI0, VI0, VI1, VT0
|
||||
#endif
|
||||
.align 3
|
||||
|
||||
.L26:
|
||||
#ifdef DOUBLE
|
||||
VCMPLT VT0, x2, x1
|
||||
vbitsel.v VM0, x1, x2, VT0
|
||||
vbitsel.v VI0, VI1, VI2, VT0
|
||||
#else
|
||||
fcmp.ceq.d $fcc0, $f15, $f10
|
||||
bceqz $fcc0, .L27
|
||||
VCMPLT VT0, VI2, VI0
|
||||
vbitsel.v VI0, VI0, VI2, VT0
|
||||
#endif
|
||||
.align 3
|
||||
|
||||
.L27:
|
||||
#ifndef DOUBLE
|
||||
fcmp.ceq.d $fcc0, $f15, $f11
|
||||
bceqz $fcc0, .L28
|
||||
VCMPLT VT0, VI3, VI0
|
||||
vbitsel.v VI0, VI0, VI3, VT0
|
||||
.align 3
|
||||
|
||||
.L28:
|
||||
fcmp.ceq.d $fcc0, $f15, $f12
|
||||
bceqz $fcc0, .L29
|
||||
VCMPLT VT0, VI4, VI0
|
||||
vbitsel.v VI0, VI0, VI4, VT0
|
||||
.align 3
|
||||
|
||||
.L29:
|
||||
#endif
|
||||
MTG i0, $f20
|
||||
.align 3
|
||||
|
||||
.L21: //N<8
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
srai.d i1, N, 3
|
||||
slli.d i1, i1, 3
|
||||
addi.d i1, i1, 1 //current index
|
||||
movgr2fr.d $f21, i1
|
||||
movgr2fr.d $f20, i0
|
||||
.align 3
|
||||
|
||||
.L22:
|
||||
fld.d $f9, X, 0
|
||||
addi.d I, I, -1
|
||||
CMPLT $fcc0, $f9, $f15
|
||||
add.d X, X, INCX
|
||||
fsel $f15, $f15, $f9, $fcc0
|
||||
fsel $f20, $f20, $f21, $fcc0
|
||||
addi.d i1, i1, 1
|
||||
movgr2fr.d $f21, i1
|
||||
blt $r0, I, .L22
|
||||
MTG i0, $f20
|
||||
.align 3
|
||||
|
||||
.L999:
|
||||
move $r4, $r17
|
||||
jirl $r0, $r1, 0x0
|
||||
.align 3
|
||||
|
||||
EPILOGUE
|
||||
|
|
@ -1,271 +0,0 @@
|
|||
#define ASSEMBLER
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define N $r4
|
||||
#define X $r5
|
||||
#define INCX $r6
|
||||
#define I $r12
|
||||
#define t1 $r13
|
||||
#define t2 $r15
|
||||
#define t3 $r18
|
||||
#define t4 $r16
|
||||
#define i0 $r17
|
||||
#define i1 $r14
|
||||
#define TEMP $r19
|
||||
#define x1 $vr9
|
||||
#define x2 $vr10
|
||||
#define x3 $vr11
|
||||
#define x4 $vr12
|
||||
#define VX0 $vr13
|
||||
#define VX1 $vr14
|
||||
#define VM0 $vr15
|
||||
#define VM1 $vr16
|
||||
#define VINC4 $vr17
|
||||
#define VINC8 $vr18
|
||||
#define VI0 $vr20
|
||||
#define VI1 $vr21
|
||||
#define VI2 $vr22
|
||||
#define VI3 $vr8
|
||||
#define VI4 $vr19
|
||||
#define VT0 $vr23
|
||||
|
||||
PROLOGUE
|
||||
li.d i0, 0
|
||||
bge $r0, N, .L999
|
||||
bge $r0, INCX, .L999
|
||||
li.d TEMP, 1
|
||||
slli.d TEMP, TEMP, BASE_SHIFT
|
||||
slli.d INCX, INCX, BASE_SHIFT
|
||||
bne INCX, TEMP, .L20
|
||||
vld VM0, X, 0
|
||||
addi.w i0, i0, 1
|
||||
srai.d I, N, 3
|
||||
bge $r0, I, .L21
|
||||
slli.w i0, i0, 2 //4
|
||||
vreplgr2vr.w VINC4, i0
|
||||
slli.w i0, i0, 1 //8
|
||||
vreplgr2vr.w VINC8, i0
|
||||
addi.w i0, i0, -15
|
||||
vinsgr2vr.w VI1, i0, 0 //initialize the index value for vectorization
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI1, i0, 1
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI1, i0, 2
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI1, i0, 3
|
||||
addi.w i0, i0, 5
|
||||
vinsgr2vr.w VI0, i0, 0 //1
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI0, i0, 1 //2
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI0, i0, 2 //3
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI0, i0, 3 //4
|
||||
.align 3
|
||||
|
||||
.L10:
|
||||
vld VX0, X, 0 * SIZE
|
||||
vadd.w VI1, VI1, VINC8
|
||||
vld VX1, X, 4 * SIZE
|
||||
vadd.w VI2, VI1, VINC4
|
||||
vfcmp.clt.s VT0, VX1, VX0
|
||||
addi.d I, I, -1
|
||||
vbitsel.v VM1, VX0, VX1, VT0
|
||||
vbitsel.v VI2, VI1, VI2, VT0
|
||||
vfcmp.clt.s VT0, VM1, VM0
|
||||
addi.d X, X, 8 * SIZE
|
||||
vbitsel.v VM0, VM0, VM1, VT0
|
||||
vbitsel.v VI0, VI0, VI2, VT0
|
||||
blt $r0, I, .L10
|
||||
.align 3
|
||||
|
||||
.L15:
|
||||
vreplvei.w VI1, VI0, 0
|
||||
vreplvei.w VI2, VI0, 1
|
||||
vreplvei.w VI3, VI0, 2
|
||||
vreplvei.w VI4, VI0, 3
|
||||
vreplvei.w x1, VM0, 0
|
||||
vreplvei.w x2, VM0, 1
|
||||
vreplvei.w x3, VM0, 2
|
||||
vreplvei.w x4, VM0, 3
|
||||
vfcmp.clt.s VT0, x2, x1
|
||||
vbitsel.v VM1, x1, x2, VT0
|
||||
vbitsel.v VINC4, VI1, VI2, VT0
|
||||
vfcmp.clt.s VT0, x4, x3
|
||||
vbitsel.v VM0, x3, x4, VT0
|
||||
vbitsel.v VINC8, VI3, VI4, VT0
|
||||
vfcmp.clt.s VT0, VM1, VM0
|
||||
vbitsel.v VM0, VM0, VM1, VT0
|
||||
vbitsel.v VI0, VINC8, VINC4, VT0
|
||||
li.d TEMP, 1 //处理尾数相等时取最小序号
|
||||
movgr2fr.w $f17, TEMP
|
||||
ffint.s.w $f17, $f17
|
||||
vfcmp.ceq.s VT0, x1, VM0
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
bceqz $fcc0, .L26
|
||||
vfcmp.clt.s VT0, VI1, VI0
|
||||
vbitsel.v VI0, VI0, VI1, VT0
|
||||
b .L26
|
||||
.align 3
|
||||
|
||||
.L20: // INCX!=1
|
||||
move TEMP, X
|
||||
addi.w i0, i0, 1
|
||||
ld.w t1, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
vinsgr2vr.w VM0, t1, 0
|
||||
srai.d I, N, 3
|
||||
bge $r0, I, .L21
|
||||
ld.w t2, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
ld.w t3, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
ld.w t4, TEMP, 0 * SIZE
|
||||
add.d TEMP, TEMP, INCX
|
||||
vinsgr2vr.w VM0, t2, 1
|
||||
vinsgr2vr.w VM0, t3, 2
|
||||
vinsgr2vr.w VM0, t4, 3
|
||||
slli.w i0, i0, 2 //4
|
||||
vreplgr2vr.w VINC4, i0
|
||||
slli.w i0, i0, 1 //8
|
||||
vreplgr2vr.w VINC8, i0
|
||||
addi.w i0, i0, -15
|
||||
vinsgr2vr.w VI1, i0, 0 //initialize the index value for vectorization
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI1, i0, 1
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI1, i0, 2
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI1, i0, 3
|
||||
addi.w i0, i0, 5
|
||||
vinsgr2vr.w VI0, i0, 0 //1
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI0, i0, 1 //2
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI0, i0, 2 //3
|
||||
addi.w i0, i0, 1
|
||||
vinsgr2vr.w VI0, i0, 3 //4
|
||||
.align 3
|
||||
|
||||
.L24:
|
||||
ld.w t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.w VX0, t1, 0
|
||||
vinsgr2vr.w VX0, t2, 1
|
||||
vinsgr2vr.w VX0, t3, 2
|
||||
vinsgr2vr.w VX0, t4, 3
|
||||
vadd.w VI1, VI1, VINC8
|
||||
ld.w t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.w VX1, t1, 0
|
||||
vinsgr2vr.w VX1, t2, 1
|
||||
vinsgr2vr.w VX1, t3, 2
|
||||
vinsgr2vr.w VX1, t4, 3
|
||||
vadd.w VI2, VI1, VINC4
|
||||
vfcmp.clt.s VT0, VX1, VX0
|
||||
addi.d I, I, -1
|
||||
vbitsel.v VM1, VX0, VX1, VT0
|
||||
vbitsel.v VI2, VI1, VI2, VT0
|
||||
vfcmp.clt.s VT0, VM1, VM0
|
||||
vbitsel.v VM0, VM0, VM1, VT0
|
||||
vbitsel.v VI0, VI0, VI2, VT0
|
||||
blt $r0, I, .L24
|
||||
.align 3
|
||||
|
||||
.L25:
|
||||
vreplvei.w VI1, VI0, 0
|
||||
vreplvei.w VI2, VI0, 1
|
||||
vreplvei.w VI3, VI0, 2
|
||||
vreplvei.w VI4, VI0, 3
|
||||
vreplvei.w x1, VM0, 0
|
||||
vreplvei.w x2, VM0, 1
|
||||
vreplvei.w x3, VM0, 2
|
||||
vreplvei.w x4, VM0, 3
|
||||
vfcmp.clt.s VT0, x2, x1
|
||||
vbitsel.v VM1, x1, x2, VT0
|
||||
vbitsel.v VINC4, VI1, VI2, VT0
|
||||
vfcmp.clt.s VT0, x4, x3
|
||||
vbitsel.v VM0, x3, x4, VT0
|
||||
vbitsel.v VINC8, VI3, VI4, VT0
|
||||
vfcmp.clt.s VT0, VM1, VM0
|
||||
vbitsel.v VM0, VM0, VM1, VT0
|
||||
vbitsel.v VI0, VINC8, VINC4, VT0
|
||||
li.d TEMP, 1 //处理尾数相等时取最小序号
|
||||
movgr2fr.w $f17, TEMP
|
||||
ffint.s.w $f17, $f17
|
||||
vfcmp.ceq.s VT0, x1, VM0
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
bceqz $fcc0, .L26
|
||||
vfcmp.clt.s VT0, VI1, VI0
|
||||
vbitsel.v VI0, VI0, VI1, VT0
|
||||
.align 3
|
||||
|
||||
.L26:
|
||||
vfcmp.ceq.s VT0, x2, VM0
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
bceqz $fcc0, .L27
|
||||
vfcmp.clt.s VT0, VI2, VI0
|
||||
vbitsel.v VI0, VI0, VI2, VT0
|
||||
.align 3
|
||||
|
||||
.L27:
|
||||
vfcmp.ceq.s VT0, x3, VM0
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
bceqz $fcc0, .L28
|
||||
vfcmp.clt.s VT0, VI3, VI0
|
||||
vbitsel.v VI0, VI0, VI3, VT0
|
||||
.align 3
|
||||
|
||||
.L28:
|
||||
vfcmp.ceq.s VT0, x4, VM0
|
||||
fcmp.ceq.s $fcc0, $f23, $f17
|
||||
bceqz $fcc0, .L29
|
||||
vfcmp.clt.s VT0, VI4, VI0
|
||||
vbitsel.v VI0, VI0, VI4, VT0
|
||||
.align 3
|
||||
|
||||
.L29:
|
||||
movfr2gr.s i0, $f20
|
||||
|
||||
.L21: //N<8
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
srai.d i1, N, 3
|
||||
slli.d i1, i1, 3
|
||||
addi.d i1, i1, 1 //current index
|
||||
movgr2fr.d $f21, i1
|
||||
movgr2fr.d $f20, i0
|
||||
.align 3
|
||||
|
||||
.L22:
|
||||
fld.d $f9, X, 0
|
||||
fcmp.clt.s $fcc0, $f9, $f15
|
||||
fsel $f15, $f15, $f9, $fcc0
|
||||
fsel $f20, $f20, $f21, $fcc0
|
||||
addi.d I, I, -1
|
||||
addi.d i1, i1, 1
|
||||
add.d X, X, INCX
|
||||
movgr2fr.d $f21, i1
|
||||
blt $r0, I, .L22
|
||||
movfr2gr.s i0, $f20
|
||||
.align 3
|
||||
|
||||
.L999:
|
||||
move $r4, $r17
|
||||
jirl $r0, $r1, 0x0
|
||||
.align 3
|
||||
|
||||
EPILOGUE
|
||||
Loading…
Reference in New Issue