loongarch64: Add and Refine asum optimization functions.
This commit is contained in:
Hao Chen
Shiyou Yin
parent
e771be185e
commit
06fd5b5995
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@ -49,8 +49,10 @@ DAXPBYKERNEL = daxpby_lsx.S
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SSUMKERNEL = sum_lsx.S
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DSUMKERNEL = sum_lsx.S
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SASUMKERNEL = sasum_lsx.S
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DASUMKERNEL = dasum_lsx.S
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SASUMKERNEL = asum_lsx.S
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DASUMKERNEL = asum_lsx.S
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CASUMKERNEL = casum_lsx.S
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ZASUMKERNEL = casum_lsx.S
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SROTKERNEL = rot_lsx.S
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DROTKERNEL = rot_lsx.S
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@ -49,8 +49,10 @@ DAXPBYKERNEL = daxpby_lasx.S
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SSUMKERNEL = sum_lasx.S
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DSUMKERNEL = sum_lasx.S
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SASUMKERNEL = sasum_lasx.S
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DASUMKERNEL = dasum_lasx.S
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SASUMKERNEL = asum_lasx.S
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DASUMKERNEL = asum_lasx.S
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CASUMKERNEL = casum_lasx.S
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ZASUMKERNEL = casum_lasx.S
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SROTKERNEL = rot_lasx.S
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DROTKERNEL = rot_lasx.S
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@ -0,0 +1,257 @@
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/***************************************************************************
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Copyright (c) 2023, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
|
||||
met:
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||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
3. Neither the name of the OpenBLAS project nor the names of
|
||||
its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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||||
USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define N $r4
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#define X $r5
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#define INCX $r6
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#define I $r17
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#define TEMP $r18
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#define t1 $r15
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#define t2 $r12
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#define t3 $r13
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#define t4 $r14
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#define VX0 $xr12
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#define VX1 $xr13
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#define VX2 $xr14
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#define VX3 $xr15
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#define VT0 $xr23
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#define VT1 $xr22
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#define res1 $xr16
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#define res2 $xr17
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#define res0 $xr18
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#define neg1 $xr19
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PROLOGUE
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xvxor.v res1, res1, res1
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xvxor.v res2, res2, res2
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xvxor.v res0, res0, res0
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bge $r0, N, .L999
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bge $r0, INCX, .L999
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#ifdef DOUBLE
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li.d t1, -1
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xvreplgr2vr.d neg1, t1
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xvffint.d.l neg1, neg1
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#else
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li.w t1, -1
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xvreplgr2vr.w neg1, t1
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xvffint.s.w neg1, neg1
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#endif
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li.d TEMP, SIZE
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slli.d INCX, INCX, BASE_SHIFT
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srai.d I, N, 3
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bne INCX, TEMP, .L20
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bge $r0, I, .L13
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.align 3
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.L11:
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#ifdef DOUBLE
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xvld VX0, X, 0 * SIZE
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xvld VX1, X, 4 * SIZE
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xvfmul.d VX2, neg1, VX0
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xvfmul.d VX3, neg1, VX1
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xvfcmp.clt.d VT0, VX0, res0
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xvfcmp.clt.d VT1, VX1, res0
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xvbitsel.v VX0, VX0, VX2, VT0
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xvbitsel.v VX1, VX1, VX3, VT1
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xvfadd.d res2, VX0, VX1
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xvfadd.d res1, res1, res2
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#else
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xvld VX0, X, 0 * SIZE
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xvfmul.s VX2, neg1, VX0
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xvfcmp.clt.s VT0, VX0, res0
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xvbitsel.v VX0, VX0, VX2, VT0
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xvfadd.s res1, VX0, res1
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#endif
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addi.d X, X, 8 * SIZE
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addi.d I, I, -1
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blt $r0, I, .L11
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.align 3
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.L12:
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#ifdef DOUBLE
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xvpickve.d VX1, res1, 1
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xvpickve.d VX2, res1, 2
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xvpickve.d VX3, res1, 3
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xvfadd.d res1, VX1, res1
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xvfadd.d res1, VX2, res1
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xvfadd.d res1, VX3, res1
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#else
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xvfadd.s res2, res1, res2
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xvpickve.w VX1, res1, 1
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xvpickve.w VX2, res1, 2
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xvpickve.w VX3, res1, 3
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xvfadd.s res1, VX1, res1
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xvfadd.s res1, VX2, res1
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xvfadd.s res1, VX3, res1
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xvpickve.w VX0, res2, 4
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xvpickve.w VX1, res2, 5
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xvpickve.w VX2, res2, 6
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xvpickve.w VX3, res2, 7
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xvfadd.s res1, VX0, res1
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xvfadd.s res1, VX1, res1
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xvfadd.s res1, VX2, res1
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xvfadd.s res1, VX2, res1
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#endif
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.align 3
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.L13:
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andi I, N, 7
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bge $r0, I, .L999
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.align 3
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.L14:
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LD $f12, X, 0 * SIZE
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FABS $f12, $f12
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ADD $f16, $f12, $f16
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addi.d I, I, -1
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addi.d X, X, SIZE
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blt $r0, I, .L14
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b .L999
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.align 3
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.L20:
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bge $r0, I, .L23
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.align 3
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.L21:
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#ifdef DOUBLE
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ld.d t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t2, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t3, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t4, X, 0 * SIZE
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add.d X, X, INCX
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xvinsgr2vr.d VX0, t1, 0
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xvinsgr2vr.d VX0, t2, 1
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xvinsgr2vr.d VX0, t3, 2
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xvinsgr2vr.d VX0, t4, 3
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ld.d t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t2, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t3, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t4, X, 0 * SIZE
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add.d X, X, INCX
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xvinsgr2vr.d VX1, t1, 0
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xvinsgr2vr.d VX1, t2, 1
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xvinsgr2vr.d VX1, t3, 2
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xvinsgr2vr.d VX1, t4, 3
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xvfmul.d VX2, neg1, VX0
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xvfmul.d VX3, neg1, VX1
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xvfcmp.clt.d VT0, VX0, res0
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xvfcmp.clt.d VT1, VX1, res0
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xvbitsel.v VX0, VX0, VX2, VT0
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xvbitsel.v VX1, VX1, VX3, VT1
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xvfadd.d res2, VX0, VX1
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xvfadd.d res1, res1, res2
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#else
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ld.w t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.w t2, X, 0 * SIZE
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add.d X, X, INCX
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ld.w t3, X, 0 * SIZE
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add.d X, X, INCX
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ld.w t4, X, 0 * SIZE
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add.d X, X, INCX
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xvinsgr2vr.w VX0, t1, 0
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xvinsgr2vr.w VX0, t2, 1
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xvinsgr2vr.w VX0, t3, 2
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xvinsgr2vr.w VX0, t4, 3
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ld.w t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.w t2, X, 0 * SIZE
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add.d X, X, INCX
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ld.w t3, X, 0 * SIZE
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add.d X, X, INCX
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ld.w t4, X, 0 * SIZE
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add.d X, X, INCX
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xvinsgr2vr.w VX0, t1, 4
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xvinsgr2vr.w VX0, t2, 5
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xvinsgr2vr.w VX0, t3, 6
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xvinsgr2vr.w VX0, t4, 7
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xvfmul.s VX2, neg1, VX0
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xvfcmp.clt.s VT0, VX0, res0
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xvbitsel.v VX0, VX0, VX2, VT0
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xvfadd.s res1, VX0, res1
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#endif
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addi.d I, I, -1
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blt $r0, I, .L21
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.align 3
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.L22:
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#ifdef DOUBLE
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xvpickve.d VX1, res1, 1
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xvpickve.d VX2, res1, 2
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xvpickve.d VX3, res1, 3
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xvfadd.d res1, VX1, res1
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xvfadd.d res1, VX2, res1
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xvfadd.d res1, VX3, res1
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#else
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xvfadd.s res2, res1, res2
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xvpickve.w VX1, res1, 1
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xvpickve.w VX2, res1, 2
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xvpickve.w VX3, res1, 3
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xvfadd.s res1, VX1, res1
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xvfadd.s res1, VX2, res1
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xvfadd.s res1, VX3, res1
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xvpickve.w VX0, res2, 4
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xvpickve.w VX1, res2, 5
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xvpickve.w VX2, res2, 6
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xvpickve.w VX3, res2, 7
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xvfadd.s res1, VX0, res1
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xvfadd.s res1, VX1, res1
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xvfadd.s res1, VX2, res1
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xvfadd.s res1, VX2, res1
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#endif
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.align 3
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.L23:
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andi I, N, 7
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bge $r0, I, .L999
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.align 3
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.L24:
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LD $f12, X, 0 * SIZE
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FABS $f12, $f12
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ADD $f16, $f12, $f16
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addi.d I, I, -1
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add.d X, X, INCX
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blt $r0, I, .L24
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.align 3
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.L999:
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MOV $f0, $f16
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jirl $r0, $r1, 0x0
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.align 3
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EPILOGUE
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@ -0,0 +1,258 @@
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/***************************************************************************
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Copyright (c) 2023, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
3. Neither the name of the OpenBLAS project nor the names of
|
||||
its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
|
||||
USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
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*****************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define N $r4
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#define X $r5
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#define INCX $r6
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#define I $r17
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#define TEMP $r18
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#define t1 $r15
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#define t2 $r12
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#define t3 $r13
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#define t4 $r14
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#define VX0 $vr12
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#define VX1 $vr13
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#define VX2 $vr14
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#define VX3 $vr15
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#define VT0 $vr23
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#define VT1 $vr22
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#define res1 $vr16
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#define res2 $vr17
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#define res0 $vr18
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#define neg1 $vr19
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PROLOGUE
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vxor.v res1, res1, res1
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vxor.v res2, res2, res2
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vxor.v res0, res0, res0
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bge $r0, N, .L999
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bge $r0, INCX, .L999
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#ifdef DOUBLE
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li.d t1, -1
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vreplgr2vr.d neg1, t1
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vffint.d.l neg1, neg1
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#else
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li.w t1, -1
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vreplgr2vr.w neg1, t1
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vffint.s.w neg1, neg1
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#endif
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li.d TEMP, SIZE
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slli.d INCX, INCX, BASE_SHIFT
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srai.d I, N, 3
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bne INCX, TEMP, .L20
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bge $r0, I, .L13
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.align 3
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.L11:
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#ifdef DOUBLE
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vld VX0, X, 0 * SIZE
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vld VX1, X, 2 * SIZE
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vfmul.d VX2, neg1, VX0
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vfmul.d VX3, neg1, VX1
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vfcmp.clt.d VT0, VX0, res0
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vfcmp.clt.d VT1, VX1, res0
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vbitsel.v VX0, VX0, VX2, VT0
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vbitsel.v VX1, VX1, VX3, VT1
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vfadd.d res2, VX0, VX1
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vfadd.d res1, res1, res2
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vld VX0, X, 4 * SIZE
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vld VX1, X, 6 * SIZE
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vfmul.d VX2, neg1, VX0
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vfmul.d VX3, neg1, VX1
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vfcmp.clt.d VT0, VX0, res0
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vfcmp.clt.d VT1, VX1, res0
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vbitsel.v VX0, VX0, VX2, VT0
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vbitsel.v VX1, VX1, VX3, VT1
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vfadd.d res2, VX0, VX1
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vfadd.d res1, res1, res2
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#else
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vld VX0, X, 0 * SIZE
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vld VX1, X, 4 * SIZE
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vfmul.s VX2, neg1, VX0
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vfmul.s VX3, neg1, VX1
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vfcmp.clt.s VT0, VX0, res0
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vfcmp.clt.s VT1, VX1, res0
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vbitsel.v VX0, VX0, VX2, VT0
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vbitsel.v VX1, VX1, VX3, VT1
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vfadd.s res2, VX0, VX1
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vfadd.s res1, res1, res2
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#endif
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addi.d X, X, 8 * SIZE
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addi.d I, I, -1
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blt $r0, I, .L11
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.align 3
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.L12:
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#ifdef DOUBLE
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vreplvei.d VX1, res1, 1
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vfadd.d res1, VX1, res1
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#else
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vreplvei.w VX1, res1, 1
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vreplvei.w VX2, res1, 2
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vreplvei.w VX3, res1, 3
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vfadd.s res1, VX1, res1
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vfadd.s res1, VX2, res1
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vfadd.s res1, VX3, res1
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#endif
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.align 3
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.L13:
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andi I, N, 7
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bge $r0, I, .L999
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.align 3
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.L14:
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LD $f12, X, 0 * SIZE
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FABS $f12, $f12
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ADD $f16, $f12, $f16
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addi.d I, I, -1
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addi.d X, X, SIZE
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blt $r0, I, .L14
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b .L999
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.align 3
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.L20:
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bge $r0, I, .L23
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.align 3
|
||||
|
||||
.L21:
|
||||
#ifdef DOUBLE
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX0, t1, 0
|
||||
vinsgr2vr.d VX0, t2, 1
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
vinsgr2vr.d VX1, t1, 0
|
||||
vinsgr2vr.d VX1, t2, 1
|
||||
add.d X, X, INCX
|
||||
vfmul.d VX2, neg1, VX0
|
||||
vfmul.d VX3, neg1, VX1
|
||||
vfcmp.clt.d VT0, VX0, res0
|
||||
vfcmp.clt.d VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.d res2, VX0, VX1
|
||||
vfadd.d res1, res1, res2
|
||||
ld.d t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX0, t3, 0
|
||||
vinsgr2vr.d VX0, t4, 1
|
||||
ld.d t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t4, X, 0 * SIZE
|
||||
vinsgr2vr.d VX1, t3, 0
|
||||
vinsgr2vr.d VX1, t4, 1
|
||||
add.d X, X, INCX
|
||||
vfmul.d VX2, neg1, VX0
|
||||
vfmul.d VX3, neg1, VX1
|
||||
vfcmp.clt.d VT0, VX0, res0
|
||||
vfcmp.clt.d VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.d res2, VX0, VX1
|
||||
vfadd.d res1, res1, res2
|
||||
#else
|
||||
ld.w t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.w VX0, t1, 0
|
||||
vinsgr2vr.w VX0, t2, 1
|
||||
vinsgr2vr.w VX0, t3, 2
|
||||
vinsgr2vr.w VX0, t4, 3
|
||||
ld.w t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.w VX1, t1, 0
|
||||
vinsgr2vr.w VX1, t2, 1
|
||||
vinsgr2vr.w VX1, t3, 2
|
||||
vinsgr2vr.w VX1, t4, 3
|
||||
vfmul.s VX2, neg1, VX0
|
||||
vfmul.s VX3, neg1, VX1
|
||||
vfcmp.clt.s VT0, VX0, res0
|
||||
vfcmp.clt.s VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.s res2, VX0, VX1
|
||||
vfadd.s res1, res1, res2
|
||||
#endif
|
||||
addi.d I, I, -1
|
||||
blt $r0, I, .L21
|
||||
.align 3
|
||||
|
||||
.L22:
|
||||
#ifdef DOUBLE
|
||||
vreplvei.d VX1, res1, 1
|
||||
vfadd.d res1, VX1, res1
|
||||
#else
|
||||
vreplvei.w VX1, res1, 1
|
||||
vreplvei.w VX2, res1, 2
|
||||
vreplvei.w VX3, res1, 3
|
||||
vfadd.s res1, VX1, res1
|
||||
vfadd.s res1, VX2, res1
|
||||
vfadd.s res1, VX3, res1
|
||||
#endif
|
||||
.align 3
|
||||
|
||||
.L23:
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
.align 3
|
||||
|
||||
.L24:
|
||||
LD $f12, X, 0 * SIZE
|
||||
FABS $f12, $f12
|
||||
ADD $f16, $f12, $f16
|
||||
addi.d I, I, -1
|
||||
add.d X, X, INCX
|
||||
blt $r0, I, .L24
|
||||
.align 3
|
||||
|
||||
.L999:
|
||||
MOV $f0, $f16
|
||||
jirl $r0, $r1, 0x0
|
||||
.align 3
|
||||
|
||||
EPILOGUE
|
||||
|
|
@ -0,0 +1,329 @@
|
|||
/***************************************************************************
|
||||
Copyright (c) 2023, The OpenBLAS Project
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
3. Neither the name of the OpenBLAS project nor the names of
|
||||
its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
|
||||
USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*****************************************************************************/
|
||||
|
||||
#define ASSEMBLER
|
||||
#include "common.h"
|
||||
|
||||
#define N $r4
|
||||
#define X $r5
|
||||
#define INCX $r6
|
||||
#define I $r17
|
||||
#define TEMP $r18
|
||||
#define t1 $r15
|
||||
#define t2 $r12
|
||||
#define t3 $r13
|
||||
#define t4 $r14
|
||||
#define a1 $f12
|
||||
#define a2 $f13
|
||||
#define a3 $f14
|
||||
#define a4 $f15
|
||||
#define s1 $f16
|
||||
#define VX0 $xr12
|
||||
#define VX1 $xr13
|
||||
#define VX2 $xr14
|
||||
#define VX3 $xr15
|
||||
#define res1 $xr16
|
||||
#define res2 $xr17
|
||||
#define res3 $xr18
|
||||
#define res0 $xr19
|
||||
#define neg1 $xr20
|
||||
#define VT0 $xr21
|
||||
#define VT1 $xr22
|
||||
|
||||
PROLOGUE
|
||||
xvxor.v res1, res1, res1
|
||||
xvxor.v res2, res2, res2
|
||||
xvxor.v res0, res0, res0
|
||||
bge $r0, N, .L999
|
||||
bge $r0, INCX, .L999
|
||||
#ifdef DOUBLE
|
||||
li.d t1, -1
|
||||
xvreplgr2vr.d neg1, t1
|
||||
xvffint.d.l neg1, neg1
|
||||
#else
|
||||
li.w t1, -1
|
||||
xvreplgr2vr.w neg1, t1
|
||||
xvffint.s.w neg1, neg1
|
||||
#endif
|
||||
li.d TEMP, 1
|
||||
slli.d TEMP, TEMP, ZBASE_SHIFT
|
||||
slli.d INCX, INCX, ZBASE_SHIFT
|
||||
srai.d I, N, 3
|
||||
bne INCX, TEMP, .L20
|
||||
bge $r0, I, .L13
|
||||
.align 3
|
||||
|
||||
.L11:
|
||||
#ifdef DOUBLE
|
||||
xvld VX0, X, 0 * SIZE
|
||||
xvld VX1, X, 4 * SIZE
|
||||
xvfmul.d VX2, neg1, VX0
|
||||
xvfmul.d VX3, neg1, VX1
|
||||
xvfcmp.clt.d VT0, VX0, res0
|
||||
xvfcmp.clt.d VT1, VX1, res0
|
||||
xvbitsel.v VX0, VX0, VX2, VT0
|
||||
xvbitsel.v VX1, VX1, VX3, VT1
|
||||
xvfadd.d res2, VX0, VX1
|
||||
xvfadd.d res1, res1, res2
|
||||
xvld VX2, X, 8 * SIZE
|
||||
xvld VX3, X, 12 * SIZE
|
||||
xvfmul.d VX0, neg1, VX2
|
||||
xvfmul.d VX1, neg1, VX3
|
||||
xvfcmp.clt.d VT0, VX2, res0
|
||||
xvfcmp.clt.d VT1, VX3, res0
|
||||
xvbitsel.v VX2, VX2, VX0, VT0
|
||||
xvbitsel.v VX3, VX3, VX1, VT1
|
||||
xvfadd.d res2, VX2, VX3
|
||||
xvfadd.d res1, res1, res2
|
||||
#else
|
||||
xvld VX0, X, 0 * SIZE
|
||||
xvld VX1, X, 8 * SIZE
|
||||
xvfmul.s VX2, neg1, VX0
|
||||
xvfmul.s VX3, neg1, VX1
|
||||
xvfcmp.clt.s VT0, VX0, res0
|
||||
xvfcmp.clt.s VT1, VX1, res0
|
||||
xvbitsel.v VX0, VX0, VX2, VT0
|
||||
xvbitsel.v VX1, VX1, VX3, VT1
|
||||
xvfadd.s res2, VX0, VX1
|
||||
xvfadd.s res1, res2, res1
|
||||
#endif
|
||||
addi.d X, X, 16 * SIZE
|
||||
addi.d I, I, -1
|
||||
blt $r0, I, .L11
|
||||
.align 3
|
||||
|
||||
.L12:
|
||||
#ifdef DOUBLE
|
||||
xvpickve.d VX1, res1, 1
|
||||
xvpickve.d VX2, res1, 2
|
||||
xvpickve.d VX3, res1, 3
|
||||
xvfadd.d res1, VX1, res1
|
||||
xvfadd.d res1, VX2, res1
|
||||
xvfadd.d res1, VX3, res1
|
||||
#else
|
||||
xvfadd.s res2, res1, res2
|
||||
xvpickve.w VX1, res1, 1
|
||||
xvpickve.w VX2, res1, 2
|
||||
xvpickve.w VX3, res1, 3
|
||||
xvfadd.s res1, VX1, res1
|
||||
xvfadd.s res1, VX2, res1
|
||||
xvfadd.s res1, VX3, res1
|
||||
xvpickve.w VX0, res2, 4
|
||||
xvpickve.w VX1, res2, 5
|
||||
xvpickve.w VX2, res2, 6
|
||||
xvpickve.w VX3, res2, 7
|
||||
xvfadd.s res1, VX0, res1
|
||||
xvfadd.s res1, VX1, res1
|
||||
xvfadd.s res1, VX2, res1
|
||||
xvfadd.s res1, VX2, res1
|
||||
#endif
|
||||
.align 3
|
||||
|
||||
.L13:
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
.align 3
|
||||
|
||||
.L14:
|
||||
LD a1, X, 0 * SIZE
|
||||
LD a2, X, 1 * SIZE
|
||||
FABS a1, a1
|
||||
FABS a2, a2
|
||||
addi.d I, I, -1
|
||||
ADD a1, a1, a2
|
||||
ADD s1, a1, s1
|
||||
addi.d X, X, 2 * SIZE
|
||||
blt $r0, I, .L14
|
||||
b .L999
|
||||
.align 3
|
||||
|
||||
.L20:
|
||||
bge $r0, I, .L23
|
||||
.align 3
|
||||
|
||||
.L21:
|
||||
#ifdef DOUBLE
|
||||
ld.d t1, X, 0 * SIZE
|
||||
ld.d t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t3, X, 0 * SIZE
|
||||
ld.d t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.d VX0, t1, 0
|
||||
xvinsgr2vr.d VX0, t2, 1
|
||||
xvinsgr2vr.d VX0, t3, 2
|
||||
xvinsgr2vr.d VX0, t4, 3
|
||||
ld.d t1, X, 0 * SIZE
|
||||
ld.d t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t3, X, 0 * SIZE
|
||||
ld.d t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.d VX1, t1, 0
|
||||
xvinsgr2vr.d VX1, t2, 1
|
||||
xvinsgr2vr.d VX1, t3, 2
|
||||
xvinsgr2vr.d VX1, t4, 3
|
||||
xvfmul.d VX2, neg1, VX0
|
||||
xvfmul.d VX3, neg1, VX1
|
||||
xvfcmp.clt.d VT0, VX0, res0
|
||||
xvfcmp.clt.d VT1, VX1, res0
|
||||
xvbitsel.v VX0, VX0, VX2, VT0
|
||||
xvbitsel.v VX1, VX1, VX3, VT1
|
||||
xvfadd.d res2, VX0, VX1
|
||||
xvfadd.d res1, res1, res2
|
||||
ld.d t1, X, 0 * SIZE
|
||||
ld.d t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t3, X, 0 * SIZE
|
||||
ld.d t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.d VX0, t1, 0
|
||||
xvinsgr2vr.d VX0, t2, 1
|
||||
xvinsgr2vr.d VX0, t3, 2
|
||||
xvinsgr2vr.d VX0, t4, 3
|
||||
ld.d t1, X, 0 * SIZE
|
||||
ld.d t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t3, X, 0 * SIZE
|
||||
ld.d t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.d VX1, t1, 0
|
||||
xvinsgr2vr.d VX1, t2, 1
|
||||
xvinsgr2vr.d VX1, t3, 2
|
||||
xvinsgr2vr.d VX1, t4, 3
|
||||
xvfmul.d VX2, neg1, VX0
|
||||
xvfmul.d VX3, neg1, VX1
|
||||
xvfcmp.clt.d VT0, VX0, res0
|
||||
xvfcmp.clt.d VT1, VX1, res0
|
||||
xvbitsel.v VX0, VX0, VX2, VT0
|
||||
xvbitsel.v VX1, VX1, VX3, VT1
|
||||
xvfadd.d res2, VX0, VX1
|
||||
xvfadd.d res1, res1, res2
|
||||
#else
|
||||
ld.w t1, X, 0 * SIZE
|
||||
ld.w t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
ld.w t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.w VX0, t1, 0
|
||||
xvinsgr2vr.w VX0, t2, 1
|
||||
xvinsgr2vr.w VX0, t3, 2
|
||||
xvinsgr2vr.w VX0, t4, 3
|
||||
ld.w t1, X, 0 * SIZE
|
||||
ld.w t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
ld.w t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.w VX0, t1, 4
|
||||
xvinsgr2vr.w VX0, t2, 5
|
||||
xvinsgr2vr.w VX0, t3, 6
|
||||
xvinsgr2vr.w VX0, t4, 7
|
||||
ld.w t1, X, 0 * SIZE
|
||||
ld.w t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
ld.w t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.w VX1, t1, 0
|
||||
xvinsgr2vr.w VX1, t2, 1
|
||||
xvinsgr2vr.w VX1, t3, 2
|
||||
xvinsgr2vr.w VX1, t4, 3
|
||||
ld.w t1, X, 0 * SIZE
|
||||
ld.w t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
ld.w t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.w VX1, t1, 4
|
||||
xvinsgr2vr.w VX1, t2, 5
|
||||
xvinsgr2vr.w VX1, t3, 6
|
||||
xvinsgr2vr.w VX1, t4, 7
|
||||
xvfmul.s VX2, neg1, VX0
|
||||
xvfmul.s VX3, neg1, VX1
|
||||
xvfcmp.clt.s VT0, VX0, res0
|
||||
xvfcmp.clt.s VT1, VX1, res0
|
||||
xvbitsel.v VX0, VX0, VX2, VT0
|
||||
xvbitsel.v VX1, VX1, VX3, VT1
|
||||
xvfadd.s res2, VX0, VX1
|
||||
xvfadd.s res1, res2, res1
|
||||
#endif
|
||||
addi.d I, I, -1
|
||||
blt $r0, I, .L21
|
||||
.align 3
|
||||
|
||||
.L22:
|
||||
#ifdef DOUBLE
|
||||
xvpickve.d VX1, res1, 1
|
||||
xvpickve.d VX2, res1, 2
|
||||
xvpickve.d VX3, res1, 3
|
||||
xvfadd.d res1, VX1, res1
|
||||
xvfadd.d res1, VX2, res1
|
||||
xvfadd.d res1, VX3, res1
|
||||
#else
|
||||
xvfadd.s res2, res1, res2
|
||||
xvpickve.w VX1, res1, 1
|
||||
xvpickve.w VX2, res1, 2
|
||||
xvpickve.w VX3, res1, 3
|
||||
xvfadd.s res1, VX1, res1
|
||||
xvfadd.s res1, VX2, res1
|
||||
xvfadd.s res1, VX3, res1
|
||||
xvpickve.w VX0, res2, 4
|
||||
xvpickve.w VX1, res2, 5
|
||||
xvpickve.w VX2, res2, 6
|
||||
xvpickve.w VX3, res2, 7
|
||||
xvfadd.s res1, VX0, res1
|
||||
xvfadd.s res1, VX1, res1
|
||||
xvfadd.s res1, VX2, res1
|
||||
xvfadd.s res1, VX2, res1
|
||||
#endif
|
||||
.align 3
|
||||
|
||||
.L23:
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
.align 3
|
||||
|
||||
.L24:
|
||||
LD a1, X, 0 * SIZE
|
||||
LD a2, X, 1 * SIZE
|
||||
FABS a1, a1
|
||||
FABS a2, a2
|
||||
addi.d I, I, -1
|
||||
ADD a1, a1, a2
|
||||
ADD s1, a1, s1
|
||||
add.d X, X, INCX
|
||||
blt $r0, I, .L24
|
||||
.align 3
|
||||
|
||||
.L999:
|
||||
MOV $f0, $f16
|
||||
jirl $r0, $r1, 0x0
|
||||
.align 3
|
||||
|
||||
EPILOGUE
|
||||
|
|
@ -0,0 +1,358 @@
|
|||
/***************************************************************************
|
||||
Copyright (c) 2023, The OpenBLAS Project
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
3. Neither the name of the OpenBLAS project nor the names of
|
||||
its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
|
||||
USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*****************************************************************************/
|
||||
|
||||
#define ASSEMBLER
|
||||
#include "common.h"
|
||||
|
||||
#define N $r4
|
||||
#define X $r5
|
||||
#define INCX $r6
|
||||
#define I $r17
|
||||
#define TEMP $r18
|
||||
#define t1 $r15
|
||||
#define t2 $r12
|
||||
#define t3 $r13
|
||||
#define t4 $r14
|
||||
#define a1 $f12
|
||||
#define a2 $f13
|
||||
#define a3 $f14
|
||||
#define a4 $f15
|
||||
#define s1 $f16
|
||||
#define VX0 $vr12
|
||||
#define VX1 $vr13
|
||||
#define VX2 $vr14
|
||||
#define VX3 $vr15
|
||||
#define res1 $vr16
|
||||
#define res2 $vr17
|
||||
#define res3 $vr18
|
||||
#define res0 $vr19
|
||||
#define neg1 $vr20
|
||||
#define VT0 $vr21
|
||||
#define VT1 $vr22
|
||||
|
||||
PROLOGUE
|
||||
vxor.v res1, res1, res1
|
||||
vxor.v res2, res2, res2
|
||||
vxor.v res0, res0, res0
|
||||
bge $r0, N, .L999
|
||||
bge $r0, INCX, .L999
|
||||
#ifdef DOUBLE
|
||||
li.d t1, -1
|
||||
vreplgr2vr.d neg1, t1
|
||||
vffint.d.l neg1, neg1
|
||||
#else
|
||||
li.w t1, -1
|
||||
vreplgr2vr.w neg1, t1
|
||||
vffint.s.w neg1, neg1
|
||||
#endif
|
||||
li.d TEMP, 1
|
||||
slli.d TEMP, TEMP, ZBASE_SHIFT
|
||||
slli.d INCX, INCX, ZBASE_SHIFT
|
||||
srai.d I, N, 3
|
||||
bne INCX, TEMP, .L20
|
||||
bge $r0, I, .L13
|
||||
.align 3
|
||||
|
||||
.L11:
|
||||
#ifdef DOUBLE
|
||||
vld VX0, X, 0 * SIZE
|
||||
vld VX1, X, 2 * SIZE
|
||||
vfmul.d VX2, neg1, VX0
|
||||
vfmul.d VX3, neg1, VX1
|
||||
vfcmp.clt.d VT0, VX0, res0
|
||||
vfcmp.clt.d VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.d res2, VX0, VX1
|
||||
vfadd.d res1, res1, res2
|
||||
vld VX2, X, 4 * SIZE
|
||||
vld VX3, X, 6 * SIZE
|
||||
vfmul.d VX0, neg1, VX2
|
||||
vfmul.d VX1, neg1, VX3
|
||||
vfcmp.clt.d VT0, VX2, res0
|
||||
vfcmp.clt.d VT1, VX3, res0
|
||||
vbitsel.v VX2, VX2, VX0, VT0
|
||||
vbitsel.v VX3, VX3, VX1, VT1
|
||||
vfadd.d res2, VX2, VX3
|
||||
vfadd.d res1, res1, res2
|
||||
vld VX0, X, 8 * SIZE
|
||||
vld VX1, X, 10 * SIZE
|
||||
vfmul.d VX2, neg1, VX0
|
||||
vfmul.d VX3, neg1, VX1
|
||||
vfcmp.clt.d VT0, VX0, res0
|
||||
vfcmp.clt.d VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.d res2, VX0, VX1
|
||||
vfadd.d res1, res1, res2
|
||||
vld VX2, X, 12 * SIZE
|
||||
vld VX3, X, 14 * SIZE
|
||||
vfmul.d VX0, neg1, VX2
|
||||
vfmul.d VX1, neg1, VX3
|
||||
vfcmp.clt.d VT0, VX2, res0
|
||||
vfcmp.clt.d VT1, VX3, res0
|
||||
vbitsel.v VX2, VX2, VX0, VT0
|
||||
vbitsel.v VX3, VX3, VX1, VT1
|
||||
vfadd.d res2, VX2, VX3
|
||||
vfadd.d res1, res1, res2
|
||||
addi.d I, I, -1
|
||||
#else
|
||||
vld VX0, X, 0 * SIZE
|
||||
vld VX1, X, 4 * SIZE
|
||||
vfmul.s VX2, neg1, VX0
|
||||
vfmul.s VX3, neg1, VX1
|
||||
vfcmp.clt.s VT0, VX0, res0
|
||||
vfcmp.clt.s VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.s res2, VX0, VX1
|
||||
vld VX0, X, 8 * SIZE
|
||||
vld VX1, X, 12 * SIZE
|
||||
addi.d I, I, -1
|
||||
vfmul.s VX2, neg1, VX0
|
||||
vfmul.s VX3, neg1, VX1
|
||||
vfcmp.clt.s VT0, VX0, res0
|
||||
vfcmp.clt.s VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.s res3, VX1, VX0
|
||||
vfadd.s res2, res3, res2
|
||||
vfadd.s res1, res1, res2
|
||||
#endif
|
||||
addi.d X, X, 16 * SIZE
|
||||
blt $r0, I, .L11
|
||||
.align 3
|
||||
|
||||
.L12:
|
||||
#ifdef DOUBLE
|
||||
vreplvei.d VX1, res1, 1
|
||||
vfadd.d res1, VX1, res1
|
||||
#else
|
||||
vreplvei.w VX1, res1, 1
|
||||
vreplvei.w VX2, res1, 2
|
||||
vreplvei.w VX3, res1, 3
|
||||
vfadd.s res1, VX1, res1
|
||||
vfadd.s res1, VX2, res1
|
||||
vfadd.s res1, VX3, res1
|
||||
#endif
|
||||
.align 3
|
||||
|
||||
.L13:
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
.align 3
|
||||
|
||||
.L14:
|
||||
LD a1, X, 0 * SIZE
|
||||
LD a2, X, 1 * SIZE
|
||||
FABS a1, a1
|
||||
FABS a2, a2
|
||||
addi.d I, I, -1
|
||||
ADD a1, a1, a2
|
||||
ADD s1, a1, s1
|
||||
addi.d X, X, 2 * SIZE
|
||||
blt $r0, I, .L14
|
||||
b .L999
|
||||
.align 3
|
||||
|
||||
.L20:
|
||||
bge $r0, I, .L23
|
||||
.align 3
|
||||
|
||||
.L21:
|
||||
#ifdef DOUBLE
|
||||
ld.d t1, X, 0 * SIZE
|
||||
ld.d t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX0, t1, 0
|
||||
vinsgr2vr.d VX0, t2, 1
|
||||
ld.d t1, X, 0 * SIZE
|
||||
ld.d t2, X, 1 * SIZE
|
||||
vinsgr2vr.d VX1, t1, 0
|
||||
vinsgr2vr.d VX1, t2, 1
|
||||
add.d X, X, INCX
|
||||
vfmul.d VX2, neg1, VX0
|
||||
vfmul.d VX3, neg1, VX1
|
||||
vfcmp.clt.d VT0, VX0, res0
|
||||
vfcmp.clt.d VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.d res2, VX0, VX1
|
||||
vfadd.d res1, res1, res2
|
||||
ld.d t3, X, 0 * SIZE
|
||||
ld.d t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX0, t3, 0
|
||||
vinsgr2vr.d VX0, t4, 1
|
||||
ld.d t3, X, 0 * SIZE
|
||||
ld.d t4, X, 1 * SIZE
|
||||
vinsgr2vr.d VX1, t3, 0
|
||||
vinsgr2vr.d VX1, t4, 1
|
||||
add.d X, X, INCX
|
||||
vfmul.d VX2, neg1, VX0
|
||||
vfmul.d VX3, neg1, VX1
|
||||
vfcmp.clt.d VT0, VX0, res0
|
||||
vfcmp.clt.d VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.d res2, VX0, VX1
|
||||
vfadd.d res1, res1, res2
|
||||
ld.d t1, X, 0 * SIZE
|
||||
ld.d t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX0, t1, 0
|
||||
vinsgr2vr.d VX0, t2, 1
|
||||
ld.d t1, X, 0 * SIZE
|
||||
ld.d t2, X, 1 * SIZE
|
||||
vinsgr2vr.d VX1, t1, 0
|
||||
vinsgr2vr.d VX1, t2, 1
|
||||
add.d X, X, INCX
|
||||
vfmul.d VX2, neg1, VX0
|
||||
vfmul.d VX3, neg1, VX1
|
||||
vfcmp.clt.d VT0, VX0, res0
|
||||
vfcmp.clt.d VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.d res2, VX0, VX1
|
||||
vfadd.d res1, res1, res2
|
||||
ld.d t3, X, 0 * SIZE
|
||||
ld.d t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX0, t3, 0
|
||||
vinsgr2vr.d VX0, t4, 1
|
||||
ld.d t3, X, 0 * SIZE
|
||||
ld.d t4, X, 1 * SIZE
|
||||
vinsgr2vr.d VX1, t3, 0
|
||||
vinsgr2vr.d VX1, t4, 1
|
||||
add.d X, X, INCX
|
||||
vfmul.d VX2, neg1, VX0
|
||||
vfmul.d VX3, neg1, VX1
|
||||
vfcmp.clt.d VT0, VX0, res0
|
||||
vfcmp.clt.d VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.d res2, VX0, VX1
|
||||
vfadd.d res1, res1, res2
|
||||
#else
|
||||
ld.w t1, X, 0 * SIZE
|
||||
ld.w t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
ld.w t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.w VX0, t1, 0
|
||||
vinsgr2vr.w VX0, t2, 1
|
||||
vinsgr2vr.w VX0, t3, 2
|
||||
vinsgr2vr.w VX0, t4, 3
|
||||
ld.w t1, X, 0 * SIZE
|
||||
ld.w t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
ld.w t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.w VX1, t1, 0
|
||||
vinsgr2vr.w VX1, t2, 1
|
||||
vinsgr2vr.w VX1, t3, 2
|
||||
vinsgr2vr.w VX1, t4, 3
|
||||
vfmul.s VX2, neg1, VX0
|
||||
vfmul.s VX3, neg1, VX1
|
||||
vfcmp.clt.s VT0, VX0, res0
|
||||
vfcmp.clt.s VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.s res2, VX0, VX1
|
||||
ld.w t1, X, 0 * SIZE
|
||||
ld.w t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
ld.w t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.w VX2, t1, 0
|
||||
vinsgr2vr.w VX2, t2, 1
|
||||
vinsgr2vr.w VX2, t3, 2
|
||||
vinsgr2vr.w VX2, t4, 3
|
||||
ld.w t1, X, 0 * SIZE
|
||||
ld.w t2, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
ld.w t4, X, 1 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.w VX3, t1, 0
|
||||
vinsgr2vr.w VX3, t2, 1
|
||||
vinsgr2vr.w VX3, t3, 2
|
||||
vinsgr2vr.w VX3, t4, 3
|
||||
vfmul.s VX0, neg1, VX2
|
||||
vfmul.s VX1, neg1, VX3
|
||||
vfcmp.clt.s VT0, VX2, res0
|
||||
vfcmp.clt.s VT1, VX3, res0
|
||||
vbitsel.v VX2, VX2, VX0, VT0
|
||||
vbitsel.v VX3, VX3, VX1, VT1
|
||||
vfadd.s res3, VX2, VX3
|
||||
vfadd.s res2, res3, res2
|
||||
vfadd.s res1, res1, res2
|
||||
#endif
|
||||
addi.d I, I, -1
|
||||
blt $r0, I, .L21
|
||||
.align 3
|
||||
|
||||
.L22:
|
||||
#ifdef DOUBLE
|
||||
vreplvei.d VX1, res1, 1
|
||||
vfadd.d res1, VX1, res1
|
||||
#else
|
||||
vreplvei.w VX1, res1, 1
|
||||
vreplvei.w VX2, res1, 2
|
||||
vreplvei.w VX3, res1, 3
|
||||
vfadd.s res1, VX1, res1
|
||||
vfadd.s res1, VX2, res1
|
||||
vfadd.s res1, VX3, res1
|
||||
#endif
|
||||
.align 3
|
||||
|
||||
.L23:
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
.align 3
|
||||
|
||||
.L24:
|
||||
LD a1, X, 0 * SIZE
|
||||
LD a2, X, 1 * SIZE
|
||||
FABS a1, a1
|
||||
FABS a2, a2
|
||||
addi.d I, I, -1
|
||||
ADD a1, a1, a2
|
||||
ADD s1, a1, s1
|
||||
add.d X, X, INCX
|
||||
blt $r0, I, .L24
|
||||
.align 3
|
||||
|
||||
.L999:
|
||||
MOV $f0, $f16
|
||||
jirl $r0, $r1, 0x0
|
||||
.align 3
|
||||
|
||||
EPILOGUE
|
||||
|
|
@ -1,148 +0,0 @@
|
|||
#define ASSEMBLER
|
||||
#include "common.h"
|
||||
#define N $r4
|
||||
#define X $r5
|
||||
#define INCX $r6
|
||||
#define I $r17
|
||||
#define TEMP $r18
|
||||
#define t1 $r15
|
||||
#define t2 $r12
|
||||
#define t3 $r13
|
||||
#define t4 $r14
|
||||
#define VX0 $xr12
|
||||
#define VX1 $xr13
|
||||
#define VX2 $xr14
|
||||
#define VX3 $xr15
|
||||
#define VT0 $xr23
|
||||
#define VT1 $xr22
|
||||
#define res1 $xr16
|
||||
#define res2 $xr17
|
||||
#define res0 $xr18
|
||||
#define neg1 $xr19
|
||||
|
||||
PROLOGUE
|
||||
xvxor.v res1, res1, res1
|
||||
xvxor.v res2, res2, res2
|
||||
xvxor.v res0, res0, res0
|
||||
bge $r0, N, .L999
|
||||
bge $r0, INCX, .L999
|
||||
li.d t1, -1
|
||||
xvreplgr2vr.d neg1, t1
|
||||
xvffint.d.l neg1, neg1
|
||||
li.d TEMP, SIZE
|
||||
slli.d INCX, INCX, BASE_SHIFT
|
||||
srai.d I, N, 3
|
||||
bne INCX, TEMP, .L20
|
||||
bge $r0, I, .L13
|
||||
.align 3
|
||||
|
||||
.L11:
|
||||
xvld VX0, X, 0 * SIZE
|
||||
xvld VX1, X, 4 * SIZE
|
||||
xvfmul.d VX2, neg1, VX0
|
||||
xvfmul.d VX3, neg1, VX1
|
||||
xvfcmp.clt.d VT0, VX0, res0
|
||||
xvfcmp.clt.d VT1, VX1, res0
|
||||
xvbitsel.v VX0, VX0, VX2, VT0
|
||||
xvbitsel.v VX1, VX1, VX3, VT1
|
||||
xvfadd.d res2, VX0, VX1
|
||||
xvfadd.d res1, res1, res2
|
||||
addi.d X, X, 8 * SIZE
|
||||
addi.d I, I, -1
|
||||
blt $r0, I, .L11
|
||||
.align 3
|
||||
|
||||
.L12:
|
||||
xvpickve.d VX1, res1, 1
|
||||
xvpickve.d VX2, res1, 2
|
||||
xvpickve.d VX3, res1, 3
|
||||
xvfadd.d res1, VX1, res1
|
||||
xvfadd.d res1, VX2, res1
|
||||
xvfadd.d res1, VX3, res1
|
||||
.align 3
|
||||
|
||||
.L13:
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
.align 3
|
||||
|
||||
.L14:
|
||||
fld.d $f12, X, 0 * SIZE
|
||||
fabs.d $f12, $f12
|
||||
fadd.d $f16, $f12, $f16
|
||||
addi.d I, I, -1
|
||||
addi.d X, X, SIZE
|
||||
blt $r0, I, .L14
|
||||
b .L999
|
||||
.align 3
|
||||
|
||||
.L20:
|
||||
bge $r0, I, .L23
|
||||
.align 3
|
||||
|
||||
.L21:
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.d VX0, t1, 0
|
||||
xvinsgr2vr.d VX0, t2, 1
|
||||
xvinsgr2vr.d VX0, t3, 2
|
||||
xvinsgr2vr.d VX0, t4, 3
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.d VX1, t1, 0
|
||||
xvinsgr2vr.d VX1, t2, 1
|
||||
xvinsgr2vr.d VX1, t3, 2
|
||||
xvinsgr2vr.d VX1, t4, 3
|
||||
xvfmul.d VX2, neg1, VX0
|
||||
xvfmul.d VX3, neg1, VX1
|
||||
xvfcmp.clt.d VT0, VX0, res0
|
||||
xvfcmp.clt.d VT1, VX1, res0
|
||||
xvbitsel.v VX0, VX0, VX2, VT0
|
||||
xvbitsel.v VX1, VX1, VX3, VT1
|
||||
xvfadd.d res2, VX0, VX1
|
||||
xvfadd.d res1, res1, res2
|
||||
addi.d I, I, -1
|
||||
blt $r0, I, .L21
|
||||
.align 3
|
||||
|
||||
.L22:
|
||||
xvpickve.d VX1, res1, 1
|
||||
xvpickve.d VX2, res1, 2
|
||||
xvpickve.d VX3, res1, 3
|
||||
xvfadd.d res1, VX1, res1
|
||||
xvfadd.d res1, VX2, res1
|
||||
xvfadd.d res1, VX3, res1
|
||||
.align 3
|
||||
|
||||
.L23:
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
.align 3
|
||||
|
||||
.L24:
|
||||
fld.d $f12, X, 0 * SIZE
|
||||
fabs.d $f12, $f12
|
||||
fadd.d $f16, $f12, $f16
|
||||
addi.d I, I, -1
|
||||
add.d X, X, INCX
|
||||
blt $r0, I, .L24
|
||||
.align 3
|
||||
|
||||
.L999:
|
||||
fmov.d $f0, $f16
|
||||
jirl $r0, $r1, 0x0
|
||||
.align 3
|
||||
|
||||
EPILOGUE
|
||||
|
|
@ -1,158 +0,0 @@
|
|||
#define ASSEMBLER
|
||||
#include "common.h"
|
||||
#define N $r4
|
||||
#define X $r5
|
||||
#define INCX $r6
|
||||
#define I $r17
|
||||
#define TEMP $r18
|
||||
#define t1 $r15
|
||||
#define t2 $r12
|
||||
#define t3 $r13
|
||||
#define t4 $r14
|
||||
#define VX0 $vr12
|
||||
#define VX1 $vr13
|
||||
#define VX2 $vr14
|
||||
#define VX3 $vr15
|
||||
#define VT0 $vr23
|
||||
#define VT1 $vr22
|
||||
#define res1 $vr16
|
||||
#define res2 $vr17
|
||||
#define res0 $vr18
|
||||
#define neg1 $vr19
|
||||
|
||||
PROLOGUE
|
||||
vxor.v res1, res1, res1
|
||||
vxor.v res2, res2, res2
|
||||
vxor.v res0, res0, res0
|
||||
bge $r0, N, .L999
|
||||
bge $r0, INCX, .L999
|
||||
li.d t1, -1
|
||||
vreplgr2vr.d neg1, t1
|
||||
vffint.d.l neg1, neg1
|
||||
li.d TEMP, SIZE
|
||||
slli.d INCX, INCX, BASE_SHIFT
|
||||
srai.d I, N, 3
|
||||
bne INCX, TEMP, .L20
|
||||
bge $r0, I, .L13
|
||||
.align 3
|
||||
|
||||
.L11:
|
||||
vld VX0, X, 0 * SIZE
|
||||
vld VX1, X, 2 * SIZE
|
||||
vfmul.d VX2, neg1, VX0
|
||||
vfmul.d VX3, neg1, VX1
|
||||
vfcmp.clt.d VT0, VX0, res0
|
||||
vfcmp.clt.d VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.d res2, VX0, VX1
|
||||
vfadd.d res1, res1, res2
|
||||
vld VX0, X, 4 * SIZE
|
||||
vld VX1, X, 6 * SIZE
|
||||
vfmul.d VX2, neg1, VX0
|
||||
vfmul.d VX3, neg1, VX1
|
||||
vfcmp.clt.d VT0, VX0, res0
|
||||
vfcmp.clt.d VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.d res2, VX0, VX1
|
||||
vfadd.d res1, res1, res2
|
||||
addi.d X, X, 8 * SIZE
|
||||
addi.d I, I, -1
|
||||
blt $r0, I, .L11
|
||||
.align 3
|
||||
|
||||
.L12:
|
||||
vreplvei.d VX1, res1, 1
|
||||
vfadd.d res1, VX1, res1
|
||||
.align 3
|
||||
|
||||
.L13:
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
.align 3
|
||||
|
||||
.L14:
|
||||
fld.d $f12, X, 0 * SIZE
|
||||
fabs.d $f12, $f12
|
||||
fadd.d $f16, $f12, $f16
|
||||
addi.d I, I, -1
|
||||
addi.d X, X, SIZE
|
||||
blt $r0, I, .L14
|
||||
b .L999
|
||||
.align 3
|
||||
|
||||
.L20:
|
||||
bge $r0, I, .L23
|
||||
.align 3
|
||||
|
||||
.L21:
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX0, t1, 0
|
||||
vinsgr2vr.d VX0, t2, 1
|
||||
ld.d t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t2, X, 0 * SIZE
|
||||
vinsgr2vr.d VX1, t1, 0
|
||||
vinsgr2vr.d VX1, t2, 1
|
||||
add.d X, X, INCX
|
||||
vfmul.d VX2, neg1, VX0
|
||||
vfmul.d VX3, neg1, VX1
|
||||
vfcmp.clt.d VT0, VX0, res0
|
||||
vfcmp.clt.d VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.d res2, VX0, VX1
|
||||
vfadd.d res1, res1, res2
|
||||
ld.d t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.d VX0, t3, 0
|
||||
vinsgr2vr.d VX0, t4, 1
|
||||
ld.d t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.d t4, X, 0 * SIZE
|
||||
vinsgr2vr.d VX1, t3, 0
|
||||
vinsgr2vr.d VX1, t4, 1
|
||||
add.d X, X, INCX
|
||||
vfmul.d VX2, neg1, VX0
|
||||
vfmul.d VX3, neg1, VX1
|
||||
vfcmp.clt.d VT0, VX0, res0
|
||||
vfcmp.clt.d VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.d res2, VX0, VX1
|
||||
vfadd.d res1, res1, res2
|
||||
addi.d I, I, -1
|
||||
blt $r0, I, .L21
|
||||
.align 3
|
||||
|
||||
.L22:
|
||||
vreplvei.d VX1, res1, 1
|
||||
vfadd.d res1, VX1, res1
|
||||
.align 3
|
||||
|
||||
.L23:
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
.align 3
|
||||
|
||||
.L24:
|
||||
fld.d $f12, X, 0 * SIZE
|
||||
fabs.d $f12, $f12
|
||||
fadd.d $f16, $f12, $f16
|
||||
addi.d I, I, -1
|
||||
add.d X, X, INCX
|
||||
blt $r0, I, .L24
|
||||
.align 3
|
||||
|
||||
.L999:
|
||||
fmov.d $f0, $f16
|
||||
jirl $r0, $r1, 0x0
|
||||
.align 3
|
||||
|
||||
EPILOGUE
|
||||
|
|
@ -1,157 +0,0 @@
|
|||
#define ASSEMBLER
|
||||
#include "common.h"
|
||||
#define N $r4
|
||||
#define X $r5
|
||||
#define INCX $r6
|
||||
#define I $r17
|
||||
#define TEMP $r18
|
||||
#define t1 $r15
|
||||
#define t2 $r12
|
||||
#define t3 $r13
|
||||
#define t4 $r14
|
||||
#define VX0 $xr12
|
||||
#define VX1 $xr13
|
||||
#define VX2 $xr14
|
||||
#define VX3 $xr15
|
||||
#define VT0 $xr23
|
||||
#define VT1 $xr22
|
||||
#define res1 $xr16
|
||||
#define res2 $xr17
|
||||
#define res0 $xr18
|
||||
#define neg1 $xr19
|
||||
|
||||
PROLOGUE
|
||||
xvxor.v res1, res1, res1
|
||||
xvxor.v res2, res2, res2
|
||||
xvxor.v res0, res0, res0
|
||||
bge $r0, N, .L999
|
||||
bge $r0, INCX, .L999
|
||||
li.w t1, -1
|
||||
xvreplgr2vr.w neg1, t1
|
||||
xvffint.s.w neg1, neg1
|
||||
li.d TEMP, SIZE
|
||||
slli.d INCX, INCX, BASE_SHIFT
|
||||
srai.d I, N, 3
|
||||
bne INCX, TEMP, .L20
|
||||
bge $r0, I, .L13
|
||||
.align 3
|
||||
|
||||
.L11:
|
||||
xvld VX0, X, 0 * SIZE
|
||||
xvfmul.s VX2, neg1, VX0
|
||||
xvfcmp.clt.s VT0, VX0, res0
|
||||
xvbitsel.v VX0, VX0, VX2, VT0
|
||||
xvfadd.s res1, VX0, res1
|
||||
addi.d X, X, 8 * SIZE
|
||||
addi.d I, I, -1
|
||||
blt $r0, I, .L11
|
||||
.align 3
|
||||
|
||||
.L12:
|
||||
xvfadd.s res2, res1, res2
|
||||
xvpickve.w VX1, res1, 1
|
||||
xvpickve.w VX2, res1, 2
|
||||
xvpickve.w VX3, res1, 3
|
||||
xvfadd.s res1, VX1, res1
|
||||
xvfadd.s res1, VX2, res1
|
||||
xvfadd.s res1, VX3, res1
|
||||
xvpickve.w VX0, res2, 4
|
||||
xvpickve.w VX1, res2, 5
|
||||
xvpickve.w VX2, res2, 6
|
||||
xvpickve.w VX3, res2, 7
|
||||
xvfadd.s res1, VX0, res1
|
||||
xvfadd.s res1, VX1, res1
|
||||
xvfadd.s res1, VX2, res1
|
||||
xvfadd.s res1, VX2, res1
|
||||
.align 3
|
||||
|
||||
.L13:
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
.align 3
|
||||
|
||||
.L14:
|
||||
fld.s $f12, X, 0 * SIZE
|
||||
fabs.s $f12, $f12
|
||||
fadd.s $f16, $f12, $f16
|
||||
addi.d I, I, -1
|
||||
addi.d X, X, SIZE
|
||||
blt $r0, I, .L14
|
||||
b .L999
|
||||
.align 3
|
||||
|
||||
.L20:
|
||||
bge $r0, I, .L23
|
||||
.align 3
|
||||
|
||||
.L21:
|
||||
ld.w t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.w VX0, t1, 0
|
||||
xvinsgr2vr.w VX0, t2, 1
|
||||
xvinsgr2vr.w VX0, t3, 2
|
||||
xvinsgr2vr.w VX0, t4, 3
|
||||
ld.w t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
xvinsgr2vr.w VX0, t1, 4
|
||||
xvinsgr2vr.w VX0, t2, 5
|
||||
xvinsgr2vr.w VX0, t3, 6
|
||||
xvinsgr2vr.w VX0, t4, 7
|
||||
xvfmul.s VX2, neg1, VX0
|
||||
xvfcmp.clt.s VT0, VX0, res0
|
||||
xvbitsel.v VX0, VX0, VX2, VT0
|
||||
xvfadd.s res1, VX0, res1
|
||||
addi.d I, I, -1
|
||||
blt $r0, I, .L21
|
||||
.align 3
|
||||
|
||||
.L22:
|
||||
xvfadd.s res2, res1, res2
|
||||
xvpickve.w VX1, res1, 1
|
||||
xvpickve.w VX2, res1, 2
|
||||
xvpickve.w VX3, res1, 3
|
||||
xvfadd.s res1, VX1, res1
|
||||
xvfadd.s res1, VX2, res1
|
||||
xvfadd.s res1, VX3, res1
|
||||
xvpickve.w VX0, res2, 4
|
||||
xvpickve.w VX1, res2, 5
|
||||
xvpickve.w VX2, res2, 6
|
||||
xvpickve.w VX3, res2, 7
|
||||
xvfadd.s res1, VX0, res1
|
||||
xvfadd.s res1, VX1, res1
|
||||
xvfadd.s res1, VX2, res1
|
||||
xvfadd.s res1, VX2, res1
|
||||
.align 3
|
||||
|
||||
.L23:
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
.align 3
|
||||
|
||||
.L24:
|
||||
fld.s $f12, X, 0 * SIZE
|
||||
fabs.s $f12, $f12
|
||||
fadd.s $f16, $f12, $f16
|
||||
addi.d I, I, -1
|
||||
add.d X, X, INCX
|
||||
blt $r0, I, .L24
|
||||
.align 3
|
||||
|
||||
.L999:
|
||||
fmov.s $f0, $f16
|
||||
jirl $r0, $r1, 0x0
|
||||
.align 3
|
||||
|
||||
EPILOGUE
|
||||
|
|
@ -1,148 +0,0 @@
|
|||
#define ASSEMBLER
|
||||
#include "common.h"
|
||||
#define N $r4
|
||||
#define X $r5
|
||||
#define INCX $r6
|
||||
#define I $r17
|
||||
#define TEMP $r18
|
||||
#define t1 $r15
|
||||
#define t2 $r12
|
||||
#define t3 $r13
|
||||
#define t4 $r14
|
||||
#define VX0 $vr12
|
||||
#define VX1 $vr13
|
||||
#define VX2 $vr14
|
||||
#define VX3 $vr15
|
||||
#define VT0 $vr23
|
||||
#define VT1 $vr22
|
||||
#define res1 $vr16
|
||||
#define res2 $vr17
|
||||
#define res0 $vr18
|
||||
#define neg1 $vr19
|
||||
|
||||
PROLOGUE
|
||||
vxor.v res1, res1, res1
|
||||
vxor.v res2, res2, res2
|
||||
vxor.v res0, res0, res0
|
||||
bge $r0, N, .L999
|
||||
bge $r0, INCX, .L999
|
||||
li.w t1, -1
|
||||
vreplgr2vr.w neg1, t1
|
||||
vffint.s.w neg1, neg1
|
||||
li.d TEMP, SIZE
|
||||
slli.d INCX, INCX, BASE_SHIFT
|
||||
srai.d I, N, 3
|
||||
bne INCX, TEMP, .L20
|
||||
bge $r0, I, .L13
|
||||
.align 3
|
||||
|
||||
.L11:
|
||||
vld VX0, X, 0 * SIZE
|
||||
vld VX1, X, 4 * SIZE
|
||||
vfmul.s VX2, neg1, VX0
|
||||
vfmul.s VX3, neg1, VX1
|
||||
vfcmp.clt.s VT0, VX0, res0
|
||||
vfcmp.clt.s VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.s res2, VX0, VX1
|
||||
vfadd.s res1, res1, res2
|
||||
addi.d X, X, 8 * SIZE
|
||||
addi.d I, I, -1
|
||||
blt $r0, I, .L11
|
||||
.align 3
|
||||
|
||||
.L12:
|
||||
vreplvei.w VX1, res1, 1
|
||||
vreplvei.w VX2, res1, 2
|
||||
vreplvei.w VX3, res1, 3
|
||||
vfadd.s res1, VX1, res1
|
||||
vfadd.s res1, VX2, res1
|
||||
vfadd.s res1, VX3, res1
|
||||
.align 3
|
||||
|
||||
.L13:
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
.align 3
|
||||
|
||||
.L14:
|
||||
fld.s $f12, X, 0 * SIZE
|
||||
fabs.s $f12, $f12
|
||||
fadd.s $f16, $f12, $f16
|
||||
addi.d I, I, -1
|
||||
addi.d X, X, SIZE
|
||||
blt $r0, I, .L14
|
||||
b .L999
|
||||
.align 3
|
||||
|
||||
.L20:
|
||||
bge $r0, I, .L23
|
||||
.align 3
|
||||
|
||||
.L21:
|
||||
ld.w t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.w VX0, t1, 0
|
||||
vinsgr2vr.w VX0, t2, 1
|
||||
vinsgr2vr.w VX0, t3, 2
|
||||
vinsgr2vr.w VX0, t4, 3
|
||||
ld.w t1, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t2, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t3, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
ld.w t4, X, 0 * SIZE
|
||||
add.d X, X, INCX
|
||||
vinsgr2vr.w VX1, t1, 0
|
||||
vinsgr2vr.w VX1, t2, 1
|
||||
vinsgr2vr.w VX1, t3, 2
|
||||
vinsgr2vr.w VX1, t4, 3
|
||||
vfmul.s VX2, neg1, VX0
|
||||
vfmul.s VX3, neg1, VX1
|
||||
vfcmp.clt.s VT0, VX0, res0
|
||||
vfcmp.clt.s VT1, VX1, res0
|
||||
vbitsel.v VX0, VX0, VX2, VT0
|
||||
vbitsel.v VX1, VX1, VX3, VT1
|
||||
vfadd.s res2, VX0, VX1
|
||||
vfadd.s res1, res1, res2
|
||||
addi.d I, I, -1
|
||||
blt $r0, I, .L21
|
||||
.align 3
|
||||
|
||||
.L22:
|
||||
vreplvei.w VX1, res1, 1
|
||||
vreplvei.w VX2, res1, 2
|
||||
vreplvei.w VX3, res1, 3
|
||||
vfadd.s res1, VX1, res1
|
||||
vfadd.s res1, VX2, res1
|
||||
vfadd.s res1, VX3, res1
|
||||
.align 3
|
||||
|
||||
.L23:
|
||||
andi I, N, 7
|
||||
bge $r0, I, .L999
|
||||
.align 3
|
||||
|
||||
.L24:
|
||||
fld.s $f12, X, 0 * SIZE
|
||||
fabs.s $f12, $f12
|
||||
fadd.s $f16, $f12, $f16
|
||||
addi.d I, I, -1
|
||||
add.d X, X, INCX
|
||||
blt $r0, I, .L24
|
||||
.align 3
|
||||
|
||||
.L999:
|
||||
fmov.s $f0, $f16
|
||||
jirl $r0, $r1, 0x0
|
||||
.align 3
|
||||
|
||||
EPILOGUE
|
||||
Loading…
Reference in New Issue