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Correctly detect ARM Neoverse V2 CPUs.

This commit is contained in:
Matthias Langer 2024-05-16 09:59:52 +00:00
parent ce96e0e50f
commit 0050a9660b
3 changed files with 35 additions and 2 deletions
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10
Makefile.arm64
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@ -176,6 +176,16 @@ endif
endif endif
endif endif
# Detect ARM Neoverse V2.
ifeq ($(CORE), NEOVERSEV2)
ifeq (1, $(filter 1,$(GCCVERSIONGTEQ12) $(ISCLANG)))
CCOMMON_OPT += -march=armv9-a -mtune=neoverse-v2
ifneq ($(F_COMPILER), NAG)
FCOMMON_OPT += -march=armv9-a -mtune=neoverse-v2
endif
endif
endif
# Use a53 tunings because a55 is only available in GCC>=8.1 # Use a53 tunings because a55 is only available in GCC>=8.1
ifeq ($(CORE), CORTEXA55) ifeq ($(CORE), CORTEXA55)
ifeq (1, $(filter 1,$(GCCVERSIONGTEQ7) $(ISCLANG))) ifeq (1, $(filter 1,$(GCCVERSIONGTEQ7) $(ISCLANG)))

26
cpuid_arm64.c
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@ -46,6 +46,7 @@ size_t length64=sizeof(value64);
#define CPU_NEOVERSEN1 11 #define CPU_NEOVERSEN1 11
#define CPU_NEOVERSEV1 16 #define CPU_NEOVERSEV1 16
#define CPU_NEOVERSEN2 17 #define CPU_NEOVERSEN2 17
#define CPU_NEOVERSEV2 24
#define CPU_CORTEXX1 18 #define CPU_CORTEXX1 18
#define CPU_CORTEXX2 19 #define CPU_CORTEXX2 19
#define CPU_CORTEXA510 20 #define CPU_CORTEXA510 20
@ -91,7 +92,8 @@ static char *cpuname[] = {
"CORTEXA510", "CORTEXA510",
"CORTEXA710", "CORTEXA710",
"FT2000", "FT2000",
"CORTEXA76" "CORTEXA76",
"NEOVERSEV2"
}; };
static char *cpuname_lower[] = { static char *cpuname_lower[] = {
@ -118,7 +120,8 @@ static char *cpuname_lower[] = {
"cortexa510", "cortexa510",
"cortexa710", "cortexa710",
"ft2000", "ft2000",
"cortexa76" "cortexa76",
"neoversev2"
}; };
int get_feature(char *search) int get_feature(char *search)
@ -213,6 +216,8 @@ int detect(void)
return CPU_CORTEXX2; return CPU_CORTEXX2;
else if (strstr(cpu_part, "0xd4e")) //X3 else if (strstr(cpu_part, "0xd4e")) //X3
return CPU_CORTEXX2; return CPU_CORTEXX2;
else if (strstr(cpu_part, "0xd4f")) //NVIDIA Grace et al.
return CPU_NEOVERSEV2;
else if (strstr(cpu_part, "0xd0b")) else if (strstr(cpu_part, "0xd0b"))
return CPU_CORTEXA76; return CPU_CORTEXA76;
} }
@ -425,6 +430,23 @@ void get_cpuconfig(void)
printf("#define DTB_DEFAULT_ENTRIES 48\n"); printf("#define DTB_DEFAULT_ENTRIES 48\n");
printf("#define DTB_SIZE 4096\n"); printf("#define DTB_SIZE 4096\n");
break; break;
case CPU_NEOVERSEV2:
printf("#define ARMV9\n");
printf("#define %s\n", cpuname[d]);
printf("#define L1_CODE_SIZE 65536\n");
printf("#define L1_CODE_LINESIZE 64\n");
printf("#define L1_CODE_ASSOCIATIVE 4\n");
printf("#define L1_DATA_SIZE 65536\n");
printf("#define L1_DATA_LINESIZE 64\n");
printf("#define L1_DATA_ASSOCIATIVE 4\n");
printf("#define L2_SIZE 1048576\n");
printf("#define L2_LINESIZE 64\n");
printf("#define L2_ASSOCIATIVE 8\n");
// L1 Data TLB = 48 entries
// L2 Data TLB = 2048 entries
printf("#define DTB_DEFAULT_ENTRIES 48\n");
printf("#define DTB_SIZE 4096\n"); // Set to 4096 for symmetry with other configs.
break;
case CPU_CORTEXA510: case CPU_CORTEXA510:
case CPU_CORTEXA710: case CPU_CORTEXA710:
case CPU_CORTEXX1: case CPU_CORTEXX1:

1
kernel/arm64/KERNEL.NEOVERSEV2 Normal file
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@ -0,0 +1 @@
include $(KERNELDIR)/KERNEL.ARMV8SVE