forked from xuos/xiuos
239 lines
6.5 KiB
ArmAsm
239 lines
6.5 KiB
ArmAsm
/* ------------------------------------------------------------------------- */
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/* @file: startup_RV32M1_ri5cy.s */
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/* @purpose: RI5CY Core Device Startup File */
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/* RV32M1_ri5cy */
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/* @version: 1.0 */
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/* @date: 2018-10-2 */
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/* @build: b180926 */
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/* ------------------------------------------------------------------------- */
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/* */
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/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
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/* Copyright 2016-2018 NXP */
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/* All rights reserved. */
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/* */
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/* SPDX-License-Identifier: BSD-3-Clause */
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// Copyright 2017 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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/*************************************************
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File name: startup_RV32M1_ri5cy.s
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Description:
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Others: take for references
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https://github.com/open-isa-org/open-isa.org
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History:
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1. Date: 2022-02-16
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Author: AIIT XUOS Lab
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Modification:
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*************************************************/
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.extern Rv32m1VgeaStart
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#define EXCEPTION_STACK_SIZE 0x58
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.text
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.section .vectors, "ax"
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.option norvc;
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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jal x0, IRQ_Handler
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// reset vector
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jal x0, Reset_Handler
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// Illegal instrution exception
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jal x0, IllegalInstruction_Handler
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// ecall handler
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jal x0, Ecall_Handler
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// LSU error
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jal x0, LSU_Handler
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.section .startup
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/* Reset Handler */
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Reset_Handler:
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# Disable global interrupt. */
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csrci mstatus, 8
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# initialize stack pointer
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la sp, __StackTop
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# initialize global pointer
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la gp, __global_pointer
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#ifndef __NO_SYSTEM_INIT
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jal SystemInit
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#endif
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# call __libc_init_array
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# Enable global interrupt. */
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# csrsi mstatus, 8
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jal Rv32m1VgeaStart
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ebreak
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.size Reset_Handler, . - Reset_Handler
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.global _init
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.global _fini
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_init:
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_fini:
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ret
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// saves all caller-saved registers (except return address)
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store_regs:
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sw x3, 0x00(x2) // gp
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sw x4, 0x04(x2) // tp
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sw x5, 0x08(x2) // t0
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sw x6, 0x0c(x2) // t1
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sw x7, 0x10(x2) // t2
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sw x10, 0x14(x2) // a0
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sw x11, 0x18(x2) // a1
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sw x12, 0x1c(x2) // a2
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sw x13, 0x20(x2) // a3
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sw x14, 0x24(x2) // a4
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sw x15, 0x28(x2) // a5
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sw x16, 0x2c(x2) // a6
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sw x17, 0x30(x2) // a7
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csrr a0, 0x7B0
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csrr a1, 0x7B1
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csrr a2, 0x7B2
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sw a0, 0x34(x2) // lpstart[0]
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sw a1, 0x38(x2) // lpend[0]
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sw a2, 0x3c(x2) // lpcount[0]
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csrr a0, 0x7B4
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csrr a1, 0x7B5
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csrr a2, 0x7B6
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sw a0, 0x40(x2) // lpstart[1]
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sw a1, 0x44(x2) // lpend[1]
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sw a2, 0x48(x2) // lpcount[1]
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csrr a0, 0x341
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sw a0, 0x4c(x2) // mepc
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csrr a1, 0x300
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sw a1, 0x50(x2) // mstatus
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jalr x0, x1
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// load back registers from stack
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end_except:
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lw a1, 0x50(x2) // mstatus
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csrrw x0, 0x300, a1
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lw a0, 0x4c(x2) // mepc
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csrrw x0, 0x341, a0
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lw a0, 0x40(x2) // lpstart[1]
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lw a1, 0x44(x2) // lpend[1]
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lw a2, 0x48(x2) // lpcount[1]
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csrrw x0, 0x7B4, a0
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csrrw x0, 0x7B5, a1
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csrrw x0, 0x7B6, a2
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lw a0, 0x34(x2) // lpstart[0]
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lw a1, 0x38(x2) // lpend[0]
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lw a2, 0x3c(x2) // lpcount[0]
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csrrw x0, 0x7B0, a0
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csrrw x0, 0x7B1, a1
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csrrw x0, 0x7B2, a2
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lw x3, 0x00(x2) // gp
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lw x4, 0x04(x2) // tp
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lw x5, 0x08(x2) // t0
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lw x6, 0x0c(x2) // t1
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lw x7, 0x10(x2) // t2
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lw x10, 0x14(x2) // a0
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lw x11, 0x18(x2) // a1
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lw x12, 0x1c(x2) // a2
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lw x13, 0x20(x2) // a3
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lw x14, 0x24(x2) // a4
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lw x15, 0x28(x2) // a5
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lw x16, 0x2c(x2) // a6
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lw x17, 0x30(x2) // a7
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lw x1, 0x54(x2)
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addi x2, x2, EXCEPTION_STACK_SIZE
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mret
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.weak IRQ_Handler
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.type IRQ_Handler, %function
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IRQ_Handler:
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addi x2, x2, -EXCEPTION_STACK_SIZE
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sw x1, 0x54(x2)
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jal x1, store_regs
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la x1, end_except
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csrr a0, mcause
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jal x0, SystemIrqHandler
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.size IRQ_Handler, . - IRQ_Handler
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.macro define_exception_entry entry_name handler_name
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.weak \entry_name
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\entry_name:
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addi x2, x2, -EXCEPTION_STACK_SIZE
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sw x1, 0x54(x2)
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jal x1, store_regs
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la x1, end_except
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jal x0, \handler_name
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.endm
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define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc
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define_exception_entry Ecall_Handler Ecall_HandlerFunc
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define_exception_entry LSU_Handler LSU_HandlerFunc
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.weak IllegalInstruction_HandlerFunc
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.type IllegalInstruction_HandlerFunc, %function
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IllegalInstruction_HandlerFunc:
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j .
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.size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc
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.weak Ecall_HandlerFunc
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.type Ecall_HandlerFunc, %function
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Ecall_HandlerFunc:
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j .
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.size Ecall_HandlerFunc, . - Ecall_HandlerFunc
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.weak LSU_HandlerFunc
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.type LSU_HandlerFunc, %function
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LSU_HandlerFunc:
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j .
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.size LSU_HandlerFunc, . - LSU_HandlerFunc
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