forked from xuos/xiuos
132 lines
2.9 KiB
ArmAsm
132 lines
2.9 KiB
ArmAsm
/****************************************************************************//**
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* @file startup_M2354.S
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* @version V1.00
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* @brief CMSIS Device Startup File
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2018-2020 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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/**
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* @file boot.S
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* @brief derived from M2354_SERIES_BSP_CMSIS_V3.00.002
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* @version 1.1
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* @author AIIT XUOS Lab
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* @date 2022-02-23
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*/
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/*************************************************
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File name: boot.S
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Description: Reset and init function
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Others:
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History:
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1. Date: 2022-02-23
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Author: AIIT XUOS Lab
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Modification:
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1. take startup_M2354.S for XiUOS
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*************************************************/
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.syntax unified
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.arch armv8 - m.base
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.fpu softvfp
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.thumb
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Check SecureWorld */
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MOV R0, R15
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LSLS R0, R0, #3
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BMI.N GotoSystemInit
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/* Unlock Register */
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LDR R0, =0x40000100
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LDR R1, =0x59
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STR R1, [R0]
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LDR R1, =0x16
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STR R1, [R0]
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LDR R1, =0x88
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STR R1, [R0]
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/* power gating */
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/* M32(0x400001f4) = 0xfffffffful; */
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LDR R0, =0x400001f4
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LDR R1, =0xffffffff
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STR R1, [R0]
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/* M32(0x400000dC) = 0ul; */
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LDR R0, =0x400000dC
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LDR R1, =0x0
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STR R1, [R0]
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/* Enable GPIO clks, SRAM clks, Trace clk */
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/* CLK->AHBCLK |= (0xffful << 20) | (1ul << 14); */
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LDR R0, =0x40000200
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LDR R1, [R0,#0x4]
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LDR R2, =0xfff02000
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ORRS R1, R1, R2
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STR R1, [R0,#0x4]
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GotoSystemInit:
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/* Lock register */
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LDR R0, =0x40000100
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MOVS R1, #0
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STR R1, [R0]
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2, #4]
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adds r2, r2, #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call the application's entry point.*/
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bl entry
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bx lr
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.size Reset_Handler, .-Reset_Handler
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