forked from xuos/xiuos
148 lines
4.4 KiB
ArmAsm
148 lines
4.4 KiB
ArmAsm
/* ------------------------------------------------------------------------- */
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/* @file: startup_MIMXRT1052.s */
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/* @purpose: CMSIS Cortex-M7 Core Device Startup File */
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/* MIMXRT1052 */
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/* @version: 1.0 */
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/* @date: 2018-9-21 */
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/* @build: b180921 */
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/* ------------------------------------------------------------------------- */
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/* */
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/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
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/* Copyright 2016-2018 NXP */
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/* All rights reserved. */
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/* */
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*****************************************************************************/
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/* Version: GCC for ARM Embedded Processors */
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/*****************************************************************************/
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/**
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* @file boot.S
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* @brief Contex-M7 start function
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2021-05-28
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*/
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/*************************************************
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File name: boot.S
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Description: Contex-M7 start function function
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Others: take startup_MIMXRT1052.s for references
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History:
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1. Date: 2021-05-28
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Author: AIIT XUOS Lab
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Modification:
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1. add OS entry function
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*************************************************/
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.syntax unified
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.arch armv7-m
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.text
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.thumb
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/* Reset Handler */
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.thumb_func
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.align 2
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.globl Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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cpsid i /* Mask interrupts */
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.equ VTOR, 0xE000ED08
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ldr r0, =VTOR
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ldr r1, =__isr_vector
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str r1, [r0]
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ldr r2, [r1]
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msr msp, r2
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#ifndef __NO_SYSTEM_INIT
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ldr r0,=SystemInit
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blx r0
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#endif
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/* Loop to copy data from read only memory to RAM. The ranges
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* of copy from/to are specified by following symbols evaluated in
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* linker script.
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* __etext: End of code section, i.e., begin of data sections to copy from.
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* __data_start__/__data_end__: RAM address range that data should be
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* __noncachedata_start__/__noncachedata_end__ : none cachable region
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* copied to. Both must be aligned to 4 bytes boundary. */
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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#if 1
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/* Here are two copies of loop implemenations. First one favors code size
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* and the second one favors performance. Default uses the first one.
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* Change to "#if 0" to use the second one */
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.LC0:
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cmp r2, r3
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ittt lt
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ldrlt r0, [r1], #4
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strlt r0, [r2], #4
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blt .LC0
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#else
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subs r3, r2
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ble .LC1
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.LC0:
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subs r3, #4
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ldr r0, [r1, r3]
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str r0, [r2, r3]
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bgt .LC0
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.LC1:
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#endif
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#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
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ldr r2, =__noncachedata_start__
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ldr r3, =__noncachedata_init_end__
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#if 1
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.LC2:
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cmp r2, r3
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ittt lt
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ldrlt r0, [r1], #4
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strlt r0, [r2], #4
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blt .LC2
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#else
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subs r3, r2
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ble .LC3
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.LC2:
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subs r3, #4
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ldr r0, [r1, r3]
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str r0, [r2, r3]
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bgt .LC2
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.LC3:
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#endif
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/* zero inited ncache section initialization */
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ldr r3, =__noncachedata_end__
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movs r0,0
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.LC4:
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cmp r2,r3
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itt lt
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strlt r0,[r2],#4
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blt .LC4
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#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
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#ifdef __STARTUP_CLEAR_BSS
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/* This part of work usually is done in C library startup code. Otherwise,
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* define this macro to enable it in this startup.
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*
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* Loop to zero out BSS section, which uses following symbols
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* in linker script:
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* __bss_start__: start of BSS section. Must align to 4
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* __bss_end__: end of BSS section. Must align to 4
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*/
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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movs r0, 0
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.LC5:
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cmp r1, r2
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itt lt
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strlt r0, [r1], #4
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blt .LC5
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#endif /* __STARTUP_CLEAR_BSS */
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ldr r0,=entry
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blx r0
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.size Reset_Handler, . - Reset_Handler |