forked from xuos/xiuos
111 lines
3.6 KiB
ArmAsm
111 lines
3.6 KiB
ArmAsm
/**
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******************************************************************************
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* @file startup_stm32f407xx.s
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* @author MCD Application Team
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* @brief STM32F407xx Devices vector table for GCC based toolchains.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M4 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/**
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* @file boot.S
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* @brief derived from ST standard peripheral library
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2021-04-25
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*/
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/*************************************************
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File name: boot.S
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Description: Reset and init function
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Others:
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History:
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1. Date: 2021-04-29
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Author: AIIT XUOS Lab
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Modification:
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1. take startup_stm32f407xx.s for XiUOS
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*************************************************/
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.syntax unified
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.cpu cortex-m4
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.fpu softvfp
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.thumb
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.word _sidata
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.word _sdata
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.word _edata
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.word __bss_start
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.word __bss_end
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr sp, =__stack_tp
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movs r1, #0
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/* Copy the data segment initializers from flash to SRAM */
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DataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcs DataInitEnd
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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b DataInit
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DataInitEnd:
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ldr r2, =__bss_start
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/* Zero fill the bss segment. */
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BSSInit:
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ldr r3, = __bss_end
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cmp r2, r3
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bcs BSSInitEnd
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movs r3, #0
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str r3, [r2], #4
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b BSSInit
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BSSInitEnd:
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bl SystemInit
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bl entry
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bx lr
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.size Reset_Handler, .-Reset_Handler |