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1,098 Commits 13 Branches 2 Tags
e4f2c3e5aad08e60427115da12bfbfa877b95259
Commit Graph

111 Commits

Author SHA1 Message Date
Liu_Weichao e4f2c3e5aa support uart3 and uart4 on xidatong-arm32 board 2022-09-01 09:23:49 +08:00
Liu_Weichao 5de4b9eec0 add ch438 for xidatong-riscv64 board 2022-09-01 09:20:15 +08:00
Liu_Weichao f55022fc46 delete useless H file on xidatong-riscv64 board 2022-08-31 10:51:14 +08:00
Liu_Weichao 09ff679c4c Merge branch 'prepare_for_master' of https://gitlink.org.cn/xuos/xiuos into sensor_485_function 2022-08-30 14:12:53 +08:00
Liu_Weichao 2756937f88 delete useless kd233 kconfig configuration 2022-08-30 14:11:33 +08:00
xuedongliang f376e568fd optimize xidatong-riscv64 third_party_driver and connection_framework form Liu_weichao 
it is OK
 2022-08-29 11:57:43 +08:00
Liu_Weichao 76017d0d0d delete useless config on riscv-board 2022-08-24 17:33:38 +08:00
Wang_Weigen d5e47d36f4 Merge branch 'prepare_for_master' of https://git.trustie.net/xuos/xiuos into develop 2022-08-19 16:17:35 +08:00
Wang_Weigen 1ce5ee8e8b add imxrt1176-sbc board for xizi 2022-08-19 16:17:19 +08:00
xuedongliang 3ec17025d1 add musl for XiUOS, support arm32 and riscv64 from Tu_yuyang 
it is OK
 2022-08-01 19:58:58 +08:00
TXuian 906398da9f fit musl for riscv64 boards. 2022-07-27 05:42:26 -07:00
TXuian cb4a9d03e0 fit musl for riscv64 boards. 2022-07-27 05:35:56 -07:00
TXuian 214cf55603 fit musl lib for arm boards. 2022-07-26 01:08:20 -07:00
Wang_Weigen d94a57c919 remove critical area operation in shell task to aviod system lag at xidatong-arm board 2022-07-26 14:22:01 +08:00
TXuian e1999f5af9 add get touch coordinate function to xidatong-riscv64. 2022-07-15 01:26:58 -07:00
TXuian 1818e23744 add get touch coordinate function to xidatong-riscv64. 2022-07-15 01:08:18 -07:00
Wang_Weigen 74fd934a02 add xidatong-riscv64 board 2022-07-05 10:54:24 +08:00
xuedongliang 314f162836 Port openPOWERLINK to XiUOS from shi_jia_rui 
it is OK
 2022-07-01 16:12:49 +08:00
Jiacheng Shi c50767094a minor: remove unnecessary changes 2022-06-22 20:10:31 +08:00
Jiacheng Shi 320998dee5 powerlink: implement edrv-xiuos.c 2022-06-22 20:10:31 +08:00
Jiacheng Shi b0e6e4fe49 minor: fix some bugs 2022-06-22 20:10:31 +08:00
Jiacheng Shi b7648f0f08 powerlink: build liboplkmn.a and liboplkcn.a 2022-06-22 20:09:24 +08:00
Jiacheng Shi 7e1307a3bb fix: fix the compilation error on cortex-m4-emulator 2022-06-22 20:08:06 +08:00
Wang_Weigen 578680f6e5 rename board name 'gd32vf103_rvstar' as 'gd32vf103-rvstar' 2022-06-22 17:11:04 +08:00
Wang_Weigen 29a205e467 rename board name 'rv32m1_vega' as 'rv32m1-vega' 2022-06-22 16:42:52 +08:00
Wang_Weigen 42cf1290d1 rename board name 'xidatong' as 'xidatong-arm32' 2022-06-22 15:52:23 +08:00
Wang_Weigen f5f9dbe59d Merge branch 'develop' of https://git.trustie.net/wwg666/xiuos into develop 2022-06-22 15:05:16 +08:00
Wang_Weigen ebf362bc89 Merge branch 'prepare_for_master' of https://git.trustie.net/xuos/xiuos into develop 2022-06-22 14:57:51 +08:00
Wang_Weigen 517825a52f repair the task shcedule failed problem of arm,update the assign task before pendsv fault 2022-06-22 14:57:25 +08:00
Liu_Weichao f0f1b1c988 delete error description and wrong define 2022-06-14 16:43:00 +08:00
Liu_Weichao b3d51efc13 fix pin_mux compile error 2022-06-14 14:46:18 +08:00
Liu_Weichao 8e1f0e1af0 Merge branch 'prepare_for_master' of https://git.trustie.net/xuos/xiuos into xidatong 2022-06-14 14:39:48 +08:00
Wang_Weigen 5f49d2ba87 add config for queue manage 2022-06-14 10:54:08 +08:00
Liu_Weichao 80e08450fe fix compile error include watchdog and uart configure error 2022-06-08 11:09:50 +08:00
Liu_Weichao c14f2f73e0 feat support uart8 and ec200t device on xidatong board 2022-06-08 10:41:21 +08:00
Wang_Weigen 7607282f2a delete usless info 2022-06-02 17:41:59 +08:00
Wang_Weigen d57d8e0a4d repair the timeout problem of i2c interrupt for xidatong 2022-06-02 15:53:24 +08:00
Wang_Weigen 2bd07aa244 1、add i2c driver for xidatong;2、add touch driver for xidatong;3、add input device for lvgl;4、repair interrupt for m7;5、repair startup sequence for xidatong 2022-05-30 16:19:38 +08:00
Runji Wang b9d2ccee80 make XiZi compile on macOS 
Signed-off-by: Runji Wang <wangrunji0408@163.com>
 2022-05-23 17:52:49 +08:00
Liu_Weichao 3c9347b856 feat add ch438 register clear when receiving interrrupts 2022-05-10 13:43:24 +08:00
Wang_Weigen 0267668149 delete unused info 2022-05-07 10:52:36 +08:00
Wang_Weigen 709fbc5a4b sync the upstream 2022-05-07 10:47:23 +08:00
Wang_Weigen 5338598158 add lcd driver for xidatong 2022-05-06 17:53:48 +08:00
Liu_Weichao 67666c1707 feat add watchdog on xidatong board 2022-05-06 15:58:01 +08:00
Liu_Weichao 46291764d4 Merge branch 'prepare_for_master' of https://git.trustie.net/xuos/xiuos into xidatong 2022-04-29 11:02:42 +08:00
Liu_Weichao 808f00ade1 feat add sem obtain wait_time and modify e220 lora receive len operation 2022-04-26 17:57:32 +08:00
zhangcaiqian c4613c8866 Enable LWIP receive timeout, send timeout, and socket forced shutdown 2022-04-26 16:14:13 +08:00
Wang_Weigen afc4b58b74 repair the timeout for sem and mutex 2022-04-26 11:27:44 +08:00
Liu_Weichao 63d26584b7 Merge branch 'prepare_for_master' of https://git.trustie.net/xuos/xiuos into xidatong 2022-04-25 10:53:35 +08:00
Liu_Weichao e5296efa91 fix e220 lora send and receive bug using ch438 uart in xidatong board 2022-04-25 10:52:05 +08:00