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This commit is contained in:
Wang_Weigen 2021-12-07 09:47:13 +08:00
parent b76b1506cd 4405b85eae
commit fa1637ffbd
146 changed files with 64392 additions and 7234 deletions
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2
Ubiquitous/XiUOS/Makefile
View File

@ -5,7 +5,7 @@ MAKEFLAGS += --no-print-directory
.PHONY:COMPILE_APP COMPILE_KERNEL
support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator cortex-m4-emulator ok1052-c gapuino gd32vf103_rvstar
support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator cortex-m4-emulator ok1052-c gapuino stm32f103-nano gd32vf103_rvstar
SRC_DIR:=
export BOARD ?=kd233

4
Ubiquitous/XiUOS/arch/arm/Makefile
View File

@ -5,6 +5,10 @@ ifeq ($(CONFIG_BOARD_CORTEX_M3_EVB),y)
SRC_DIR +=cortex-m3
endif
ifeq ($(CONFIG_BOARD_STM32F103_NANO),y)
SRC_DIR +=cortex-m3
endif
ifeq ($(CONFIG_BOARD_STM32F407_EVB),y)
SRC_DIR +=cortex-m4
endif

10
Ubiquitous/XiUOS/arch/arm/cortex-m3/Makefile
View File

@ -1,3 +1,11 @@
SRC_FILES := boot.c interrupt.c interrupt_vector.S
ifeq ($(CONFIG_BOARD_CORTEX_M3_EVB),y)
SRC_FILES := boot.c interrupt_vector_evb.S
endif
ifeq ($(CONFIG_BOARD_STM32F103_NANO),y)
SRC_FILES := boot.S interrupt_vector_nano.S
endif
SRC_FILES += interrupt.c
include $(KERNEL_ROOT)/compiler.mk

8
Ubiquitous/XiUOS/arch/arm/cortex-m3/arch_interrupt.h
View File

@ -15,12 +15,20 @@
#include <xs_base.h>
#ifdef BOARD_CORTEX_M3_EVB
#define ARCH_MAX_IRQ_NUM (256)
#endif
#ifdef BOARD_STM32F103_NANO
#define ARCH_MAX_IRQ_NUM (64)
#endif
#define ARCH_IRQ_NUM_OFFSET 0
#ifdef BOARD_CORTEX_M3_EVB
#define SYSTICK_IRQN 15
#define UART1_IRQn 21
#endif
int32 ArchEnableHwIrq(uint32 irq_num);
int32 ArchDisableHwIrq(uint32 irq_num);

114
Ubiquitous/XiUOS/arch/arm/cortex-m3/boot.S Normal file
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@ -0,0 +1,114 @@
/**
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
* @file startup_stm32f103xb.s
* @author MCD Application Team
* @brief STM32F103xB Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/**
* @file boot.S
* @brief derived from ST standard peripheral library
* @version 1.1
* @author AIIT XUOS Lab
* @date 2021-11-30
*/
/*************************************************
File name: boot.S
Description: Reset and init function
Others:
History:
1. Date: 2021-11-30
Author: AIIT XUOS Lab
Modification:
1. take startup_stm32f103xb.s for XiUOS
*************************************************/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl entry
bx lr
.size Reset_Handler, .-Reset_Handler

6
Ubiquitous/XiUOS/arch/arm/cortex-m3/interrupt_vector.S → Ubiquitous/XiUOS/arch/arm/cortex-m3/interrupt_vector_evb.S
View File

@ -38,7 +38,7 @@
//*****************************************************************************
/**
* @file interrupt_vector.S
* @file interrupt_vector_evb.S
* @brief derived from Stellaris Firmware Development Package
* @version 1.0
* @author AIIT XUOS Lab
@ -46,7 +46,7 @@
*/
/*************************************************
File name: interrupt_vector.S
File name: interrupt_vector_evb.S
Description: vector table for a Cortex M3
Others:
History:
@ -87,7 +87,7 @@ InterruptVectors:
.word IsrEntry //DebugMon_Handler
.word IsrEntry
.word PendSV_Handler
.word IsrEntry //systick
.word SysTick_Handler //systick
.word IsrEntry // GPIO Port A
.word IsrEntry // GPIO Port B
.word IsrEntry // GPIO Port C

130
Ubiquitous/XiUOS/arch/arm/cortex-m3/interrupt_vector_nano.S Normal file
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@ -0,0 +1,130 @@
/**
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
* @file startup_stm32f103xb.s
* @author MCD Application Team
* @brief STM32F103xB Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/**
* @file interrupt_vector_nano.S
* @brief derived from Stellaris Firmware Development Package
* @version 1.1
* @author AIIT XUOS Lab
* @date 2021-12-02
*/
/*************************************************
File name: interrupt_vector_nano.S
Description: vector table for a stm32f103xb
Others:
History:
1. Date: 2021-12-02
Author: AIIT XUOS Lab
Modification:
1. take startup_stm32f103xb.s for XiUOS reference
*************************************************/
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
//*****************************************************************************
.globl InterruptVectors
/******************************************************************************
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type InterruptVectors, %object
.size InterruptVectors, .-InterruptVectors
InterruptVectors:
.word _sp
.word Reset_Handler
.word NMI_Handler
.word HardFaultHandler
.word MemFaultHandler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word IsrEntry
.word IsrEntry
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word UartIsr1
.word IsrEntry //UartIsr2
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0

2
Ubiquitous/XiUOS/arch/arm/shared/prepare_ahwstack.c
View File

@ -15,7 +15,9 @@
#include <xs_assign.h>
#include "svc_handle.h"
#include <board.h>
#ifdef TOOL_SHELL
#include <shell.h>
#endif
#if (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__))
#define USE_FPU 1

59
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210730193816
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@ -1,59 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_STM32F407_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "stm32f407-st-discovery feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "/XiUOS_stm32f407-st-discovery_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

59
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134238
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@ -1,59 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "stm32f407-st-discovery feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "/XiUOS_stm32f407-st-discovery_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

59
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134239
View File

@ -1,59 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "stm32f407-st-discovery feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "/XiUOS_stm32f407-st-discovery_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

59
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134303
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@ -1,59 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "/XiUOS_stm32f407-st-discovery_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

63
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134546
View File

@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

63
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134553
View File

@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

63
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134554
View File

@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

63
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134556
View File

@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

63
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134557
View File

@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

63
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134558
View File

@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

63
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134605
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@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

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@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

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@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

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@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

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@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

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@ -1,59 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

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@ -1,59 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

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@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

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@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

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@ -1,63 +0,0 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "/XiUOS_cortex-m4-emulator_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

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@ -1,125 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.c
* @brief support stm32f407-st-discovery-board init configure and start-up
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: board.c
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
Others:
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. support stm32f407-st-discovery-board InitBoardHardware
*************************************************/
#include <xiuos.h>
#include "hardware_rcc.h"
#include "board.h"
#include "connect_usart.h"
#include "misc.h"
#include <xs_service.h>
static void ClockConfiguration()
{
int cr,cfgr,pllcfgr;
int cr1,cfgr1,pllcfgr1;
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
RCC_HSEConfig(RCC_HSE_ON);
if (RCC_WaitForHSEStartUp() == SUCCESS)
{
RCC_HCLKConfig(RCC_SYSCLK_Div1);
RCC_PCLK2Config(RCC_HCLK_Div2);
RCC_PCLK1Config(RCC_HCLK_Div4);
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
RCC_PLLCmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
}
SystemCoreClockUpdate();
}
void NVIC_Configuration(void)
{
#ifdef VECT_TAB_RAM
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
#else
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
#endif
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
}
void SysTickConfiguration(void)
{
RCC_ClocksTypeDef rcc_clocks;
uint32 cnts;
RCC_GetClocksFreq(&rcc_clocks);
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
cnts = cnts / 8;
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
}
void SysTick_Handler(int irqn, void *arg)
{
TickAndTaskTimesliceUpdate();
}
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
void InitBoardHardware()
{
int i = 0;
int ret = 0;
ClockConfiguration();
NVIC_Configuration();
SysTickConfiguration();
#ifdef BSP_USING_UART
Stm32HwUsartInit();
#endif
#ifdef KERNEL_CONSOLE
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
RCC_ClocksTypeDef rcc_clocks;
RCC_GetClocksFreq(&rcc_clocks);
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
KPrintf("\nconsole init completed.\n");
KPrintf("board initialization......\n");
#endif
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
}

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@ -1,78 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.h
* @brief define stm32f407-st-discovery-board init configure and start-up function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: board.h
Description: define stm32f407-st-discovery-board board init function and struct
Others:
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. define stm32f407-st-discovery-board InitBoardHardware
2. define stm32f407-st-discovery-board data and bss struct
*************************************************/
#ifndef BOARD_H
#define BOARD_H
#include <stdint.h>
extern int __stack_end__;
extern unsigned int g_service_table_start;
extern unsigned int g_service_table_end;
#define SURPORT_MPU
#define MEMORY_START_ADDRESS (&__stack_end__)
#define MEM_OFFSET 128
#define MEMORY_END_ADDRESS (0x20000000 + MEM_OFFSET * 1024)
#ifdef SEPARATE_COMPILE
typedef int (*main_t)(int argc, char *argv[]);
typedef void (*exit_t)(void);
struct userspace_s
{
main_t us_entrypoint;
exit_t us_taskquit;
uintptr_t us_textstart;
uintptr_t us_textend;
uintptr_t us_datasource;
uintptr_t us_datastart;
uintptr_t us_dataend;
uintptr_t us_bssstart;
uintptr_t us_bssend;
uintptr_t us_heapend;
};
#define USERSPACE (( struct userspace_s *)(0x08080000))
#ifndef SERVICE_TABLE_ADDRESS
#define SERVICE_TABLE_ADDRESS (0x20000000)
#endif
#define USER_SRAM_SIZE 64
#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend)
#define USER_MEMORY_END_ADDRESS (0x10000000 + USER_SRAM_SIZE * 1024)
#endif
void InitBoardHardware(void);
#endif

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@ -1,125 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.c
* @brief support stm32f407-st-discovery-board init configure and start-up
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: board.c
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
Others:
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. support stm32f407-st-discovery-board InitBoardHardware
*************************************************/
#include <xiuos.h>
#include "hardware_rcc.h"
#include "board.h"
#include "connect_usart.h"
#include "misc.h"
#include <xs_service.h>
static void ClockConfiguration()
{
int cr,cfgr,pllcfgr;
int cr1,cfgr1,pllcfgr1;
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
RCC_HSEConfig(RCC_HSE_ON);
if (RCC_WaitForHSEStartUp() == SUCCESS)
{
RCC_HCLKConfig(RCC_SYSCLK_Div1);
RCC_PCLK2Config(RCC_HCLK_Div2);
RCC_PCLK1Config(RCC_HCLK_Div4);
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
RCC_PLLCmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
}
SystemCoreClockUpdate();
}
void NVIC_Configuration(void)
{
#ifdef VECT_TAB_RAM
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
#else
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
#endif
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
}
void SysTickConfiguration(void)
{
RCC_ClocksTypeDef rcc_clocks;
uint32 cnts;
RCC_GetClocksFreq(&rcc_clocks);
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
cnts = cnts / 8;
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
}
void SysTick_Handler(int irqn, void *arg)
{
TickAndTaskTimesliceUpdate();
}
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
void InitBoardHardware()
{
int i = 0;
int ret = 0;
ClockConfiguration();
NVIC_Configuration();
SysTickConfiguration();
#ifdef BSP_USING_UART
InitHwUsart();
#endif
#ifdef KERNEL_CONSOLE
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
RCC_ClocksTypeDef rcc_clocks;
RCC_GetClocksFreq(&rcc_clocks);
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
KPrintf("\nconsole init completed.\n");
KPrintf("board initialization......\n");
#endif
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
}

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@ -1,125 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.c
* @brief support stm32f407-st-discovery-board init configure and start-up
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: board.c
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
Others:
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. support stm32f407-st-discovery-board InitBoardHardware
*************************************************/
#include <xiuos.h>
#include "hardware_rcc.h"
#include "board.h"
#include "connect_usart.h"
#include "misc.h"
#include <xs_service.h>
static void ClockConfiguration()
{
int cr,cfgr,pllcfgr;
int cr1,cfgr1,pllcfgr1;
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
RCC_HSEConfig(RCC_HSE_ON);
if (RCC_WaitForHSEStartUp() == SUCCESS)
{
RCC_HCLKConfig(RCC_SYSCLK_Div1);
RCC_PCLK2Config(RCC_HCLK_Div2);
RCC_PCLK1Config(RCC_HCLK_Div4);
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
RCC_PLLCmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
}
SystemCoreClockUpdate();
}
void NVIC_Configuration(void)
{
#ifdef VECT_TAB_RAM
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
#else
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
#endif
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
}
void SysTickConfiguration(void)
{
RCC_ClocksTypeDef rcc_clocks;
uint32 cnts;
RCC_GetClocksFreq(&rcc_clocks);
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
cnts = cnts / 8;
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
}
void SysTick_Handler(int irqn, void *arg)
{
TickAndTaskTimesliceUpdate();
}
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
void InitBoardHardware()
{
int i = 0;
int ret = 0;
ClockConfiguration();
NVIC_Configuration();
SysTickConfiguration();
#ifdef BSP_USING_UART
InitHwUsart();
#endif
#ifdef KERNEL_CONSOLE
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
RCC_ClocksTypeDef rcc_clocks;
RCC_GetClocksFreq(&rcc_clocks);
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
KPrintf("\nconsole init completed.\n");
KPrintf("board initialization......\n");
#endif
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
}

125
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825135623.c
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@ -1,125 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.c
* @brief support stm32f407-st-discovery-board init configure and start-up
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: board.c
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
Others:
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. support stm32f407-st-discovery-board InitBoardHardware
*************************************************/
#include <xiuos.h>
#include "hardware_rcc.h"
#include "board.h"
#include "connect_usart.h"
#include "misc.h"
#include <xs_service.h>
static void ClockConfiguration()
{
int cr,cfgr,pllcfgr;
int cr1,cfgr1,pllcfgr1;
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
RCC_HSEConfig(RCC_HSE_ON);
if (RCC_WaitForHSEStartUp() == SUCCESS)
{
RCC_HCLKConfig(RCC_SYSCLK_Div1);
RCC_PCLK2Config(RCC_HCLK_Div2);
RCC_PCLK1Config(RCC_HCLK_Div4);
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
RCC_PLLCmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
}
SystemCoreClockUpdate();
}
void NVIC_Configuration(void)
{
#ifdef VECT_TAB_RAM
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
#else
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
#endif
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
}
void SysTickConfiguration(void)
{
RCC_ClocksTypeDef rcc_clocks;
uint32 cnts;
RCC_GetClocksFreq(&rcc_clocks);
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
cnts = cnts / 8;
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
}
void SysTick_Handler(int irqn, void *arg)
{
TickAndTaskTimesliceUpdate();
}
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
void InitBoardHardware()
{
int i = 0;
int ret = 0;
ClockConfiguration();
NVIC_Configuration();
SysTickConfiguration();
#ifdef BSP_USING_UART
InitHwUsart();
#endif
#ifdef KERNEL_CONSOLE
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
RCC_ClocksTypeDef rcc_clocks;
RCC_GetClocksFreq(&rcc_clocks);
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
KPrintf("\nconsole init completed.\n");
KPrintf("board initialization......\n");
#endif
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
}

125
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825140908.c
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@ -1,125 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.c
* @brief support stm32f407-st-discovery-board init configure and start-up
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: board.c
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
Others:
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. support stm32f407-st-discovery-board InitBoardHardware
*************************************************/
#include <xiuos.h>
#include "hardware_rcc.h"
#include "board.h"
#include "connect_usart.h"
#include "misc.h"
#include <xs_service.h>
static void ClockConfiguration()
{
int cr,cfgr,pllcfgr;
int cr1,cfgr1,pllcfgr1;
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
RCC_HSEConfig(RCC_HSE_ON);
if (RCC_WaitForHSEStartUp() == SUCCESS)
{
RCC_HCLKConfig(RCC_SYSCLK_Div1);
RCC_PCLK2Config(RCC_HCLK_Div2);
RCC_PCLK1Config(RCC_HCLK_Div4);
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
RCC_PLLCmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
}
SystemCoreClockUpdate();
}
void NVIC_Configuration(void)
{
#ifdef VECT_TAB_RAM
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
#else
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
#endif
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
}
void SysTickConfiguration(void)
{
RCC_ClocksTypeDef rcc_clocks;
uint32 cnts;
RCC_GetClocksFreq(&rcc_clocks);
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
cnts = cnts / 8;
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
}
void SysTick_Handler(int irqn, void *arg)
{
TickAndTaskTimesliceUpdate();
}
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
void InitBoardHardware()
{
int i = 0;
int ret = 0;
ClockConfiguration();
NVIC_Configuration();
SysTickConfiguration();
#ifdef BSP_USING_UART
InitHwUsart();
#endif
#ifdef KERNEL_CONSOLE
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
RCC_ClocksTypeDef rcc_clocks;
RCC_GetClocksFreq(&rcc_clocks);
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
KPrintf("\nconsole init completed.\n");
KPrintf("board initialization......\n");
#endif
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
}

78
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825210606.h
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@ -1,78 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.h
* @brief define stm32f407-st-discovery-board init configure and start-up function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: board.h
Description: define stm32f407-st-discovery-board board init function and struct
Others:
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. define stm32f407-st-discovery-board InitBoardHardware
2. define stm32f407-st-discovery-board data and bss struct
*************************************************/
#ifndef BOARD_H
#define BOARD_H
#include <stdint.h>
extern int __stack_end__;
extern unsigned int g_service_table_start;
extern unsigned int g_service_table_end;
#define SURPORT_MPU
#define MEMORY_START_ADDRESS (&__stack_end__)
#define MEM_OFFSET 128
#define MEMORY_END_ADDRESS (0x20000000 + MEM_OFFSET * 1024)
#ifdef SEPARATE_COMPILE
typedef int (*main_t)(int argc, char *argv[]);
typedef void (*exit_t)(void);
struct userspace_s
{
main_t us_entrypoint;
exit_t us_taskquit;
uintptr_t us_textstart;
uintptr_t us_textend;
uintptr_t us_datasource;
uintptr_t us_datastart;
uintptr_t us_dataend;
uintptr_t us_bssstart;
uintptr_t us_bssend;
uintptr_t us_heapend;
};
#define USERSPACE (( struct userspace_s *)(0x08080000))
#ifndef SERVICE_TABLE_ADDRESS
#define SERVICE_TABLE_ADDRESS (0x20000000)
#endif
#define USER_SRAM_SIZE 64
#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend)
#define USER_MEMORY_END_ADDRESS (0x10000000 + USER_SRAM_SIZE * 1024)
#endif
void InitBoardHardware(void);
#endif

125
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210826182559.c
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@ -1,125 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.c
* @brief support stm32f407-st-discovery-board init configure and start-up
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: board.c
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
Others:
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. support stm32f407-st-discovery-board InitBoardHardware
*************************************************/
#include <xiuos.h>
#include "hardware_rcc.h"
#include "board.h"
#include "connect_usart.h"
#include "misc.h"
#include <xs_service.h>
static void ClockConfiguration()
{
int cr,cfgr,pllcfgr;
int cr1,cfgr1,pllcfgr1;
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
RCC_HSEConfig(RCC_HSE_ON);
if (RCC_WaitForHSEStartUp() == SUCCESS)
{
RCC_HCLKConfig(RCC_SYSCLK_Div1);
RCC_PCLK2Config(RCC_HCLK_Div2);
RCC_PCLK1Config(RCC_HCLK_Div4);
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
RCC_PLLCmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
}
SystemCoreClockUpdate();
}
void NVIC_Configuration(void)
{
#ifdef VECT_TAB_RAM
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
#else
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
#endif
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
}
void SysTickConfiguration(void)
{
RCC_ClocksTypeDef rcc_clocks;
uint32 cnts;
RCC_GetClocksFreq(&rcc_clocks);
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
cnts = cnts / 8;
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
}
void SysTick_Handler(int irqn, void *arg)
{
TickAndTaskTimesliceUpdate();
}
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
void InitBoardHardware()
{
int i = 0;
int ret = 0;
ClockConfiguration();
NVIC_Configuration();
SysTickConfiguration();
#ifdef BSP_USING_UART
Stm32HwUsartInit();
#endif
#ifdef KERNEL_CONSOLE
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
RCC_ClocksTypeDef rcc_clocks;
RCC_GetClocksFreq(&rcc_clocks);
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
KPrintf("\nconsole init completed.\n");
KPrintf("board initialization......\n");
#endif
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
}

125
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210826182600.c
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@ -1,125 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.c
* @brief support stm32f407-st-discovery-board init configure and start-up
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: board.c
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
Others:
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. support stm32f407-st-discovery-board InitBoardHardware
*************************************************/
#include <xiuos.h>
#include "hardware_rcc.h"
#include "board.h"
#include "connect_usart.h"
#include "misc.h"
#include <xs_service.h>
static void ClockConfiguration()
{
int cr,cfgr,pllcfgr;
int cr1,cfgr1,pllcfgr1;
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
RCC_HSEConfig(RCC_HSE_ON);
if (RCC_WaitForHSEStartUp() == SUCCESS)
{
RCC_HCLKConfig(RCC_SYSCLK_Div1);
RCC_PCLK2Config(RCC_HCLK_Div2);
RCC_PCLK1Config(RCC_HCLK_Div4);
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
RCC_PLLCmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
}
SystemCoreClockUpdate();
}
void NVIC_Configuration(void)
{
#ifdef VECT_TAB_RAM
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
#else
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
#endif
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
}
void SysTickConfiguration(void)
{
RCC_ClocksTypeDef rcc_clocks;
uint32 cnts;
RCC_GetClocksFreq(&rcc_clocks);
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
cnts = cnts / 8;
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
}
void SysTick_Handler(int irqn, void *arg)
{
TickAndTaskTimesliceUpdate();
}
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
void InitBoardHardware()
{
int i = 0;
int ret = 0;
ClockConfiguration();
NVIC_Configuration();
SysTickConfiguration();
#ifdef BSP_USING_UART
Stm32HwUsartInit();
#endif
#ifdef KERNEL_CONSOLE
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
RCC_ClocksTypeDef rcc_clocks;
RCC_GetClocksFreq(&rcc_clocks);
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
KPrintf("\nconsole init completed.\n");
KPrintf("board initialization......\n");
#endif
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
}

125
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210826182601.c
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@ -1,125 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.c
* @brief support stm32f407-st-discovery-board init configure and start-up
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: board.c
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
Others:
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. support stm32f407-st-discovery-board InitBoardHardware
*************************************************/
#include <xiuos.h>
#include "hardware_rcc.h"
#include "board.h"
#include "connect_usart.h"
#include "misc.h"
#include <xs_service.h>
static void ClockConfiguration()
{
int cr,cfgr,pllcfgr;
int cr1,cfgr1,pllcfgr1;
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
RCC_HSEConfig(RCC_HSE_ON);
if (RCC_WaitForHSEStartUp() == SUCCESS)
{
RCC_HCLKConfig(RCC_SYSCLK_Div1);
RCC_PCLK2Config(RCC_HCLK_Div2);
RCC_PCLK1Config(RCC_HCLK_Div4);
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
RCC_PLLCmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
}
SystemCoreClockUpdate();
}
void NVIC_Configuration(void)
{
#ifdef VECT_TAB_RAM
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
#else
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
#endif
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
}
void SysTickConfiguration(void)
{
RCC_ClocksTypeDef rcc_clocks;
uint32 cnts;
RCC_GetClocksFreq(&rcc_clocks);
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
cnts = cnts / 8;
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
}
void SysTick_Handler(int irqn, void *arg)
{
TickAndTaskTimesliceUpdate();
}
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
void InitBoardHardware()
{
int i = 0;
int ret = 0;
ClockConfiguration();
NVIC_Configuration();
SysTickConfiguration();
#ifdef BSP_USING_UART
Stm32HwUsartInit();
#endif
#ifdef KERNEL_CONSOLE
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
RCC_ClocksTypeDef rcc_clocks;
RCC_GetClocksFreq(&rcc_clocks);
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
KPrintf("\nconsole init completed.\n");
KPrintf("board initialization......\n");
#endif
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
}

17
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210824125750.mk
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export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
export DEFINES := -DHAVE_CCONFIG_H -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
export USING_NEWLIB =1
export USING_VFS = 1
export USING_SPI = 1
export ARCH = arm
export USING_LORA = 1

14
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210825140049.mk
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export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
export DEFINES := -DHAVE_CCONFIG_H -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
export ARCH = arm
export USING_LORA = 1

14
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210825140050.mk
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export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
export DEFINES := -DHAVE_CCONFIG_H -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
export ARCH = arm
export USING_LORA = 1

14
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210825140057.mk
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export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
export DEFINES := -DHAVE_CCONFIG_H
export ARCH = arm
export USING_LORA = 1

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Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210825140058.mk
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export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
export DEFINES := -DHAVE_CCONFIG_H
export ARCH = arm
export USING_LORA = 1

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Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/include/connect_usart_20210730193816.h
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_usart.h
* @brief define stm32f407-st-discovery-board usart function and struct
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
#ifndef CONNECT_USART_H
#define CONNECT_USART_H
#include <device.h>
#include "hardware_usart.h"
#include "hardware_dma.h"
#ifdef __cplusplus
extern "C" {
#endif
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
struct UsartHwCfg
{
USART_TypeDef *uart_device;
IRQn_Type irq;
};
struct Stm32Usart
{
struct Stm32UsartDma
{
DMA_Stream_TypeDef *RxStream;
uint32 RxCh;
uint32 RxFlag;
uint8 RxIrqCh;
x_size_t SettingRecvLen;
x_size_t LastRecvIndex;
} dma;
struct SerialBus serial_bus;
};
int Stm32HwUsartInit(void);
#ifdef __cplusplus
}
#endif
#endif

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Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/uart/connect_usart_20210730193816.c
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/*
* Copyright (c) 2020 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
/**
* @file connect_usart.c
* @brief support stm32f407-st-discovery-board usart function and register to bus framework
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: connect_uart.c
Description: support stm32f407-st-discovery-board usart configure and uart bus register function
Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. support stm32f407-st-discovery-board usart configure, write and read
2. support stm32f407-st-discovery-board usart bus device and driver register
*************************************************/
#include "stm32f4xx.h"
#include "board.h"
#include "misc.h"
#include "connect_usart.h"
#include "hardware_gpio.h"
#include "hardware_rcc.h"
/* UART GPIO define. */
#define UART1_GPIO_TX GPIO_Pin_6
#define UART1_TX_PIN_SOURCE GPIO_PinSource6
#define UART1_GPIO_RX GPIO_Pin_7
#define UART1_RX_PIN_SOURCE GPIO_PinSource7
#define UART1_GPIO GPIOB
#define UART1_GPIO_RCC RCC_AHB1Periph_GPIOB
#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
#define UART2_GPIO_TX GPIO_Pin_2
#define UART2_TX_PIN_SOURCE GPIO_PinSource2
#define UART2_GPIO_RX GPIO_Pin_3
#define UART2_RX_PIN_SOURCE GPIO_PinSource3
#define UART2_GPIO GPIOA
#define UART2_GPIO_RCC RCC_AHB1Periph_GPIOA
#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
#define UART3_GPIO_TX GPIO_Pin_8
#define UART3_TX_PIN_SOURCE GPIO_PinSource8
#define UART3_GPIO_RX GPIO_Pin_9
#define UART3_RX_PIN_SOURCE GPIO_PinSource9
#define UART3_GPIO GPIOD
#define UART3_GPIO_RCC RCC_AHB1Periph_GPIOD
#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
#define UART4_GPIO_TX GPIO_Pin_10
#define UART4_TX_PIN_SOURCE GPIO_PinSource10
#define UART4_GPIO_RX GPIO_Pin_11
#define UART4_RX_PIN_SOURCE GPIO_PinSource11
#define UART4_GPIO GPIOC
#define UART4_GPIO_RCC RCC_AHB1Periph_GPIOC
#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4
#define UART5_GPIO_TX GPIO_Pin_12
#define UART5_TX_PIN_SOURCE GPIO_PinSource12
#define UART5_GPIO_RX GPIO_Pin_2
#define UART5_RX_PIN_SOURCE GPIO_PinSource2
#define UART5_TX GPIOC
#define UART5_RX GPIOD
#define UART5_GPIO_RCC_TX RCC_AHB1Periph_GPIOC
#define UART5_GPIO_RCC_RX RCC_AHB1Periph_GPIOD
#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5
#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n))
#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n))
static void RCCConfiguration(void)
{
#ifdef BSP_USING_USART1
RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
#endif
#ifdef BSP_USING_USART2
RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
#endif
#ifdef BSP_USING_USART3
RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
#endif
#ifdef BSP_USING_UART4
RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE);
#endif
#ifdef BSP_USING_UART5
RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE);
#endif
}
static void GPIOConfiguration(void)
{
GPIO_InitTypeDef gpio_initstructure;
gpio_initstructure.GPIO_Mode = GPIO_Mode_AF;
gpio_initstructure.GPIO_OType = GPIO_OType_PP;
gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP;
gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz;
#ifdef BSP_USING_USART1
gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1);
GPIO_Init(UART1_GPIO, &gpio_initstructure);
#endif
#ifdef BSP_USING_USART2
gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX;
GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2);
GPIO_Init(UART2_GPIO, &gpio_initstructure);
#endif
#ifdef BSP_USING_USART3
gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX;
GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3);
GPIO_Init(UART3_GPIO, &gpio_initstructure);
#endif
#ifdef BSP_USING_UART4
gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX;
GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4);
GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4);
GPIO_Init(UART4_GPIO, &gpio_initstructure);
#endif
#ifdef BSP_USING_UART5
gpio_initstructure.GPIO_Pin = UART5_GPIO_TX;
GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5);
GPIO_Init(UART5_TX, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = UART5_GPIO_RX;
GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5);
GPIO_Init(UART5_RX, &gpio_initstructure);
#endif
}
static void NVIC_Configuration(IRQn_Type irq)
{
NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = irq;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr)
{
DMA_InitTypeDef DMA_InitStructure;
dma->SettingRecvLen = SettingRecvLen;
DMA_DeInit(dma->RxStream);
while (DMA_GetCmdStatus(dma->RxStream) != DISABLE);
DMA_InitStructure.DMA_Channel = dma->RxCh;
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR);
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_Init(dma->RxStream, &DMA_InitStructure);
}
static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
{
struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
struct Stm32UsartDma *dma = &serial->dma;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
NVIC_InitTypeDef NVIC_InitStructure;
USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer);
DMA_ClearFlag(dma->RxStream, dma->RxFlag);
DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE);
USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE);
DMA_Cmd(dma->RxStream, ENABLE);
NVIC_InitStructure.NVIC_IRQChannel = dma->RxIrqCh;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
{
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
}
if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
}
if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
}
if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
}
if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
}
if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
}
if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
}
static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(serial_drv);
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if (configure_info->private_data) {
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
USART_InitTypeDef USART_InitStructure;
USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
} else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
}
if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
USART_InitStructure.USART_StopBits = USART_StopBits_1;
} else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
USART_InitStructure.USART_StopBits = USART_StopBits_2;
}
if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
USART_InitStructure.USART_Parity = USART_Parity_No;
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
USART_InitStructure.USART_Parity = USART_Parity_Odd;
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
USART_InitStructure.USART_Parity = USART_Parity_Even;
}
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure);
USART_Cmd(serial_hw_cfg->uart_device, ENABLE);
return EOK;
}
static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
{
NULL_PARAM_CHECK(serial_drv);
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
switch (serial_operation_cmd)
{
case OPER_CLR_INT:
UART_DISABLE_IRQ(serial_hw_cfg->irq);
USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE);
break;
case OPER_SET_INT:
UART_ENABLE_IRQ(serial_hw_cfg->irq);
USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE);
break;
case OPER_CONFIG :
if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode){
DMAConfiguration(serial_dev, serial_hw_cfg->uart_device);
}
}
return EOK;
}
static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c)
{
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE));
serial_hw_cfg->uart_device->DR = c;
return EOK;
}
static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
{
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
int ch = -1;
if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
ch = serial_hw_cfg->uart_device->DR & 0xff;
}
return ch;
}
static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device)
{
x_base level = CriticalAreaLock();
x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream);
x_size_t recv_len = recv_total_index - dma->LastRecvIndex;
dma->LastRecvIndex = recv_total_index;
CriticalAreaUnLock(level);
if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
USART_ReceiveData(uart_device);
}
static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
{
struct Stm32UsartDma *dma = &serial->dma;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
x_base level = CriticalAreaLock();
x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
dma->LastRecvIndex = 0;
CriticalAreaUnLock(level);
if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
DMA_ClearFlag(dma->RxStream, dma->RxFlag);
}
}
static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
{
struct Stm32UsartDma *dma = &serial->dma;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
}
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
}
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
}
if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
USART_ReceiveData(serial_hw_cfg->uart_device);
}
}
#ifdef BSP_USING_USART1
struct Stm32Usart serial_1;
struct SerialDriver serial_driver_1;
struct SerialHardwareDevice serial_device_1;
static const struct Stm32UsartDma usart_dma_1 =
{
DMA2_Stream5,
DMA_Channel_4,
DMA_FLAG_TCIF5,
DMA2_Stream5_IRQn,
0,
0,
};
void USART1_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_1, &serial_driver_1, &serial_device_1);
}
DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE);
void DMA2_Stream5_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1);
}
DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE);
#endif
#ifdef BSP_USING_USART2
struct Stm32Usart serial_2;
struct SerialDriver serial_driver_2;
struct SerialHardwareDevice serial_device_2;
static const struct Stm32UsartDma usart_dma_2 =
{
DMA1_Stream5,
DMA_Channel_4,
DMA_FLAG_TCIF5,
DMA1_Stream5_IRQn,
0,
0,
};
void USART2_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_2, &serial_driver_2, &serial_device_2);
}
DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE);
void DMA1_Stream5_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2);
}
DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE);
#endif
#ifdef BSP_USING_USART3
struct Stm32Usart serial_3;
struct SerialDriver serial_driver_3;
struct SerialHardwareDevice serial_device_3;
static const struct Stm32UsartDma usart_dma_3 =
{
DMA1_Stream1,
DMA_Channel_4,
DMA_FLAG_TCIF1,
DMA1_Stream1_IRQn,
0,
0,
};
void USART3_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_3, &serial_driver_3, &serial_device_3);
}
DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE);
void DMA1_Stream1_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3);
}
DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE);
#endif
#ifdef BSP_USING_UART4
struct Stm32Usart serial_4;
struct SerialDriver serial_driver_4;
struct SerialHardwareDevice serial_device_4;
static const struct Stm32UsartDma uart_dma_4 =
{
DMA1_Stream2,
DMA_Channel_4,
DMA_FLAG_TCIF2,
DMA1_Stream2_IRQn,
0,
0,
};
void UART4_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_4, &serial_driver_4, &serial_device_4);
}
DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE);
void DMA1_Stream2_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4);
}
DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
#endif
#ifdef BSP_USING_UART5
struct Stm32Usart serial_5;
struct SerialDriver serial_driver_5;
struct SerialHardwareDevice serial_device_5;
static const struct Stm32UsartDma uart_dma_5 =
{
DMA1_Stream0,
DMA_Channel_4,
DMA_FLAG_TCIF0,
DMA1_Stream0_IRQn,
0,
0,
};
void UART5_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_5, &serial_driver_5, &serial_device_5);
}
DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE);
void DMA1_Stream0_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5);
}
DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE);
#endif
static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
x_err_t ret = EOK;
int serial_operation_cmd;
struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = Stm32SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
}
return ret;
}
static const struct SerialDataCfg data_cfg_init =
{
.serial_baud_rate = BAUD_RATE_115200,
.serial_data_bits = DATA_BITS_8,
.serial_stop_bits = STOP_BITS_1,
.serial_parity_mode = PARITY_NONE,
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
};
/*manage the serial device operations*/
static const struct SerialDrvDone drv_done =
{
.init = Stm32SerialInit,
.configure = Stm32SerialConfigure,
};
/*manage the serial device hal operations*/
static struct SerialHwDevDone hwdev_done =
{
.put_char = Stm32SerialPutchar,
.get_char = Stm32SerialGetchar,
};
static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
{
x_err_t ret = EOK;
/*Init the serial bus */
ret = SerialBusInit(serial_bus, bus_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
return ERROR;
}
/*Init the serial driver*/
ret = SerialDriverInit(serial_driver, drv_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the serial driver to the serial bus*/
ret = SerialDriverAttachToBus(drv_name, bus_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
return ERROR;
}
return ret;
}
/*Attach the serial device to the serial bus*/
static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
{
x_err_t ret = EOK;
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
return ERROR;
}
ret = SerialDeviceAttachToBus(dev_name, bus_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
return ERROR;
}
return ret;
}
int InitHwUsart(void)
{
x_err_t ret = EOK;
RCCConfiguration();
GPIOConfiguration();
#ifdef BSP_USING_USART1
static struct SerialCfgParam serial_cfg_1;
memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_1;
memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_1;
memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
serial_1.dma = usart_dma_1;
serial_driver_1.drv_done = &drv_done;
serial_driver_1.configure = &Stm32SerialDrvConfigure;
serial_device_1.hwdev_done = &hwdev_done;
serial_cfg_1.data_cfg = data_cfg_init;
serial_hw_cfg_1.uart_device = USART1;
serial_hw_cfg_1.irq = USART1_IRQn;
serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1;
serial_driver_1.private_data = (void *)&serial_cfg_1;
serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
NVIC_Configuration(serial_hw_cfg_1.irq);
ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
if (EOK != ret) {
KPrintf("InitHwUsart usart1 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart1 error ret %u\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_USART2
static struct SerialCfgParam serial_cfg_2;
memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_2;
memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_2;
memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
serial_2.dma = usart_dma_2;
serial_driver_2.drv_done = &drv_done;
serial_driver_2.configure = &Stm32SerialDrvConfigure;
serial_device_2.hwdev_done = &hwdev_done;
serial_cfg_2.data_cfg = data_cfg_init;
serial_hw_cfg_2.uart_device = USART2;
serial_hw_cfg_2.irq = USART2_IRQn;
serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2;
serial_driver_2.private_data = (void *)&serial_cfg_2;
serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
NVIC_Configuration(serial_hw_cfg_2.irq);
ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
if (EOK != ret) {
KPrintf("InitHwUsart usart2 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart2 error ret %u\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_USART3
static struct SerialCfgParam serial_cfg_3;
memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_3;
memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_3;
memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam));
serial_3.dma = usart_dma_3;
serial_driver_3.drv_done = &drv_done;
serial_driver_3.configure = &Stm32SerialDrvConfigure;
serial_device_3.hwdev_done = &hwdev_done;
serial_cfg_3.data_cfg = data_cfg_init;
serial_hw_cfg_3.uart_device = USART3;
serial_hw_cfg_3.irq = USART3_IRQn;
serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3;
serial_driver_3.private_data = (void *)&serial_cfg_3;
serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_3.haldev.private_data = (void *)&serial_dev_param_3;
NVIC_Configuration(serial_hw_cfg_3.irq);
ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
if (EOK != ret) {
KPrintf("InitHwUsart usart3 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart3 error ret %u\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_UART4
static struct SerialCfgParam serial_cfg_4;
memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_4;
memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_4;
memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam));
serial_4.dma = uart_dma_4;
serial_driver_4.drv_done = &drv_done;
serial_driver_4.configure = &Stm32SerialDrvConfigure;
serial_device_4.hwdev_done = &hwdev_done;
serial_cfg_4.data_cfg = data_cfg_init;
serial_hw_cfg_4.uart_device = UART4;
serial_hw_cfg_4.irq = UART4_IRQn;
serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4;
serial_driver_4.private_data = (void *)&serial_cfg_4;
serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_4.haldev.private_data = (void *)&serial_dev_param_4;
NVIC_Configuration(serial_hw_cfg_4.irq);
ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
if (EOK != ret) {
KPrintf("InitHwUsart usart4 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart4 error ret %u\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_UART5
static struct SerialCfgParam serial_cfg_5;
memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_5;
memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_5;
memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam));
serial_5.dma = uart_dma_5;
serial_driver_5.drv_done = &drv_done;
serial_driver_5.configure = &Stm32SerialDrvConfigure;
serial_device_5.hwdev_done = &hwdev_done;
serial_cfg_5.data_cfg = data_cfg_init;
serial_hw_cfg_5.uart_device = UART5;
serial_hw_cfg_5.irq = UART5_IRQn;
serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5;
serial_driver_5.private_data = (void *)&serial_cfg_5;
serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_5.haldev.private_data = (void *)&serial_dev_param_5;
NVIC_Configuration(serial_hw_cfg_5.irq);
ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
if (EOK != ret) {
KPrintf("InitHwUsart usart5 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart5 error ret %u\n", ret);
return ERROR;
}
#endif
return ret;
}

858
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/uart/connect_usart_20210825135244.c
View File

@ -1,858 +0,0 @@
/*
* Copyright (c) 2020 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
/**
* @file connect_usart.c
* @brief support stm32f407-st-discovery-board usart function and register to bus framework
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: connect_uart.c
Description: support stm32f407-st-discovery-board usart configure and uart bus register function
Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. support stm32f407-st-discovery-board usart configure, write and read
2. support stm32f407-st-discovery-board usart bus device and driver register
*************************************************/
#include "stm32f4xx.h"
#include "board.h"
#include "misc.h"
#include "connect_usart.h"
#include "hardware_gpio.h"
#include "hardware_rcc.h"
/* UART GPIO define. */
#define UART1_GPIO_TX GPIO_Pin_6
#define UART1_TX_PIN_SOURCE GPIO_PinSource6
#define UART1_GPIO_RX GPIO_Pin_7
#define UART1_RX_PIN_SOURCE GPIO_PinSource7
#define UART1_GPIO GPIOB
#define UART1_GPIO_RCC RCC_AHB1Periph_GPIOB
#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
#define UART2_GPIO_TX GPIO_Pin_2
#define UART2_TX_PIN_SOURCE GPIO_PinSource2
#define UART2_GPIO_RX GPIO_Pin_3
#define UART2_RX_PIN_SOURCE GPIO_PinSource3
#define UART2_GPIO GPIOA
#define UART2_GPIO_RCC RCC_AHB1Periph_GPIOA
#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
#define UART3_GPIO_TX GPIO_Pin_8
#define UART3_TX_PIN_SOURCE GPIO_PinSource8
#define UART3_GPIO_RX GPIO_Pin_9
#define UART3_RX_PIN_SOURCE GPIO_PinSource9
#define UART3_GPIO GPIOD
#define UART3_GPIO_RCC RCC_AHB1Periph_GPIOD
#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
#define UART4_GPIO_TX GPIO_Pin_10
#define UART4_TX_PIN_SOURCE GPIO_PinSource10
#define UART4_GPIO_RX GPIO_Pin_11
#define UART4_RX_PIN_SOURCE GPIO_PinSource11
#define UART4_GPIO GPIOC
#define UART4_GPIO_RCC RCC_AHB1Periph_GPIOC
#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4
#define UART5_GPIO_TX GPIO_Pin_12
#define UART5_TX_PIN_SOURCE GPIO_PinSource12
#define UART5_GPIO_RX GPIO_Pin_2
#define UART5_RX_PIN_SOURCE GPIO_PinSource2
#define UART5_TX GPIOC
#define UART5_RX GPIOD
#define UART5_GPIO_RCC_TX RCC_AHB1Periph_GPIOC
#define UART5_GPIO_RCC_RX RCC_AHB1Periph_GPIOD
#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5
#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n))
#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n))
static void RCCConfiguration(void)
{
#ifdef BSP_USING_USART1
RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
#endif
#ifdef BSP_USING_USART2
RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
#endif
#ifdef BSP_USING_USART3
RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
#endif
#ifdef BSP_USING_UART4
RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE);
#endif
#ifdef BSP_USING_UART5
RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE);
#endif
}
static void GPIOConfiguration(void)
{
GPIO_InitTypeDef gpio_initstructure;
gpio_initstructure.GPIO_Mode = GPIO_Mode_AF;
gpio_initstructure.GPIO_OType = GPIO_OType_PP;
gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP;
gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz;
#ifdef BSP_USING_USART1
gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1);
GPIO_Init(UART1_GPIO, &gpio_initstructure);
#endif
#ifdef BSP_USING_USART2
gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX;
GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2);
GPIO_Init(UART2_GPIO, &gpio_initstructure);
#endif
#ifdef BSP_USING_USART3
gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX;
GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3);
GPIO_Init(UART3_GPIO, &gpio_initstructure);
#endif
#ifdef BSP_USING_UART4
gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX;
GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4);
GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4);
GPIO_Init(UART4_GPIO, &gpio_initstructure);
#endif
#ifdef BSP_USING_UART5
gpio_initstructure.GPIO_Pin = UART5_GPIO_TX;
GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5);
GPIO_Init(UART5_TX, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = UART5_GPIO_RX;
GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5);
GPIO_Init(UART5_RX, &gpio_initstructure);
#endif
}
static void NVIC_Configuration(IRQn_Type irq)
{
NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = irq;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr)
{
DMA_InitTypeDef DMA_InitStructure;
dma->SettingRecvLen = SettingRecvLen;
DMA_DeInit(dma->RxStream);
while (DMA_GetCmdStatus(dma->RxStream) != DISABLE);
DMA_InitStructure.DMA_Channel = dma->RxCh;
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR);
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_Init(dma->RxStream, &DMA_InitStructure);
}
static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
{
struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
struct Stm32UsartDma *dma = &serial->dma;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
NVIC_InitTypeDef NVIC_InitStructure;
USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer);
DMA_ClearFlag(dma->RxStream, dma->RxFlag);
DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE);
USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE);
DMA_Cmd(dma->RxStream, ENABLE);
NVIC_InitStructure.NVIC_IRQChannel = dma->RxIrqCh;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
{
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
}
if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
}
if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
}
if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
}
if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
}
if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
}
if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
}
static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(serial_drv);
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if (configure_info->private_data) {
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
USART_InitTypeDef USART_InitStructure;
USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
} else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
}
if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
USART_InitStructure.USART_StopBits = USART_StopBits_1;
} else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
USART_InitStructure.USART_StopBits = USART_StopBits_2;
}
if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
USART_InitStructure.USART_Parity = USART_Parity_No;
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
USART_InitStructure.USART_Parity = USART_Parity_Odd;
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
USART_InitStructure.USART_Parity = USART_Parity_Even;
}
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure);
USART_Cmd(serial_hw_cfg->uart_device, ENABLE);
return EOK;
}
static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
{
NULL_PARAM_CHECK(serial_drv);
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
switch (serial_operation_cmd)
{
case OPER_CLR_INT:
UART_DISABLE_IRQ(serial_hw_cfg->irq);
USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE);
break;
case OPER_SET_INT:
UART_ENABLE_IRQ(serial_hw_cfg->irq);
USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE);
break;
case OPER_CONFIG :
if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode){
DMAConfiguration(serial_dev, serial_hw_cfg->uart_device);
}
}
return EOK;
}
static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c)
{
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE));
serial_hw_cfg->uart_device->DR = c;
return EOK;
}
static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
{
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
int ch = -1;
if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
ch = serial_hw_cfg->uart_device->DR & 0xff;
}
return ch;
}
static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device)
{
x_base level = CriticalAreaLock();
x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream);
x_size_t recv_len = recv_total_index - dma->LastRecvIndex;
dma->LastRecvIndex = recv_total_index;
CriticalAreaUnLock(level);
if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
USART_ReceiveData(uart_device);
}
static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
{
struct Stm32UsartDma *dma = &serial->dma;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
x_base level = CriticalAreaLock();
x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
dma->LastRecvIndex = 0;
CriticalAreaUnLock(level);
if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
DMA_ClearFlag(dma->RxStream, dma->RxFlag);
}
}
static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
{
struct Stm32UsartDma *dma = &serial->dma;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
}
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
}
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
}
if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
USART_ReceiveData(serial_hw_cfg->uart_device);
}
}
#ifdef BSP_USING_USART1
struct Stm32Usart serial_1;
struct SerialDriver serial_driver_1;
struct SerialHardwareDevice serial_device_1;
static const struct Stm32UsartDma usart_dma_1 =
{
DMA2_Stream5,
DMA_Channel_4,
DMA_FLAG_TCIF5,
DMA2_Stream5_IRQn,
0,
0,
};
void USART1_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_1, &serial_driver_1, &serial_device_1);
}
DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE);
void DMA2_Stream5_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1);
}
DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE);
#endif
#ifdef BSP_USING_USART2
struct Stm32Usart serial_2;
struct SerialDriver serial_driver_2;
struct SerialHardwareDevice serial_device_2;
static const struct Stm32UsartDma usart_dma_2 =
{
DMA1_Stream5,
DMA_Channel_4,
DMA_FLAG_TCIF5,
DMA1_Stream5_IRQn,
0,
0,
};
void USART2_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_2, &serial_driver_2, &serial_device_2);
}
DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE);
void DMA1_Stream5_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2);
}
DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE);
#endif
#ifdef BSP_USING_USART3
struct Stm32Usart serial_3;
struct SerialDriver serial_driver_3;
struct SerialHardwareDevice serial_device_3;
static const struct Stm32UsartDma usart_dma_3 =
{
DMA1_Stream1,
DMA_Channel_4,
DMA_FLAG_TCIF1,
DMA1_Stream1_IRQn,
0,
0,
};
void USART3_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_3, &serial_driver_3, &serial_device_3);
}
DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE);
void DMA1_Stream1_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3);
}
DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE);
#endif
#ifdef BSP_USING_UART4
struct Stm32Usart serial_4;
struct SerialDriver serial_driver_4;
struct SerialHardwareDevice serial_device_4;
static const struct Stm32UsartDma uart_dma_4 =
{
DMA1_Stream2,
DMA_Channel_4,
DMA_FLAG_TCIF2,
DMA1_Stream2_IRQn,
0,
0,
};
void UART4_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_4, &serial_driver_4, &serial_device_4);
}
DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE);
void DMA1_Stream2_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4);
}
DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
#endif
#ifdef BSP_USING_UART5
struct Stm32Usart serial_5;
struct SerialDriver serial_driver_5;
struct SerialHardwareDevice serial_device_5;
static const struct Stm32UsartDma uart_dma_5 =
{
DMA1_Stream0,
DMA_Channel_4,
DMA_FLAG_TCIF0,
DMA1_Stream0_IRQn,
0,
0,
};
void UART5_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_5, &serial_driver_5, &serial_device_5);
}
DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE);
void DMA1_Stream0_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5);
}
DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE);
#endif
static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
x_err_t ret = EOK;
int serial_operation_cmd;
struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = Stm32SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
}
return ret;
}
static const struct SerialDataCfg data_cfg_init =
{
.serial_baud_rate = BAUD_RATE_115200,
.serial_data_bits = DATA_BITS_8,
.serial_stop_bits = STOP_BITS_1,
.serial_parity_mode = PARITY_NONE,
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
};
/*manage the serial device operations*/
static const struct SerialDrvDone drv_done =
{
.init = Stm32SerialInit,
.configure = Stm32SerialConfigure,
};
/*manage the serial device hal operations*/
static struct SerialHwDevDone hwdev_done =
{
.put_char = Stm32SerialPutchar,
.get_char = Stm32SerialGetchar,
};
static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
{
x_err_t ret = EOK;
/*Init the serial bus */
ret = SerialBusInit(serial_bus, bus_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
return ERROR;
}
/*Init the serial driver*/
ret = SerialDriverInit(serial_driver, drv_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the serial driver to the serial bus*/
ret = SerialDriverAttachToBus(drv_name, bus_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
return ERROR;
}
return ret;
}
/*Attach the serial device to the serial bus*/
static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
{
x_err_t ret = EOK;
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
return ERROR;
}
ret = SerialDeviceAttachToBus(dev_name, bus_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
return ERROR;
}
return ret;
}
int InitHwUsart(void)
{
x_err_t ret = EOK;
RCCConfiguration();
GPIOConfiguration();
#ifdef BSP_USING_USART1
static struct SerialCfgParam serial_cfg_1;
memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_1;
memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_1;
memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
serial_1.dma = usart_dma_1;
serial_driver_1.drv_done = &drv_done;
serial_driver_1.configure = &Stm32SerialDrvConfigure;
serial_device_1.hwdev_done = &hwdev_done;
serial_cfg_1.data_cfg = data_cfg_init;
serial_hw_cfg_1.uart_device = USART1;
serial_hw_cfg_1.irq = USART1_IRQn;
serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1;
serial_driver_1.private_data = (void *)&serial_cfg_1;
serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
NVIC_Configuration(serial_hw_cfg_1.irq);
ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
if (EOK != ret) {
KPrintf("InitHwUsart usart1 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart1 error ret %u\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_USART2
static struct SerialCfgParam serial_cfg_2;
memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_2;
memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_2;
memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
serial_2.dma = usart_dma_2;
serial_driver_2.drv_done = &drv_done;
serial_driver_2.configure = &Stm32SerialDrvConfigure;
serial_device_2.hwdev_done = &hwdev_done;
serial_cfg_2.data_cfg = data_cfg_init;
serial_hw_cfg_2.uart_device = USART2;
serial_hw_cfg_2.irq = USART2_IRQn;
serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2;
serial_driver_2.private_data = (void *)&serial_cfg_2;
serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
NVIC_Configuration(serial_hw_cfg_2.irq);
ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
if (EOK != ret) {
KPrintf("InitHwUsart usart2 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart2 error ret %u\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_USART3
static struct SerialCfgParam serial_cfg_3;
memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_3;
memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_3;
memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam));
serial_3.dma = usart_dma_3;
serial_driver_3.drv_done = &drv_done;
serial_driver_3.configure = &Stm32SerialDrvConfigure;
serial_device_3.hwdev_done = &hwdev_done;
serial_cfg_3.data_cfg = data_cfg_init;
serial_hw_cfg_3.uart_device = USART3;
serial_hw_cfg_3.irq = USART3_IRQn;
serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3;
serial_driver_3.private_data = (void *)&serial_cfg_3;
serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_3.haldev.private_data = (void *)&serial_dev_param_3;
NVIC_Configuration(serial_hw_cfg_3.irq);
ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
if (EOK != ret) {
KPrintf("InitHwUsart usart3 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart3 error ret %u\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_UART4
static struct SerialCfgParam serial_cfg_4;
memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_4;
memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_4;
memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam));
serial_4.dma = uart_dma_4;
serial_driver_4.drv_done = &drv_done;
serial_driver_4.configure = &Stm32SerialDrvConfigure;
serial_device_4.hwdev_done = &hwdev_done;
serial_cfg_4.data_cfg = data_cfg_init;
serial_hw_cfg_4.uart_device = UART4;
serial_hw_cfg_4.irq = UART4_IRQn;
serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4;
serial_driver_4.private_data = (void *)&serial_cfg_4;
serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_4.haldev.private_data = (void *)&serial_dev_param_4;
NVIC_Configuration(serial_hw_cfg_4.irq);
ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
if (EOK != ret) {
KPrintf("InitHwUsart usart4 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart4 error ret %u\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_UART5
static struct SerialCfgParam serial_cfg_5;
memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_5;
memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_5;
memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam));
serial_5.dma = uart_dma_5;
serial_driver_5.drv_done = &drv_done;
serial_driver_5.configure = &Stm32SerialDrvConfigure;
serial_device_5.hwdev_done = &hwdev_done;
serial_cfg_5.data_cfg = data_cfg_init;
serial_hw_cfg_5.uart_device = UART5;
serial_hw_cfg_5.irq = UART5_IRQn;
serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5;
serial_driver_5.private_data = (void *)&serial_cfg_5;
serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_5.haldev.private_data = (void *)&serial_dev_param_5;
NVIC_Configuration(serial_hw_cfg_5.irq);
ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
if (EOK != ret) {
KPrintf("InitHwUsart usart5 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart5 error ret %u\n", ret);
return ERROR;
}
#endif
return ret;
}

858
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/uart/connect_usart_20210825135326.c
View File

@ -1,858 +0,0 @@
/*
* Copyright (c) 2020 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
/**
* @file connect_usart.c
* @brief support stm32f407-st-discovery-board usart function and register to bus framework
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: connect_uart.c
Description: support stm32f407-st-discovery-board usart configure and uart bus register function
Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. support stm32f407-st-discovery-board usart configure, write and read
2. support stm32f407-st-discovery-board usart bus device and driver register
*************************************************/
#include "stm32f4xx.h"
#include "board.h"
#include "misc.h"
#include "connect_usart.h"
#include "hardware_gpio.h"
#include "hardware_rcc.h"
/* UART GPIO define. */
#define UART1_GPIO_TX GPIO_Pin_6
#define UART1_TX_PIN_SOURCE GPIO_PinSource6
#define UART1_GPIO_RX GPIO_Pin_7
#define UART1_RX_PIN_SOURCE GPIO_PinSource7
#define UART1_GPIO GPIOB
#define UART1_GPIO_RCC RCC_AHB1Periph_GPIOB
#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
#define UART2_GPIO_TX GPIO_Pin_2
#define UART2_TX_PIN_SOURCE GPIO_PinSource2
#define UART2_GPIO_RX GPIO_Pin_3
#define UART2_RX_PIN_SOURCE GPIO_PinSource3
#define UART2_GPIO GPIOA
#define UART2_GPIO_RCC RCC_AHB1Periph_GPIOA
#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
#define UART3_GPIO_TX GPIO_Pin_8
#define UART3_TX_PIN_SOURCE GPIO_PinSource8
#define UART3_GPIO_RX GPIO_Pin_9
#define UART3_RX_PIN_SOURCE GPIO_PinSource9
#define UART3_GPIO GPIOD
#define UART3_GPIO_RCC RCC_AHB1Periph_GPIOD
#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
#define UART4_GPIO_TX GPIO_Pin_10
#define UART4_TX_PIN_SOURCE GPIO_PinSource10
#define UART4_GPIO_RX GPIO_Pin_11
#define UART4_RX_PIN_SOURCE GPIO_PinSource11
#define UART4_GPIO GPIOC
#define UART4_GPIO_RCC RCC_AHB1Periph_GPIOC
#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4
#define UART5_GPIO_TX GPIO_Pin_12
#define UART5_TX_PIN_SOURCE GPIO_PinSource12
#define UART5_GPIO_RX GPIO_Pin_2
#define UART5_RX_PIN_SOURCE GPIO_PinSource2
#define UART5_TX GPIOC
#define UART5_RX GPIOD
#define UART5_GPIO_RCC_TX RCC_AHB1Periph_GPIOC
#define UART5_GPIO_RCC_RX RCC_AHB1Periph_GPIOD
#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5
#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n))
#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n))
static void RCCConfiguration(void)
{
#ifdef BSP_USING_USART1
RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
#endif
#ifdef BSP_USING_USART2
RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
#endif
#ifdef BSP_USING_USART3
RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
#endif
#ifdef BSP_USING_UART4
RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE);
#endif
#ifdef BSP_USING_UART5
RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE);
#endif
}
static void GPIOConfiguration(void)
{
GPIO_InitTypeDef gpio_initstructure;
gpio_initstructure.GPIO_Mode = GPIO_Mode_AF;
gpio_initstructure.GPIO_OType = GPIO_OType_PP;
gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP;
gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz;
#ifdef BSP_USING_USART1
gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1);
GPIO_Init(UART1_GPIO, &gpio_initstructure);
#endif
#ifdef BSP_USING_USART2
gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX;
GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2);
GPIO_Init(UART2_GPIO, &gpio_initstructure);
#endif
#ifdef BSP_USING_USART3
gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX;
GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3);
GPIO_Init(UART3_GPIO, &gpio_initstructure);
#endif
#ifdef BSP_USING_UART4
gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX;
GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4);
GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4);
GPIO_Init(UART4_GPIO, &gpio_initstructure);
#endif
#ifdef BSP_USING_UART5
gpio_initstructure.GPIO_Pin = UART5_GPIO_TX;
GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5);
GPIO_Init(UART5_TX, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = UART5_GPIO_RX;
GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5);
GPIO_Init(UART5_RX, &gpio_initstructure);
#endif
}
static void NVIC_Configuration(IRQn_Type irq)
{
NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = irq;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr)
{
DMA_InitTypeDef DMA_InitStructure;
dma->SettingRecvLen = SettingRecvLen;
DMA_DeInit(dma->RxStream);
while (DMA_GetCmdStatus(dma->RxStream) != DISABLE);
DMA_InitStructure.DMA_Channel = dma->RxCh;
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR);
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_Init(dma->RxStream, &DMA_InitStructure);
}
static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
{
struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
struct Stm32UsartDma *dma = &serial->dma;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
NVIC_InitTypeDef NVIC_InitStructure;
USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer);
DMA_ClearFlag(dma->RxStream, dma->RxFlag);
DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE);
USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE);
DMA_Cmd(dma->RxStream, ENABLE);
NVIC_InitStructure.NVIC_IRQChannel = dma->RxIrqCh;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
{
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
}
if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
}
if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
}
if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
}
if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
}
if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
}
if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
}
static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(serial_drv);
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if (configure_info->private_data) {
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
USART_InitTypeDef USART_InitStructure;
USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
} else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
}
if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
USART_InitStructure.USART_StopBits = USART_StopBits_1;
} else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
USART_InitStructure.USART_StopBits = USART_StopBits_2;
}
if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
USART_InitStructure.USART_Parity = USART_Parity_No;
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
USART_InitStructure.USART_Parity = USART_Parity_Odd;
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
USART_InitStructure.USART_Parity = USART_Parity_Even;
}
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure);
USART_Cmd(serial_hw_cfg->uart_device, ENABLE);
return EOK;
}
static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
{
NULL_PARAM_CHECK(serial_drv);
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
switch (serial_operation_cmd)
{
case OPER_CLR_INT:
UART_DISABLE_IRQ(serial_hw_cfg->irq);
USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE);
break;
case OPER_SET_INT:
UART_ENABLE_IRQ(serial_hw_cfg->irq);
USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE);
break;
case OPER_CONFIG :
if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode){
DMAConfiguration(serial_dev, serial_hw_cfg->uart_device);
}
}
return EOK;
}
static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c)
{
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE));
serial_hw_cfg->uart_device->DR = c;
return EOK;
}
static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
{
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
int ch = -1;
if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
ch = serial_hw_cfg->uart_device->DR & 0xff;
}
return ch;
}
static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device)
{
x_base level = CriticalAreaLock();
x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream);
x_size_t recv_len = recv_total_index - dma->LastRecvIndex;
dma->LastRecvIndex = recv_total_index;
CriticalAreaUnLock(level);
if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
USART_ReceiveData(uart_device);
}
static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
{
struct Stm32UsartDma *dma = &serial->dma;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
x_base level = CriticalAreaLock();
x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
dma->LastRecvIndex = 0;
CriticalAreaUnLock(level);
if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
DMA_ClearFlag(dma->RxStream, dma->RxFlag);
}
}
static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
{
struct Stm32UsartDma *dma = &serial->dma;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
}
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
}
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
}
if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
USART_ReceiveData(serial_hw_cfg->uart_device);
}
}
#ifdef BSP_USING_USART1
struct Stm32Usart serial_1;
struct SerialDriver serial_driver_1;
struct SerialHardwareDevice serial_device_1;
static const struct Stm32UsartDma usart_dma_1 =
{
DMA2_Stream5,
DMA_Channel_4,
DMA_FLAG_TCIF5,
DMA2_Stream5_IRQn,
0,
0,
};
void USART1_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_1, &serial_driver_1, &serial_device_1);
}
DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE);
void DMA2_Stream5_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1);
}
DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE);
#endif
#ifdef BSP_USING_USART2
struct Stm32Usart serial_2;
struct SerialDriver serial_driver_2;
struct SerialHardwareDevice serial_device_2;
static const struct Stm32UsartDma usart_dma_2 =
{
DMA1_Stream5,
DMA_Channel_4,
DMA_FLAG_TCIF5,
DMA1_Stream5_IRQn,
0,
0,
};
void USART2_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_2, &serial_driver_2, &serial_device_2);
}
DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE);
void DMA1_Stream5_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2);
}
DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE);
#endif
#ifdef BSP_USING_USART3
struct Stm32Usart serial_3;
struct SerialDriver serial_driver_3;
struct SerialHardwareDevice serial_device_3;
static const struct Stm32UsartDma usart_dma_3 =
{
DMA1_Stream1,
DMA_Channel_4,
DMA_FLAG_TCIF1,
DMA1_Stream1_IRQn,
0,
0,
};
void USART3_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_3, &serial_driver_3, &serial_device_3);
}
DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE);
void DMA1_Stream1_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3);
}
DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE);
#endif
#ifdef BSP_USING_UART4
struct Stm32Usart serial_4;
struct SerialDriver serial_driver_4;
struct SerialHardwareDevice serial_device_4;
static const struct Stm32UsartDma uart_dma_4 =
{
DMA1_Stream2,
DMA_Channel_4,
DMA_FLAG_TCIF2,
DMA1_Stream2_IRQn,
0,
0,
};
void UART4_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_4, &serial_driver_4, &serial_device_4);
}
DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE);
void DMA1_Stream2_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4);
}
DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
#endif
#ifdef BSP_USING_UART5
struct Stm32Usart serial_5;
struct SerialDriver serial_driver_5;
struct SerialHardwareDevice serial_device_5;
static const struct Stm32UsartDma uart_dma_5 =
{
DMA1_Stream0,
DMA_Channel_4,
DMA_FLAG_TCIF0,
DMA1_Stream0_IRQn,
0,
0,
};
void UART5_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_5, &serial_driver_5, &serial_device_5);
}
DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE);
void DMA1_Stream0_IRQHandler(int irq_num, void *arg) {
DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5);
}
DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE);
#endif
static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
x_err_t ret = EOK;
int serial_operation_cmd;
struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = Stm32SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
}
return ret;
}
static const struct SerialDataCfg data_cfg_init =
{
.serial_baud_rate = BAUD_RATE_115200,
.serial_data_bits = DATA_BITS_8,
.serial_stop_bits = STOP_BITS_1,
.serial_parity_mode = PARITY_NONE,
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
};
/*manage the serial device operations*/
static const struct SerialDrvDone drv_done =
{
.init = Stm32SerialInit,
.configure = Stm32SerialConfigure,
};
/*manage the serial device hal operations*/
static struct SerialHwDevDone hwdev_done =
{
.put_char = Stm32SerialPutchar,
.get_char = Stm32SerialGetchar,
};
static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
{
x_err_t ret = EOK;
/*Init the serial bus */
ret = SerialBusInit(serial_bus, bus_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
return ERROR;
}
/*Init the serial driver*/
ret = SerialDriverInit(serial_driver, drv_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the serial driver to the serial bus*/
ret = SerialDriverAttachToBus(drv_name, bus_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
return ERROR;
}
return ret;
}
/*Attach the serial device to the serial bus*/
static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
{
x_err_t ret = EOK;
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
return ERROR;
}
ret = SerialDeviceAttachToBus(dev_name, bus_name);
if (EOK != ret) {
KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
return ERROR;
}
return ret;
}
int InitHwUsart(void)
{
x_err_t ret = EOK;
RCCConfiguration();
GPIOConfiguration();
#ifdef BSP_USING_USART1
static struct SerialCfgParam serial_cfg_1;
memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_1;
memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_1;
memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
serial_1.dma = usart_dma_1;
serial_driver_1.drv_done = &drv_done;
serial_driver_1.configure = &Stm32SerialDrvConfigure;
serial_device_1.hwdev_done = &hwdev_done;
serial_cfg_1.data_cfg = data_cfg_init;
serial_hw_cfg_1.uart_device = USART1;
serial_hw_cfg_1.irq = USART1_IRQn;
serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1;
serial_driver_1.private_data = (void *)&serial_cfg_1;
serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
NVIC_Configuration(serial_hw_cfg_1.irq);
ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
if (EOK != ret) {
KPrintf("InitHwUsart usart1 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart1 error ret %u\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_USART2
static struct SerialCfgParam serial_cfg_2;
memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_2;
memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_2;
memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
serial_2.dma = usart_dma_2;
serial_driver_2.drv_done = &drv_done;
serial_driver_2.configure = &Stm32SerialDrvConfigure;
serial_device_2.hwdev_done = &hwdev_done;
serial_cfg_2.data_cfg = data_cfg_init;
serial_hw_cfg_2.uart_device = USART2;
serial_hw_cfg_2.irq = USART2_IRQn;
serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2;
serial_driver_2.private_data = (void *)&serial_cfg_2;
serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
NVIC_Configuration(serial_hw_cfg_2.irq);
ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
if (EOK != ret) {
KPrintf("InitHwUsart usart2 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart2 error ret %u\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_USART3
static struct SerialCfgParam serial_cfg_3;
memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_3;
memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_3;
memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam));
serial_3.dma = usart_dma_3;
serial_driver_3.drv_done = &drv_done;
serial_driver_3.configure = &Stm32SerialDrvConfigure;
serial_device_3.hwdev_done = &hwdev_done;
serial_cfg_3.data_cfg = data_cfg_init;
serial_hw_cfg_3.uart_device = USART3;
serial_hw_cfg_3.irq = USART3_IRQn;
serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3;
serial_driver_3.private_data = (void *)&serial_cfg_3;
serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_3.haldev.private_data = (void *)&serial_dev_param_3;
NVIC_Configuration(serial_hw_cfg_3.irq);
ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
if (EOK != ret) {
KPrintf("InitHwUsart usart3 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart3 error ret %u\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_UART4
static struct SerialCfgParam serial_cfg_4;
memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_4;
memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_4;
memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam));
serial_4.dma = uart_dma_4;
serial_driver_4.drv_done = &drv_done;
serial_driver_4.configure = &Stm32SerialDrvConfigure;
serial_device_4.hwdev_done = &hwdev_done;
serial_cfg_4.data_cfg = data_cfg_init;
serial_hw_cfg_4.uart_device = UART4;
serial_hw_cfg_4.irq = UART4_IRQn;
serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4;
serial_driver_4.private_data = (void *)&serial_cfg_4;
serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_4.haldev.private_data = (void *)&serial_dev_param_4;
NVIC_Configuration(serial_hw_cfg_4.irq);
ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
if (EOK != ret) {
KPrintf("InitHwUsart usart4 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart4 error ret %u\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_UART5
static struct SerialCfgParam serial_cfg_5;
memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam));
static struct UsartHwCfg serial_hw_cfg_5;
memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg));
static struct SerialDevParam serial_dev_param_5;
memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam));
serial_5.dma = uart_dma_5;
serial_driver_5.drv_done = &drv_done;
serial_driver_5.configure = &Stm32SerialDrvConfigure;
serial_device_5.hwdev_done = &hwdev_done;
serial_cfg_5.data_cfg = data_cfg_init;
serial_hw_cfg_5.uart_device = UART5;
serial_hw_cfg_5.irq = UART5_IRQn;
serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5;
serial_driver_5.private_data = (void *)&serial_cfg_5;
serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_5.haldev.private_data = (void *)&serial_dev_param_5;
NVIC_Configuration(serial_hw_cfg_5.irq);
ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
if (EOK != ret) {
KPrintf("InitHwUsart usart5 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUsart usart5 error ret %u\n", ret);
return ERROR;
}
#endif
return ret;
}

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#ifndef XS_CONFIG_H__
#define XS_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XiUOS Project Configuration */
#define BOARD_STM32F407_EVB
#define ARCH_ARM
/* stm32f407-st-discovery feature */
#define BSP_USING_DMA
#define BSP_USING_GPIO
#define PIN_BUS_NAME "pin"
#define PIN_DRIVER_NAME "pin_drv"
#define PIN_DEVICE_NAME "pin_dev"
#define BSP_USING_UART
#define BSP_USING_USART1
#define SERIAL_BUS_NAME_1 "usart1"
#define SERIAL_DRV_NAME_1 "usart1_drv"
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
#define BSP_USING_USART2
#define SERIAL_BUS_NAME_2 "usart2"
#define SERIAL_DRV_NAME_2 "usart2_drv"
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
#define BSP_USING_USART3
#define SERIAL_BUS_NAME_3 "usart3"
#define SERIAL_DRV_NAME_3 "usart3_drv"
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
#define BSP_USING_WDT
#define WDT_BUS_NAME "wdt"
#define WDT_DRIVER_NAME "wdt_drv"
#define WDT_DEVICE_NAME "wdt_dev"
/* config default board resources */
/* config board app name */
#define BOARD_APP_NAME "/XiUOS_stm32f407-st-discovery_app.bin"
/* config board service table */
#define SERVICE_TABLE_ADDRESS 0x20000000
/* config hardware resources for connection */
/* Hardware feature */
#define RESOURCES_SERIAL
#define SERIAL_USING_DMA
#define SERIAL_RB_BUFSZ 128
#define RESOURCES_PIN
#define RESOURCES_WDT
/* Kernel feature */
/* separate compile(choose none for compile once) */
#define APP_STARTUP_FROM_FLASH
/* Memory Management */
#define MEM_ALIGN_SIZE 8
#define MM_PAGE_SIZE 4096
/* Using small memory allocator */
#define KERNEL_SMALL_MEM_ALLOC
#define SMALL_NUMBER_32B 64
#define SMALL_NUMBER_64B 32
/* Task feature */
#define USER_APPLICATION
/* Inter-Task communication */
#define KERNEL_SEMAPHORE
#define KERNEL_MUTEX
#define KERNEL_EVENT
#define KERNEL_MESSAGEQUEUE
#define KERNEL_SOFTTIMER
#define SCHED_POLICY_RR_REMAINSLICE
#define KTASK_PRIORITY_32
#define KTASK_PRIORITY_MAX 32
#define TICK_PER_SECOND 1000
#define KERNEL_STACK_OVERFLOW_CHECK
#define IDLE_KTASK_STACKSIZE 256
#define ZOMBIE_KTASK_STACKSIZE 2048
/* Kernel Console */
#define KERNEL_CONSOLE
#define KERNEL_BANNER
#define KERNEL_CONSOLEBUF_SIZE 128
/* Kernel Hook */
/* Command shell */
#define TOOL_SHELL
#define SHELL_ENTER_CR
#define SHELL_ENTER_LF
#define SHELL_ENTER_CR_AND_LF
/* Set shell user control */
#define SHELL_DEFAULT_USER "letter"
#define SHELL_DEFAULT_USER_PASSWORD ""
#define SHELL_LOCK_TIMEOUT 10000
/* Set shell config param */
#define SHELL_TASK_STACK_SIZE 4096
#define SHELL_TASK_PRIORITY 20
#define SHELL_MAX_NUMBER 5
#define SHELL_PARAMETER_MAX_NUMBER 8
#define SHELL_HISTORY_MAX_NUMBER 5
#define SHELL_PRINT_BUFFER 128
#define SHELL_HELP_SHOW_PERMISSION
/* Kernel data structure Manage */
#define KERNEL_QUEUEMANAGE
#define KERNEL_WORKQUEUE
#define WORKQUEUE_KTASK_STACKSIZE 512
#define WORKQUEUE_KTASK_PRIORITY 23
#define QUEUE_MAX 16
#define KERNEL_WAITQUEUE
#define KERNEL_DATAQUEUE
/* Kernel components init */
#define KERNEL_COMPONENTS_INIT
#define ENV_INIT_KTASK_STACK_SIZE 8192
#define KERNEL_USER_MAIN
#define NAME_NUM_MAX 32
/* hash table config */
#define ID_HTABLE_SIZE 16
#define ID_NUM_MAX 128
/* File system */
#define FS_VFS
#define VFS_USING_WORKDIR
#define FS_VFS_DEVFS
#define FS_VFS_FATFS
/* APP Framework */
/* Perception */
/* connection */
/* Intelligence */
/* Control */
/* Lib */
#define LIB
#define LIB_POSIX
/* C++ features */
#define LIB_NEWLIB
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 2048
#define MAIN_KTASK_PRIORITY 10
#endif

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#ifndef XS_CONFIG_H__
#define XS_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XiUOS Project Configuration */
#define BOARD_CORTEX_M4_EVB
#define ARCH_ARM
/* stm32f407-st-discovery feature */
#define BSP_USING_DMA
#define BSP_USING_GPIO
#define PIN_BUS_NAME "pin"
#define PIN_DRIVER_NAME "pin_drv"
#define PIN_DEVICE_NAME "pin_dev"
#define BSP_USING_UART
#define BSP_USING_USART1
#define SERIAL_BUS_NAME_1 "usart1"
#define SERIAL_DRV_NAME_1 "usart1_drv"
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
#define BSP_USING_USART2
#define SERIAL_BUS_NAME_2 "usart2"
#define SERIAL_DRV_NAME_2 "usart2_drv"
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
#define BSP_USING_USART3
#define SERIAL_BUS_NAME_3 "usart3"
#define SERIAL_DRV_NAME_3 "usart3_drv"
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
#define BSP_USING_WDT
#define WDT_BUS_NAME "wdt"
#define WDT_DRIVER_NAME "wdt_drv"
#define WDT_DEVICE_NAME "wdt_dev"
/* config default board resources */
/* config board app name */
#define BOARD_APP_NAME "/XiUOS_stm32f407-st-discovery_app.bin"
/* config board service table */
#define SERVICE_TABLE_ADDRESS 0x20000000
/* config hardware resources for connection */
/* Hardware feature */
#define RESOURCES_SERIAL
#define SERIAL_USING_DMA
#define SERIAL_RB_BUFSZ 128
#define RESOURCES_PIN
#define RESOURCES_WDT
/* Kernel feature */
/* separate compile(choose none for compile once) */
#define APP_STARTUP_FROM_FLASH
/* Memory Management */
#define MEM_ALIGN_SIZE 8
#define MM_PAGE_SIZE 4096
/* Using small memory allocator */
#define KERNEL_SMALL_MEM_ALLOC
#define SMALL_NUMBER_32B 64
#define SMALL_NUMBER_64B 32
/* Task feature */
#define USER_APPLICATION
/* Inter-Task communication */
#define KERNEL_SEMAPHORE
#define KERNEL_MUTEX
#define KERNEL_EVENT
#define KERNEL_MESSAGEQUEUE
#define KERNEL_SOFTTIMER
#define SCHED_POLICY_RR_REMAINSLICE
#define KTASK_PRIORITY_32
#define KTASK_PRIORITY_MAX 32
#define TICK_PER_SECOND 1000
#define KERNEL_STACK_OVERFLOW_CHECK
#define IDLE_KTASK_STACKSIZE 256
#define ZOMBIE_KTASK_STACKSIZE 2048
/* Kernel Console */
#define KERNEL_CONSOLE
#define KERNEL_BANNER
#define KERNEL_CONSOLEBUF_SIZE 128
/* Kernel Hook */
/* Command shell */
#define TOOL_SHELL
#define SHELL_ENTER_CR
#define SHELL_ENTER_LF
#define SHELL_ENTER_CR_AND_LF
/* Set shell user control */
#define SHELL_DEFAULT_USER "letter"
#define SHELL_DEFAULT_USER_PASSWORD ""
#define SHELL_LOCK_TIMEOUT 10000
/* Set shell config param */
#define SHELL_TASK_STACK_SIZE 4096
#define SHELL_TASK_PRIORITY 20
#define SHELL_MAX_NUMBER 5
#define SHELL_PARAMETER_MAX_NUMBER 8
#define SHELL_HISTORY_MAX_NUMBER 5
#define SHELL_PRINT_BUFFER 128
#define SHELL_HELP_SHOW_PERMISSION
/* Kernel data structure Manage */
#define KERNEL_QUEUEMANAGE
#define KERNEL_WORKQUEUE
#define WORKQUEUE_KTASK_STACKSIZE 512
#define WORKQUEUE_KTASK_PRIORITY 23
#define QUEUE_MAX 16
#define KERNEL_WAITQUEUE
#define KERNEL_DATAQUEUE
/* Kernel components init */
#define KERNEL_COMPONENTS_INIT
#define ENV_INIT_KTASK_STACK_SIZE 8192
#define KERNEL_USER_MAIN
#define NAME_NUM_MAX 32
/* hash table config */
#define ID_HTABLE_SIZE 16
#define ID_NUM_MAX 128
/* File system */
#define FS_VFS
#define VFS_USING_WORKDIR
#define FS_VFS_DEVFS
#define FS_VFS_FATFS
/* APP Framework */
/* Perception */
/* connection */
/* Intelligence */
/* Control */
/* Lib */
#define LIB
#define LIB_POSIX
/* C++ features */
#define LIB_NEWLIB
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 2048
#define MAIN_KTASK_PRIORITY 10
#endif

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#ifndef XS_CONFIG_H__
#define XS_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XiUOS Project Configuration */
#define BOARD_CORTEX_M4_EVB
#define ARCH_ARM
/* stm32f407-st-discovery feature */
#define BSP_USING_DMA
#define BSP_USING_GPIO
#define PIN_BUS_NAME "pin"
#define PIN_DRIVER_NAME "pin_drv"
#define PIN_DEVICE_NAME "pin_dev"
#define BSP_USING_UART
#define BSP_USING_USART1
#define SERIAL_BUS_NAME_1 "usart1"
#define SERIAL_DRV_NAME_1 "usart1_drv"
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
#define BSP_USING_USART2
#define SERIAL_BUS_NAME_2 "usart2"
#define SERIAL_DRV_NAME_2 "usart2_drv"
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
#define BSP_USING_USART3
#define SERIAL_BUS_NAME_3 "usart3"
#define SERIAL_DRV_NAME_3 "usart3_drv"
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
#define BSP_USING_WDT
#define WDT_BUS_NAME "wdt"
#define WDT_DRIVER_NAME "wdt_drv"
#define WDT_DEVICE_NAME "wdt_dev"
/* config default board resources */
/* config board app name */
#define BOARD_APP_NAME "/XiUOS_stm32f407-st-discovery_app.bin"
/* config board service table */
#define SERVICE_TABLE_ADDRESS 0x20000000
/* config hardware resources for connection */
/* Hardware feature */
#define RESOURCES_SERIAL
#define SERIAL_USING_DMA
#define SERIAL_RB_BUFSZ 128
#define RESOURCES_PIN
#define RESOURCES_WDT
/* Kernel feature */
/* separate compile(choose none for compile once) */
#define APP_STARTUP_FROM_FLASH
/* Memory Management */
#define MEM_ALIGN_SIZE 8
#define MM_PAGE_SIZE 4096
/* Using small memory allocator */
#define KERNEL_SMALL_MEM_ALLOC
#define SMALL_NUMBER_32B 64
#define SMALL_NUMBER_64B 32
/* Task feature */
#define USER_APPLICATION
/* Inter-Task communication */
#define KERNEL_SEMAPHORE
#define KERNEL_MUTEX
#define KERNEL_EVENT
#define KERNEL_MESSAGEQUEUE
#define KERNEL_SOFTTIMER
#define SCHED_POLICY_RR_REMAINSLICE
#define KTASK_PRIORITY_32
#define KTASK_PRIORITY_MAX 32
#define TICK_PER_SECOND 1000
#define KERNEL_STACK_OVERFLOW_CHECK
#define IDLE_KTASK_STACKSIZE 256
#define ZOMBIE_KTASK_STACKSIZE 2048
/* Kernel Console */
#define KERNEL_CONSOLE
#define KERNEL_BANNER
#define KERNEL_CONSOLEBUF_SIZE 128
/* Kernel Hook */
/* Command shell */
#define TOOL_SHELL
#define SHELL_ENTER_CR
#define SHELL_ENTER_LF
#define SHELL_ENTER_CR_AND_LF
/* Set shell user control */
#define SHELL_DEFAULT_USER "letter"
#define SHELL_DEFAULT_USER_PASSWORD ""
#define SHELL_LOCK_TIMEOUT 10000
/* Set shell config param */
#define SHELL_TASK_STACK_SIZE 4096
#define SHELL_TASK_PRIORITY 20
#define SHELL_MAX_NUMBER 5
#define SHELL_PARAMETER_MAX_NUMBER 8
#define SHELL_HISTORY_MAX_NUMBER 5
#define SHELL_PRINT_BUFFER 128
#define SHELL_HELP_SHOW_PERMISSION
/* Kernel data structure Manage */
#define KERNEL_QUEUEMANAGE
#define KERNEL_WORKQUEUE
#define WORKQUEUE_KTASK_STACKSIZE 512
#define WORKQUEUE_KTASK_PRIORITY 23
#define QUEUE_MAX 16
#define KERNEL_WAITQUEUE
#define KERNEL_DATAQUEUE
/* Kernel components init */
#define KERNEL_COMPONENTS_INIT
#define ENV_INIT_KTASK_STACK_SIZE 8192
#define KERNEL_USER_MAIN
#define NAME_NUM_MAX 32
/* hash table config */
#define ID_HTABLE_SIZE 16
#define ID_NUM_MAX 128
/* File system */
#define FS_VFS
#define VFS_USING_WORKDIR
#define FS_VFS_DEVFS
#define FS_VFS_FATFS
/* APP Framework */
/* Perception */
/* connection */
/* Intelligence */
/* Control */
/* Lib */
#define LIB
#define LIB_POSIX
/* C++ features */
#define LIB_NEWLIB
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 2048
#define MAIN_KTASK_PRIORITY 10
#endif

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#ifndef XS_CONFIG_H__
#define XS_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XiUOS Project Configuration */
#define BOARD_CORTEX_M4_EVB
#define ARCH_ARM
/* stm32f407-st-discovery feature */
#define BSP_USING_DMA
#define BSP_USING_GPIO
#define PIN_BUS_NAME "pin"
#define PIN_DRIVER_NAME "pin_drv"
#define PIN_DEVICE_NAME "pin_dev"
#define BSP_USING_UART
#define BSP_USING_USART1
#define SERIAL_BUS_NAME_1 "usart1"
#define SERIAL_DRV_NAME_1 "usart1_drv"
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
#define BSP_USING_USART2
#define SERIAL_BUS_NAME_2 "usart2"
#define SERIAL_DRV_NAME_2 "usart2_drv"
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
#define BSP_USING_USART3
#define SERIAL_BUS_NAME_3 "usart3"
#define SERIAL_DRV_NAME_3 "usart3_drv"
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
#define BSP_USING_WDT
#define WDT_BUS_NAME "wdt"
#define WDT_DRIVER_NAME "wdt_drv"
#define WDT_DEVICE_NAME "wdt_dev"
/* config default board resources */
/* config board app name */
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
/* config board service table */
#define SERVICE_TABLE_ADDRESS 0x20000000
/* config hardware resources for connection */
/* Hardware feature */
#define RESOURCES_SERIAL
#define SERIAL_USING_DMA
#define SERIAL_RB_BUFSZ 128
#define RESOURCES_PIN
#define RESOURCES_WDT
/* Kernel feature */
/* separate compile(choose none for compile once) */
#define APP_STARTUP_FROM_FLASH
/* Memory Management */
#define MEM_ALIGN_SIZE 8
#define MM_PAGE_SIZE 4096
/* Using small memory allocator */
#define KERNEL_SMALL_MEM_ALLOC
#define SMALL_NUMBER_32B 64
#define SMALL_NUMBER_64B 32
/* Task feature */
#define USER_APPLICATION
/* Inter-Task communication */
#define KERNEL_SEMAPHORE
#define KERNEL_MUTEX
#define KERNEL_EVENT
#define KERNEL_MESSAGEQUEUE
#define KERNEL_SOFTTIMER
#define SCHED_POLICY_RR_REMAINSLICE
#define KTASK_PRIORITY_32
#define KTASK_PRIORITY_MAX 32
#define TICK_PER_SECOND 1000
#define KERNEL_STACK_OVERFLOW_CHECK
#define IDLE_KTASK_STACKSIZE 256
#define ZOMBIE_KTASK_STACKSIZE 2048
/* Kernel Console */
#define KERNEL_CONSOLE
#define KERNEL_BANNER
#define KERNEL_CONSOLEBUF_SIZE 128
/* Kernel Hook */
/* Command shell */
#define TOOL_SHELL
#define SHELL_ENTER_CR
#define SHELL_ENTER_LF
#define SHELL_ENTER_CR_AND_LF
/* Set shell user control */
#define SHELL_DEFAULT_USER "letter"
#define SHELL_DEFAULT_USER_PASSWORD ""
#define SHELL_LOCK_TIMEOUT 10000
/* Set shell config param */
#define SHELL_TASK_STACK_SIZE 4096
#define SHELL_TASK_PRIORITY 20
#define SHELL_MAX_NUMBER 5
#define SHELL_PARAMETER_MAX_NUMBER 8
#define SHELL_HISTORY_MAX_NUMBER 5
#define SHELL_PRINT_BUFFER 128
#define SHELL_HELP_SHOW_PERMISSION
/* Kernel data structure Manage */
#define KERNEL_QUEUEMANAGE
#define KERNEL_WORKQUEUE
#define WORKQUEUE_KTASK_STACKSIZE 512
#define WORKQUEUE_KTASK_PRIORITY 23
#define QUEUE_MAX 16
#define KERNEL_WAITQUEUE
#define KERNEL_DATAQUEUE
/* Kernel components init */
#define KERNEL_COMPONENTS_INIT
#define ENV_INIT_KTASK_STACK_SIZE 8192
#define KERNEL_USER_MAIN
#define NAME_NUM_MAX 32
/* hash table config */
#define ID_HTABLE_SIZE 16
#define ID_NUM_MAX 128
/* File system */
#define FS_VFS
#define VFS_USING_WORKDIR
#define FS_VFS_DEVFS
#define FS_VFS_FATFS
/* APP Framework */
/* Perception */
/* connection */
/* Intelligence */
/* Control */
/* Lib */
#define LIB
#define LIB_POSIX
/* C++ features */
#define LIB_NEWLIB
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 2048
#define MAIN_KTASK_PRIORITY 10
#endif

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#ifndef XS_CONFIG_H__
#define XS_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XiUOS Project Configuration */
#define BOARD_CORTEX_M4_EVB
#define ARCH_ARM
/* stm32f407-st-discovery feature */
#define BSP_USING_DMA
#define BSP_USING_GPIO
#define PIN_BUS_NAME "pin"
#define PIN_DRIVER_NAME "pin_drv"
#define PIN_DEVICE_NAME "pin_dev"
#define BSP_USING_UART
#define BSP_USING_USART1
#define SERIAL_BUS_NAME_1 "usart1"
#define SERIAL_DRV_NAME_1 "usart1_drv"
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
#define BSP_USING_USART2
#define SERIAL_BUS_NAME_2 "usart2"
#define SERIAL_DRV_NAME_2 "usart2_drv"
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
#define BSP_USING_USART3
#define SERIAL_BUS_NAME_3 "usart3"
#define SERIAL_DRV_NAME_3 "usart3_drv"
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
#define BSP_USING_WDT
#define WDT_BUS_NAME "wdt"
#define WDT_DRIVER_NAME "wdt_drv"
#define WDT_DEVICE_NAME "wdt_dev"
/* config default board resources */
/* config board app name */
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
/* config board service table */
#define SERVICE_TABLE_ADDRESS 0x20000000
/* config hardware resources for connection */
/* Hardware feature */
#define RESOURCES_SERIAL
#define SERIAL_USING_DMA
#define SERIAL_RB_BUFSZ 128
#define RESOURCES_PIN
#define RESOURCES_WDT
/* Kernel feature */
/* separate compile(choose none for compile once) */
#define APP_STARTUP_FROM_FLASH
/* Memory Management */
#define MEM_ALIGN_SIZE 8
#define MM_PAGE_SIZE 4096
/* Using small memory allocator */
#define KERNEL_SMALL_MEM_ALLOC
#define SMALL_NUMBER_32B 64
#define SMALL_NUMBER_64B 32
/* Task feature */
#define USER_APPLICATION
/* Inter-Task communication */
#define KERNEL_SEMAPHORE
#define KERNEL_MUTEX
#define KERNEL_EVENT
#define KERNEL_MESSAGEQUEUE
#define KERNEL_SOFTTIMER
#define SCHED_POLICY_RR_REMAINSLICE
#define KTASK_PRIORITY_32
#define KTASK_PRIORITY_MAX 32
#define TICK_PER_SECOND 1000
#define KERNEL_STACK_OVERFLOW_CHECK
#define IDLE_KTASK_STACKSIZE 256
#define ZOMBIE_KTASK_STACKSIZE 2048
/* Kernel Console */
#define KERNEL_CONSOLE
#define KERNEL_BANNER
#define KERNEL_CONSOLEBUF_SIZE 128
/* Kernel Hook */
/* Command shell */
#define TOOL_SHELL
#define SHELL_ENTER_CR
#define SHELL_ENTER_LF
#define SHELL_ENTER_CR_AND_LF
/* Set shell user control */
#define SHELL_DEFAULT_USER "letter"
#define SHELL_DEFAULT_USER_PASSWORD ""
#define SHELL_LOCK_TIMEOUT 10000
/* Set shell config param */
#define SHELL_TASK_STACK_SIZE 4096
#define SHELL_TASK_PRIORITY 20
#define SHELL_MAX_NUMBER 5
#define SHELL_PARAMETER_MAX_NUMBER 8
#define SHELL_HISTORY_MAX_NUMBER 5
#define SHELL_PRINT_BUFFER 128
#define SHELL_HELP_SHOW_PERMISSION
/* Kernel data structure Manage */
#define KERNEL_QUEUEMANAGE
#define KERNEL_WORKQUEUE
#define WORKQUEUE_KTASK_STACKSIZE 512
#define WORKQUEUE_KTASK_PRIORITY 23
#define QUEUE_MAX 16
#define KERNEL_WAITQUEUE
#define KERNEL_DATAQUEUE
/* Kernel components init */
#define KERNEL_COMPONENTS_INIT
#define ENV_INIT_KTASK_STACK_SIZE 8192
#define KERNEL_USER_MAIN
#define NAME_NUM_MAX 32
/* hash table config */
#define ID_HTABLE_SIZE 16
#define ID_NUM_MAX 128
/* File system */
#define FS_VFS
#define VFS_USING_WORKDIR
#define FS_VFS_DEVFS
#define FS_VFS_FATFS
/* APP Framework */
/* Perception */
/* connection */
/* Intelligence */
/* Control */
/* Lib */
#define LIB
#define LIB_POSIX
/* C++ features */
#define LIB_NEWLIB
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 2048
#define MAIN_KTASK_PRIORITY 10
#endif

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#ifndef XS_CONFIG_H__
#define XS_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XiUOS Project Configuration */
#define BOARD_CORTEX_M4_EVB
#define ARCH_ARM
/* BOARD_CORTEX_M4_EVB feature */
#define BSP_USING_DMA
#define BSP_USING_GPIO
#define PIN_BUS_NAME "pin"
#define PIN_DRIVER_NAME "pin_drv"
#define PIN_DEVICE_NAME "pin_dev"
#define BSP_USING_UART
#define BSP_USING_USART1
#define SERIAL_BUS_NAME_1 "usart1"
#define SERIAL_DRV_NAME_1 "usart1_drv"
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
#define BSP_USING_USART2
#define SERIAL_BUS_NAME_2 "usart2"
#define SERIAL_DRV_NAME_2 "usart2_drv"
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
#define BSP_USING_USART3
#define SERIAL_BUS_NAME_3 "usart3"
#define SERIAL_DRV_NAME_3 "usart3_drv"
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
#define BSP_USING_WDT
#define WDT_BUS_NAME "wdt"
#define WDT_DRIVER_NAME "wdt_drv"
#define WDT_DEVICE_NAME "wdt_dev"
/* config default board resources */
/* config board app name */
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
/* config board service table */
#define SERVICE_TABLE_ADDRESS 0x20000000
/* config hardware resources for connection */
/* Hardware feature */
#define RESOURCES_SERIAL
#define SERIAL_USING_DMA
#define SERIAL_RB_BUFSZ 128
#define RESOURCES_PIN
#define RESOURCES_WDT
/* Kernel feature */
/* separate compile(choose none for compile once) */
#define APP_STARTUP_FROM_FLASH
/* Memory Management */
#define MEM_ALIGN_SIZE 8
#define MM_PAGE_SIZE 4096
/* Using small memory allocator */
#define KERNEL_SMALL_MEM_ALLOC
#define SMALL_NUMBER_32B 64
#define SMALL_NUMBER_64B 32
/* Task feature */
#define USER_APPLICATION
/* Inter-Task communication */
#define KERNEL_SEMAPHORE
#define KERNEL_MUTEX
#define KERNEL_EVENT
#define KERNEL_MESSAGEQUEUE
#define KERNEL_SOFTTIMER
#define SCHED_POLICY_RR_REMAINSLICE
#define KTASK_PRIORITY_32
#define KTASK_PRIORITY_MAX 32
#define TICK_PER_SECOND 1000
#define KERNEL_STACK_OVERFLOW_CHECK
#define IDLE_KTASK_STACKSIZE 256
#define ZOMBIE_KTASK_STACKSIZE 2048
/* Kernel Console */
#define KERNEL_CONSOLE
#define KERNEL_BANNER
#define KERNEL_CONSOLEBUF_SIZE 128
/* Kernel Hook */
/* Command shell */
#define TOOL_SHELL
#define SHELL_ENTER_CR
#define SHELL_ENTER_LF
#define SHELL_ENTER_CR_AND_LF
/* Set shell user control */
#define SHELL_DEFAULT_USER "letter"
#define SHELL_DEFAULT_USER_PASSWORD ""
#define SHELL_LOCK_TIMEOUT 10000
/* Set shell config param */
#define SHELL_TASK_STACK_SIZE 4096
#define SHELL_TASK_PRIORITY 20
#define SHELL_MAX_NUMBER 5
#define SHELL_PARAMETER_MAX_NUMBER 8
#define SHELL_HISTORY_MAX_NUMBER 5
#define SHELL_PRINT_BUFFER 128
#define SHELL_HELP_SHOW_PERMISSION
/* Kernel data structure Manage */
#define KERNEL_QUEUEMANAGE
#define KERNEL_WORKQUEUE
#define WORKQUEUE_KTASK_STACKSIZE 512
#define WORKQUEUE_KTASK_PRIORITY 23
#define QUEUE_MAX 16
#define KERNEL_WAITQUEUE
#define KERNEL_DATAQUEUE
/* Kernel components init */
#define KERNEL_COMPONENTS_INIT
#define ENV_INIT_KTASK_STACK_SIZE 8192
#define KERNEL_USER_MAIN
#define NAME_NUM_MAX 32
/* hash table config */
#define ID_HTABLE_SIZE 16
#define ID_NUM_MAX 128
/* File system */
#define FS_VFS
#define VFS_USING_WORKDIR
#define FS_VFS_DEVFS
#define FS_VFS_FATFS
/* APP Framework */
/* Perception */
/* connection */
/* Intelligence */
/* Control */
/* Lib */
#define LIB
#define LIB_POSIX
/* C++ features */
#define LIB_NEWLIB
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 2048
#define MAIN_KTASK_PRIORITY 10
#endif

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#ifndef XS_CONFIG_H__
#define XS_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XiUOS Project Configuration */
#define BOARD_CORTEX_M4_EVB
#define ARCH_ARM
/* BOARD_CORTEX_M4_EVB feature */
#define BSP_USING_DMA
#define BSP_USING_GPIO
#define PIN_BUS_NAME "pin"
#define PIN_DRIVER_NAME "pin_drv"
#define PIN_DEVICE_NAME "pin_dev"
#define BSP_USING_UART
#define BSP_USING_USART1
#define SERIAL_BUS_NAME_1 "usart1"
#define SERIAL_DRV_NAME_1 "usart1_drv"
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
#define BSP_USING_USART2
#define SERIAL_BUS_NAME_2 "usart2"
#define SERIAL_DRV_NAME_2 "usart2_drv"
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
#define BSP_USING_USART3
#define SERIAL_BUS_NAME_3 "usart3"
#define SERIAL_DRV_NAME_3 "usart3_drv"
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
#define BSP_USING_WDT
#define WDT_BUS_NAME "wdt"
#define WDT_DRIVER_NAME "wdt_drv"
#define WDT_DEVICE_NAME "wdt_dev"
/* config default board resources */
/* config board app name */
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
/* config board service table */
#define SERVICE_TABLE_ADDRESS 0x20000000
/* config hardware resources for connection */
/* Hardware feature */
#define RESOURCES_SERIAL
#define SERIAL_USING_DMA
#define SERIAL_RB_BUFSZ 128
#define RESOURCES_PIN
#define RESOURCES_WDT
/* Kernel feature */
/* separate compile(choose none for compile once) */
#define APP_STARTUP_FROM_FLASH
/* Memory Management */
#define MEM_ALIGN_SIZE 8
#define MM_PAGE_SIZE 4096
/* Using small memory allocator */
#define KERNEL_SMALL_MEM_ALLOC
#define SMALL_NUMBER_32B 64
#define SMALL_NUMBER_64B 32
/* Task feature */
#define USER_APPLICATION
/* Inter-Task communication */
#define KERNEL_SEMAPHORE
#define KERNEL_MUTEX
#define KERNEL_EVENT
#define KERNEL_MESSAGEQUEUE
#define KERNEL_SOFTTIMER
#define SCHED_POLICY_RR_REMAINSLICE
#define KTASK_PRIORITY_32
#define KTASK_PRIORITY_MAX 32
#define TICK_PER_SECOND 1000
#define KERNEL_STACK_OVERFLOW_CHECK
#define IDLE_KTASK_STACKSIZE 256
#define ZOMBIE_KTASK_STACKSIZE 2048
/* Kernel Console */
#define KERNEL_CONSOLE
#define KERNEL_BANNER
#define KERNEL_CONSOLEBUF_SIZE 128
/* Kernel Hook */
/* Command shell */
#define TOOL_SHELL
#define SHELL_ENTER_CR
#define SHELL_ENTER_LF
#define SHELL_ENTER_CR_AND_LF
/* Set shell user control */
#define SHELL_DEFAULT_USER "letter"
#define SHELL_DEFAULT_USER_PASSWORD ""
#define SHELL_LOCK_TIMEOUT 10000
/* Set shell config param */
#define SHELL_TASK_STACK_SIZE 4096
#define SHELL_TASK_PRIORITY 20
#define SHELL_MAX_NUMBER 5
#define SHELL_PARAMETER_MAX_NUMBER 8
#define SHELL_HISTORY_MAX_NUMBER 5
#define SHELL_PRINT_BUFFER 128
#define SHELL_HELP_SHOW_PERMISSION
/* Kernel data structure Manage */
#define KERNEL_QUEUEMANAGE
#define KERNEL_WORKQUEUE
#define WORKQUEUE_KTASK_STACKSIZE 512
#define WORKQUEUE_KTASK_PRIORITY 23
#define QUEUE_MAX 16
#define KERNEL_WAITQUEUE
#define KERNEL_DATAQUEUE
/* Kernel components init */
#define KERNEL_COMPONENTS_INIT
#define ENV_INIT_KTASK_STACK_SIZE 8192
#define KERNEL_USER_MAIN
#define NAME_NUM_MAX 32
/* hash table config */
#define ID_HTABLE_SIZE 16
#define ID_NUM_MAX 128
/* File system */
#define FS_VFS
#define VFS_USING_WORKDIR
#define FS_VFS_DEVFS
#define FS_VFS_FATFS
/* APP Framework */
/* Perception */
/* connection */
/* Intelligence */
/* Control */
/* Lib */
#define LIB
#define LIB_POSIX
/* C++ features */
#define LIB_NEWLIB
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 2048
#define MAIN_KTASK_PRIORITY 10
#endif

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#ifndef XS_CONFIG_H__
#define XS_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XiUOS Project Configuration */
#define BOARD_CORTEX_M4_EVB
#define ARCH_ARM
/* BOARD_CORTEX_M4_EVB feature */
#define BSP_USING_DMA
#define BSP_USING_GPIO
#define PIN_BUS_NAME "pin"
#define PIN_DRIVER_NAME "pin_drv"
#define PIN_DEVICE_NAME "pin_dev"
#define BSP_USING_UART
#define BSP_USING_USART1
#define SERIAL_BUS_NAME_1 "usart1"
#define SERIAL_DRV_NAME_1 "usart1_drv"
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
#define BSP_USING_USART2
#define SERIAL_BUS_NAME_2 "usart2"
#define SERIAL_DRV_NAME_2 "usart2_drv"
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
#define BSP_USING_USART3
#define SERIAL_BUS_NAME_3 "usart3"
#define SERIAL_DRV_NAME_3 "usart3_drv"
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
#define BSP_USING_WDT
#define WDT_BUS_NAME "wdt"
#define WDT_DRIVER_NAME "wdt_drv"
#define WDT_DEVICE_NAME "wdt_dev"
/* config default board resources */
/* config board app name */
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
/* config board service table */
#define SERVICE_TABLE_ADDRESS 0x20000000
/* config hardware resources for connection */
/* Hardware feature */
#define RESOURCES_SERIAL
#define SERIAL_USING_DMA
#define SERIAL_RB_BUFSZ 128
#define RESOURCES_PIN
#define RESOURCES_WDT
/* Kernel feature */
/* separate compile(choose none for compile once) */
#define APP_STARTUP_FROM_FLASH
/* Memory Management */
#define MEM_ALIGN_SIZE 8
#define MM_PAGE_SIZE 4096
/* Using small memory allocator */
#define KERNEL_SMALL_MEM_ALLOC
#define SMALL_NUMBER_32B 64
#define SMALL_NUMBER_64B 32
/* Task feature */
#define USER_APPLICATION
/* Inter-Task communication */
#define KERNEL_SEMAPHORE
#define KERNEL_MUTEX
#define KERNEL_EVENT
#define KERNEL_MESSAGEQUEUE
#define KERNEL_SOFTTIMER
#define SCHED_POLICY_RR_REMAINSLICE
#define KTASK_PRIORITY_32
#define KTASK_PRIORITY_MAX 32
#define TICK_PER_SECOND 1000
#define KERNEL_STACK_OVERFLOW_CHECK
#define IDLE_KTASK_STACKSIZE 256
#define ZOMBIE_KTASK_STACKSIZE 2048
/* Kernel Console */
#define KERNEL_CONSOLE
#define KERNEL_BANNER
#define KERNEL_CONSOLEBUF_SIZE 128
/* Kernel Hook */
/* Command shell */
#define TOOL_SHELL
#define SHELL_ENTER_CR
#define SHELL_ENTER_LF
#define SHELL_ENTER_CR_AND_LF
/* Set shell user control */
#define SHELL_DEFAULT_USER "letter"
#define SHELL_DEFAULT_USER_PASSWORD ""
#define SHELL_LOCK_TIMEOUT 10000
/* Set shell config param */
#define SHELL_TASK_STACK_SIZE 4096
#define SHELL_TASK_PRIORITY 20
#define SHELL_MAX_NUMBER 5
#define SHELL_PARAMETER_MAX_NUMBER 8
#define SHELL_HISTORY_MAX_NUMBER 5
#define SHELL_PRINT_BUFFER 128
#define SHELL_HELP_SHOW_PERMISSION
/* Kernel data structure Manage */
#define KERNEL_QUEUEMANAGE
#define KERNEL_WORKQUEUE
#define WORKQUEUE_KTASK_STACKSIZE 512
#define WORKQUEUE_KTASK_PRIORITY 23
#define QUEUE_MAX 16
#define KERNEL_WAITQUEUE
#define KERNEL_DATAQUEUE
/* Kernel components init */
#define KERNEL_COMPONENTS_INIT
#define ENV_INIT_KTASK_STACK_SIZE 8192
#define KERNEL_USER_MAIN
#define NAME_NUM_MAX 32
/* hash table config */
#define ID_HTABLE_SIZE 16
#define ID_NUM_MAX 128
/* File system */
#define FS_VFS
#define VFS_USING_WORKDIR
#define FS_VFS_DEVFS
#define FS_VFS_FATFS
/* APP Framework */
/* Perception */
/* connection */
/* Intelligence */
/* Control */
/* Lib */
#define LIB
#define LIB_POSIX
/* C++ features */
#define LIB_NEWLIB
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 2048
#define MAIN_KTASK_PRIORITY 10
#endif

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#ifndef XS_CONFIG_H__
#define XS_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XiUOS Project Configuration */
#define BOARD_CORTEX_M4_EVB
#define ARCH_ARM
/* BOARD_CORTEX_M4_EVB feature */
#define BSP_USING_DMA
#define BSP_USING_GPIO
#define PIN_BUS_NAME "pin"
#define PIN_DRIVER_NAME "pin_drv"
#define PIN_DEVICE_NAME "pin_dev"
#define BSP_USING_UART
#define BSP_USING_USART1
#define SERIAL_BUS_NAME_1 "usart1"
#define SERIAL_DRV_NAME_1 "usart1_drv"
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
#define BSP_USING_USART2
#define SERIAL_BUS_NAME_2 "usart2"
#define SERIAL_DRV_NAME_2 "usart2_drv"
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
#define BSP_USING_USART3
#define SERIAL_BUS_NAME_3 "usart3"
#define SERIAL_DRV_NAME_3 "usart3_drv"
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
#define BSP_USING_WDT
#define WDT_BUS_NAME "wdt"
#define WDT_DRIVER_NAME "wdt_drv"
#define WDT_DEVICE_NAME "wdt_dev"
/* config default board resources */
/* config board app name */
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
/* config board service table */
#define SERVICE_TABLE_ADDRESS 0x20000000
/* config hardware resources for connection */
/* Hardware feature */
#define RESOURCES_SERIAL
#define SERIAL_USING_DMA
#define SERIAL_RB_BUFSZ 128
#define RESOURCES_PIN
#define RESOURCES_WDT
/* Kernel feature */
/* separate compile(choose none for compile once) */
#define APP_STARTUP_FROM_FLASH
/* Memory Management */
#define MEM_ALIGN_SIZE 8
#define MM_PAGE_SIZE 4096
/* Using small memory allocator */
#define KERNEL_SMALL_MEM_ALLOC
#define SMALL_NUMBER_32B 64
#define SMALL_NUMBER_64B 32
/* Task feature */
#define USER_APPLICATION
/* Inter-Task communication */
#define KERNEL_SEMAPHORE
#define KERNEL_MUTEX
#define KERNEL_EVENT
#define KERNEL_MESSAGEQUEUE
#define KERNEL_SOFTTIMER
#define SCHED_POLICY_RR_REMAINSLICE
#define KTASK_PRIORITY_32
#define KTASK_PRIORITY_MAX 32
#define TICK_PER_SECOND 1000
#define KERNEL_STACK_OVERFLOW_CHECK
#define IDLE_KTASK_STACKSIZE 256
#define ZOMBIE_KTASK_STACKSIZE 2048
/* Kernel Console */
#define KERNEL_CONSOLE
#define KERNEL_BANNER
#define KERNEL_CONSOLEBUF_SIZE 128
/* Kernel Hook */
/* Command shell */
#define TOOL_SHELL
#define SHELL_ENTER_CR
#define SHELL_ENTER_LF
#define SHELL_ENTER_CR_AND_LF
/* Set shell user control */
#define SHELL_DEFAULT_USER "letter"
#define SHELL_DEFAULT_USER_PASSWORD ""
#define SHELL_LOCK_TIMEOUT 10000
/* Set shell config param */
#define SHELL_TASK_STACK_SIZE 4096
#define SHELL_TASK_PRIORITY 20
#define SHELL_MAX_NUMBER 5
#define SHELL_PARAMETER_MAX_NUMBER 8
#define SHELL_HISTORY_MAX_NUMBER 5
#define SHELL_PRINT_BUFFER 128
#define SHELL_HELP_SHOW_PERMISSION
/* Kernel data structure Manage */
#define KERNEL_QUEUEMANAGE
#define KERNEL_WORKQUEUE
#define WORKQUEUE_KTASK_STACKSIZE 512
#define WORKQUEUE_KTASK_PRIORITY 23
#define QUEUE_MAX 16
#define KERNEL_WAITQUEUE
#define KERNEL_DATAQUEUE
/* Kernel components init */
#define KERNEL_COMPONENTS_INIT
#define ENV_INIT_KTASK_STACK_SIZE 8192
#define KERNEL_USER_MAIN
#define NAME_NUM_MAX 32
/* hash table config */
#define ID_HTABLE_SIZE 16
#define ID_NUM_MAX 128
/* File system */
#define FS_VFS
#define VFS_USING_WORKDIR
#define FS_VFS_DEVFS
#define FS_VFS_FATFS
/* APP Framework */
/* Perception */
/* connection */
/* Intelligence */
/* Control */
/* Lib */
#define LIB
#define LIB_POSIX
/* C++ features */
#define LIB_NEWLIB
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 2048
#define MAIN_KTASK_PRIORITY 10
#endif

185
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140903.h
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@ -1,185 +0,0 @@
#ifndef XS_CONFIG_H__
#define XS_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XiUOS Project Configuration */
#define BOARD_CORTEX_M4_EVB
#define ARCH_ARM
/* BOARD_CORTEX_M4_EVB feature */
#define BSP_USING_DMA
#define BSP_USING_GPIO
#define PIN_BUS_NAME "pin"
#define PIN_DRIVER_NAME "pin_drv"
#define PIN_DEVICE_NAME "pin_dev"
#define BSP_USING_UART
#define BSP_USING_USART1
#define SERIAL_BUS_NAME_1 "usart1"
#define SERIAL_DRV_NAME_1 "usart1_drv"
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
#define BSP_USING_USART2
#define SERIAL_BUS_NAME_2 "usart2"
#define SERIAL_DRV_NAME_2 "usart2_drv"
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
#define BSP_USING_USART3
#define SERIAL_BUS_NAME_3 "usart3"
#define SERIAL_DRV_NAME_3 "usart3_drv"
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
#define BSP_USING_WDT
#define WDT_BUS_NAME "wdt"
#define WDT_DRIVER_NAME "wdt_drv"
#define WDT_DEVICE_NAME "wdt_dev"
/* config default board resources */
/* config board app name */
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
/* config board service table */
#define SERVICE_TABLE_ADDRESS 0x20000000
/* config hardware resources for connection */
/* Hardware feature */
#define RESOURCES_SERIAL
#define SERIAL_USING_DMA
#define SERIAL_RB_BUFSZ 128
#define RESOURCES_PIN
#define RESOURCES_WDT
/* Kernel feature */
/* separate compile(choose none for compile once) */
#define APP_STARTUP_FROM_FLASH
/* Memory Management */
#define MEM_ALIGN_SIZE 8
#define MM_PAGE_SIZE 4096
/* Using small memory allocator */
#define KERNEL_SMALL_MEM_ALLOC
#define SMALL_NUMBER_32B 64
#define SMALL_NUMBER_64B 32
/* Task feature */
#define USER_APPLICATION
/* Inter-Task communication */
#define KERNEL_SEMAPHORE
#define KERNEL_MUTEX
#define KERNEL_EVENT
#define KERNEL_MESSAGEQUEUE
#define KERNEL_SOFTTIMER
#define SCHED_POLICY_RR_REMAINSLICE
#define KTASK_PRIORITY_32
#define KTASK_PRIORITY_MAX 32
#define TICK_PER_SECOND 1000
#define KERNEL_STACK_OVERFLOW_CHECK
#define IDLE_KTASK_STACKSIZE 256
#define ZOMBIE_KTASK_STACKSIZE 2048
/* Kernel Console */
#define KERNEL_CONSOLE
#define KERNEL_BANNER
#define KERNEL_CONSOLEBUF_SIZE 128
/* Kernel Hook */
/* Command shell */
#define TOOL_SHELL
#define SHELL_ENTER_CR
#define SHELL_ENTER_LF
#define SHELL_ENTER_CR_AND_LF
/* Set shell user control */
#define SHELL_DEFAULT_USER "letter"
#define SHELL_DEFAULT_USER_PASSWORD ""
#define SHELL_LOCK_TIMEOUT 10000
/* Set shell config param */
#define SHELL_TASK_STACK_SIZE 4096
#define SHELL_TASK_PRIORITY 20
#define SHELL_MAX_NUMBER 5
#define SHELL_PARAMETER_MAX_NUMBER 8
#define SHELL_HISTORY_MAX_NUMBER 5
#define SHELL_PRINT_BUFFER 128
#define SHELL_HELP_SHOW_PERMISSION
/* Kernel data structure Manage */
#define KERNEL_QUEUEMANAGE
#define KERNEL_WORKQUEUE
#define WORKQUEUE_KTASK_STACKSIZE 512
#define WORKQUEUE_KTASK_PRIORITY 23
#define QUEUE_MAX 16
#define KERNEL_WAITQUEUE
#define KERNEL_DATAQUEUE
/* Kernel components init */
#define KERNEL_COMPONENTS_INIT
#define ENV_INIT_KTASK_STACK_SIZE 8192
#define KERNEL_USER_MAIN
#define NAME_NUM_MAX 32
/* hash table config */
#define ID_HTABLE_SIZE 16
#define ID_NUM_MAX 128
/* File system */
#define FS_VFS
#define VFS_USING_WORKDIR
#define FS_VFS_DEVFS
#define FS_VFS_FATFS
/* APP Framework */
/* Perception */
/* connection */
/* Intelligence */
/* Control */
/* Lib */
#define LIB
#define LIB_POSIX
/* C++ features */
#define LIB_NEWLIB
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 2048
#define MAIN_KTASK_PRIORITY 10
#endif

185
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140904.h
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@ -1,185 +0,0 @@
#ifndef XS_CONFIG_H__
#define XS_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XiUOS Project Configuration */
#define BOARD_CORTEX_M4_EVB
#define ARCH_ARM
/* BOARD_CORTEX_M4_EVB feature */
#define BSP_USING_DMA
#define BSP_USING_GPIO
#define PIN_BUS_NAME "pin"
#define PIN_DRIVER_NAME "pin_drv"
#define PIN_DEVICE_NAME "pin_dev"
#define BSP_USING_UART
#define BSP_USING_USART1
#define SERIAL_BUS_NAME_1 "usart1"
#define SERIAL_DRV_NAME_1 "usart1_drv"
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
#define BSP_USING_USART2
#define SERIAL_BUS_NAME_2 "usart2"
#define SERIAL_DRV_NAME_2 "usart2_drv"
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
#define BSP_USING_USART3
#define SERIAL_BUS_NAME_3 "usart3"
#define SERIAL_DRV_NAME_3 "usart3_drv"
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
#define BSP_USING_WDT
#define WDT_BUS_NAME "wdt"
#define WDT_DRIVER_NAME "wdt_drv"
#define WDT_DEVICE_NAME "wdt_dev"
/* config default board resources */
/* config board app name */
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
/* config board service table */
#define SERVICE_TABLE_ADDRESS 0x20000000
/* config hardware resources for connection */
/* Hardware feature */
#define RESOURCES_SERIAL
#define SERIAL_USING_DMA
#define SERIAL_RB_BUFSZ 128
#define RESOURCES_PIN
#define RESOURCES_WDT
/* Kernel feature */
/* separate compile(choose none for compile once) */
#define APP_STARTUP_FROM_FLASH
/* Memory Management */
#define MEM_ALIGN_SIZE 8
#define MM_PAGE_SIZE 4096
/* Using small memory allocator */
#define KERNEL_SMALL_MEM_ALLOC
#define SMALL_NUMBER_32B 64
#define SMALL_NUMBER_64B 32
/* Task feature */
#define USER_APPLICATION
/* Inter-Task communication */
#define KERNEL_SEMAPHORE
#define KERNEL_MUTEX
#define KERNEL_EVENT
#define KERNEL_MESSAGEQUEUE
#define KERNEL_SOFTTIMER
#define SCHED_POLICY_RR_REMAINSLICE
#define KTASK_PRIORITY_32
#define KTASK_PRIORITY_MAX 32
#define TICK_PER_SECOND 1000
#define KERNEL_STACK_OVERFLOW_CHECK
#define IDLE_KTASK_STACKSIZE 256
#define ZOMBIE_KTASK_STACKSIZE 2048
/* Kernel Console */
#define KERNEL_CONSOLE
#define KERNEL_BANNER
#define KERNEL_CONSOLEBUF_SIZE 128
/* Kernel Hook */
/* Command shell */
#define TOOL_SHELL
#define SHELL_ENTER_CR
#define SHELL_ENTER_LF
#define SHELL_ENTER_CR_AND_LF
/* Set shell user control */
#define SHELL_DEFAULT_USER "letter"
#define SHELL_DEFAULT_USER_PASSWORD ""
#define SHELL_LOCK_TIMEOUT 10000
/* Set shell config param */
#define SHELL_TASK_STACK_SIZE 4096
#define SHELL_TASK_PRIORITY 20
#define SHELL_MAX_NUMBER 5
#define SHELL_PARAMETER_MAX_NUMBER 8
#define SHELL_HISTORY_MAX_NUMBER 5
#define SHELL_PRINT_BUFFER 128
#define SHELL_HELP_SHOW_PERMISSION
/* Kernel data structure Manage */
#define KERNEL_QUEUEMANAGE
#define KERNEL_WORKQUEUE
#define WORKQUEUE_KTASK_STACKSIZE 512
#define WORKQUEUE_KTASK_PRIORITY 23
#define QUEUE_MAX 16
#define KERNEL_WAITQUEUE
#define KERNEL_DATAQUEUE
/* Kernel components init */
#define KERNEL_COMPONENTS_INIT
#define ENV_INIT_KTASK_STACK_SIZE 8192
#define KERNEL_USER_MAIN
#define NAME_NUM_MAX 32
/* hash table config */
#define ID_HTABLE_SIZE 16
#define ID_NUM_MAX 128
/* File system */
#define FS_VFS
#define VFS_USING_WORKDIR
#define FS_VFS_DEVFS
#define FS_VFS_FATFS
/* APP Framework */
/* Perception */
/* connection */
/* Intelligence */
/* Control */
/* Lib */
#define LIB
#define LIB_POSIX
/* C++ features */
#define LIB_NEWLIB
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 2048
#define MAIN_KTASK_PRIORITY 10
#endif

218
Ubiquitous/XiUOS/board/stm32f103-nano/.defconfig Normal file
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@ -0,0 +1,218 @@
#
# Automatically generated file; DO NOT EDIT.
# XiUOS Project Configuration
#
CONFIG_BOARD_STM32F103_NANO=y
CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uart1"
CONFIG_ARCH_ARM=y
#
# stm32f103-nano feature
#
# CONFIG_BSP_USING_DMA is not set
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_LCD is not set
# CONFIG_BSP_USING_EXTMEM is not set
# CONFIG_BSP_USING_SDIO is not set
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_HWTIMER is not set
# CONFIG_BSP_USING_WDT is not set
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_USB is not set
# CONFIG_BSP_USING_USBH is not set
#
# Hardware feature
#
CONFIG_RESOURCES_SERIAL=y
# CONFIG_SERIAL_USING_DMA is not set
# CONFIG_SERIAL_RB_BUFSZ is not set
# CONFIG_RESOURCES_CAN is not set
# CONFIG_RESOURCES_HWTIMER is not set
# CONFIG_RESOURCES_I2C is not set
# CONFIG_RESOURCES_LCD is not set
# CONFIG_RESOURCES_SDIO is not set
# CONFIG_RESOURCES_TOUCH is not set
CONFIG_RESOURCES_PIN=y
# CONFIG_RESOURCES_RTC is not set
# CONFIG_RESOURCES_SPI is not set
# CONFIG_RESOURCES_SPI_SD is not set
# CONFIG_RESOURCES_SPI_SFUD is not set
# SFUD_USING_SFDP is not set
# SFUD_USING_FLASH_INFO_TABLE is not set
# SFUD_DEBUG_LOG is not set
# CONFIG_RESOURCES_WDT is not set
# CONFIG_RESOURCES_USB is not set
# CONFIG_RESOURCES_USB_HOST is not set
# CONFIG_UDISK_MOUNTPOINT is not set
# CONFIG_USBH_MSTORAGE is not set
# CONFIG_RESOURCES_USB_DEVICE is not set
# CONFIG_USBD_THREAD_STACK_SZ is not set
#
# Kernel feature
#
# CONFIG_SEPARATE_COMPILE is not set
# CONFIG_COMPILER_APP is not set
# CONFIG_COMPILER_KERNEL is not set
#
# Kernel Device Object
#
CONFIG_KERNEL_DEVICE=y
CONFIG_KERNEL_CONSOLE=y
CONFIG_KERNEL_CONSOLEBUF_SIZE=128
#
# Task feature
#
CONFIG_SCHED_POLICY_RR_REMAINSLICE=y
# CONFIG_SCHED_POLICY_RR is not set
# CONFIG_SCHED_POLICY_FIFO is not set
#
# Inter-Task communication
#
CONFIG_KERNEL_SEMAPHORE=y
CONFIG_KERNEL_MUTEX=y
CONFIG_KERNEL_EVENT=y
CONFIG_KERNEL_MESSAGEQUEUE=y
# CONFIG_KTASK_PRIORITY_8 is not set
CONFIG_KTASK_PRIORITY_32=y
# CONFIG_KTASK_PRIORITY_256 is not set
CONFIG_KTASK_PRIORITY_MAX=32
CONFIG_TICK_PER_SECOND=1000
CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y
CONFIG_KERNEL_BANNER=y
# CONFIG_KERNEL_HOOK is not set
CONFIG_KERNEL_SOFTTIMER=y
CONFIG_KERNEL_IDLE_HOOK=y
CONFIG_IDEL_HOOK_LIST_SIZE=4
CONFIG_IDLE_KTASK_STACKSIZE=256
CONFIG_USER_APPLICATION=y
# CONFIG_TASK_ISOLATION is not set
#
# Memory Management
#
# CONFIG_KERNEL_MEMBLOCK is not set
#
# Command shell
#
CONFIG_TOOL_SHELL=y
CONFIG_SHELL_ENTER_CR=y
CONFIG_SHELL_ENTER_LF=y
CONFIG_SHELL_ENTER_CR_AND_LF=y
# CONFIG_SHELL_ENTER_CRLF is not set
#
# User Control
#
CONFIG_SHELL_DEFAULT_USER="letter"
CONFIG_SHELL_DEFAULT_USER_PASSWORD=""
CONFIG_SHELL_LOCK_TIMEOUT=10000
CONFIG_SHELL_TASK_STACK_SIZE=4096
CONFIG_SHELL_TASK_PRIORITY=20
CONFIG_SHELL_MAX_NUMBER=5
CONFIG_SHELL_PARAMETER_MAX_NUMBER=8
CONFIG_SHELL_HISTORY_MAX_NUMBER=5
CONFIG_SHELL_PRINT_BUFFER=128
CONFIG_SHELL_USING_CMD_EXPORT=y
CONFIG_SHELL_HELP_SHOW_PERMISSION=y
# CONFIG_SHELL_HELP_LIST_USER is not set
# CONFIG_SHELL_HELP_LIST_VAR is not set
# CONFIG_SHELL_HELP_LIST_KEY is not set
# CONFIG_KERNEL_QUEUEMANAGE is not set
# CONFIG_KERNEL_WORKQUEUE is not set
# CONFIG_WORKQUEUE_KTASK_STACKSIZE is not set
# CONFIG_WORKQUEUE_KTASK_PRIORITY is not set
# CONFIG_KERNEL_WAITQUEUE is not set
# CONFIG_KERNEL_DATAQUEUE is not set
# CONFIG_KERNEL_CIRCULAR_AREA is not set
# CONFIG_KERNEL_AVL_TREE is not set
CONFIG_NAME_MAX=8
CONFIG_ALIGN_SIZE=4
CONFIG_KERNEL_COMPONENTS_INIT=y
CONFIG_KERNEL_USER_MAIN=y
CONFIG_MAIN_KTASK_STACK_SIZE=256
CONFIG_ENV_INIT_KTASK_STACK_SIZE=1024
CONFIG_MAIN_KTASK_PRIORITY=10
# CONFIG_USER_TEST is not set
# CONFIG_TOOL_TEST_SEM is not set
# CONFIG_TOOL_TEST_MUTEX is not set
# CONFIG_TOOL_TEST_EVENT is not set
# CONFIG_TOOL_TEST_MSG is not set
# CONFIG_TOOL_TEST_AVLTREE is not set
# CONFIG_TEST_CRICULAR_AREA is not set
# CONFIG_TOOL_TEST_MEM is not set
# CONFIG_TOOL_TEST_TIMER is not set
# CONFIG_TOOL_TEST_IWG is not set
# CONFIG_TOOL_TEST_REALTIME is not set
# CONFIG_TOOL_TEST_DBG is not set
# CONFIG_TOOL_TEST_SCHED is not set
# CONFIG_KERNEL_DEBUG is not set
CONFIG_DEBUG_INIT_CONFIG=y
CONFIG_DBG_INIT=1
# CONFIG_ARCH_SMP is not set
#
# File system
#
# CONFIG_FS_VFS is not set
# CONFIG_VFS_USING_WORKDIR is not set
# CONFIG_FS_VFS_DEVFS is not set
#
# Fat filesystem
#
#
# IOT-Device File system
#
#
# Lwext4 filesystem
#
#
# APP Framework
#
#
# connection
#
# CONFIG_CONNECTION_AT is not set
# CONFIG_CONNECTION_MQTT is not set
#
# medium communication
#
#
# Intelligence
#
#
# Control
#
#
# Lib
#
CONFIG_LIB=y
CONFIG_LIB_POSIX=y
CONFIG_LIB_NEWLIB=y
CONFIG_LITTLEVGL2RTT_USING_DEMO=y
#
# Security
#

20
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134324 → Ubiquitous/XiUOS/board/stm32f103-nano/Kconfig
View File

@ -10,21 +10,21 @@ config KERNEL_DIR
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M4_EVB
config BOARD_STM32F103_NANO
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "cortex-m4 emulator feature"
menu "stm32f103-nano feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "//XiUOS_cortex-m4-emulator_app.bin"
default "/XiUOS_stm32f103nano_app.bin"
endmenu
menu "config board service table"
@ -33,20 +33,6 @@ menu "cortex-m4 emulator feature"
default 0x20000000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/usart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/usart3_dev3"
endif
endmenu
endmenu
endmenu

8
Ubiquitous/XiUOS/board/stm32f103-nano/Makefile Normal file
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@ -0,0 +1,8 @@
SRC_FILES := board.c
SRC_DIR := third_party_driver
include $(KERNEL_ROOT)/compiler.mk

222
Ubiquitous/XiUOS/board/stm32f103-nano/README.md Normal file
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@ -0,0 +1,222 @@
# 从零开始构建矽璓工业物联操作系统：使用ARM架构的STM32F103-nano开发板
[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓工业物联操作系统是一款面向工业物联场景的泛在操作系统，来自泛在操作系统研究计划。所谓泛在操作系统(UOS: Ubiquitous Operating Systems)，是支持互联网时代人机物融合泛在计算应用模式的新型操作系统，是传统操作系统概念的泛化与延伸。在泛在操作系统技术体系中，不同的泛在计算设备和泛在应用场景需要符合各自特性的不同UOS，XiUOS即是面向工业物联场景的一种UOS，主要由一个极简的微型实时操作系统(RTOS)内核和其上的智能工业物联框架构成，支持工业物联网(IIoT: Industrial Internet of Things)应用。
## 开发环境搭建
### 推荐使用：
**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改）
第一步:打开sources.list文件
```c
sudo vim /etc/apt/sources.list
```
第二步:将以下内容复制到sources.list文件
```c
deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
```
第三步:更新源和系统软件
```c
sudo apt-get update
sudo apt-get upgrade
```
**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
### 依赖包安装：
```
$ sudo apt install build-essential pkg-config git
$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
```
**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：
```c
mkdir test && cd test
git clone https://git.trustie.net/xuos/xiuos.git
```
打开源码文件包可以看到以下目录：
| 名称 | 说明 |
| -- | -- |
| application | 应用代码 |
| board | 板级支持包 |
| framework | 应用框架 |
| fs | 文件系统 |
| kernel | 内核源码 |
| resources | 驱动文件 |
| tool | 系统工具 |
使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：
<div align= "center">
<img src = img/vscode.jpg width =1000>
</div>
### 裁减配置工具的下载
裁减配置工具：
**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
```c
mkdir kfrontends && cd kfrontends
git clone https://git.trustie.net/xuos/kconfig-frontends.git
```
下载源码后按以下步骤执行软件安装：
```c
cd kconfig-frontends
./xs_build.sh
```
### 编译工具链：
ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。
```shell
$ sudo apt install gcc-arm-none-eabi
```
# 在STM32F103-nano上创建第一个应用 --helloworld
## 1. 简介
| 硬件 | 描述 |
| -- | -- |
|芯片型号| Stm32F103RBT6|
|CPU|arm cortex-m3|
|主频| 72MHz |
|片内SRAM| 20KB |
|片上FLASH| 128KB |
| 外设 | -- |
| | ADC、DAC、USB、GPIO、UART、SPI、SDIO、RTC、CAN、DMA、MAC、I²C、WDT、Timer等 |
XiUOS板级驱动当前支持使用GPIO、UART。
## 2. 编译说明
### 编辑环境：`Ubuntu18.04`
### 编译工具链：`arm-none-eabi-gcc`
使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目
修改`APP_Framework/Applications`文件夹下`main.c`
在输出函数中写入 `Hello, world!`完成代码编辑。
![main](img/main.png)
编译步骤：
1.在VScode命令终端中执行以下命令，生成配置文件。
```c
make BOARD=stm32f103-nano distclean
make BOARD=stm32f103-nano menuconfig
```
2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）。
![menuconfig1](img/menuconfig1.png)
退出时选择`yes`保存上面所配置的内容，如下图所示：
![menuconfig2](img/menuconfig2.png)
3.需要注意的是，stm32f103-nano开发板中CPU RAM大小为20KB，需要调整XiUOS中堆栈相关配置的默认值，避免出现超出堆栈大小而无法正常启动。
（1）ID hash table配置，ID num配置为16，减少.bss段大小;
![ID_HASH_TABLE](img/ID_HASH_TABLE.png)
（2）IPC feature配置，保留信号量、互斥锁等必需的进程间通信，关闭队列等未用到的方式;
![IPC_FEATURE](img/IPC_FEATURE.png)
（3）ENV task配置，该线程栈大小配置为1024;
![KTASK_SIZE](img/KTASK_SIZE.png)
（4）MAIN task配置，该线程栈大小配置为256;
![MAIN_STACK_SIZE](img/MAIN_STACK_SIZE.png)
（5）大内存分配页对齐配置，页对齐配置为1KB，减少页对齐后优化的ram空间，增加可分配的堆大小;
![MEMORY_PAGE_SIZE](img/MEMORY_PAGE_SIZE.png)
（6）SHELL task配置，该线程栈大小配置为4096，建议无优化空间时再选择减少SHELL线程栈大小，避免出现SHELL工作异常的情况;
![SHELL_STACK_SIZE](img/SHELL_STACK_SIZE.png)
（7）WORKQUEUE配置，若未用到工作队列，可关闭该功能，减少堆栈空间申请;
![WORKQUEUE](img/WORKQUEUE.png)
（7）ZOMBIE RECYCLE task配置 ，僵尸线程回收线程栈大小同样在无优化空间时可选择减少。
![ZOMBIE_STACK_SIZE](img/ZOMBIE_STACK_SIZE.png)
4.继续执行以下命令，进行编译
```c
make BOARD=stm32f103-nano
```
5.如果编译正确无误，会产生XiUOS_stm32f103-nano.elf、XiUOS_stm32f103-nano.bin文件。其中XiUOS_stm32f103-nano.bin需要烧写到设备中进行运行。
## 3. 烧写及执行
stm32f103-nano开发板内置板载st-link SWD下载接口，连接USB后便可使用st-flash工具进行烧写bin文件。
![stm32f103-nano](img/stm32f103-nano.png)
### 烧写工具
ARM：ST-LINK, stm32f103-nano 板卡内置st-link SWD, 因此无需额外外接工具，只需安装st-flash相关依赖驱动即可。
下载并以下执行命令以下命令安装st-link工具(本文使用v1.5.1版本)。
```
sudo apt install libusb-dev
sudo apt install libusb-1.0-0-dev
sudo apt install cmake
cd stlink
make
cd build/Release && make install DESTDIR=_install
```
将生成的st-flash（在stlink/build/Release/bin文件夹下）复制到/usr/bin下就可使用了
代码根目录下执行st-flash工具烧录
```
sudo st-flash write build/XiUOS_stm32f103-nano.bin 0x8000000
```
### 3.1 运行结果
如果编译 & 烧写无误，将会在串口终端上看到信息打印输出。
![terminal](img/terminal.png)

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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.c
* @brief support stm32f103-nano-board init configure and start-up
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-11-25
*/
#include <board.h>
#include <xiuos.h>
#include <device.h>
#include <arch_interrupt.h>
#include <stm32f1xx_hal_rcc.h>
#include <stm32f1xx_hal_rcc_ex.h>
extern int InitHwUart(void);
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
|RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
//Error_Handler();
}
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
//Error_Handler();
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC;
PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
//Error_Handler();
}
}
void SysTick_Handler(int irqn, void *arg)
{
TickAndTaskTimesliceUpdate();
}
void InitBoardHardware()
{
HAL_Init();
/* enable interrupt */
__set_PRIMASK(0);
/* System clock initialization */
SystemClock_Config();
/* disable interrupt */
__set_PRIMASK(1);
InitHwUart();
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
InitBoardMemory((void*)HEAP_START, (void*)HEAP_END);
}

35
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.h
* @brief define stm32f103-nano init configure and start-up function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-11-25
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <stm32f1xx.h>
#include <connect_uart.h>
extern void *__bss_end;
extern void *_heap_end;
#define HEAP_START ((void *)&__bss_end)
#define HEAP_END ((void *)&_heap_end)
void SystemClock_Config(void);
#endif

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export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
export CFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb
export AFLAGS := -c -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
export LFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f103-nano.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
export CXXFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g
export APPLFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
export DEFINES := -DHAVE_CCONFIG_H
export ARCH = arm
export MCU = cortex-m3

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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. October 2015
* $Revision: V.1.4.5 a
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
/* extern const q31_t realCoefAQ31[1024]; */
/* extern const q31_t realCoefBQ31[1024]; */
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. March 2015
* $Revision: V.1.4.5
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
* @date 19. June 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

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Ubiquitous/XiUOS/board/stm32f103-nano/include/stm32f1xx.h Normal file
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/**
******************************************************************************
* @file stm32f1xx.h
* @author MCD Application Team
* @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F1xx device used in the target application
* - To use or not the peripheral<EFBFBD>s drivers in application code(i.e.
* code will be based on direct access to peripheral<EFBFBD>s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f1xx
* @{
*/
#ifndef __STM32F1XX_H
#define __STM32F1XX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F1)
#define STM32F1
#endif /* STM32F1 */
#if !defined (STM32F103xB)
#define STM32F103xB
#define USE_HAL_DRIVER
#endif
/* Uncomment the line below according to the target STM32L device used in your
application
*/
#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
!defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
!defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
/* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
/* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
/* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
/* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
/* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
/* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
/* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
/* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
/* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
/* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
/* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
/* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
/* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
/* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V4.3.1
*/
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F1_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32F100xB)
#include "stm32f100xb.h"
#elif defined(STM32F100xE)
#include "stm32f100xe.h"
#elif defined(STM32F101x6)
#include "stm32f101x6.h"
#elif defined(STM32F101xB)
#include "stm32f101xb.h"
#elif defined(STM32F101xE)
#include "stm32f101xe.h"
#elif defined(STM32F101xG)
#include "stm32f101xg.h"
#elif defined(STM32F102x6)
#include "stm32f102x6.h"
#elif defined(STM32F102xB)
#include "stm32f102xb.h"
#elif defined(STM32F103x6)
#include "stm32f103x6.h"
#elif defined(STM32F103xB)
#include "stm32f103xb.h"
#elif defined(STM32F103xE)
#include "stm32f103xe.h"
#elif defined(STM32F103xG)
#include "stm32f103xg.h"
#elif defined(STM32F105xC)
#include "stm32f105xc.h"
#elif defined(STM32F107xC)
#include "stm32f107xc.h"
#else
#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0U,
ST_ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include <stm32f1xx_hal.h>
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F1xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

85
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f1xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_IT_H
#define __STM32F1xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void USART1_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

98
Ubiquitous/XiUOS/board/stm32f103-nano/include/system_stm32f1xx.h Normal file
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/**
******************************************************************************
* @file system_stm32f10x.h
* @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f10x_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F10X_H
#define __SYSTEM_STM32F10X_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F10x_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_types
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F10X_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Ubiquitous/XiUOS/board/stm32f103-nano/link.lds Normal file
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/*
* linker script for STM32F10x with GNU ld
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
flash (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */
sram (rw) : ORIGIN = 0x20000000, LENGTH = 20k /* 20K sram */
}
OUTPUT_ARCH(arm)
ENTRY(Reset_Handler)
_system_stack_size = 0x200;
SECTIONS
{
.text :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
/* section information for shell */
. = ALIGN(4);
_shell_command_start = .;
KEEP (*(shellCommand))
_shell_command_end = .;
. = ALIGN(4);
__isrtbl_idx_start = .;
KEEP(*(.isrtbl.idx))
__isrtbl_start = .;
KEEP(*(.isrtbl))
__isrtbl_end = .;
. = ALIGN(4);
PROVIDE(g_service_table_start = ABSOLUTE(.));
KEEP(*(.g_service_table))
PROVIDE(g_service_table_end = ABSOLUTE(.));
PROVIDE(_etext = ABSOLUTE(.));
_etext = .;
} > flash = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > flash
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >sram
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
} > sram
__bss_end = .;
_end = .;
.stack ORIGIN(sram) + LENGTH(sram) - _system_stack_size :
{
PROVIDE( _heap_end = . );
. = _system_stack_size;
PROVIDE( _sp = . );
} >sram
}

7
Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/Kconfig Executable file
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@ -0,0 +1,7 @@
menuconfig BSP_USING_UART
bool "Using UART device"
default y
select RESOURCES_SERIAL
if BSP_USING_UART
source "$BSP_DIR/third_party_driver/uart/Kconfig"
endif

7
Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/Makefile Normal file
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@ -0,0 +1,7 @@
SRC_DIR := libraries
ifeq ($(CONFIG_BSP_USING_UART),y)
SRC_DIR += uart
endif
include $(KERNEL_ROOT)/compiler.mk

48
Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/include/connect_usart_20210825135326.h → Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/include/connect_uart.h
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@ -11,50 +11,38 @@
*/
/**
* @file connect_usart.h
* @brief define stm32f407-st-discovery-board usart function and struct
* @file connect_uart.h
* @brief define stm32f103-nano-board uart function and struct
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
* @date 2021-11-25
*/
#ifndef CONNECT_USART_H
#define CONNECT_USART_H
#ifndef CONNECT_UART_H
#define CONNECT_UART_H
#include <device.h>
#include "hardware_usart.h"
#include "hardware_dma.h"
#include <stm32f1xx_hal_uart.h>
#include <stm32f103xb.h>
#ifdef __cplusplus
extern "C" {
#endif
#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG
struct Stm32UartHwCfg
{
UART_HandleTypeDef uart_handle;
USART_TypeDef *uart_device;
IRQn_Type irq_type;
};
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
struct UsartHwCfg
{
USART_TypeDef *uart_device;
IRQn_Type irq;
};
struct Stm32Usart
{
struct Stm32UsartDma
{
DMA_Stream_TypeDef *RxStream;
uint32 RxCh;
uint32 RxFlag;
uint8 RxIrqCh;
x_size_t SettingRecvLen;
x_size_t LastRecvIndex;
} dma;
struct SerialBus serial_bus;
};
int InitHwUsart(void);
int InitHwUart(void);
#ifdef __cplusplus
}

3
Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/CMSIS/Makefile Normal file
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@ -0,0 +1,3 @@
SRC_FILES := system_stm32f1xx.c
include $(KERNEL_ROOT)/compiler.mk

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