forked from xuos/xiuos
support rtc SPI I2C eeprom ADC
This commit is contained in:
wlyu
parent
30ab8676f1
commit
f69edc63ba
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@ -1,644 +0,0 @@
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/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/**
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* @file board.c
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* @brief relative configure for ok1052-c
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2021.11.11
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*/
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#include "fsl_common.h"
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#include "board.h"
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#include "pin_mux.h"
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#ifdef BSP_USING_SEMC
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extern status_t BOARD_InitSEMC(void);
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#ifdef BSP_USING_EXTSRAM
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extern int ExtSramInit(void);
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#endif
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#endif
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#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
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#include "fsl_lpi2c.h"
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#endif /* SDK_I2C_BASED_COMPONENT_USED */
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#include "fsl_iomuxc.h"
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#include "fsl_gpio.h"
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#include "fsl_lpuart.h"
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#include <connect_ethernet.h>
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#include <connect_uart.h>
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#include <connect_adc.h>
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#include <connect_spi.h>
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#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
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4 bits for subpriority */
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#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
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3 bits for subpriority */
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#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
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2 bits for subpriority */
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#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
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1 bits for subpriority */
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#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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#if 0
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/* Get debug console frequency. */
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uint32_t BOARD_DebugConsoleSrcFreq(void)
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{
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uint32_t freq;
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/* To make it simple, we assume default PLL and divider settings, and the only variable
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from application is use PLL3 source or OSC source */
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if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
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{
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freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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else
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{
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freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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return freq;
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}
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/* Initialize debug console. */
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void BOARD_InitDebugConsole(void)
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{
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uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
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DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
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}
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#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
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void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
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{
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lpi2c_master_config_t lpi2cConfig = {0};
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/*
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* lpi2cConfig.debugEnable = false;
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* lpi2cConfig.ignoreAck = false;
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* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
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* lpi2cConfig.baudRate_Hz = 100000U;
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* lpi2cConfig.busIdleTimeout_ns = 0;
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* lpi2cConfig.pinLowTimeout_ns = 0;
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* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
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* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
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*/
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LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
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LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
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}
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status_t BOARD_LPI2C_Send(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *txBuff,
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uint8_t txBuffSize)
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{
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status_t reVal;
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/* Send master blocking data to slave */
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reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
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if (kStatus_Success == reVal)
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{
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while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
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{
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}
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reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterSend(base, txBuff, txBuffSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterStop(base);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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}
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return reVal;
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}
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status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *rxBuff,
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uint8_t rxBuffSize)
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{
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status_t reVal;
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reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
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if (kStatus_Success == reVal)
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{
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while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
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{
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}
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reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterRepeatedStart(base, deviceAddress, kLPI2C_Read);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterStop(base);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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}
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return reVal;
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}
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status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *txBuff,
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uint8_t txBuffSize)
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{
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return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize);
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}
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status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *rxBuff,
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uint8_t rxBuffSize)
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{
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status_t reVal;
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reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
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if (kStatus_Success == reVal)
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{
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while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
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{
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}
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reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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/* SCCB does not support LPI2C repeat start, must stop then start. */
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reVal = LPI2C_MasterStop(base);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Read);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterStop(base);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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}
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return reVal;
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}
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void BOARD_Accel_I2C_Init(void)
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{
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BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
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}
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status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
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{
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uint8_t data = (uint8_t)txBuff;
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return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
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}
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status_t BOARD_Accel_I2C_Receive(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
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{
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return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
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}
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void BOARD_Codec_I2C_Init(void)
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{
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BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
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}
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status_t BOARD_Codec_I2C_Send(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
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{
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return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
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txBuffSize);
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}
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status_t BOARD_Codec_I2C_Receive(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
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{
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return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
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}
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void BOARD_Camera_I2C_Init(void)
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{
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CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
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CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
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BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
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}
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status_t BOARD_Camera_I2C_Send(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
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{
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return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
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txBuffSize);
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}
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status_t BOARD_Camera_I2C_Receive(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
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{
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return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
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rxBuffSize);
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}
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status_t BOARD_Camera_I2C_SendSCCB(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
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{
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return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
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txBuffSize);
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}
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status_t BOARD_Camera_I2C_ReceiveSCCB(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
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{
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return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
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rxBuffSize);
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}
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#endif /* SDK_I2C_BASED_COMPONENT_USED */
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#endif
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void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
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{
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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}
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void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
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{
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
}
|
||||
|
||||
/* MPU configuration. */
|
||||
void BOARD_ConfigMPU(void)
|
||||
{
|
||||
/* Disable I cache and D cache */
|
||||
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
|
||||
{
|
||||
SCB_DisableICache();
|
||||
}
|
||||
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
|
||||
{
|
||||
SCB_DisableDCache();
|
||||
}
|
||||
|
||||
/* Disable MPU */
|
||||
ARM_MPU_Disable();
|
||||
|
||||
/* MPU configure:
|
||||
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
|
||||
* SubRegionDisable, Size)
|
||||
* API in mpu_armv7.h.
|
||||
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
|
||||
* disabled.
|
||||
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
|
||||
* Privileged mode.
|
||||
* Use MACROS defined in mpu_armv7.h:
|
||||
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
|
||||
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
|
||||
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
|
||||
* 0 x 0 0 Strongly Ordered shareable
|
||||
* 0 x 0 1 Device shareable
|
||||
* 0 0 1 0 Normal not shareable Outer and inner write
|
||||
* through no write allocate
|
||||
* 0 0 1 1 Normal not shareable Outer and inner write
|
||||
* back no write allocate
|
||||
* 0 1 1 0 Normal shareable Outer and inner write
|
||||
* through no write allocate
|
||||
* 0 1 1 1 Normal shareable Outer and inner write
|
||||
* back no write allocate
|
||||
* 1 0 0 0 Normal not shareable outer and inner
|
||||
* noncache
|
||||
* 1 1 0 0 Normal shareable outer and inner
|
||||
* noncache
|
||||
* 1 0 1 1 Normal not shareable outer and inner write
|
||||
* back write/read acllocate
|
||||
* 1 1 1 1 Normal shareable outer and inner write
|
||||
* back write/read acllocate
|
||||
* 2 x 0 0 Device not shareable
|
||||
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
|
||||
* policy.
|
||||
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
|
||||
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
|
||||
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
|
||||
* mpu_armv7.h.
|
||||
*/
|
||||
|
||||
/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||
|
||||
/* Region 2 setting */
|
||||
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
|
||||
/* Setting Memory with Normal type, not shareable, outer/inner write back. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
|
||||
#else
|
||||
/* Setting Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_64MB);
|
||||
#endif
|
||||
|
||||
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||
|
||||
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
||||
|
||||
/* The define sets the cacheable memory to shareable,
|
||||
* this suggestion is referred from chapter 2.2.1 Memory regions,
|
||||
* types and attributes in Cortex-M7 Devices, Generic User Guide */
|
||||
#if defined(SDRAM_IS_SHAREABLE)
|
||||
/* Region 7 setting: Memory with Normal type, shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
||||
#else
|
||||
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
||||
#endif
|
||||
|
||||
/* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
|
||||
* accessed by cache can be put here */
|
||||
/* Memory with Normal type, not shareable, non-cacheable */
|
||||
MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
|
||||
|
||||
/* Enable MPU */
|
||||
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
||||
|
||||
/* Enable I cache and D cache */
|
||||
SCB_EnableDCache();
|
||||
SCB_EnableICache();
|
||||
}
|
||||
|
||||
|
||||
/* This is the timer interrupt service routine. */
|
||||
void SysTick_Handler(int irqn, void *arg)
|
||||
{
|
||||
TickAndTaskTimesliceUpdate();
|
||||
}
|
||||
DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE);
|
||||
|
||||
#ifdef BSP_USING_LPUART
|
||||
void imxrt_uart_pins_init(void)
|
||||
{
|
||||
#ifdef BSP_USING_LPUART1
|
||||
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
|
||||
0x10B0u); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
|
||||
0x10B0u); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
#endif
|
||||
#ifdef BSP_USING_LPUART2
|
||||
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
|
||||
0U);
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
|
||||
0U);
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
|
||||
0x10B0u);
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
|
||||
0x10B0u);
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif /* BSP_USING_LPUART */
|
||||
|
||||
/**
|
||||
* This function will initial rt1050 board.
|
||||
*/
|
||||
void InitBoardHardware()
|
||||
{
|
||||
BOARD_ConfigMPU();
|
||||
BOARD_InitPins();
|
||||
BOARD_BootClockRUN();
|
||||
|
||||
#ifndef BSP_USING_LWIP
|
||||
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_LPUART
|
||||
imxrt_uart_pins_init();
|
||||
#endif
|
||||
|
||||
InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#ifdef BSP_USING_SEMC
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd2, 29);
|
||||
/* Set semc clock to 163.86 MHz */
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 1);
|
||||
CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
|
||||
|
||||
if (BOARD_InitSEMC() != kStatus_Success)
|
||||
{
|
||||
KPrintf("\r\n SEMC Init Failed\r\n");
|
||||
}
|
||||
#ifdef MEM_EXTERN_SRAM
|
||||
else
|
||||
{
|
||||
ExtSramInit();
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_LWIP
|
||||
ETH_BSP_Config();
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_LPUART
|
||||
Imrt1052HwUartInit();
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC
|
||||
Imrt1052HwAdcInit();
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI
|
||||
Imrt1052HwSpiInit();
|
||||
#endif
|
||||
|
||||
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
||||
}
|
||||
|
||||
|
|
@ -1,310 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.h
|
||||
* @brief define imxrt1052-board init configure and start-up function
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-28
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.h
|
||||
Description: define imxrt1052-board board init function and struct
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-05-28
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. define imxrt-board InitBoardHardware
|
||||
2. define imxrt-board heap struct
|
||||
*************************************************/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "fsl_clock.h"
|
||||
#include "fsl_enet.h"
|
||||
#include "clock_config.h"
|
||||
#include <xiuos.h>
|
||||
#include <arch_interrupt.h>
|
||||
#include "enet_ethernetif.h"
|
||||
|
||||
extern int heap_start;
|
||||
extern int heap_end;
|
||||
#define HEAP_BEGIN (&heap_start)
|
||||
#define HEAP_END (&heap_end)
|
||||
|
||||
#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
|
||||
|
||||
void InitBoardHardware(void);
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief The board name */
|
||||
#define BOARD_NAME "IMXRT1050-EVKB"
|
||||
|
||||
/* The UART to use for debug messages. */
|
||||
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
|
||||
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
|
||||
#define BOARD_DEBUG_UART_INSTANCE 1U
|
||||
|
||||
#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
|
||||
|
||||
#define BOARD_UART_IRQ LPUART1_IRQn
|
||||
#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
|
||||
|
||||
#ifndef BOARD_DEBUG_UART_BAUDRATE
|
||||
#define BOARD_DEBUG_UART_BAUDRATE (115200U)
|
||||
#endif /* BOARD_DEBUG_UART_BAUDRATE */
|
||||
|
||||
/*! @brief The USER_LED used for board */
|
||||
#define LOGIC_LED_ON (0U)
|
||||
#define LOGIC_LED_OFF (1U)
|
||||
#ifndef BOARD_USER_LED_GPIO
|
||||
#define BOARD_USER_LED_GPIO GPIO1
|
||||
#endif
|
||||
#ifndef BOARD_USER_LED_GPIO_PIN
|
||||
#define BOARD_USER_LED_GPIO_PIN (9U)
|
||||
#endif
|
||||
|
||||
#define USER_LED_INIT(output) \
|
||||
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
|
||||
BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
|
||||
#define USER_LED_ON() \
|
||||
GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
|
||||
#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
|
||||
#define USER_LED_TOGGLE() \
|
||||
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
|
||||
0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
|
||||
|
||||
/*! @brief Define the port interrupt number for the board switches */
|
||||
#ifndef BOARD_USER_BUTTON_GPIO
|
||||
#define BOARD_USER_BUTTON_GPIO GPIO5
|
||||
#endif
|
||||
#ifndef BOARD_USER_BUTTON_GPIO_PIN
|
||||
#define BOARD_USER_BUTTON_GPIO_PIN (0U)
|
||||
#endif
|
||||
#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
|
||||
#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
|
||||
#define BOARD_USER_BUTTON_NAME "SW8"
|
||||
|
||||
/*! @brief The hyper flash size */
|
||||
#define BOARD_FLASH_SIZE (0x4000000U)
|
||||
|
||||
/*! @brief The ENET PHY address. */
|
||||
#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
|
||||
|
||||
/* USB PHY condfiguration */
|
||||
#define BOARD_USB_PHY_D_CAL (0x0CU)
|
||||
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
|
||||
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
|
||||
|
||||
#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
|
||||
#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
|
||||
#define BOARD_ARDUINO_I2C_INDEX (1)
|
||||
#define BOARD_USDHC1_BASEADDR USDHC1
|
||||
#define BOARD_USDHC2_BASEADDR USDHC2
|
||||
#define BOARD_USDHC_CD_GPIO_BASE GPIO2
|
||||
#define BOARD_USDHC_CD_GPIO_PIN 28
|
||||
#define BOARD_USDHC_CD_PORT_IRQ GPIO2_Combined_16_31_IRQn
|
||||
#define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO2_Combined_16_31_IRQHandler
|
||||
|
||||
#define BOARD_USDHC_CD_STATUS() (GPIO_PinRead(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
|
||||
|
||||
#define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_PortGetInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
|
||||
#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
|
||||
|
||||
#define BOARD_USDHC_CD_GPIO_INIT() \
|
||||
{ \
|
||||
gpio_pin_config_t sw_config = { \
|
||||
kGPIO_DigitalInput, \
|
||||
0, \
|
||||
kGPIO_IntRisingOrFallingEdge, \
|
||||
}; \
|
||||
GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config); \
|
||||
GPIO_PortEnableInterrupts(BOARD_USDHC_CD_GPIO_BASE, 1U << BOARD_USDHC_CD_GPIO_PIN); \
|
||||
GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, ~0); \
|
||||
}
|
||||
#define BOARD_HAS_SDCARD (1U)
|
||||
#define BOARD_SD_POWER_RESET_GPIO (GPIO1)
|
||||
#define BOARD_SD_POWER_RESET_GPIO_PIN (5U)
|
||||
|
||||
#define BOARD_USDHC_CARD_INSERT_CD_LEVEL (0U)
|
||||
|
||||
#define BOARD_USDHC_MMCCARD_POWER_CONTROL(state)
|
||||
|
||||
#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() \
|
||||
{ \
|
||||
gpio_pin_config_t sw_config = { \
|
||||
kGPIO_DigitalOutput, \
|
||||
0, \
|
||||
kGPIO_NoIntmode, \
|
||||
}; \
|
||||
GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
|
||||
GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, true); \
|
||||
}
|
||||
|
||||
#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() \
|
||||
{ \
|
||||
gpio_pin_config_t sw_config = { \
|
||||
kGPIO_DigitalOutput, \
|
||||
0, \
|
||||
kGPIO_NoIntmode, \
|
||||
}; \
|
||||
GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
|
||||
}
|
||||
|
||||
#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \
|
||||
(GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state))
|
||||
|
||||
#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U))
|
||||
#define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U))
|
||||
|
||||
#define BOARD_SD_HOST_BASEADDR BOARD_USDHC1_BASEADDR
|
||||
#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ
|
||||
#define BOARD_SD_HOST_IRQ USDHC1_IRQn
|
||||
|
||||
#define BOARD_MMC_HOST_BASEADDR BOARD_USDHC2_BASEADDR
|
||||
#define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC2_CLK_FREQ
|
||||
#define BOARD_MMC_HOST_IRQ USDHC2_IRQn
|
||||
#define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindow170to195
|
||||
#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
|
||||
/* we are using the BB SD socket to DEMO the MMC example,but the
|
||||
* SD socket provide 4bit bus only, so we define this macro to avoid
|
||||
* 8bit data bus test
|
||||
*/
|
||||
#define BOARD_MMC_SUPPORT_8BIT_BUS (1U)
|
||||
|
||||
#define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (200000000U)
|
||||
#define BOARD_SD_HOST_SUPPORT_HS200_FREQ (180000000U)
|
||||
|
||||
/*! @brief The WIFI-QCA shield pin. */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 3U /*!< PIO4 pin index: 3 */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_3 /*!< Pin name */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
|
||||
|
||||
#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
|
||||
#define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
|
||||
#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 19U /*!< PIO1 pin index: 19 */
|
||||
#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_19 /*!< Pin name */
|
||||
#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
|
||||
#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
|
||||
#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
|
||||
|
||||
/*! @brief The WIFI-QCA Silex 2401 shield pin. */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 9U /*!< PIO4 pin index: 9 */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_9 /*!< Pin name */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
|
||||
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 11U /*!< PIO1 pin index: 11 */
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_11 /*!< Pin name */
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
|
||||
|
||||
/* @Brief Board accelerator sensor configuration */
|
||||
#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
|
||||
/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
|
||||
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
|
||||
/* Clock divider for LPI2C clock source */
|
||||
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||
#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
|
||||
|
||||
#define BOARD_CODEC_I2C_BASEADDR LPI2C1
|
||||
#define BOARD_CODEC_I2C_INSTANCE 1U
|
||||
#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
|
||||
#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||
#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
|
||||
|
||||
/* @Brief Board CAMERA configuration */
|
||||
#define BOARD_CAMERA_I2C_BASEADDR LPI2C1
|
||||
#define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||
#define BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT (0U) /* Select USB1 PLL (480 MHz) as LPI2C's clock source */
|
||||
#define BOARD_CAMERA_I2C_CLOCK_FREQ \
|
||||
(CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER + 1U))
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
uint32_t BOARD_DebugConsoleSrcFreq(void);
|
||||
|
||||
void BOARD_InitDebugConsole(void);
|
||||
|
||||
void BOARD_ConfigMPU(void);
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
|
||||
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize);
|
||||
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize);
|
||||
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize);
|
||||
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize);
|
||||
void BOARD_Accel_I2C_Init(void);
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
void BOARD_Codec_I2C_Init(void);
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
void BOARD_Camera_I2C_Init(void);
|
||||
status_t BOARD_Camera_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Camera_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
|
||||
status_t BOARD_Camera_I2C_SendSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Camera_I2C_ReceiveSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
|
||||
void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
menuconfig BSP_USING_LPUART
|
||||
bool "Using UART device"
|
||||
default y
|
||||
select RESOURCES_SERIAL
|
||||
|
||||
if BSP_USING_LPUART
|
||||
source "$BSP_DIR/third_party_driver/uart/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_LWIP
|
||||
bool "Using LwIP device"
|
||||
default n
|
||||
select RESOURCES_LWIP
|
||||
|
||||
menuconfig BSP_USING_GPIO
|
||||
bool "Using GPIO device "
|
||||
default y
|
||||
select RESOURCES_PIN
|
||||
|
||||
if BSP_USING_GPIO
|
||||
source "$BSP_DIR/third_party_driver/gpio/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C
|
||||
bool "Using I2C device"
|
||||
default y
|
||||
select RESOURCES_I2C
|
||||
|
||||
if BSP_USING_I2C
|
||||
source "$BSP_DIR/third_party_driver/i2c/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Using ADC device"
|
||||
default y
|
||||
select RESOURCES_ADC
|
||||
|
||||
if BSP_USING_ADC
|
||||
source "$BSP_DIR/third_party_driver/adc/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SPI
|
||||
bool "Using SPI device"
|
||||
default y
|
||||
select RESOURCES_SPI
|
||||
|
||||
if BSP_USING_SPI
|
||||
source "$BSP_DIR/third_party_driver/spi/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SEMC
|
||||
bool "Using SEMC device"
|
||||
default y
|
||||
|
||||
if BSP_USING_SEMC
|
||||
source "$BSP_DIR/third_party_driver/semc/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_RTC
|
||||
bool "Using RTC device"
|
||||
default n
|
||||
select RESOURCES_RTC
|
||||
if BSP_USING_RTC
|
||||
source "$BSP_DIR/third_party_driver/rtc/Kconfig"
|
||||
endif
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
SRC_DIR := common gpio
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_LPUART),y)
|
||||
SRC_DIR += uart
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_LWIP),y)
|
||||
SRC_DIR += ethernet
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_I2C),y)
|
||||
SRC_DIR += i2c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_ADC),y)
|
||||
SRC_DIR += adc
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_SPI),y)
|
||||
SRC_DIR += spi
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_SEMC),y)
|
||||
SRC_DIR += semc
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_RTC),y)
|
||||
SRC_DIR += rtc
|
||||
endif
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -1,989 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file pin_mux.c
|
||||
* @brief support imxrt1052-board pin configure
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-29
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v4.1
|
||||
processor: MIMXRT1052xxxxB
|
||||
package_id: MIMXRT1052DVL6B
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 5.0.2
|
||||
board: IMXRT1050-EVKB
|
||||
pin_labels:
|
||||
- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: BSP_LED, identifier: BSP_LED}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins ( void )
|
||||
{
|
||||
BOARD_InitPins();
|
||||
}
|
||||
|
||||
void SemcPinmuxConfig ( void )
|
||||
{
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 is configured as SEMC_DATA00 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 is configured as SEMC_DATA01 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 is configured as SEMC_DATA02 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 is configured as SEMC_DATA03 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 is configured as SEMC_DATA04 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 is configured as SEMC_DATA05 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 is configured as SEMC_DATA06 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 is configured as SEMC_DATA07 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 is configured as SEMC_DM00 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_09_SEMC_ADDR00, /* GPIO_EMC_09 is configured as SEMC_ADDR00 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_10_SEMC_ADDR01, /* GPIO_EMC_10 is configured as SEMC_ADDR01 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_11_SEMC_ADDR02, /* GPIO_EMC_11 is configured as SEMC_ADDR02 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_12_SEMC_ADDR03, /* GPIO_EMC_12 is configured as SEMC_ADDR03 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_13_SEMC_ADDR04, /* GPIO_EMC_13 is configured as SEMC_ADDR04 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_14_SEMC_ADDR05, /* GPIO_EMC_14 is configured as SEMC_ADDR05 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_15_SEMC_ADDR06, /* GPIO_EMC_15 is configured as SEMC_ADDR06 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_16_SEMC_ADDR07, /* GPIO_EMC_16 is configured as SEMC_ADDR07 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_17_SEMC_ADDR08, /* GPIO_EMC_17 is configured as SEMC_ADDR08 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_18_SEMC_ADDR09, /* GPIO_EMC_18 is configured as SEMC_ADDR09 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_19_SEMC_ADDR11, /* GPIO_EMC_19 is configured as SEMC_ADDR11 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_20_SEMC_ADDR12, /* GPIO_EMC_20 is configured as SEMC_ADDR12 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_21_SEMC_BA0, /* GPIO_EMC_21 is configured as SEMC_BA0 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_22_SEMC_BA1, /* GPIO_EMC_22 is configured as SEMC_BA1 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_23_SEMC_ADDR10, /* GPIO_EMC_23 is configured as SEMC_ADDR10 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_24_SEMC_CAS, /* GPIO_EMC_24 is configured as SEMC_CAS */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_25_SEMC_RAS, /* GPIO_EMC_25 is configured as SEMC_RAS */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_26_SEMC_CLK, /* GPIO_EMC_26 is configured as SEMC_CLK */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_27_SEMC_CKE, /* GPIO_EMC_27 is configured as SEMC_CKE */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_28_SEMC_WE, /* GPIO_EMC_28 is configured as SEMC_WE */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_29_SEMC_CS0, /* GPIO_EMC_29 is configured as SEMC_CS0 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_30_SEMC_DATA08, /* GPIO_EMC_30 is configured as SEMC_DATA08 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_31_SEMC_DATA09, /* GPIO_EMC_31 is configured as SEMC_DATA09 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_32_SEMC_DATA10, /* GPIO_EMC_32 is configured as SEMC_DATA10 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_33_SEMC_DATA11, /* GPIO_EMC_33 is configured as SEMC_DATA11 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_34_SEMC_DATA12, /* GPIO_EMC_34 is configured as SEMC_DATA12 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_35_SEMC_DATA13, /* GPIO_EMC_35 is configured as SEMC_DATA13 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_36_SEMC_DATA14, /* GPIO_EMC_36 is configured as SEMC_DATA14 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_37_SEMC_DATA15, /* GPIO_EMC_37 is configured as SEMC_DATA15 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_38_SEMC_DM01, /* GPIO_EMC_38 is configured as SEMC_DM01 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_39_SEMC_DQS, /* GPIO_EMC_39 is configured as SEMC_DQS */
|
||||
1U ); /* Software Input On Field: Force input path of pad GPIO_EMC_39 */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_40_SEMC_RDY, /* GPIO_EMC_40 is configured as SEMC_RDY */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_41_SEMC_CSX00, /* GPIO_EMC_41 is configured as SEMC_CSX00 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_09_SEMC_ADDR00, /* GPIO_EMC_09 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_10_SEMC_ADDR01, /* GPIO_EMC_10 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_11_SEMC_ADDR02, /* GPIO_EMC_11 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_12_SEMC_ADDR03, /* GPIO_EMC_12 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_13_SEMC_ADDR04, /* GPIO_EMC_13 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_14_SEMC_ADDR05, /* GPIO_EMC_14 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_15_SEMC_ADDR06, /* GPIO_EMC_15 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_16_SEMC_ADDR07, /* GPIO_EMC_16 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_17_SEMC_ADDR08, /* GPIO_EMC_17 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_18_SEMC_ADDR09, /* GPIO_EMC_18 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_19_SEMC_ADDR11, /* GPIO_EMC_19 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_20_SEMC_ADDR12, /* GPIO_EMC_20 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_21_SEMC_BA0, /* GPIO_EMC_21 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_22_SEMC_BA1, /* GPIO_EMC_22 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_23_SEMC_ADDR10, /* GPIO_EMC_23 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_24_SEMC_CAS, /* GPIO_EMC_24 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_25_SEMC_RAS, /* GPIO_EMC_25 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_26_SEMC_CLK, /* GPIO_EMC_26 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_27_SEMC_CKE, /* GPIO_EMC_27 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_28_SEMC_WE, /* GPIO_EMC_28 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_29_SEMC_CS0, /* GPIO_EMC_29 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_30_SEMC_DATA08, /* GPIO_EMC_30 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_31_SEMC_DATA09, /* GPIO_EMC_31 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_32_SEMC_DATA10, /* GPIO_EMC_32 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_33_SEMC_DATA11, /* GPIO_EMC_33 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_34_SEMC_DATA12, /* GPIO_EMC_34 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_35_SEMC_DATA13, /* GPIO_EMC_35 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_36_SEMC_DATA14, /* GPIO_EMC_36 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_37_SEMC_DATA15, /* GPIO_EMC_37 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_38_SEMC_DM01, /* GPIO_EMC_38 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_39_SEMC_DQS, /* GPIO_EMC_39 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_40_SEMC_RDY, /* GPIO_EMC_40 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_41_SEMC_CSX00, /* GPIO_EMC_41 PAD functional properties : */
|
||||
0x0110F9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
}
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
|
||||
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
|
||||
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
|
||||
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
|
||||
- {pin_num: A7, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_40, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_100K_Ohm,
|
||||
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_200, drive_strength: R0_5, slew_rate: Fast}
|
||||
- {pin_num: C7, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_41, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_100K_Ohm,
|
||||
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_50, drive_strength: R0_5, slew_rate: Fast}
|
||||
- {pin_num: B13, peripheral: ENET, signal: enet_ref_clk, pin_signal: GPIO_B1_10, software_input_on: Enable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
|
||||
pull_keeper_select: Keeper, pull_keeper_enable: Disable, open_drain: Disable, speed: MHZ_50, drive_strength: R0_6, slew_rate: Fast}
|
||||
- {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_100K_Ohm,
|
||||
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_200, drive_strength: R0_5, slew_rate: Fast}
|
||||
- {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_100K_Ohm,
|
||||
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_200, drive_strength: R0_5, slew_rate: Fast}
|
||||
- {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_100K_Ohm,
|
||||
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_200, drive_strength: R0_5, slew_rate: Fast}
|
||||
- {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_100K_Ohm,
|
||||
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_200, drive_strength: R0_5, slew_rate: Fast}
|
||||
- {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_100K_Ohm,
|
||||
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_200, drive_strength: R0_5, slew_rate: Fast}
|
||||
- {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_100K_Ohm,
|
||||
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_200, drive_strength: R0_5, slew_rate: Fast}
|
||||
- {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_100K_Ohm,
|
||||
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_200, drive_strength: R0_5, slew_rate: Fast}
|
||||
- {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_100K_Ohm,
|
||||
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_5, slew_rate: Fast}
|
||||
- {pin_num: G13, peripheral: GPIO1, signal: 'gpio_io, 10', pin_signal: GPIO_AD_B0_10, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_100K_Ohm,
|
||||
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_5, slew_rate: Fast}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
|
||||
void BOARD_InitSPIPins ( void )
|
||||
{
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK, /* GPIO_AD_B0_00 is configured as LPSPI3_SCK */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, /* GPIO_AD_B0_01 is configured as LPSPI3_SDO */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, /* GPIO_AD_B0_02 is configured as LPSPI3_SDI */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0, /* GPIO_AD_B0_03 is configured as LPSPI3_PCS0 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_SD_B0_00 is configured as LPSPI1_SCK */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0, /* GPIO_SD_B0_01 is configured as LPSPI1_PCS0 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO, /* GPIO_SD_B0_02 is configured as LPSPI1_SDO */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI, /* GPIO_SD_B0_03 is configured as LPSPI1_SDI */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_AD_B0_00 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, /* GPIO_AD_B0_01 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, /* GPIO_AD_B0_02 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0, /* GPIO_AD_B0_03 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_SD_B0_00 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0, /* GPIO_SD_B0_01 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO, /* GPIO_SD_B0_02 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI, /* GPIO_SD_B0_03 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
}
|
||||
|
||||
|
||||
void BOARD_InitPins ( void )
|
||||
{
|
||||
CLOCK_EnableClock ( kCLOCK_Iomuxc ); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
|
||||
// IOMUXC_SetPinMux(
|
||||
// IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
|
||||
// 0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
SemcPinmuxConfig();
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B0_03_GPIO1_IO03, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */
|
||||
1U ); /* Software Input On Field: Force input path of pad GPIO_B1_10 */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
// IOMUXC_SetPinConfig(
|
||||
// IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
|
||||
// 0xB0A9u); /* Slew Rate Field: Fast Slew Rate
|
||||
// Drive Strength Field: R0/5
|
||||
// Speed Field: medium(100MHz)
|
||||
// Open Drain Enable Field: Open Drain Disabled
|
||||
// Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
// Pull / Keep Select Field: Pull
|
||||
// Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||
// Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B0_03_GPIO1_IO03, /* GPIO_AD_B0_09 PAD functional properties : */
|
||||
0xB0A9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/5
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Pull
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */
|
||||
0xB0A9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/5
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Pull
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
#if UART_DEBUG
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
#endif
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */
|
||||
0xB0E9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/5
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Pull
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */
|
||||
0xB0E9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/5
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Pull
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */
|
||||
0xB0E9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/5
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Pull
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */
|
||||
0xB0E9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/5
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Pull
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */
|
||||
0xB0E9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/5
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Pull
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */
|
||||
0xB0E9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/5
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Pull
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */
|
||||
0x31u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: low(50MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Disabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */
|
||||
0xB0E9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/5
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Pull
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */
|
||||
0xB0E9u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/5
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Pull
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */
|
||||
0xB829u ); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/5
|
||||
Speed Field: low(50MHz)
|
||||
Open Drain Enable Field: Open Drain Enabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Pull
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
}
|
||||
|
||||
void BOARD_InitI2C1Pins ( void )
|
||||
{
|
||||
CLOCK_EnableClock ( kCLOCK_Iomuxc ); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */
|
||||
1U ); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */
|
||||
1U ); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 PAD functional properties : */
|
||||
0xD8B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Enabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 22K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 PAD functional properties : */
|
||||
0xD8B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Enabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 22K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
}
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
|
|
@ -1,593 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_common.h
|
||||
* @brief common drivers header
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
*/
|
||||
|
||||
#ifndef _FSL_COMMON_H_
|
||||
#define _FSL_COMMON_H_
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#include <stddef.h>
|
||||
#endif
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup ksdk_common
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Construct a status code value from a group and code number. */
|
||||
#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
|
||||
|
||||
/*! @brief Construct the version number for drivers. */
|
||||
#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief common driver version 2.0.1. */
|
||||
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*@}*/
|
||||
|
||||
/* Debug console type definition. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
|
||||
|
||||
/*! @brief Status group numbers. */
|
||||
enum _status_groups
|
||||
{
|
||||
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
|
||||
kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
|
||||
kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
|
||||
kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
|
||||
kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
|
||||
kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
|
||||
kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
|
||||
kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
|
||||
kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
|
||||
kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
|
||||
kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
|
||||
kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
|
||||
kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
|
||||
kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
|
||||
kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
|
||||
kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
|
||||
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
|
||||
kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
|
||||
kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
|
||||
kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
|
||||
kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
|
||||
kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
|
||||
kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
|
||||
kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
|
||||
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
|
||||
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
|
||||
kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
|
||||
kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
|
||||
kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
|
||||
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
|
||||
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
|
||||
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
|
||||
kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
|
||||
kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
|
||||
kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
|
||||
kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
|
||||
kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
|
||||
kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
|
||||
kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
|
||||
kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
|
||||
kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
|
||||
kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
|
||||
kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
|
||||
kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
|
||||
kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
|
||||
kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
|
||||
kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
|
||||
kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
|
||||
kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
|
||||
kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
|
||||
kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
|
||||
kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
|
||||
kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
|
||||
kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
|
||||
kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
|
||||
kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
|
||||
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
|
||||
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
|
||||
kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
|
||||
kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */
|
||||
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
|
||||
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
|
||||
kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
|
||||
kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
|
||||
kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
|
||||
kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
|
||||
kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
|
||||
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
|
||||
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
|
||||
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
|
||||
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
|
||||
kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
|
||||
|
||||
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
|
||||
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
|
||||
kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */
|
||||
kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */
|
||||
kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */
|
||||
kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */
|
||||
kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
|
||||
kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
|
||||
kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
|
||||
kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
|
||||
kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
|
||||
kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */
|
||||
kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */
|
||||
kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */
|
||||
kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */
|
||||
kStatusGroup_LIST = 142, /*!< Group number for List status codes. */
|
||||
kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
|
||||
kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
|
||||
kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
|
||||
};
|
||||
|
||||
/*! @brief Generic status return codes. */
|
||||
enum _generic_status
|
||||
{
|
||||
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
|
||||
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
|
||||
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
|
||||
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
|
||||
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
|
||||
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
|
||||
kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
|
||||
};
|
||||
|
||||
/*! @brief Type used for all status and error return values. */
|
||||
typedef int32_t status_t;
|
||||
|
||||
/*
|
||||
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
|
||||
* defined in previous of this file.
|
||||
*/
|
||||
#include "fsl_clock.h"
|
||||
|
||||
/*
|
||||
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
|
||||
*/
|
||||
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
|
||||
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
|
||||
#include "fsl_reset.h"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Macro guard for whether to use default weak IRQ implementation in drivers
|
||||
*/
|
||||
#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
|
||||
#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
|
||||
#endif
|
||||
|
||||
/*! @name Min/max macros */
|
||||
/* @{ */
|
||||
#if !defined(MIN)
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
#if !defined(MAX)
|
||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @brief Computes the number of elements in an array. */
|
||||
#if !defined(ARRAY_SIZE)
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
#endif
|
||||
|
||||
/*! @name UINT16_MAX/UINT32_MAX value */
|
||||
/* @{ */
|
||||
#if !defined(UINT16_MAX)
|
||||
#define UINT16_MAX ((uint16_t)-1)
|
||||
#endif
|
||||
|
||||
#if !defined(UINT32_MAX)
|
||||
#define UINT32_MAX ((uint32_t)-1)
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @name Timer utilities */
|
||||
/* @{ */
|
||||
/*! Macro to convert a microsecond period to raw count value */
|
||||
#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
|
||||
/*! Macro to convert a raw count value to microsecond */
|
||||
#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
|
||||
|
||||
/*! Macro to convert a millisecond period to raw count value */
|
||||
#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
|
||||
/*! Macro to convert a raw count value to millisecond */
|
||||
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
|
||||
/* @} */
|
||||
|
||||
/*! @name Alignment variable definition macros */
|
||||
/* @{ */
|
||||
#if (defined(__ICCARM__))
|
||||
/**
|
||||
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
|
||||
* http://supp.iar.com/Support/?note=24725
|
||||
*/
|
||||
_Pragma("diag_suppress=Pm120")
|
||||
#define SDK_PRAGMA(x) _Pragma(#x)
|
||||
_Pragma("diag_error=Pm120")
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
|
||||
#endif
|
||||
#elif defined(__GNUC__)
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
|
||||
#endif
|
||||
#else
|
||||
#error Toolchain not supported
|
||||
#define SDK_ALIGN(var, alignbytes) var
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) var
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) var
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! Macro to change a value to a given size aligned value */
|
||||
#define SDK_SIZEALIGN(var, alignbytes) \
|
||||
((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
|
||||
/* @} */
|
||||
|
||||
/*! @name Non-cacheable region definition macros */
|
||||
/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
|
||||
* "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
|
||||
* please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
|
||||
* will be initialized to zero in system startup.
|
||||
*/
|
||||
/* @{ */
|
||||
#if (defined(__ICCARM__))
|
||||
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
||||
#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
#endif
|
||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
||||
#endif
|
||||
#elif(defined(__GNUC__))
|
||||
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
|
||||
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
|
||||
*/
|
||||
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
|
||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
#endif
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @name Time sensitive region */
|
||||
/* @{ */
|
||||
#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
|
||||
#if (defined(__ICCARM__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
|
||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
|
||||
#elif(defined(__GNUC__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#endif /* defined(__ICCARM__) */
|
||||
#else
|
||||
#if (defined(__ICCARM__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) func
|
||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) func
|
||||
#elif(defined(__GNUC__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) func
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#endif
|
||||
#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
|
||||
/* @} */
|
||||
|
||||
/*! @name Ram Function */
|
||||
#if (defined(__ICCARM__))
|
||||
#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
|
||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
||||
#elif(defined(__GNUC__))
|
||||
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#endif /* defined(__ICCARM__) */
|
||||
/* @} */
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Enable specific interrupt.
|
||||
*
|
||||
* Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
* @retval kStatus_Success Interrupt enabled successfully
|
||||
* @retval kStatus_Fail Failed to enable the interrupt
|
||||
*/
|
||||
static inline status_t EnableIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_EnableIRQ(interrupt);
|
||||
#else
|
||||
NVIC_EnableIRQ(interrupt);
|
||||
#endif
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable specific interrupt.
|
||||
*
|
||||
* Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
* @retval kStatus_Success Interrupt disabled successfully
|
||||
* @retval kStatus_Fail Failed to disable the interrupt
|
||||
*/
|
||||
static inline status_t DisableIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_DisableIRQ(interrupt);
|
||||
#else
|
||||
NVIC_DisableIRQ(interrupt);
|
||||
#endif
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the global IRQ
|
||||
*
|
||||
* Disable the global interrupt and return the current primask register. User is required to provided the primask
|
||||
* register for the EnableGlobalIRQ().
|
||||
*
|
||||
* @return Current primask value.
|
||||
*/
|
||||
static inline uint32_t DisableGlobalIRQ(void)
|
||||
{
|
||||
#if defined(CPSR_I_Msk)
|
||||
uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
|
||||
|
||||
__disable_irq();
|
||||
|
||||
return cpsr;
|
||||
#else
|
||||
uint32_t regPrimask = __get_PRIMASK();
|
||||
|
||||
__disable_irq();
|
||||
|
||||
return regPrimask;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the global IRQ
|
||||
*
|
||||
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
|
||||
* convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
|
||||
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
|
||||
*
|
||||
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the
|
||||
* DisableGlobalIRQ().
|
||||
*/
|
||||
static inline void EnableGlobalIRQ(uint32_t primask)
|
||||
{
|
||||
#if defined(CPSR_I_Msk)
|
||||
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
|
||||
#else
|
||||
__set_PRIMASK(primask);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
||||
/*!
|
||||
* @brief install IRQ handler
|
||||
*
|
||||
* @param irq IRQ number
|
||||
* @param irqHandler IRQ handler address
|
||||
* @return The old IRQ handler address
|
||||
*/
|
||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
||||
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
||||
|
||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||
/*!
|
||||
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
|
||||
*
|
||||
* Enable the interrupt for wake-up from deep sleep mode.
|
||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||
* making these wake-ups possible.
|
||||
*
|
||||
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
*/
|
||||
void EnableDeepSleepIRQ(IRQn_Type interrupt);
|
||||
|
||||
/*!
|
||||
* @brief Disable specific interrupt for wake-up from deep-sleep mode.
|
||||
*
|
||||
* Disable the interrupt for wake-up from deep sleep mode.
|
||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||
* making these wake-ups possible.
|
||||
*
|
||||
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
*/
|
||||
void DisableDeepSleepIRQ(IRQn_Type interrupt);
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||
|
||||
/*!
|
||||
* @brief Allocate memory with given alignment and aligned size.
|
||||
*
|
||||
* This is provided to support the dynamically allocated memory
|
||||
* used in cache-able region.
|
||||
* @param size The length required to malloc.
|
||||
* @param alignbytes The alignment size.
|
||||
* @retval The allocated memory.
|
||||
*/
|
||||
void *SDK_Malloc(size_t size, size_t alignbytes);
|
||||
|
||||
/*!
|
||||
* @brief Free memory.
|
||||
*
|
||||
* @param ptr The memory to be release.
|
||||
*/
|
||||
void SDK_Free(void *ptr);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_COMMON_H_ */
|
||||
|
|
@ -1,247 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file: user_api.h
|
||||
* @brief: the priviate user api for application
|
||||
* @version: 1.0
|
||||
* @author: AIIT XUOS Lab
|
||||
* @date: 2020/4/20
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef XS_USER_API_H
|
||||
#define XS_USER_API_H
|
||||
|
||||
|
||||
// #include <xiuos.h>
|
||||
|
||||
#include <xsconfig.h>
|
||||
#include "../../../kernel/include/xs_service.h"
|
||||
#include "../../../kernel/include/xs_base.h"
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include "../../../arch/kswitch.h"
|
||||
#include <libc.h>
|
||||
|
||||
|
||||
#ifdef SEPARATE_COMPILE
|
||||
|
||||
#define TASK_INFO 1
|
||||
#define MEM_INFO 2
|
||||
#define SEM_INFO 3
|
||||
#define EVENT_INFO 4
|
||||
#define MUTEX_INFO 5
|
||||
#define MEMPOOL_INFO 6
|
||||
#define MSGQUEUE_INFO 7
|
||||
#define DEVICE_INFO 8
|
||||
#define TIMER_INFO 9
|
||||
|
||||
int UserPrintInfo(unsigned long i);
|
||||
|
||||
struct utask
|
||||
{
|
||||
char name[NAME_NUM_MAX];
|
||||
void *func_entry;
|
||||
void *func_param;
|
||||
int32_t stack_size;
|
||||
uint8_t prio;
|
||||
};
|
||||
typedef struct utask UtaskType;
|
||||
|
||||
typedef void DIR;
|
||||
|
||||
int32_t UserTaskCreate(UtaskType utask);
|
||||
|
||||
x_err_t UserTaskStartup(int32_t id);
|
||||
x_err_t UserTaskDelete(int32_t id);
|
||||
void UserTaskQuit(void);
|
||||
x_err_t UserTaskDelay(int32_t ms);
|
||||
x_err_t UserGetTaskName(int32_t id ,char *name);
|
||||
int32_t UserGetTaskID(void);
|
||||
uint8_t UserGetTaskStat(int32_t id);
|
||||
|
||||
#ifdef ARCH_SMP
|
||||
x_err_t UserTaskCoreCombine(int32_t id,uint8_t core_id);
|
||||
x_err_t UserTaskCoreUnCombine(int32_t id);
|
||||
uint8_t UserGetTaskCombinedCore(int32_t id);
|
||||
uint8_t UserGetTaskRunningCore(int32_t id);
|
||||
#endif
|
||||
|
||||
x_err_t UserGetTaskErrorstatus(int32_t id);
|
||||
uint8_t UserGetTaskPriority(int32_t id);
|
||||
|
||||
|
||||
void *UserMalloc(size_t size);
|
||||
void *UserRealloc(void *pointer, size_t size);
|
||||
void *UserCalloc(size_t count, size_t size);
|
||||
void UserFree(void *pointer);
|
||||
|
||||
#ifdef KERNEL_MUTEX
|
||||
int32_t UserMutexCreate();
|
||||
void UserMutexDelete(int32_t mutex);
|
||||
int32_t UserMutexObtain(int32_t mutex, int32_t wait_time);
|
||||
int32_t UserMutexAbandon(int32_t mutex);
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef KERNEL_SEMAPHORE
|
||||
typedef int32 sem_t;
|
||||
sem_t UserSemaphoreCreate(uint16_t val);
|
||||
x_err_t UserSemaphoreDelete(sem_t sem);
|
||||
x_err_t UserSemaphoreObtain(sem_t sem, int32_t wait_time);
|
||||
x_err_t UserSemaphoreAbandon(sem_t sem);
|
||||
x_err_t UserSemaphoreSetValue(sem_t sem, uint16_t val);
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef KERNEL_EVENT
|
||||
typedef int32 EventIdType;
|
||||
EventIdType UserEventCreate(uint8_t flag);
|
||||
void UserEventDelete(EventIdType event);
|
||||
x_err_t UserEventTrigger(EventIdType event, uint32_t set);
|
||||
x_err_t UserEventProcess(EventIdType event, uint32_t set, uint8_t option,
|
||||
int32_t wait_time, uint32_t *Recved);
|
||||
x_err_t UserEventReinit(EventIdType event);
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef KERNEL_MESSAGEQUEUE
|
||||
int32_t UserMsgQueueCreate(size_t msg_size, size_t max_msgs);
|
||||
x_err_t UserMsgQueueDelete(int32_t mq );
|
||||
x_err_t UserMsgQueueSendwait(int32_t mq, const void *buffer,
|
||||
size_t size, int32_t wait_time);
|
||||
x_err_t UserMsgQueueSend(int32_t mq, const void *buffer, size_t size);
|
||||
x_err_t UserMsgQueueUrgentSend(int32_t mq, const void *buffer, size_t size);
|
||||
x_err_t UserMsgQueueRecv(int32_t mq, void *buffer, size_t size,int32_t wait_time);
|
||||
x_err_t UserMsgQueueReinit(int32_t mq);
|
||||
#endif
|
||||
|
||||
int open(const char *path, int flags, ...);
|
||||
int read(int fd, void *buf, size_t len);
|
||||
int write(int fd, const void *buf, size_t len);
|
||||
int close(int fd);
|
||||
int ioctl(int fd, int cmd, void *args);
|
||||
off_t lseek(int fd, off_t offset, int whence);
|
||||
int rename(const char *from, const char *to);
|
||||
int unlink(const char *path);
|
||||
int stat(const char *path, struct stat *buf);
|
||||
int fstat(int fd, struct stat *buf);
|
||||
int fsync(int fd);
|
||||
int ftruncate(int fd, off_t length);
|
||||
|
||||
int mkdir(const char *path, mode_t mode);
|
||||
DIR *opendir(const char *path);
|
||||
int closedir(DIR *dirp);
|
||||
struct dirent *readdir(DIR *dirp);
|
||||
int rmdir(const char *path);
|
||||
int chdir(const char *path);
|
||||
char *getcwd(char *buf, size_t size);
|
||||
long telldir(DIR *dirp);
|
||||
void seekdir(DIR *dirp, off_t offset);
|
||||
void rewinddir(DIR *dirp);
|
||||
|
||||
#ifdef FS_VFS
|
||||
struct statfs {
|
||||
size_t f_bsize;
|
||||
size_t f_blocks;
|
||||
size_t f_bfree;
|
||||
};
|
||||
|
||||
int statfs(const char *path, struct statfs *buf);
|
||||
#endif
|
||||
|
||||
int Userprintf(const char *fmt, ...);
|
||||
|
||||
#define printf Userprintf
|
||||
|
||||
#else
|
||||
|
||||
#ifdef FS_VFS
|
||||
#include <iot-vfs_posix.h>
|
||||
#endif
|
||||
|
||||
struct utask
|
||||
{
|
||||
char name[NAME_NUM_MAX];
|
||||
void *func_entry;
|
||||
void *func_param;
|
||||
int32_t stack_size;
|
||||
uint8_t prio;
|
||||
};
|
||||
typedef struct utask UtaskType;
|
||||
int32_t UserTaskCreate(UtaskType utask);
|
||||
|
||||
#define UserTaskStartup StartupKTask
|
||||
#define UserTaskDelete KTaskDelete
|
||||
#define UserTaskQuit KTaskQuit
|
||||
#define UserTaskDelay MdelayKTask
|
||||
|
||||
x_err_t UserGetTaskName(int32_t id ,char *name);
|
||||
int32_t UserGetTaskID(void);
|
||||
uint8_t UserGetTaskStat(int32_t id);
|
||||
|
||||
#ifdef ARCH_SMP
|
||||
#define UserTaskCoreCombine KTaskCoreCombine
|
||||
#define UserTaskCoreUnCombine KTaskCoreUnCombine
|
||||
|
||||
uint8_t UserGetTaskCombinedCore(int32_t id);
|
||||
uint8_t UserGetTaskRunningCore(int32_t id);
|
||||
#endif
|
||||
|
||||
x_err_t UserGetTaskErrorstatus(int32_t id);
|
||||
uint8_t UserGetTaskPriority(int32_t id);
|
||||
|
||||
#define UserMalloc x_malloc
|
||||
#define UserRealloc x_realloc
|
||||
#define UserCalloc x_calloc
|
||||
#define UserFree x_free
|
||||
|
||||
#ifdef KERNEL_MUTEX
|
||||
#define UserMutexCreate KMutexCreate
|
||||
#define UserMutexDelete KMutexDelete
|
||||
#define UserMutexObtain KMutexObtain
|
||||
#define UserMutexAbandon KMutexAbandon
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef KERNEL_SEMAPHORE
|
||||
#define UserSemaphoreCreate KSemaphoreCreate
|
||||
#define UserSemaphoreDelete KSemaphoreDelete
|
||||
#define UserSemaphoreObtain KSemaphoreObtain
|
||||
#define UserSemaphoreAbandon KSemaphoreAbandon
|
||||
#define UserSemaphoreSetValue KSemaphoreSetValue
|
||||
#endif
|
||||
|
||||
#ifdef KERNEL_EVENT
|
||||
#define UserEventCreate KEventCreate
|
||||
#define UserEventDelete KEventDelete
|
||||
#define UserEventTrigger KEventTrigger
|
||||
#define UserEventProcess KEventProcess
|
||||
#endif
|
||||
|
||||
#ifdef KERNEL_MESSAGEQUEUE
|
||||
#define UserMsgQueueCreate KCreateMsgQueue
|
||||
#define UserMsgQueueDelete KDeleteMsgQueue
|
||||
#define UserMsgQueueSendwait KMsgQueueSendwait
|
||||
#define UserMsgQueueSend KMsgQueueSend
|
||||
#define UserMsgQueueUrgentSend KMsgQueueUrgentSend
|
||||
#define UserMsgQueueRecv KMsgQueueRecv
|
||||
#define UserMsgQueueReinit KMsgQueueReinit
|
||||
#endif
|
||||
|
||||
#define UserPrintf KPrintf
|
||||
#define printf KPrintf
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,180 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file test_i2c.c
|
||||
* @brief support to test i2c function
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-24
|
||||
*/
|
||||
|
||||
#include <xiuos.h>
|
||||
#include <device.h>
|
||||
#include <bus.h>
|
||||
|
||||
/*********************************************************************************************************************************************************/
|
||||
/*
|
||||
* function: I2C device sample support reading temperature and humidity sensor data and printfing on the terminal
|
||||
* shell cmd: i2c_HS3000_sample i2c1
|
||||
* shell cmd param: i2c device name,if null means default i2c device name
|
||||
*/
|
||||
|
||||
#define HS_I2C_BUS_NAME I2C_BUS_NAME_1 /* I2C bus name */
|
||||
#define HS_I2C_DEV_NAME I2C_1_DEVICE_NAME_0 /* I2C device name */
|
||||
#define HS_I2C_DRV_NAME I2C_DRV_NAME_1 /* I2C driver name */
|
||||
#define ADDR 0x44 /* slave address */
|
||||
|
||||
static struct Bus *i2c_bus = NONE; /* I2C bus handle */
|
||||
|
||||
typedef struct Hs300xData
|
||||
{
|
||||
int humi_high;
|
||||
int humi_low;
|
||||
int temp_high;
|
||||
int temp_low;
|
||||
}Hs300xDataType;
|
||||
|
||||
Hs300xDataType g_hs300x_data;
|
||||
|
||||
static x_err_t WriteReg(struct HardwareDev *dev)
|
||||
{
|
||||
struct BusBlockWriteParam write_param;
|
||||
|
||||
/* use I2C device API transfer data */
|
||||
if(1 == BusDevWriteData(dev, &write_param)) {
|
||||
return EOK;
|
||||
}
|
||||
else{
|
||||
return -ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* read sensor register data */
|
||||
static x_err_t ReadRegs(struct HardwareDev *dev, uint8 len, uint8 *buf)
|
||||
{
|
||||
struct BusBlockReadParam read_param;
|
||||
|
||||
read_param.buffer = (void *)buf;
|
||||
read_param.size = len;
|
||||
|
||||
/* use I2C device API transfer data */
|
||||
if(1 == BusDevReadData(dev, &read_param)){
|
||||
return EOK;
|
||||
}
|
||||
else{
|
||||
return -ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
static void ReadTempHumi(float *cur_temp, float *cur_humi)
|
||||
{
|
||||
uint8 temp[4],ret=0;
|
||||
MdelayKTask(15);
|
||||
ret = WriteReg(i2c_bus->owner_haldev); //reset
|
||||
if(EOK != ret){
|
||||
KPrintf("ReadTempHumi WriteReg failed!\n");
|
||||
}
|
||||
MdelayKTask(50);
|
||||
ret = ReadRegs(i2c_bus->owner_haldev, 4, temp); /* get sensor data */
|
||||
if(EOK != ret){
|
||||
KPrintf("ReadTempHumi ReadRegs failed\n");
|
||||
}
|
||||
|
||||
*cur_humi = ((temp[0] <<8 | temp[1] )& 0x3fff ) * 100.0 / ( (1 << 14) - 1); /* humidity data */
|
||||
|
||||
*cur_temp = ((temp[2] << 8 | temp[3]) >> 2) * 165.0 /( (1 << 14) - 1) - 40.0; /* temperature data */
|
||||
}
|
||||
|
||||
static void HS3000Init(const char *bus_name, const char *dev_name, const char *drv_name)
|
||||
{
|
||||
/* find I2C device and get I2C handle */
|
||||
i2c_bus = BusFind(bus_name);
|
||||
if (NONE == i2c_bus){
|
||||
KPrintf("HS3000Init can't find %s bus!\n", bus_name);
|
||||
}
|
||||
else{
|
||||
KPrintf("HS3000Init find %s bus!\n", bus_name);
|
||||
}
|
||||
|
||||
i2c_bus->owner_haldev = BusFindDevice(i2c_bus, dev_name);
|
||||
i2c_bus->owner_driver = BusFindDriver(i2c_bus, drv_name);
|
||||
|
||||
if(i2c_bus->match(i2c_bus->owner_driver, i2c_bus->owner_haldev)){
|
||||
KPrintf("i2c match drv %s %p dev %s %p error\n", drv_name, i2c_bus->owner_driver, dev_name, i2c_bus->owner_haldev);
|
||||
}
|
||||
else{
|
||||
KPrintf("HS3000Init successfully!write %p read %p\n",
|
||||
i2c_bus->owner_haldev->dev_done->write,
|
||||
i2c_bus->owner_haldev->dev_done->read);
|
||||
}
|
||||
}
|
||||
|
||||
void Hs300xInit(void)
|
||||
{
|
||||
HS3000Init(HS_I2C_BUS_NAME, HS_I2C_DEV_NAME, HS_I2C_DRV_NAME); /* init sensor */
|
||||
}
|
||||
|
||||
void Hs300xRead(Hs300xDataType *Hs300xDataType)
|
||||
{
|
||||
float humidity = 0.0, temperature = 0.0;
|
||||
ReadTempHumi(&temperature, &humidity); /* read temperature and humidity sensor data */
|
||||
Hs300xDataType->humi_high = (int)humidity;
|
||||
Hs300xDataType->humi_low = (int)(humidity*10)%10;
|
||||
if( temperature >= 0 ) {
|
||||
Hs300xDataType->temp_high = (int)temperature;
|
||||
Hs300xDataType->temp_low = (int)(temperature*10)%10;
|
||||
}
|
||||
else{
|
||||
Hs300xDataType->temp_high = (int)temperature;
|
||||
Hs300xDataType->temp_low = (int)(-temperature*10)%10;
|
||||
}
|
||||
}
|
||||
|
||||
void TskHs300xTest()
|
||||
{
|
||||
memset(&g_hs300x_data, 0, sizeof(Hs300xDataType));
|
||||
KPrintf("Tsk create successfully!\n");
|
||||
|
||||
while(1)
|
||||
{
|
||||
Hs300xRead(&g_hs300x_data);
|
||||
|
||||
KPrintf("HS300X:I2C humidity:%d.%d temperature:%d.%d\n",
|
||||
g_hs300x_data.humi_high,
|
||||
g_hs300x_data.humi_low,
|
||||
g_hs300x_data.temp_high,
|
||||
g_hs300x_data.temp_low);
|
||||
|
||||
MdelayKTask(1000);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void Hs300xI2cTest(void)
|
||||
{
|
||||
Hs300xInit();
|
||||
MdelayKTask(1000);
|
||||
|
||||
x_err_t flag;
|
||||
int32 Tsk_hs300x = KTaskCreate("Tsk_hs300x", TskHs300xTest, NONE, 2048, 10);
|
||||
flag = StartupKTask(Tsk_hs300x);
|
||||
if (EOK != flag){
|
||||
KPrintf("Hs300xI2cTest StartupKTask failed!\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),
|
||||
Hs300xI2cTest, Hs300xI2cTest, Test the HS300X using I2C);
|
||||
|
||||
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
|
||||
export APPPATHS :=-I$(BSP_ROOT) \
|
||||
|
||||
APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Applications/general_functions/list \
|
||||
-I$(KERNEL_ROOT)/../../APP_Framework/lib/app_newlib/include \
|
||||
-I$(KERNEL_ROOT)/../../APP_Framework/Framework/sensor #
|
||||
|
||||
ifeq ($(CONFIG_ADD_XIUOS_FETURES), y)
|
||||
APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/transform_layer/xiuos \
|
||||
-I$(KERNEL_ROOT)/../../APP_Framework/Framework/transform_layer/xiuos/user_api/switch_api \
|
||||
-I$(KERNEL_ROOT)/../../APP_Framework/Framework/transform_layer/xiuos/user_api/posix_support/include #
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SUPPORT_CONNECTION_FRAMEWORK), y)
|
||||
APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/connection #
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SUPPORT_KNOWING_FRAMEWORK), y)
|
||||
APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing #
|
||||
APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source #
|
||||
APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/gemmlowp #
|
||||
APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/flatbuffers/include #
|
||||
APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/ruy #
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SUPPORT_CONTROL_FRAMEWORK), y)
|
||||
APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control #
|
||||
APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control/plc/interoperability/opcua #
|
||||
APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework\lib\cJSON
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_CRYPTO), y)
|
||||
APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/security/crypto/include #
|
||||
endif
|
||||
|
||||
COMPILE_APP:
|
||||
@$(eval CPPPATHS=$(APPPATHS))
|
||||
@echo $(SRC_APP_DIR)
|
||||
@for dir in $(SRC_APP_DIR);do \
|
||||
$(MAKE) -C $$dir; \
|
||||
done
|
||||
@cp link.mk build/Makefile
|
||||
@$(MAKE) -C build COMPILE_TYPE="_app" TARGET=XiUOS_$(BOARD)_app.elf LINK_FLAGS=APPLFLAGS
|
||||
@rm build/Makefile build/make.obj
|
||||
|
||||
|
|
@ -1,326 +0,0 @@
|
|||
|
||||
export KERNELPATHS:=
|
||||
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/kd233)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(BSP_ROOT)/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/camera \
|
||||
-I$(BSP_ROOT)/third_party_driver/drivers \
|
||||
-I$(BSP_ROOT)/third_party_driver/lcd \
|
||||
-I$(KERNEL_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/maix-go)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(BSP_ROOT)/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/camera \
|
||||
-I$(BSP_ROOT)/third_party_driver/drivers \
|
||||
-I$(BSP_ROOT)/third_party_driver/lcd \
|
||||
-I$(KERNEL_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/stm32f407-st-discovery)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m4 \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/sdio \
|
||||
-I$(BSP_ROOT)/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/usb/STM32_USB_OTG_Driver/inc \
|
||||
-I$(KERNEL_ROOT)/include \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/compat \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/netif \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/apps \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/priv \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/prot \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/arch \
|
||||
-I$(BSP_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/aiit-arm32-board)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m4 \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/spi/third_party_spi_lora/inc \
|
||||
-I$(BSP_ROOT)/third_party_driver/spi/third_party_spi_lora/src/radio \
|
||||
-I$(BSP_ROOT)/third_party_driver/usb/STM32_USB_OTG_Driver/inc \
|
||||
-I$(KERNEL_ROOT)/include \
|
||||
-I$(BSP_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/stm32f407zgt6)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m4 \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/sdio\
|
||||
-I$(BSP_ROOT)/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/usb/STM32_USB_OTG_Driver/inc \
|
||||
-I$(KERNEL_ROOT)/include \
|
||||
-I$(BSP_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/gapuino)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(KERNEL_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/gd32vf103_rvstar)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/risc-v/gd32vf103_rvstar \
|
||||
-I$(BSP_ROOT)/include \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(KERNEL_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/hifive1-rev-B)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/include/sifive \
|
||||
-I$(BSP_ROOT)/third_party_driver/include/sifive/devices \
|
||||
-I$(BSP_ROOT)/third_party_driver/fe300prci \
|
||||
-I$(BSP_ROOT)/third_party_driver/plic\
|
||||
-I$(KERNEL_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/hifive1-emulator)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/include/sifive \
|
||||
-I$(BSP_ROOT)/third_party_driver/include/sifive/devices \
|
||||
-I$(BSP_ROOT)/third_party_driver/fe300prci \
|
||||
-I$(BSP_ROOT)/third_party_driver/plic\
|
||||
-I$(KERNEL_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/k210-emulator)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/spi/third_party_spi_lora/inc \
|
||||
-I$(BSP_ROOT)/third_party_driver/spi/third_party_spi_lora/src/radio \
|
||||
-I$(BSP_ROOT)/third_party_driver/camera \
|
||||
-I$(BSP_ROOT)/third_party_driver/drivers \
|
||||
-I$(BSP_ROOT)/third_party_driver/lcd \
|
||||
-I$(KERNEL_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/aiit-riscv64-board)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/spi/third_party_spi_lora/inc \
|
||||
-I$(BSP_ROOT)/third_party_driver/spi/third_party_spi_lora/src/radio \
|
||||
-I$(BSP_ROOT)/third_party_driver/camera \
|
||||
-I$(BSP_ROOT)/third_party_driver/drivers \
|
||||
-I$(BSP_ROOT)/third_party_driver/lcd \
|
||||
-I$(KERNEL_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/cortex-m0-emulator)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m0 \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/Libraries/driverlib \
|
||||
-I$(BSP_ROOT)/third_party_driver/Libraries/ \
|
||||
-I$(BSP_ROOT)/third_party_driver/Libraries/inc \
|
||||
-I$(KERNEL_ROOT)/include \
|
||||
-I$(BSP_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/cortex-m3-emulator)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m3 \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/Libraries/driverlib \
|
||||
-I$(BSP_ROOT)/third_party_driver/Libraries/ \
|
||||
-I$(BSP_ROOT)/third_party_driver/Libraries/inc \
|
||||
-I$(KERNEL_ROOT)/include \
|
||||
-I$(BSP_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/cortex-m4-emulator)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m4 \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/sdio\
|
||||
-I$(BSP_ROOT)/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/usb/STM32_USB_OTG_Driver/inc \
|
||||
-I$(KERNEL_ROOT)/include \
|
||||
-I$(BSP_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/ok1052-c)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m7 \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/ethernet \
|
||||
-I$(BSP_ROOT)/third_party_driver/ethernet/ksz8081 \
|
||||
-I$(BSP_ROOT)/third_party_driver/MIMXRT1052 \
|
||||
-I$(BSP_ROOT)/third_party_driver/MIMXRT1052/drivers \
|
||||
-I$(BSP_ROOT)/third_party_driver/CMSIS/Include \
|
||||
-I$(KERNEL_ROOT)/include \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/compat \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/netif \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/apps \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/priv \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/prot \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/arch \
|
||||
-I$(KERNEL_ROOT)/resources/include \
|
||||
-I$(BSP_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/stm32f103-nano)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m3 \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/libraries/STM32F1xx_HAL/inc \
|
||||
-I$(BSP_ROOT)/third_party_driver/libraries/CMSIS \
|
||||
-I$(KERNEL_ROOT)/include \
|
||||
-I$(BSP_ROOT)/include #
|
||||
endif
|
||||
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/arch \
|
||||
-I$(KERNEL_ROOT)/arch/risc-v/shared/kernel_service #
|
||||
|
||||
ifeq ($(CONFIG_FS_VFS), y)
|
||||
KERNELPATHS +=-I$(KERNEL_ROOT)/fs/devfs \
|
||||
-I$(KERNEL_ROOT)/fs/fatfs \
|
||||
-I$(KERNEL_ROOT)/fs/shared/include #
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_FS_CH376), y)
|
||||
KERNELPATHS +=-I$(KERNEL_ROOT)/fs/compatibility_ch376 #
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_TRANSFORM_LAYER_ATTRIUBUTE), y)
|
||||
ifeq ($(CONFIG_ADD_XIUOS_FETURES), y)
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/transform_layer/xiuos/user_api/posix_support/include #
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/transform_layer/xiuos #
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ADD_NUTTX_FETURES), y)
|
||||
#
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ADD_RTTHREAD_FETURES), y)
|
||||
#
|
||||
endif
|
||||
|
||||
endif
|
||||
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Applications/general_functions/list #
|
||||
|
||||
ifeq ($(CONFIG_SUPPORT_SENSOR_FRAMEWORK), y)
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/sensor #
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SUPPORT_CONNECTION_FRAMEWORK), y)
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/connection #
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/connection/zigbee #
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SUPPORT_KNOWING_FRAMEWORK), y)
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing #
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source #
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/gemmlowp #
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/flatbuffers/include #
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/ruy #
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LIB_LV),y)
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/lib/lvgl #
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/lib/lvgl/examples/porting #
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SUPPORT_CONTROL_FRAMEWORK), y)
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control #
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control/plc/interoperability/opcua #
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control/plc/shared #
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/lib/cJSON
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_CRYPTO), y)
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/framework/security/crypto/include #
|
||||
endif
|
||||
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/resources/include #
|
||||
|
||||
ifeq ($(CONFIG_RESOURCES_SPI), y)
|
||||
KERNELPATHS +=-I$(KERNEL_ROOT)/resources/spi #
|
||||
|
||||
ifeq ($(CONFIG_RESOURCES_SPI_SFUD),y)
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/resources/spi/third_party_spi/SFUD/sfud/inc #
|
||||
endif
|
||||
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_TOOL_SHELL), y)
|
||||
KERNELPATHS +=-I$(KERNEL_ROOT)/tool/shell/letter-shell \
|
||||
-I$(KERNEL_ROOT)/tool/shell/letter-shell/file_ext #
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(CONFIG_LIB_NEWLIB),y)
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/lib/newlib/include #
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(ARCH), risc-v)
|
||||
KERNELPATHS +=-I$(KERNEL_ROOT)/arch/risc-v/shared
|
||||
ifeq ($(MCU), k210)
|
||||
KERNELPATHS +=-I$(KERNEL_ROOT)/arch/risc-v/k210
|
||||
endif
|
||||
ifeq ($(MCU), FE310)
|
||||
KERNELPATHS +=-I$(KERNEL_ROOT)/arch/risc-v/fe310
|
||||
endif
|
||||
ifeq ($(MCU), GAP8)
|
||||
KERNELPATHS +=-I$(KERNEL_ROOT)/arch/risc-v/gap8
|
||||
endif
|
||||
ifeq ($(MCU), GD32VF103)
|
||||
KERNELPATHS +=-I$(KERNEL_ROOT)/arch/risc-v/gd32vf103
|
||||
endif
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(ARCH), arm)
|
||||
KERNELPATHS +=-I$(KERNEL_ROOT)/arch/arm/shared \
|
||||
-I$(KERNEL_ROOT)/lib/comlibc/common #
|
||||
endif
|
||||
|
||||
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/kernel/include #
|
||||
|
||||
|
||||
COMPILE_KERNEL:
|
||||
@$(eval CPPPATHS=$(KERNELPATHS))
|
||||
@for dir in $(SRC_KERNEL_DIR);do \
|
||||
$(MAKE) -C $$dir; \
|
||||
done
|
||||
@cp link.mk build/Makefile
|
||||
@$(MAKE) -C build COMPILE_TYPE="_kernel" TARGET=XiUOS_$(BOARD)_kernel.elf LINK_FLAGS=LFLAGS
|
||||
@rm build/Makefile build/make.obj
|
||||
|
||||
|
|
@ -1,261 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file lwipopts.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 31-July-2013
|
||||
* @brief lwIP Options Configuration.
|
||||
* This file is based on Utilities\lwip_v1.4.1\src\include\lwip\opt.h
|
||||
* and contains the lwIP configuration for the STM32F4x7 demonstration.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __LWIPOPTS_H__
|
||||
#define __LWIPOPTS_H__
|
||||
|
||||
/**
|
||||
* SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
|
||||
* critical regions during buffer allocation, deallocation and memory
|
||||
* allocation and deallocation.
|
||||
*/
|
||||
#define SYS_LIGHTWEIGHT_PROT 1
|
||||
|
||||
/**
|
||||
* NO_SYS==1: Provides VERY minimal functionality. Otherwise,
|
||||
* use lwIP facilities.
|
||||
*/
|
||||
#define NO_SYS 0
|
||||
|
||||
/**
|
||||
* NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1
|
||||
* Mainly for compatibility to old versions.
|
||||
*/
|
||||
#define NO_SYS_NO_TIMERS 0
|
||||
|
||||
/* ---------- Memory options ---------- */
|
||||
/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
|
||||
lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
|
||||
byte alignment -> define MEM_ALIGNMENT to 2. */
|
||||
#define MEM_ALIGNMENT 4
|
||||
|
||||
/* MEM_SIZE: the size of the heap memory. If the application will send
|
||||
a lot of data that needs to be copied, this should be set high. */
|
||||
#define MEM_SIZE (25*1024)
|
||||
|
||||
/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
|
||||
sends a lot of data out of ROM (or other static memory), this
|
||||
should be set high. */
|
||||
#define MEMP_NUM_PBUF 15
|
||||
/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
|
||||
per active UDP "connection". */
|
||||
#define MEMP_NUM_UDP_PCB 4
|
||||
/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
|
||||
connections. */
|
||||
#define MEMP_NUM_TCP_PCB 4
|
||||
/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
|
||||
connections. */
|
||||
#define MEMP_NUM_TCP_PCB_LISTEN 2
|
||||
/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
|
||||
segments. */
|
||||
#define MEMP_NUM_TCP_SEG 120
|
||||
/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
|
||||
timeouts. */
|
||||
#define MEMP_NUM_SYS_TIMEOUT 6
|
||||
|
||||
|
||||
/* ---------- Pbuf options ---------- */
|
||||
/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
|
||||
#define PBUF_POOL_SIZE 20
|
||||
/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
|
||||
#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_ENCAPSULATION_HLEN+PBUF_LINK_HLEN)
|
||||
|
||||
|
||||
/* ---------- TCP options ---------- */
|
||||
#define LWIP_TCP 1
|
||||
#define TCP_TTL 255
|
||||
|
||||
/* Controls if TCP should queue segments that arrive out of
|
||||
order. Define to 0 if your device is low on memory. */
|
||||
#define TCP_QUEUE_OOSEQ 0
|
||||
|
||||
/* TCP Maximum segment size. */
|
||||
#define TCP_MSS (1500 - 40) /* TCP_MSS = (Ethernet MTU - IP header size - TCP header size) */
|
||||
|
||||
/* TCP sender buffer space (bytes). */
|
||||
#define TCP_SND_BUF (11*TCP_MSS)
|
||||
|
||||
/* TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
|
||||
as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. */
|
||||
|
||||
#define TCP_SND_QUEUELEN (8* TCP_SND_BUF/TCP_MSS)
|
||||
|
||||
/* TCP receive window. */
|
||||
#define TCP_WND (12*TCP_MSS)
|
||||
|
||||
|
||||
/* ---------- ICMP options ---------- */
|
||||
#define LWIP_ICMP 1
|
||||
|
||||
|
||||
/* ---------- DHCP options ---------- */
|
||||
/* Define LWIP_DHCP to 1 if you want DHCP configuration of
|
||||
interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
|
||||
turning this on does currently not work. */
|
||||
#define LWIP_DHCP 1
|
||||
|
||||
|
||||
/* ---------- UDP options ---------- */
|
||||
#define LWIP_UDP 1
|
||||
#define UDP_TTL 255
|
||||
|
||||
|
||||
/* ---------- Statistics options ---------- */
|
||||
#define LWIP_STATS 0
|
||||
#define LWIP_PROVIDE_ERRNO 1
|
||||
|
||||
/* ---------- link callback options ---------- */
|
||||
/* LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
|
||||
* whenever the link changes (i.e., link down)
|
||||
*/
|
||||
#define LWIP_NETIF_LINK_CALLBACK 0
|
||||
/*
|
||||
--------------------------------------
|
||||
---------- Checksum options ----------
|
||||
--------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
The STM32F4x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums by hardware:
|
||||
- To use this feature let the following define uncommented.
|
||||
- To disable it and process by CPU comment the the checksum.
|
||||
*/
|
||||
//#define CHECKSUM_BY_HARDWARE
|
||||
|
||||
#ifdef CHECKSUM_BY_HARDWARE
|
||||
/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/
|
||||
#define CHECKSUM_GEN_IP 0
|
||||
/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/
|
||||
#define CHECKSUM_GEN_UDP 0
|
||||
/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/
|
||||
#define CHECKSUM_GEN_TCP 0
|
||||
/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/
|
||||
#define CHECKSUM_CHECK_IP 0
|
||||
/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/
|
||||
#define CHECKSUM_CHECK_UDP 0
|
||||
/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/
|
||||
#define CHECKSUM_CHECK_TCP 0
|
||||
/* CHECKSUM_CHECK_ICMP==0: Check checksums by hardware for incoming ICMP packets.*/
|
||||
#define CHECKSUM_GEN_ICMP 0
|
||||
#else
|
||||
/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/
|
||||
#define CHECKSUM_GEN_IP 1
|
||||
/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/
|
||||
#define CHECKSUM_GEN_UDP 1
|
||||
/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/
|
||||
#define CHECKSUM_GEN_TCP 1
|
||||
/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/
|
||||
#define CHECKSUM_CHECK_IP 1
|
||||
/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/
|
||||
#define CHECKSUM_CHECK_UDP 1
|
||||
/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/
|
||||
#define CHECKSUM_CHECK_TCP 1
|
||||
/* CHECKSUM_CHECK_ICMP==1: Check checksums by hardware for incoming ICMP packets.*/
|
||||
#define CHECKSUM_GEN_ICMP 1
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
----------------------------------------------
|
||||
---------- Sequential layer options ----------
|
||||
----------------------------------------------
|
||||
*/
|
||||
/**
|
||||
* LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
|
||||
*/
|
||||
#define LWIP_NETCONN 1
|
||||
|
||||
/*
|
||||
------------------------------------
|
||||
---------- Socket options ----------
|
||||
------------------------------------
|
||||
*/
|
||||
/**
|
||||
* LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
|
||||
*/
|
||||
#define LWIP_SOCKET 1
|
||||
|
||||
/*
|
||||
---------------------------------
|
||||
---------- OS options ----------
|
||||
---------------------------------
|
||||
*/
|
||||
|
||||
#define DEFAULT_RAW_RECVMBOX_SIZE 10
|
||||
#define DEFAULT_UDP_RECVMBOX_SIZE 10
|
||||
#define DEFAULT_TCP_RECVMBOX_SIZE 10
|
||||
#define DEFAULT_ACCEPTMBOX_SIZE 10
|
||||
|
||||
#define DEFAULT_THREAD_PRIO 20
|
||||
#define DEFAULT_THREAD_STACKSIZE 1024
|
||||
|
||||
#define TCPIP_THREAD_NAME "tcp"
|
||||
#define TCPIP_THREAD_STACKSIZE 4096
|
||||
#define TCPIP_MBOX_SIZE 10
|
||||
#define TCPIP_THREAD_PRIO 15
|
||||
|
||||
//#define IPERF_SERVER_THREAD_NAME "iperf_server"
|
||||
//#define IPERF_SERVER_THREAD_STACKSIZE 1024
|
||||
//#define IPERF_SERVER_THREAD_PRIO 0
|
||||
|
||||
//#define BLOCK_TIME 250
|
||||
//#define BLOCK_TIME_WAITING_FOR_INPUT ( ( portTickType ) 100 )
|
||||
|
||||
/*
|
||||
----------------------------------------
|
||||
---------- Lwip Debug options ----------
|
||||
----------------------------------------
|
||||
*/
|
||||
#define LWIP_DEBUG 1
|
||||
|
||||
#define LWIP_IPV4 1
|
||||
#define LWIP_RAW 1
|
||||
#define LWIP_DNS 1
|
||||
|
||||
#if LWIP_DNS
|
||||
#define LWIP_RAND rand
|
||||
#endif
|
||||
|
||||
#ifndef nfds_t
|
||||
typedef unsigned int nfds_t;
|
||||
#endif
|
||||
|
||||
#define FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
|
||||
|
||||
#define MEMP_LIB_MALLOC 1
|
||||
#define MEMP_MEM_MALLOC 1
|
||||
|
||||
#define lw_print //KPrintf
|
||||
#define lw_trace() //KPrintf("lw: [%s][%d] passed!\n", __func__, __LINE__)
|
||||
#define lw_error() //KPrintf("lw: [%s][%d] failed!\n", __func__, __LINE__)
|
||||
#define lw_pr_info KPrintf
|
||||
#endif /* __LWIPOPTS_H__ */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -1,582 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Simon Goldschmidt
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the lwIP TCP/IP stack.
|
||||
*
|
||||
* Author: Simon Goldschmidt
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file sys_arch.c
|
||||
* @brief In order to adapt to XiUOS, some changes have been made to implement the LwIP interface.
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-29
|
||||
*/
|
||||
|
||||
#include "debug.h"
|
||||
|
||||
#include <lwip/opt.h>
|
||||
#include <lwip/arch.h>
|
||||
|
||||
#include "tcpip.h"
|
||||
#include "lwip/init.h"
|
||||
#include "lwip/netif.h"
|
||||
#include "lwip/sio.h"
|
||||
#include <lwip/stats.h>
|
||||
#include <lwip/debug.h>
|
||||
#include <lwip/sys.h>
|
||||
#include "lwip/dhcp.h"
|
||||
#include "tcpip_priv.h"
|
||||
|
||||
#if !NO_SYS
|
||||
#include "sys_arch.h"
|
||||
#endif
|
||||
|
||||
#include <string.h>
|
||||
#include <xs_ktask.h>
|
||||
#include <xs_ktick.h>
|
||||
#include <xs_assign.h>
|
||||
#include <xs_sem.h>
|
||||
#include <xs_mutex.h>
|
||||
#include <xs_ktask.h>
|
||||
#include <xs_msg.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "ethernet.h"
|
||||
#include "enet_ethernetif.h"
|
||||
|
||||
char lwip_ipaddr[] = {192, 168, 250, 253};
|
||||
char lwip_netmask[] = {255, 255, 255, 0};
|
||||
char lwip_gwaddr[] = {192, 168, 250, 252};
|
||||
char lwip_flag = 0;
|
||||
|
||||
x_ticks_t lwip_sys_now;
|
||||
|
||||
struct sys_timeouts {
|
||||
struct sys_timeo *next;
|
||||
};
|
||||
|
||||
struct timeoutlist
|
||||
{
|
||||
struct sys_timeouts timeouts;
|
||||
int32 pid;
|
||||
};
|
||||
|
||||
#define SYS_THREAD_MAX 4
|
||||
|
||||
static struct timeoutlist s_timeoutlist[SYS_THREAD_MAX];
|
||||
|
||||
static u16_t s_nextthread = 0;
|
||||
|
||||
u32_t
|
||||
sys_jiffies(void)
|
||||
{
|
||||
lwip_sys_now = CurrentTicksGain();
|
||||
return lwip_sys_now;
|
||||
}
|
||||
|
||||
u32_t
|
||||
sys_now(void)
|
||||
{
|
||||
lwip_sys_now = CurrentTicksGain();
|
||||
return lwip_sys_now;
|
||||
}
|
||||
|
||||
void
|
||||
sys_init(void)
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < SYS_THREAD_MAX; i++)
|
||||
{
|
||||
s_timeoutlist[i].pid = 0;
|
||||
s_timeoutlist[i].timeouts.next = NULL;
|
||||
}
|
||||
s_nextthread = 0;
|
||||
}
|
||||
|
||||
struct sys_timeouts *sys_arch_timeouts(void)
|
||||
{
|
||||
int i;
|
||||
int32 pid;
|
||||
struct timeoutlist *tl;
|
||||
pid = (int32)GetKTaskDescriptor()->id.id;
|
||||
for(i = 0; i < s_nextthread; i++)
|
||||
{
|
||||
tl = &(s_timeoutlist[i]);
|
||||
if(tl->pid == pid)
|
||||
{
|
||||
return &(tl->timeouts);
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
sys_prot_t sys_arch_protect(void)
|
||||
{
|
||||
return CriticalAreaLock();
|
||||
}
|
||||
|
||||
void sys_arch_unprotect(sys_prot_t pval)
|
||||
{
|
||||
CriticalAreaUnLock(pval);
|
||||
}
|
||||
|
||||
#if !NO_SYS
|
||||
|
||||
err_t
|
||||
sys_sem_new(sys_sem_t *sem, u8_t count)
|
||||
{
|
||||
*sem = KSemaphoreCreate((uint16)count);
|
||||
|
||||
#if SYS_STATS
|
||||
++lwip_stats.sys.sem.used;
|
||||
if (lwip_stats.sys.sem.max < lwip_stats.sys.sem.used) {
|
||||
lwip_stats.sys.sem.max = lwip_stats.sys.sem.used;
|
||||
}
|
||||
#endif /* SYS_STATS */
|
||||
|
||||
if(*sem >= 0)
|
||||
return ERR_OK;
|
||||
else
|
||||
{
|
||||
#if SYS_STATS
|
||||
++lwip_stats.sys.sem.err;
|
||||
#endif /* SYS_STATS */
|
||||
KPrintf("[sys_arch]:new sem fail!\n");
|
||||
return ERR_MEM;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
sys_sem_free(sys_sem_t *sem)
|
||||
{
|
||||
#if SYS_STATS
|
||||
--lwip_stats.sys.sem.used;
|
||||
#endif /* SYS_STATS */
|
||||
KSemaphoreDelete(*sem);
|
||||
*sem = SYS_SEM_NULL;
|
||||
}
|
||||
|
||||
int sys_sem_valid(sys_sem_t *sem)
|
||||
{
|
||||
return (*sem >= SYS_SEM_NULL);
|
||||
}
|
||||
|
||||
void
|
||||
sys_sem_set_invalid(sys_sem_t *sem)
|
||||
{
|
||||
*sem = SYS_SEM_NULL;
|
||||
}
|
||||
|
||||
u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout)
|
||||
{
|
||||
x_ticks_t start_tick = 0 ;
|
||||
int32 wait_time = 0;
|
||||
|
||||
|
||||
if(*sem == SYS_SEM_NULL)
|
||||
return SYS_ARCH_TIMEOUT;
|
||||
|
||||
|
||||
start_tick = CurrentTicksGain();
|
||||
|
||||
if (0 == timeout)
|
||||
wait_time = WAITING_FOREVER;
|
||||
else
|
||||
wait_time = timeout;
|
||||
|
||||
|
||||
if(KSemaphoreObtain(*sem, wait_time) == EOK)
|
||||
return ((CurrentTicksGain()-start_tick)*MS_PER_SYSTICK_F407);
|
||||
else
|
||||
return SYS_ARCH_TIMEOUT;
|
||||
}
|
||||
|
||||
void sys_sem_signal(sys_sem_t *sem)
|
||||
{
|
||||
if(KSemaphoreAbandon( *sem ) != EOK)
|
||||
KPrintf("[sys_arch]:sem signal fail!\n");
|
||||
}
|
||||
|
||||
err_t sys_mutex_new(sys_mutex_t *mutex)
|
||||
{
|
||||
*mutex = KMutexCreate();
|
||||
if(*mutex >= 0)
|
||||
return ERR_OK;
|
||||
else
|
||||
{
|
||||
KPrintf("[sys_arch]:new mutex fail!\n");
|
||||
return ERR_MEM;
|
||||
}
|
||||
}
|
||||
|
||||
void sys_mutex_free(sys_mutex_t *mutex)
|
||||
{
|
||||
KMutexDelete(*mutex);
|
||||
}
|
||||
|
||||
void sys_mutex_set_invalid(sys_mutex_t *mutex)
|
||||
{
|
||||
*mutex = SYS_MRTEX_NULL;
|
||||
}
|
||||
|
||||
void sys_mutex_lock(sys_mutex_t *mutex)
|
||||
{
|
||||
KMutexObtain(*mutex,
|
||||
WAITING_FOREVER);
|
||||
}
|
||||
|
||||
void sys_mutex_unlock(sys_mutex_t *mutex)
|
||||
{
|
||||
KMutexAbandon( *mutex );
|
||||
}
|
||||
|
||||
|
||||
sys_thread_t sys_thread_new(const char *name, lwip_thread_fn function, void *arg, int stacksize, int prio)
|
||||
{
|
||||
sys_thread_t handle = -1;
|
||||
handle = KTaskCreate(name,
|
||||
function,
|
||||
arg,
|
||||
(uint32)stacksize,
|
||||
(uint8)prio);
|
||||
if (handle >= 0)
|
||||
{
|
||||
StartupKTask(handle);
|
||||
lw_print("lw: [%s] create %s handle %x\n", __func__, name, handle);
|
||||
return handle;
|
||||
}
|
||||
lw_print("lw: [%s] create %s failed\n", __func__, name);
|
||||
return -ERROR;
|
||||
}
|
||||
|
||||
err_t sys_mbox_new(sys_mbox_t *mbox, int size)
|
||||
{
|
||||
*mbox = KCreateMsgQueue(sizeof(void *), size);
|
||||
|
||||
#if SYS_STATS
|
||||
++lwip_stats.sys.mbox.used;
|
||||
if (lwip_stats.sys.mbox.max < lwip_stats.sys.mbox.used) {
|
||||
lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used;
|
||||
}
|
||||
#endif /* SYS_STATS */
|
||||
if(*mbox < 0)
|
||||
{
|
||||
lw_print("lw: [%s] alloc %d mbox %p failed\n", __func__, size, mbox);
|
||||
return ERR_MEM;
|
||||
}
|
||||
|
||||
lw_print("lw: [%s] alloc %d mbox %p ok!\n", __func__, size, mbox);
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
void sys_mbox_free(sys_mbox_t *mbox)
|
||||
{
|
||||
KDeleteMsgQueue(*mbox);
|
||||
}
|
||||
|
||||
int sys_mbox_valid(sys_mbox_t *mbox)
|
||||
{
|
||||
if (*mbox <= SYS_MBOX_NULL)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
void sys_mbox_set_invalid(sys_mbox_t *mbox)
|
||||
{
|
||||
*mbox = SYS_MBOX_NULL;
|
||||
}
|
||||
|
||||
void sys_mbox_post(sys_mbox_t *q, void *msg)
|
||||
{
|
||||
while(KMsgQueueSendwait( *q, &msg, sizeof(void *), WAITING_FOREVER) != EOK);
|
||||
}
|
||||
|
||||
err_t sys_mbox_trypost(sys_mbox_t *q, void *msg)
|
||||
{
|
||||
if(KMsgQueueSend(*q, &msg, sizeof(void *)) == EOK)
|
||||
return ERR_OK;
|
||||
else
|
||||
return ERR_MEM;
|
||||
}
|
||||
|
||||
err_t sys_mbox_trypost_fromisr(sys_mbox_t *q, void *msg)
|
||||
{
|
||||
return sys_mbox_trypost(q, msg);
|
||||
}
|
||||
|
||||
u32_t sys_arch_mbox_fetch(sys_mbox_t *q, void **msg, u32_t timeout)
|
||||
{
|
||||
x_ticks_t start_tick = 0 ;
|
||||
int32 wait_time = 0;
|
||||
|
||||
start_tick = CurrentTicksGain();
|
||||
|
||||
if (0 == timeout)
|
||||
wait_time = WAITING_FOREVER;
|
||||
else
|
||||
wait_time = timeout;
|
||||
|
||||
if(KMsgQueueRecv(*q, &(*msg), sizeof(void *), wait_time) == EOK)
|
||||
return ((CurrentTicksGain()-start_tick)*MS_PER_SYSTICK_F407);
|
||||
else{
|
||||
*msg = NULL;
|
||||
return SYS_ARCH_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
u32_t sys_arch_mbox_tryfetch(sys_mbox_t *q, void **msg)
|
||||
{
|
||||
if(KMsgQueueRecv(*q, &(*msg), sizeof(void *), 0) == EOK)
|
||||
return ERR_OK;
|
||||
else
|
||||
return SYS_MBOX_EMPTY;
|
||||
}
|
||||
|
||||
#if LWIP_NETCONN_SEM_PER_THREAD
|
||||
#error LWIP_NETCONN_SEM_PER_THREAD==1 not supported
|
||||
#endif /* LWIP_NETCONN_SEM_PER_THREAD */
|
||||
|
||||
#endif /* !NO_SYS */
|
||||
|
||||
/* Variables Initialization */
|
||||
struct netif gnetif;
|
||||
ip4_addr_t ipaddr;
|
||||
ip4_addr_t netmask;
|
||||
ip4_addr_t gw;
|
||||
|
||||
void lwip_tcp_init(void)
|
||||
{
|
||||
tcpip_init(NULL, NULL);
|
||||
|
||||
/* IP addresses initialization */
|
||||
/* USER CODE BEGIN 0 */
|
||||
#if LWIP_DHCP
|
||||
ip_addr_set_zero_ip4(&ipaddr);
|
||||
ip_addr_set_zero_ip4(&netmask);
|
||||
ip_addr_set_zero_ip4(&gw);
|
||||
#else
|
||||
IP4_ADDR(&ipaddr, lwip_ipaddr[0], lwip_ipaddr[1], lwip_ipaddr[2], lwip_ipaddr[3]);
|
||||
IP4_ADDR(&netmask, lwip_netmask[0], lwip_netmask[1], lwip_netmask[2], lwip_netmask[3]);
|
||||
IP4_ADDR(&gw, lwip_gwaddr[0], lwip_gwaddr[1], lwip_gwaddr[2], lwip_gwaddr[3]);
|
||||
#endif /* USE_DHCP */
|
||||
/* USER CODE END 0 */
|
||||
/* Initilialize the LwIP stack without RTOS */
|
||||
/* add the network interface (IPv4/IPv6) without RTOS */
|
||||
netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, ðernetif0_init, &tcpip_input);
|
||||
|
||||
/* Registers the default network interface */
|
||||
netif_set_default(&gnetif);
|
||||
|
||||
if (netif_is_link_up(&gnetif))
|
||||
{
|
||||
/* When the netif is fully configured this function must be called */
|
||||
KPrintf("%s : netif_set_up\n", __func__);
|
||||
netif_set_up(&gnetif);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* When the netif link is down this function must be called */
|
||||
KPrintf("%s : netif_set_down\n", __func__);
|
||||
netif_set_down(&gnetif);
|
||||
}
|
||||
|
||||
#if LWIP_DHCP
|
||||
int err;
|
||||
/* Creates a new DHCP client for this interface on the first call.
|
||||
Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
|
||||
the predefined regular intervals after starting the client.
|
||||
You can peek in the netif->dhcp struct for the actual DHCP status.*/
|
||||
|
||||
|
||||
err = dhcp_start(&gnetif);
|
||||
if(err == ERR_OK)
|
||||
KPrintf("lwip dhcp init success...\n\n");
|
||||
else
|
||||
KPrintf("lwip dhcp init fail...\n\n");
|
||||
while(ip_addr_cmp(&(gnetif.ip_addr),&ipaddr))
|
||||
{
|
||||
DelayKTask(1);
|
||||
}
|
||||
#endif
|
||||
KPrintf("\n\nIP:%d.%d.%d.%d\n\n", \
|
||||
((gnetif.ip_addr.addr)&0x000000ff), \
|
||||
(((gnetif.ip_addr.addr)&0x0000ff00)>>8), \
|
||||
(((gnetif.ip_addr.addr)&0x00ff0000)>>16), \
|
||||
((gnetif.ip_addr.addr)&0xff000000)>>24);
|
||||
}
|
||||
|
||||
// lwip input thread to get network packet
|
||||
void lwip_input_thread(void *param)
|
||||
{
|
||||
struct netif *net = param;
|
||||
|
||||
while (1)
|
||||
{
|
||||
#ifdef FSL_RTOS_XIUOS
|
||||
if (lwip_obtain_semaphore(net) == EOK)
|
||||
#endif
|
||||
{
|
||||
/* Poll the driver, get any outstanding frames */
|
||||
ethernetif_input(net);
|
||||
sys_check_timeouts(); /* Handle all system timeouts for all core protocols */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void lwip_config_input(struct netif *net)
|
||||
{
|
||||
sys_thread_t th_id = 0;
|
||||
|
||||
th_id = sys_thread_new("eth_input", lwip_input_thread, net, LWIP_TASK_STACK_SIZE, 15);
|
||||
|
||||
if (th_id >= 0) {
|
||||
lw_print("%s %d successfully!\n", __func__, th_id);
|
||||
} else {
|
||||
lw_print("%s failed!\n", __func__);
|
||||
}
|
||||
}
|
||||
|
||||
void lwip_config_net(char *ip, char *mask, char *gw)
|
||||
{
|
||||
#if defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
|
||||
mem_range_t non_dma_memory[] = NON_DMA_MEMORY_ARRAY;
|
||||
#endif /* FSL_FEATURE_SOC_LPC_ENET_COUNT */
|
||||
ip4_addr_t net_ipaddr, net_netmask, net_gw;
|
||||
ethernetif_config_t cfg = {
|
||||
.phyAddress = BOARD_ENET0_PHY_ADDRESS,
|
||||
.clockName = kCLOCK_CoreSysClk,
|
||||
.macAddress = configMAC_ADDR,
|
||||
#if defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
|
||||
.non_dma_memory = non_dma_memory,
|
||||
#endif /* FSL_FEATURE_SOC_LPC_ENET_COUNT */
|
||||
};
|
||||
|
||||
ETH_BSP_Config();
|
||||
|
||||
if(chk_lwip_bit(LWIP_INIT_FLAG))
|
||||
{
|
||||
lw_print("lw: [%s] already ...\n", __func__);
|
||||
|
||||
IP4_ADDR(&net_ipaddr, ip[0], ip[1], ip[2], ip[3]);
|
||||
IP4_ADDR(&net_netmask, mask[0], mask[1], mask[2], mask[3]);
|
||||
IP4_ADDR(&net_gw, gw[0], gw[1], gw[2], gw[3]);
|
||||
|
||||
// update ip addr
|
||||
netif_set_down(&gnetif);
|
||||
netif_set_gw(&gnetif, &net_gw);
|
||||
netif_set_netmask(&gnetif, &net_netmask);
|
||||
netif_set_ipaddr(&gnetif, &net_ipaddr);
|
||||
netif_set_up(&gnetif);
|
||||
return;
|
||||
}
|
||||
set_lwip_bit(LWIP_INIT_FLAG);
|
||||
|
||||
lw_print("lw: [%s] start ...\n", __func__);
|
||||
|
||||
IP4_ADDR(&net_ipaddr, ip[0], ip[1], ip[2], ip[3]);
|
||||
IP4_ADDR(&net_netmask, mask[0], mask[1], mask[2], mask[3]);
|
||||
IP4_ADDR(&net_gw, gw[0], gw[1], gw[2], gw[3]);
|
||||
|
||||
lwip_init();
|
||||
|
||||
netif_add(&gnetif, &net_ipaddr, &net_netmask, &net_gw, &cfg, ethernetif0_init,
|
||||
ethernet_input);
|
||||
netif_set_default(&gnetif);
|
||||
netif_set_up(&gnetif);
|
||||
|
||||
if(chk_lwip_bit(LWIP_PRINT_FLAG))
|
||||
{
|
||||
lw_pr_info("\r\n************************************************\r\n");
|
||||
lw_pr_info(" Network Configuration\r\n");
|
||||
lw_pr_info("************************************************\r\n");
|
||||
lw_pr_info(" IPv4 Address : %u.%u.%u.%u\r\n", ((u8_t *)&net_ipaddr)[0], ((u8_t *)&net_ipaddr)[1],
|
||||
((u8_t *)&net_ipaddr)[2], ((u8_t *)&net_ipaddr)[3]);
|
||||
lw_pr_info(" IPv4 Subnet mask : %u.%u.%u.%u\r\n", ((u8_t *)&net_netmask)[0], ((u8_t *)&net_netmask)[1],
|
||||
((u8_t *)&net_netmask)[2], ((u8_t *)&net_netmask)[3]);
|
||||
lw_pr_info(" IPv4 Gateway : %u.%u.%u.%u\r\n", ((u8_t *)&net_gw)[0], ((u8_t *)&net_gw)[1],
|
||||
((u8_t *)&net_gw)[2], ((u8_t *)&net_gw)[3]);
|
||||
lw_pr_info("************************************************\r\n");
|
||||
}
|
||||
lwip_config_input(&gnetif);
|
||||
}
|
||||
|
||||
void lwip_config_tcp(char *ip, char *mask, char *gw)
|
||||
{
|
||||
#if defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
|
||||
mem_range_t non_dma_memory[] = NON_DMA_MEMORY_ARRAY;
|
||||
#endif /* FSL_FEATURE_SOC_LPC_ENET_COUNT */
|
||||
ip4_addr_t net_ipaddr, net_netmask, net_gw;
|
||||
ethernetif_config_t cfg = {
|
||||
.phyAddress = BOARD_ENET0_PHY_ADDRESS,
|
||||
.clockName = kCLOCK_CoreSysClk,
|
||||
.macAddress = configMAC_ADDR,
|
||||
#if defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
|
||||
.non_dma_memory = non_dma_memory,
|
||||
#endif /* FSL_FEATURE_SOC_LPC_ENET_COUNT */
|
||||
};
|
||||
|
||||
ETH_BSP_Config();
|
||||
|
||||
if(chk_lwip_bit(LWIP_INIT_FLAG))
|
||||
{
|
||||
lw_print("lw: [%s] already ...\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
set_lwip_bit(LWIP_INIT_FLAG);
|
||||
|
||||
tcpip_init(NULL, NULL);
|
||||
|
||||
lw_print("lw: [%s] start ...\n", __func__);
|
||||
|
||||
IP4_ADDR(&net_ipaddr, ip[0], ip[1], ip[2], ip[3]);
|
||||
IP4_ADDR(&net_netmask, mask[0], mask[1], mask[2], mask[3]);
|
||||
IP4_ADDR(&net_gw, gw[0], gw[1], gw[2], gw[3]);
|
||||
|
||||
netif_add(&gnetif, &net_ipaddr, &net_netmask, &net_gw, &cfg, ethernetif0_init,
|
||||
tcpip_input);
|
||||
|
||||
netif_set_default(&gnetif);
|
||||
netif_set_up(&gnetif);
|
||||
|
||||
lw_print("\r\n************************************************\r\n");
|
||||
lw_print(" Network Configuration\r\n");
|
||||
lw_print("************************************************\r\n");
|
||||
lw_print(" IPv4 Address : %u.%u.%u.%u\r\n", ((u8_t *)&net_ipaddr)[0], ((u8_t *)&net_ipaddr)[1],
|
||||
((u8_t *)&net_ipaddr)[2], ((u8_t *)&net_ipaddr)[3]);
|
||||
lw_print(" IPv4 Subnet mask : %u.%u.%u.%u\r\n", ((u8_t *)&net_netmask)[0], ((u8_t *)&net_netmask)[1],
|
||||
((u8_t *)&net_netmask)[2], ((u8_t *)&net_netmask)[3]);
|
||||
lw_print(" IPv4 Gateway : %u.%u.%u.%u\r\n", ((u8_t *)&net_gw)[0], ((u8_t *)&net_gw)[1],
|
||||
((u8_t *)&net_gw)[2], ((u8_t *)&net_gw)[3]);
|
||||
lw_print("************************************************\r\n");
|
||||
|
||||
lwip_config_input(&gnetif);
|
||||
}
|
||||
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Simon Goldschmidt
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the lwIP TCP/IP stack.
|
||||
*
|
||||
* Author: Simon Goldschmidt
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file sys_arch.h
|
||||
* @brief In order to adapt to XiUOS, some changes have been made to implement the LwIP interface.
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-29
|
||||
*/
|
||||
|
||||
#ifndef __SYS_ARCH__
|
||||
#define __SYS_ATCH__
|
||||
|
||||
#include <lwip/opt.h>
|
||||
#include <lwip/arch.h>
|
||||
#include <lwip/netif.h>
|
||||
|
||||
#include "tcpip.h"
|
||||
|
||||
#include <xs_base.h>
|
||||
|
||||
/* LWIP task parameter */
|
||||
#define LWIP_LOCAL_PORT 4840
|
||||
#define LWIP_TARGET_PORT LWIP_LOCAL_PORT
|
||||
|
||||
#define LWIP_DEMO_TIMES 3
|
||||
#define LWIP_TASK_STACK_SIZE 4096
|
||||
#define LWIP_DEMO_TASK_PRIO 20
|
||||
|
||||
/* MAC address configuration. */
|
||||
#define configMAC_ADDR {0x02, 0x12, 0x13, 0x10, 0x15, 0x11}
|
||||
|
||||
/* USER CODE END 0 */
|
||||
#define SYS_MBOX_NULL -1
|
||||
#define SYS_SEM_NULL 0
|
||||
#define SYS_MRTEX_NULL SYS_SEM_NULL
|
||||
|
||||
typedef int32 sys_sem_t;
|
||||
typedef int32 sys_mutex_t;
|
||||
typedef int32 sys_mbox_t;
|
||||
typedef int32 sys_thread_t;
|
||||
typedef x_base sys_prot_t;
|
||||
|
||||
#define MS_PER_SYSTICK_F407 (1000 / TICK_PER_SECOND)
|
||||
|
||||
//debug rtos with IRQ
|
||||
//#define FSL_RTOS_XIUOS
|
||||
|
||||
extern char lwip_flag;
|
||||
|
||||
#define LWIP_INIT_FLAG (1 << 0)
|
||||
#define LWIP_PRINT_FLAG (1 << 1)
|
||||
|
||||
#define set_lwip_bit(__bit) lwip_flag |= (__bit)
|
||||
#define clr_lwip_bit(__bit) lwip_flag &= ~(__bit)
|
||||
#define chk_lwip_bit(__bit) ((lwip_flag & (__bit)) == (__bit))
|
||||
|
||||
extern char lwip_ipaddr[];
|
||||
extern char lwip_netmask[];
|
||||
extern char lwip_gwaddr[];
|
||||
extern struct netif gnetif;
|
||||
|
||||
void lwip_tcp_init(void);
|
||||
void lwip_config_net(char *ip, char *mask, char *gw);
|
||||
void lwip_config_tcp(char *ip, char *mask, char *gw);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,106 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file tcp_echo_socket_demo.c
|
||||
* @brief One UDP demo based on LwIP
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-29
|
||||
*/
|
||||
#include <xiuos.h>
|
||||
#include "board.h"
|
||||
#include "sys_arch.h"
|
||||
#include <lwip/sockets.h>
|
||||
#include "lwip/sys.h"
|
||||
#include "tcpecho_raw.h"
|
||||
|
||||
#define MSG_SIZE 128
|
||||
|
||||
// this is for test in shell, in fact, shell restrict the length of input string, which is less then 128
|
||||
char tcp_send_msg[MSG_SIZE] = {0};
|
||||
char tcp_target[] = {192, 168, 250, 252};
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
static void LwipTcpSendTask(void *arg)
|
||||
{
|
||||
lw_print("LwipTcpSendTask start.\n");
|
||||
|
||||
int fd = -1;
|
||||
fd = socket(AF_INET, SOCK_STREAM, 0);
|
||||
if (fd < 0)
|
||||
{
|
||||
lw_print("Socket error\n");
|
||||
return;
|
||||
}
|
||||
|
||||
struct sockaddr_in tcp_sock;
|
||||
tcp_sock.sin_family = AF_INET;
|
||||
tcp_sock.sin_port = htons(LWIP_TARGET_PORT);
|
||||
tcp_sock.sin_addr.s_addr = PP_HTONL(LWIP_MAKEU32(tcp_target[0], tcp_target[1], tcp_target[2], tcp_target[3]));
|
||||
memset(&(tcp_sock.sin_zero), 0, sizeof(tcp_sock.sin_zero));
|
||||
|
||||
if (connect(fd, (struct sockaddr *)&tcp_sock, sizeof(struct sockaddr)))
|
||||
{
|
||||
lw_print("Unable to connect\n");
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
lw_print("tcp connect success, start to send.\n");
|
||||
lw_print("\n\nTarget Port:%d\n\n", tcp_sock.sin_port);
|
||||
|
||||
sendto(fd, tcp_send_msg, strlen(tcp_send_msg), 0, (struct sockaddr*)&tcp_sock, sizeof(struct sockaddr));
|
||||
|
||||
lw_print("Send tcp msg: %s ", tcp_send_msg);
|
||||
|
||||
__exit:
|
||||
if (fd >= 0)
|
||||
closesocket(fd);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void LwipTcpSendTest(int argc, char *argv[])
|
||||
{
|
||||
memset(tcp_send_msg, 0, MSG_SIZE);
|
||||
if(argc >= 2)
|
||||
{
|
||||
strncpy(tcp_send_msg, argv[1], strlen(argv[1]));
|
||||
}
|
||||
else
|
||||
{
|
||||
strncpy(tcp_send_msg, "hello world", strlen("hello world"));
|
||||
}
|
||||
strcat(tcp_send_msg, "\r\n");
|
||||
|
||||
if(argc >= 3)
|
||||
{
|
||||
sscanf(argv[2], "%d.%d.%d.%d", &tcp_target[0], &tcp_target[1], &tcp_target[2], &tcp_target[3]);
|
||||
}
|
||||
|
||||
lwip_config_tcp(lwip_ipaddr, lwip_netmask, lwip_gwaddr);
|
||||
sys_thread_new("tcp send", LwipTcpSendTask, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO);
|
||||
}
|
||||
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
|
||||
TCPSend, LwipTcpSendTest, TCP Send message);
|
||||
|
||||
void LwipTcpRecvTest(void)
|
||||
{
|
||||
lwip_config_net(lwip_ipaddr, lwip_netmask, lwip_gwaddr);
|
||||
tcpecho_raw_init();
|
||||
}
|
||||
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0),
|
||||
TCPRecv, LwipTcpRecvTest, TCP Recv message);
|
||||
|
||||
|
|
@ -1,165 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file lwip_udp_demo.c
|
||||
* @brief One UDP demo based on LwIP
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-29
|
||||
*/
|
||||
#include <xiuos.h>
|
||||
#include "board.h"
|
||||
#include "sys_arch.h"
|
||||
#include "lwip/udp.h"
|
||||
#include <lwip/sockets.h>
|
||||
#include "lwip/sys.h"
|
||||
|
||||
#define UDP_TASK_STACK_SIZE 4096
|
||||
#define UDP_TASK_PRIO 15
|
||||
#define PBUF_SIZE 27
|
||||
|
||||
static struct udp_pcb *udpecho_raw_pcb;
|
||||
char udp_target[] = {192, 168, 250, 252};
|
||||
char hello_str[] = {"hello world\r\n"};
|
||||
char udp_send_msg[] = "\n\nThis one is UDP pkg. Congratulations on you.\n\n";
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
static void LwipUDPSendTask(void *arg)
|
||||
{
|
||||
int cnt = LWIP_DEMO_TIMES;
|
||||
|
||||
lw_print("udp_send_demo start.\n");
|
||||
|
||||
int socket_fd = -1;
|
||||
socket_fd = socket(AF_INET, SOCK_DGRAM, 0);
|
||||
if (socket_fd < 0)
|
||||
{
|
||||
lw_print("Socket error\n");
|
||||
return;
|
||||
}
|
||||
|
||||
struct sockaddr_in udp_sock;
|
||||
udp_sock.sin_family = AF_INET;
|
||||
udp_sock.sin_port = htons(LWIP_TARGET_PORT);
|
||||
udp_sock.sin_addr.s_addr = PP_HTONL(LWIP_MAKEU32(udp_target[0],udp_target[1],udp_target[2],udp_target[3]));
|
||||
memset(&(udp_sock.sin_zero), 0, sizeof(udp_sock.sin_zero));
|
||||
|
||||
if (connect(socket_fd, (struct sockaddr *)&udp_sock, sizeof(struct sockaddr)))
|
||||
{
|
||||
lw_print("Unable to connect\n");
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
lw_print("UDP connect success, start to send.\n");
|
||||
lw_print("\n\nTarget Port:%d\n\n", udp_sock.sin_port);
|
||||
|
||||
sendto(socket_fd, udp_send_msg, strlen(udp_send_msg), 0, (struct sockaddr*)&udp_sock, sizeof(struct sockaddr));
|
||||
lw_pr_info("Send UDP msg: %s ", udp_send_msg);
|
||||
|
||||
__exit:
|
||||
if (socket_fd >= 0)
|
||||
{
|
||||
closesocket(socket_fd);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void *LwipUdpSendTest(int argc, char *argv[])
|
||||
{
|
||||
int result = 0;
|
||||
sys_thread_t th_id;
|
||||
|
||||
memset(udp_send_msg, 0, sizeof(udp_send_msg));
|
||||
|
||||
if(argc == 1)
|
||||
{
|
||||
lw_print("lw: [%s] gw %d.%d.%d.%d\n", __func__, udp_target[0], udp_target[1], udp_target[2], udp_target[3]);
|
||||
strncpy(udp_send_msg, hello_str, strlen(hello_str));
|
||||
}
|
||||
else
|
||||
{
|
||||
strncpy(udp_send_msg, argv[1], strlen(argv[1]));
|
||||
strncat(udp_send_msg, "\r\n", 2);
|
||||
if(argc == 3)
|
||||
{
|
||||
sscanf(argv[2], "%d.%d.%d.%d", &udp_target[0], &udp_target[1], &udp_target[2], &udp_target[3]);
|
||||
}
|
||||
}
|
||||
lw_print("lw: [%s] gw %d.%d.%d.%d\n", __func__, udp_target[0], udp_target[1], udp_target[2], udp_target[3]);
|
||||
|
||||
lwip_config_tcp(lwip_ipaddr, lwip_netmask, lwip_gwaddr);
|
||||
sys_thread_new("udp socket send", LwipUDPSendTask, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO);
|
||||
}
|
||||
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
|
||||
UDPSend, LwipUdpSendTest, UDP send echo);
|
||||
|
||||
static void LwipUdpRecvTask(void *arg, struct udp_pcb *upcb, struct pbuf *p,
|
||||
const ip_addr_t *addr, u16_t port)
|
||||
{
|
||||
int udp_len;
|
||||
err_t err;
|
||||
struct pbuf* udp_buf;
|
||||
|
||||
LWIP_UNUSED_ARG(arg);
|
||||
|
||||
if (p == NULL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
udp_len = p->tot_len;
|
||||
lw_pr_info("Receive data :%dB\r\n", udp_len);
|
||||
|
||||
if(udp_len <= 80)
|
||||
{
|
||||
lw_pr_info("%.*s\r\n", udp_len, (char *)(p->payload));
|
||||
}
|
||||
|
||||
udp_buf = pbuf_alloc(PBUF_TRANSPORT, PBUF_SIZE, PBUF_RAM);
|
||||
|
||||
memset(udp_buf->payload, 0, PBUF_SIZE);
|
||||
|
||||
err = pbuf_take(udp_buf, "Client receive success!\r\n", 27);
|
||||
|
||||
/* send received packet back to sender */
|
||||
udp_sendto(upcb, udp_buf, addr, port);
|
||||
|
||||
/* free the pbuf */
|
||||
pbuf_free(p);
|
||||
pbuf_free(udp_buf);
|
||||
}
|
||||
|
||||
void LwipUdpRecvTest(void)
|
||||
{
|
||||
err_t err;
|
||||
|
||||
lwip_config_net(lwip_ipaddr, lwip_netmask, lwip_gwaddr);
|
||||
|
||||
udpecho_raw_pcb = udp_new_ip_type(IPADDR_TYPE_ANY);
|
||||
if (udpecho_raw_pcb == NULL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
err = udp_bind(udpecho_raw_pcb, IP_ANY_TYPE, LWIP_LOCAL_PORT);
|
||||
if (err == ERR_OK)
|
||||
{
|
||||
udp_recv(udpecho_raw_pcb, LwipUdpRecvTask, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0),
|
||||
UDPRecv, LwipUdpRecvTest, UDP server echo);
|
||||
|
||||
|
|
@ -1,276 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file bus.h
|
||||
* @brief define bus driver framework function and common API
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-24
|
||||
*/
|
||||
|
||||
#ifndef BUS_H
|
||||
#define BUS_H
|
||||
|
||||
#include <xiuos.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define OPE_INT 0x0000
|
||||
#define OPE_CFG 0x0001
|
||||
|
||||
#define OPER_WDT_SET_TIMEOUT 0x0002
|
||||
#define OPER_WDT_KEEPALIVE 0x0003
|
||||
|
||||
typedef struct Bus *BusType;
|
||||
typedef struct HardwareDev *HardwareDevType;
|
||||
typedef struct Driver *DriverType;
|
||||
|
||||
/* need to add new bus type in ../tool/shell/letter-shell/cmd.c, ensure ShowBus cmd supported*/
|
||||
enum BusType_e
|
||||
{
|
||||
TYPE_I2C_BUS = 0,
|
||||
TYPE_SPI_BUS,
|
||||
TYPE_HWTIMER_BUS,
|
||||
TYPE_USB_BUS,
|
||||
TYPE_CAN_BUS,
|
||||
TYPE_WDT_BUS,
|
||||
TYPE_SDIO_BUS,
|
||||
TYPE_TOUCH_BUS,
|
||||
TYPE_LCD_BUS,
|
||||
TYPE_PIN_BUS,
|
||||
TYPE_RTC_BUS,
|
||||
TYPE_SERIAL_BUS,
|
||||
TYPE_ADC_BUS,
|
||||
TYPE_DAC_BUS,
|
||||
TYPE_PLC_BUS,
|
||||
TYPE_BUS_END,
|
||||
};
|
||||
|
||||
enum BusState
|
||||
{
|
||||
BUS_INIT = 0,
|
||||
BUS_INSTALL,
|
||||
BUS_UNINSTALL,
|
||||
};
|
||||
|
||||
enum DevType
|
||||
{
|
||||
TYPE_I2C_DEV = 0,
|
||||
TYPE_SPI_DEV,
|
||||
TYPE_HWTIMER_DEV,
|
||||
TYPE_USB_DEV,
|
||||
TYPE_CAN_DEV,
|
||||
TYPE_WDT_DEV,
|
||||
TYPE_SDIO_DEV,
|
||||
TYPE_TOUCH_DEV,
|
||||
TYPE_LCD_DEV,
|
||||
TYPE_PIN_DEV,
|
||||
TYPE_RTC_DEV,
|
||||
TYPE_SERIAL_DEV,
|
||||
TYPE_ADC_DEV,
|
||||
TYPE_DAC_DEV,
|
||||
TYPE_PLC_DEV,
|
||||
TYPE_DEV_END,
|
||||
};
|
||||
|
||||
enum DevState
|
||||
{
|
||||
DEV_INIT = 0,
|
||||
DEV_INSTALL,
|
||||
DEV_UNINSTALL,
|
||||
};
|
||||
|
||||
enum DriverType_e
|
||||
{
|
||||
TYPE_I2C_DRV = 0,
|
||||
TYPE_SPI_DRV,
|
||||
TYPE_HWTIMER_DRV,
|
||||
TYPE_USB_DRV,
|
||||
TYPE_CAN_DRV,
|
||||
TYPE_WDT_DRV,
|
||||
TYPE_SDIO_DRV,
|
||||
TYPE_TOUCH_DRV,
|
||||
TYPE_LCD_DRV,
|
||||
TYPE_PIN_DRV,
|
||||
TYPE_RTC_DRV,
|
||||
TYPE_SERIAL_DRV,
|
||||
TYPE_ADC_DRV,
|
||||
TYPE_DAC_DRV,
|
||||
TYPE_PLC_DRV,
|
||||
TYPE_DRV_END,
|
||||
};
|
||||
|
||||
enum DriverState
|
||||
{
|
||||
DRV_INIT = 0,
|
||||
DRV_INSTALL,
|
||||
DRV_UNINSTALL,
|
||||
};
|
||||
|
||||
struct BusConfigureInfo
|
||||
{
|
||||
int configure_cmd;
|
||||
void *private_data;
|
||||
};
|
||||
|
||||
struct BusBlockReadParam
|
||||
{
|
||||
x_OffPos pos;
|
||||
void* buffer;
|
||||
x_size_t size;
|
||||
x_size_t read_length;
|
||||
};
|
||||
|
||||
struct BusBlockWriteParam
|
||||
{
|
||||
x_OffPos pos;
|
||||
const void* buffer;
|
||||
x_size_t size;
|
||||
};
|
||||
|
||||
struct HalDevBlockParam
|
||||
{
|
||||
uint32 cmd;
|
||||
struct DeviceBlockArrange dev_block;
|
||||
struct DeviceBlockAddr *dev_addr;
|
||||
};
|
||||
|
||||
struct HalDevDone
|
||||
{
|
||||
uint32 (*open) (void *dev);
|
||||
uint32 (*close) (void *dev);
|
||||
uint32 (*write) (void *dev, struct BusBlockWriteParam *write_param);
|
||||
uint32 (*read) (void *dev, struct BusBlockReadParam *read_param);
|
||||
};
|
||||
|
||||
struct HardwareDev
|
||||
{
|
||||
int8 dev_name[NAME_NUM_MAX];
|
||||
enum DevType dev_type;
|
||||
enum DevState dev_state;
|
||||
|
||||
const struct HalDevDone *dev_done;
|
||||
|
||||
int (*dev_recv_callback) (void *dev, x_size_t length);
|
||||
int (*dev_block_control) (struct HardwareDev *dev, struct HalDevBlockParam *block_param);
|
||||
|
||||
struct Bus *owner_bus;
|
||||
void *private_data;
|
||||
|
||||
int32 dev_sem;
|
||||
|
||||
DoubleLinklistType dev_link;
|
||||
};
|
||||
|
||||
struct Driver
|
||||
{
|
||||
int8 drv_name[NAME_NUM_MAX];
|
||||
enum DriverType_e driver_type;
|
||||
enum DriverState driver_state;
|
||||
|
||||
uint32 (*configure)(void *drv, struct BusConfigureInfo *configure_info);
|
||||
|
||||
struct Bus *owner_bus;
|
||||
void *private_data;
|
||||
|
||||
DoubleLinklistType driver_link;
|
||||
};
|
||||
|
||||
struct Bus
|
||||
{
|
||||
int8 bus_name[NAME_NUM_MAX];
|
||||
enum BusType_e bus_type;
|
||||
enum BusState bus_state;
|
||||
|
||||
int32 (*match)(struct Driver *driver, struct HardwareDev *device);
|
||||
|
||||
int bus_lock;
|
||||
|
||||
struct HardwareDev *owner_haldev;
|
||||
struct Driver *owner_driver;
|
||||
|
||||
void *private_data;
|
||||
|
||||
/*manage the drv of the bus*/
|
||||
uint8 driver_cnt;
|
||||
uint8 bus_drvlink_flag;
|
||||
DoubleLinklistType bus_drvlink;
|
||||
|
||||
/*manage the dev of the bus*/
|
||||
uint8 haldev_cnt;
|
||||
uint8 bus_devlink_flag;
|
||||
DoubleLinklistType bus_devlink;
|
||||
|
||||
uint8 bus_cnt;
|
||||
uint8 bus_link_flag;
|
||||
DoubleLinklistType bus_link;
|
||||
};
|
||||
|
||||
/*Register the BUS,manage with the double linklist*/
|
||||
int BusRegister(struct Bus *bus);
|
||||
|
||||
/*Release the BUS framework*/
|
||||
int BusRelease(struct Bus *bus);
|
||||
|
||||
/*Unregister a certain kind of BUS*/
|
||||
int BusUnregister(struct Bus *bus);
|
||||
|
||||
/*Register the driver to the bus*/
|
||||
int DriverRegisterToBus(struct Bus *bus, struct Driver *driver);
|
||||
|
||||
/*Register the device to the bus*/
|
||||
int DeviceRegisterToBus(struct Bus *bus, struct HardwareDev *device);
|
||||
|
||||
/*Delete the driver from the bus*/
|
||||
int DriverDeleteFromBus(struct Bus *bus, struct Driver *driver);
|
||||
|
||||
/*Delete the device from the bus*/
|
||||
int DeviceDeleteFromBus(struct Bus *bus, struct HardwareDev *device);
|
||||
|
||||
/*Find the bus with bus name*/
|
||||
BusType BusFind(const char *bus_name);
|
||||
|
||||
/*Find the driver of cetain bus*/
|
||||
DriverType BusFindDriver(struct Bus *bus, const char *driver_name);
|
||||
|
||||
/*Find the device of certain bus*/
|
||||
HardwareDevType BusFindDevice(struct Bus *bus, const char *device_name);
|
||||
|
||||
/*Dev receive data callback function*/
|
||||
uint32 BusDevRecvCallback(struct HardwareDev *dev, int (*dev_recv_callback) (void *dev, x_size_t length));
|
||||
|
||||
/*Open the device of the bus*/
|
||||
uint32 BusDevOpen(struct HardwareDev *dev);
|
||||
|
||||
/*Close the device of the bus*/
|
||||
uint32 BusDevClose(struct HardwareDev *dev);
|
||||
|
||||
/*Write data to the device*/
|
||||
uint32 BusDevWriteData(struct HardwareDev *dev, struct BusBlockWriteParam *write_param);
|
||||
|
||||
/*Read data from the device*/
|
||||
uint32 BusDevReadData(struct HardwareDev *dev, struct BusBlockReadParam *read_param);
|
||||
|
||||
/*Configure the driver of the bus*/
|
||||
uint32 BusDrvConfigure(struct Driver *drv, struct BusConfigureInfo *configure_info);
|
||||
|
||||
/*Obtain the bus using a certain dev*/
|
||||
int DeviceObtainBus(struct Bus *bus, struct HardwareDev *dev, const char *drv_name, struct BusConfigureInfo *configure_info);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,551 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
#include <xiuos.h>
|
||||
#include "shell.h"
|
||||
#include <bus.h>
|
||||
#include <xs_ktask_stat.h>
|
||||
#include <string.h>
|
||||
|
||||
long Hello(void)
|
||||
{
|
||||
KPrintf("Hello World!\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, Hello, Hello, show Hello World information);
|
||||
|
||||
extern void ShowBanner(void);
|
||||
long ShowVersion(void)
|
||||
{
|
||||
ShowBanner();
|
||||
|
||||
return 0;
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowVersion, ShowVersion, show XiUOS version information);
|
||||
|
||||
static __inline void PrintSpace(int len)
|
||||
{
|
||||
while (len--) KPrintf(" ");
|
||||
}
|
||||
|
||||
extern DoubleLinklistType xiaoshan_task_head;
|
||||
|
||||
#ifdef KERNEL_SEMAPHORE
|
||||
extern DoubleLinklistType k_sem_list;
|
||||
#endif
|
||||
|
||||
#ifdef KERNEL_MUTEX
|
||||
extern DoubleLinklistType k_mutex_list;
|
||||
#endif
|
||||
|
||||
#ifdef KERNEL_EVENT
|
||||
extern DoubleLinklistType k_event_list;
|
||||
#endif
|
||||
|
||||
#ifdef KERNEL_MESSAGEQUEUE
|
||||
extern DoubleLinklistType k_mq_list;
|
||||
#endif
|
||||
|
||||
#ifdef KERNEL_SOFTTIMER
|
||||
extern DoubleLinklistType k_timer_list;
|
||||
#endif
|
||||
|
||||
#ifdef KERNEL_MEMBLOCK
|
||||
extern DoubleLinklistType xiaoshan_memgather_head;
|
||||
#endif
|
||||
|
||||
extern DoubleLinklistType bus_linklist;
|
||||
|
||||
long ShowTask(void)
|
||||
{
|
||||
int k = 0;
|
||||
x_ubase lock = 0;
|
||||
uint8 stat = 0;
|
||||
uint8 *ptr = NONE;
|
||||
const char *item_title = "TASK";
|
||||
struct TaskDescriptor *task = NONE;
|
||||
DoubleLinklistType *nodelink = NONE;
|
||||
|
||||
KPrintf("*************************************************************************************************\n");
|
||||
#ifdef ARCH_SMP
|
||||
for(k = 0;k < CPU_NUMBERS; k++){
|
||||
KPrintf(" CPU[%d] CURRENT RUNNING TASK[ %s ] PRI[ %d ] \n",k,Assign.smp_os_running_task[k]->task_base_info.name,Assign.smp_os_running_task[k]->task_dync_sched_member.cur_prio);
|
||||
}
|
||||
#else
|
||||
KPrintf(" CURRENT RUNNING TASK[ %s ] PRI[ %d ]\n",Assign.os_running_task->task_base_info.name,Assign.os_running_task->task_dync_sched_member.cur_prio);
|
||||
#endif
|
||||
|
||||
#ifdef SCHED_POLICY_RR_REMAINSLICE
|
||||
KPrintf(" SCHED POLICY [ RR_REMAINSLICE ]\n");
|
||||
#endif
|
||||
#ifdef SCHED_POLICY_RR
|
||||
KPrintf(" SCHED POLICY [ RR ]\n");
|
||||
#endif
|
||||
#ifdef SCHED_POLICY_FIFO
|
||||
KPrintf(" SCHED POLICY [ FIFO ]\n");
|
||||
#endif
|
||||
|
||||
KPrintf("*************************************************************************************************\n");
|
||||
#ifndef SCHED_POLICY_FIFO
|
||||
#ifdef ARCH_SMP
|
||||
KPrintf(" STAT ID %-*.s PRI CORE STACK_DEPTH USED LEFT_TICKS ERROR_STAT\n", NAME_NUM_MAX, item_title);
|
||||
#else
|
||||
KPrintf(" STAT ID %-*.s PRI STACK_DEPTH USED LEFT_TICKS ERROR_STAT\n", NAME_NUM_MAX, item_title);
|
||||
#endif
|
||||
#else
|
||||
#ifdef ARCH_SMP
|
||||
KPrintf(" STAT ID %-*.s PRI CORE STACK_DEPTH USED ERROR_STAT\n", NAME_NUM_MAX, item_title);
|
||||
#else
|
||||
KPrintf(" STAT ID %-*.s PRI STACK_DEPTH USED ERROR_STAT\n", NAME_NUM_MAX, item_title);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
lock = CriticalAreaLock();
|
||||
DOUBLE_LINKLIST_FOR_EACH(nodelink, &xiaoshan_task_head) {
|
||||
task = CONTAINER_OF(nodelink, struct TaskDescriptor, link);
|
||||
if(NONE != task) {
|
||||
stat = KTaskStatGet(task);
|
||||
if (stat == KTASK_READY) KPrintf(" READY ");
|
||||
else if (stat == KTASK_SUSPEND) KPrintf(" SUSPEND");
|
||||
else if (stat == KTASK_INIT) KPrintf(" INIT ");
|
||||
else if (stat == KTASK_CLOSE) KPrintf(" CLOSE ");
|
||||
else if (stat == KTASK_RUNNING) KPrintf(" RUNNING");
|
||||
|
||||
#ifdef ARCH_SMP
|
||||
KPrintf("%3d %-*.*s %3d %3d ", task->id.id,NAME_NUM_MAX, NAME_NUM_MAX, task->task_base_info.name, task->task_dync_sched_member.cur_prio,task->task_smp_info.runing_coreid );
|
||||
|
||||
#else
|
||||
KPrintf("%3d %-*.*s %3d ", task->id.id,NAME_NUM_MAX, NAME_NUM_MAX, task->task_base_info.name, task->task_dync_sched_member.cur_prio);
|
||||
#endif
|
||||
|
||||
#ifndef SCHED_POLICY_FIFO
|
||||
ptr = (uint8 *)task->task_base_info.stack_start;
|
||||
while (*ptr == '#')ptr ++;
|
||||
|
||||
KPrintf(" %-10d%d%% %-10d%04d\n",
|
||||
task->task_base_info.stack_depth,
|
||||
(task->task_base_info.stack_depth - ((x_ubase) ptr - (x_ubase) task->task_base_info.stack_start)) * 100 / task->task_base_info.stack_depth,
|
||||
task->task_dync_sched_member.rest_timeslice, task->exstatus);
|
||||
|
||||
#else
|
||||
ptr = (uint8 *)task->task_base_info.stack_start;
|
||||
while (*ptr == '#')ptr ++;
|
||||
|
||||
KPrintf(" %-10d%d%% %04d\n",
|
||||
task->task_base_info.stack_depth,
|
||||
(task->task_base_info.stack_depth - ((x_ubase) ptr - (x_ubase) task->task_base_info.stack_start)) * 100 / task->task_base_info.stack_depth, task->exstatus);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
}
|
||||
CriticalAreaUnLock(lock);
|
||||
|
||||
KPrintf("*************************************************************************************************\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowTask, ShowTask, show task information in XiUOS);
|
||||
|
||||
static void GetSuspendedTask(struct SysDoubleLinklistNode *list)
|
||||
{
|
||||
struct TaskDescriptor *task = NONE;
|
||||
DoubleLinklistType *nodelink = NONE;
|
||||
DOUBLE_LINKLIST_FOR_EACH(nodelink, list){
|
||||
task = CONTAINER_OF(nodelink, struct TaskDescriptor, task_dync_sched_member.sched_link);
|
||||
if(NONE != task) {
|
||||
KPrintf("%s | ", task->task_base_info.name);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef KERNEL_SEMAPHORE
|
||||
|
||||
long ShowSem(void)
|
||||
{
|
||||
x_base lock = 0;
|
||||
struct Semaphore *sem = NONE;
|
||||
DoubleLinklistType *nodelink = NONE;
|
||||
|
||||
KPrintf("******************************************************************\n");
|
||||
KPrintf(" SEM_ID VALUE SUSPEND_TASK\n");
|
||||
|
||||
lock = CriticalAreaLock();
|
||||
DOUBLE_LINKLIST_FOR_EACH(nodelink, &k_sem_list) {
|
||||
sem = CONTAINER_OF(nodelink, struct Semaphore, link);
|
||||
if(NONE != sem) {
|
||||
if (!IsDoubleLinkListEmpty(&sem->pend_list)) {
|
||||
KPrintf(" %-8d%-8d :", sem->id.id, sem->value);
|
||||
GetSuspendedTask(&(sem->pend_list));
|
||||
KPrintf("\n");
|
||||
} else {
|
||||
KPrintf(" %-8d%-8d NONE\n", sem->id.id, sem->value);
|
||||
}
|
||||
}
|
||||
}
|
||||
CriticalAreaUnLock(lock);
|
||||
KPrintf("******************************************************************\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowSem, ShowSem, show sem information in XiUOS);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef KERNEL_EVENT
|
||||
|
||||
long ShowEvent(void)
|
||||
{
|
||||
x_base lock = 0;
|
||||
struct Event *event = NONE;
|
||||
DoubleLinklistType *nodelink = NONE;
|
||||
|
||||
KPrintf("******************************************************************\n");
|
||||
KPrintf(" EVENT_ID OPTIONS EVENTS SUSPEND_TASK\n");
|
||||
|
||||
lock = CriticalAreaLock();
|
||||
DOUBLE_LINKLIST_FOR_EACH(nodelink, &k_event_list) {
|
||||
event = CONTAINER_OF(nodelink, struct Event, link);
|
||||
if(NONE != event) {
|
||||
if (!IsDoubleLinkListEmpty(&event->pend_list)) {
|
||||
KPrintf(" %-8d0x%-8x0x%-12x", event->id.id, event->options, event->events);
|
||||
GetSuspendedTask(&(event->pend_list));
|
||||
KPrintf("\n");
|
||||
} else {
|
||||
KPrintf(" %-8d0x%-8x0x%-12x NONE\n", event->id.id, event->options, event->events);
|
||||
}
|
||||
}
|
||||
}
|
||||
CriticalAreaUnLock(lock);
|
||||
KPrintf("******************************************************************\n");
|
||||
return 0;
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowEvent, ShowEvent, show event information in XiUOS);
|
||||
|
||||
#endif
|
||||
#ifdef KERNEL_MUTEX
|
||||
long ShowMutex(void)
|
||||
{
|
||||
x_base lock = 0;
|
||||
struct Mutex *mutex = NONE;
|
||||
DoubleLinklistType *nodelink = NONE;
|
||||
|
||||
KPrintf("******************************************************************\n");
|
||||
KPrintf("MUTEX_ID HOLDER RECRUSIVE_CNT SUSPEND_TASK\n");
|
||||
|
||||
lock = CriticalAreaLock();
|
||||
DOUBLE_LINKLIST_FOR_EACH(nodelink, &k_mutex_list) {
|
||||
mutex = CONTAINER_OF(nodelink, struct Mutex, link);
|
||||
if(NONE != mutex) {
|
||||
if (!IsDoubleLinkListEmpty(&mutex->pend_list)) {
|
||||
KPrintf(" %-8d%-10s%-12d", mutex->id.id, (mutex->holder == NONE ?"NONE":(mutex->holder->task_base_info.name)), mutex->recursive_cnt);
|
||||
GetSuspendedTask(&(mutex->pend_list));
|
||||
KPrintf("\n");
|
||||
} else {
|
||||
KPrintf(" %-8d%-10s%-12d NONE\n", mutex->id.id, (mutex->holder == NONE ?"NONE":(mutex->holder->task_base_info.name)), mutex->recursive_cnt);
|
||||
}
|
||||
}
|
||||
}
|
||||
CriticalAreaUnLock(lock);
|
||||
KPrintf("******************************************************************\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowMutex, ShowMutex, show mutex information in XiUOS);
|
||||
#endif
|
||||
|
||||
#ifdef KERNEL_MESSAGEQUEUE
|
||||
long ShowMsgQueue(void)
|
||||
{
|
||||
x_base lock = 0;
|
||||
struct MsgQueue *msgq = NONE;
|
||||
DoubleLinklistType *nodelink = NONE;
|
||||
|
||||
KPrintf("****************************************************************************************\n");
|
||||
KPrintf(" MSG_ID NUM_MSGS EACH_LEN MAX_MSGS %-32s%s\n","SEND_SUSPEND_TASK","RECV_SUSPEND_TASK");
|
||||
|
||||
lock = CriticalAreaLock();
|
||||
DOUBLE_LINKLIST_FOR_EACH(nodelink, &k_mq_list) {
|
||||
msgq = CONTAINER_OF(nodelink, struct MsgQueue, link);
|
||||
if(NONE != msgq) {
|
||||
KPrintf(" %-8d%-8d%-8d%-8d", msgq->id.id, msgq->num_msgs, msgq->each_len,msgq->max_msgs);
|
||||
if (!IsDoubleLinkListEmpty(&msgq->send_pend_list)) {
|
||||
GetSuspendedTask(&(msgq->send_pend_list));
|
||||
} else {
|
||||
PrintSpace(32);
|
||||
}
|
||||
|
||||
if (!IsDoubleLinkListEmpty(&msgq->recv_pend_list)){
|
||||
GetSuspendedTask(&(msgq->recv_pend_list));
|
||||
}
|
||||
|
||||
KPrintf("\n");
|
||||
}
|
||||
}
|
||||
CriticalAreaUnLock(lock);
|
||||
KPrintf("****************************************************************************************\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowMsgQueue, ShowMsgQueue, show msg queue information in XiUOS);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef KERNEL_MEMBLOCK
|
||||
long ShowGatherMem(void)
|
||||
{
|
||||
x_base lock = 0;
|
||||
struct MemGather *mg = NONE;
|
||||
DoubleLinklistType *nodelink = NONE;
|
||||
|
||||
KPrintf("****************************************************************************************\n");
|
||||
KPrintf("GATHERMEM BLOCK TOTAL FREE SUSPEND_TASK\n");
|
||||
|
||||
lock = CriticalAreaLock();
|
||||
DOUBLE_LINKLIST_FOR_EACH(nodelink, &xiaoshan_memgather_head) {
|
||||
mg = CONTAINER_OF(nodelink, struct MemGather, m_link);
|
||||
if(NONE != mg) {
|
||||
if (!IsDoubleLinkListEmpty(&mg->wait_task)) {
|
||||
KPrintf(" %-8s%-6d%-6d%-6d :",
|
||||
mg->m_name,
|
||||
mg->one_block_size,
|
||||
mg->block_total_number,
|
||||
mg->block_free_number);
|
||||
GetSuspendedTask(&(mg->wait_task));
|
||||
KPrintf("\n");
|
||||
} else {
|
||||
KPrintf(" %-8s%-6d%-6d%-6d NONE\n",
|
||||
mg->m_name,
|
||||
mg->one_block_size,
|
||||
mg->block_total_number,
|
||||
mg->block_free_number);
|
||||
}
|
||||
}
|
||||
}
|
||||
CriticalAreaUnLock(lock);
|
||||
KPrintf("****************************************************************************************\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowGatherMem, ShowGatherMem, show mem block information in XiUOS);
|
||||
|
||||
#endif
|
||||
#ifdef KERNEL_SOFTTIMER
|
||||
long ShowTimer(void)
|
||||
{
|
||||
x_base lock = 0;
|
||||
struct Timer *timer = NONE;
|
||||
DoubleLinklistType *nodelink = NONE;
|
||||
|
||||
KPrintf("****************************************************************************************\n");
|
||||
KPrintf(" TIMER_ID NAME STATUS PERIODIC DEADLINE\n");
|
||||
|
||||
lock = CriticalAreaLock();
|
||||
DOUBLE_LINKLIST_FOR_EACH(nodelink, &k_timer_list) {
|
||||
timer = CONTAINER_OF(nodelink, struct Timer, link);
|
||||
if(NONE != timer) {
|
||||
KPrintf(" %-8d%-8s%-10s%-10d%d\n", timer->id_node.id, timer->name, (timer->active_status == TIMER_ACTIVE_TRUE ? "active" : "unactive"),timer->origin_timeslice,timer->deadline_timeslice);
|
||||
}
|
||||
}
|
||||
CriticalAreaUnLock(lock);
|
||||
KPrintf("****************************************************************************************\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowTimer, ShowTimer, show timer information in XiUOS);
|
||||
#endif
|
||||
|
||||
static char *const bus_type_str[] =
|
||||
{
|
||||
"I2C_BUS",
|
||||
"SPI_BUS",
|
||||
"HWT_BUS",
|
||||
"USB_BUS",
|
||||
"CAN_BUS",
|
||||
"WDT_BUS",
|
||||
"SDIO_BUS",
|
||||
"TOUCH_BUS",
|
||||
"LCD_BUS",
|
||||
"PIN_BUS",
|
||||
"RTC_BUS",
|
||||
"SERIAL_BUS",
|
||||
"ADC_BUS",
|
||||
"DAC_BUS",
|
||||
"PLC_BUS",
|
||||
"Unknown"
|
||||
};
|
||||
|
||||
static DriverType ShowBusFindDriver(struct Bus *bus)
|
||||
{
|
||||
struct Driver *driver = NONE;
|
||||
|
||||
DoubleLinklistType *node = NONE;
|
||||
DoubleLinklistType *head = &bus->bus_drvlink;
|
||||
|
||||
for(node = head->node_next; node != head; node = node->node_next) {
|
||||
driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link);
|
||||
return driver;
|
||||
}
|
||||
return NONE;
|
||||
}
|
||||
|
||||
long ShowBus(void)
|
||||
{
|
||||
BusType bus;
|
||||
DriverType driver;
|
||||
HardwareDevType device;
|
||||
|
||||
DoubleLinklistType *bus_node = NONE;
|
||||
DoubleLinklistType *bus_head = &bus_linklist;
|
||||
|
||||
int i = 0;
|
||||
int dev_cnt, maxlen;
|
||||
const char *item_type = "bus_type";
|
||||
const char *item_name_0 = "bus_name";
|
||||
const char *item_name_1 = "drv_name";
|
||||
const char *item_name_2 = "dev_name";
|
||||
const char *item_cnt = "cnt";
|
||||
|
||||
KPrintf(" %-15s%-15s%-15s%-15s%-20s\n", item_type, item_name_0, item_name_1, item_name_2, item_cnt);
|
||||
maxlen = 65;
|
||||
while (i < maxlen) {
|
||||
i++;
|
||||
if (maxlen == i) {
|
||||
KPrintf("-\n");
|
||||
} else {
|
||||
KPrintf("-");
|
||||
}
|
||||
}
|
||||
|
||||
bus_node = bus_head->node_next;
|
||||
|
||||
do
|
||||
{
|
||||
bus = SYS_DOUBLE_LINKLIST_ENTRY(bus_node, struct Bus, bus_link);
|
||||
if (bus) {
|
||||
KPrintf("%s", " ");
|
||||
KPrintf("%-15s%-15s",
|
||||
bus_type_str[bus->bus_type],
|
||||
bus->bus_name);
|
||||
|
||||
driver = ShowBusFindDriver(bus);
|
||||
|
||||
if (driver) {
|
||||
KPrintf("%-15s", driver->drv_name);
|
||||
} else {
|
||||
KPrintf("%-15s", "nil");
|
||||
}
|
||||
|
||||
if (bus->haldev_cnt) {
|
||||
DoubleLinklistType *dev_node = NONE;
|
||||
DoubleLinklistType *dev_head = &bus->bus_devlink;
|
||||
|
||||
dev_node = dev_head->node_next;
|
||||
dev_cnt = 1;
|
||||
while (dev_node != dev_head) {
|
||||
device = SYS_DOUBLE_LINKLIST_ENTRY(dev_node, struct HardwareDev, dev_link);
|
||||
|
||||
if (1 == dev_cnt) {
|
||||
if (device) {
|
||||
KPrintf("%-16s%-4d\n", device->dev_name, dev_cnt);
|
||||
} else {
|
||||
KPrintf("%-16s%-4d\n", "nil", dev_cnt);
|
||||
}
|
||||
} else {
|
||||
KPrintf("%46s", " ");
|
||||
if (device) {
|
||||
KPrintf("%-16s%-4d\n", device->dev_name, dev_cnt);
|
||||
} else {
|
||||
KPrintf("%-16s%-4d\n", "nil", dev_cnt);
|
||||
}
|
||||
}
|
||||
dev_cnt++;
|
||||
dev_node = dev_node->node_next;
|
||||
}
|
||||
} else {
|
||||
KPrintf("\n");
|
||||
}
|
||||
}
|
||||
bus_node = bus_node->node_next;
|
||||
}
|
||||
while (bus_node != bus_head);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(1)|SHELL_CMD_DISABLE_RETURN,ShowBus, ShowBus, show bus information in XiUOS);
|
||||
|
||||
#ifdef RESOURCES_RTC
|
||||
#include "bus_rtc.h"
|
||||
static void SetDateAndTime(char argc, char **argv)
|
||||
{
|
||||
if (1 == argc) {
|
||||
time_t now;
|
||||
|
||||
now = time(NONE);
|
||||
KPrintf("%s", ctime(&now));
|
||||
} else if (argc >= 7) {
|
||||
struct RtcSetParam rtc_set_param;
|
||||
|
||||
rtc_set_param.rtc_set_cmd = OPER_RTC_SET_TIME;
|
||||
uint16 year;
|
||||
uint8 month, day, hour, min, sec;
|
||||
year = atoi(argv[1]);
|
||||
month = atoi(argv[2]);
|
||||
day = atoi(argv[3]);
|
||||
hour = atoi(argv[4]);
|
||||
min = atoi(argv[5]);
|
||||
sec = atoi(argv[6]);
|
||||
if (year > 2099 || year < 2000) {
|
||||
KPrintf("year is out of range [2000-2099]\n");
|
||||
return;
|
||||
}
|
||||
if (month == 0 || month > 12) {
|
||||
KPrintf("month is out of range [1-12]\n");
|
||||
return;
|
||||
}
|
||||
if (day == 0 || day > 31) {
|
||||
KPrintf("day is out of range [1-31]\n");
|
||||
return;
|
||||
}
|
||||
if (hour > 23) {
|
||||
KPrintf("hour is out of range [0-23]\n");
|
||||
return;
|
||||
}
|
||||
if (min > 59) {
|
||||
KPrintf("minute is out of range [0-59]\n");
|
||||
return;
|
||||
}
|
||||
if (sec > 59) {
|
||||
KPrintf("second is out of range [0-59]\n");
|
||||
return;
|
||||
}
|
||||
|
||||
rtc_set_param.date_param.year = year;
|
||||
rtc_set_param.date_param.month = month;
|
||||
rtc_set_param.date_param.day = day;
|
||||
rtc_set_param.time_param.hour = hour;
|
||||
rtc_set_param.time_param.minute = min;
|
||||
rtc_set_param.time_param.second = sec;
|
||||
|
||||
RtcDrvSetFunction(RTC_DRV_NAME, &rtc_set_param);
|
||||
} else {
|
||||
KPrintf("only support input [year month day hour min sec]\n");
|
||||
}
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(9), SetDateAndTime, SetDateAndTime, set date and time using rtc function);
|
||||
|
||||
#endif
|
||||
|
|
@ -5,19 +5,6 @@
|
|||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.h
|
||||
* @brief define imxrt1052-board init configure and start-up function
|
||||
|
|
|
|||
|
|
@ -11,6 +11,50 @@ menuconfig BSP_USING_LWIP
|
|||
default n
|
||||
select RESOURCES_LWIP
|
||||
|
||||
menuconfig BSP_USING_GPIO
|
||||
bool "Using GPIO device "
|
||||
default y
|
||||
select RESOURCES_PIN
|
||||
|
||||
if BSP_USING_GPIO
|
||||
source "$BSP_DIR/third_party_driver/gpio/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C
|
||||
bool "Using I2C device"
|
||||
default y
|
||||
select RESOURCES_I2C
|
||||
|
||||
if BSP_USING_I2C
|
||||
source "$BSP_DIR/third_party_driver/i2c/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Using ADC device"
|
||||
default y
|
||||
select RESOURCES_ADC
|
||||
|
||||
if BSP_USING_ADC
|
||||
source "$BSP_DIR/third_party_driver/adc/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SPI
|
||||
bool "Using SPI device"
|
||||
default y
|
||||
select RESOURCES_SPI
|
||||
|
||||
if BSP_USING_SPI
|
||||
source "$BSP_DIR/third_party_driver/spi/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_RTC
|
||||
bool "Using RTC device"
|
||||
default n
|
||||
select RESOURCES_RTC
|
||||
if BSP_USING_RTC
|
||||
source "$BSP_DIR/third_party_driver/rtc/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SEMC
|
||||
bool "Using SEMC device"
|
||||
default n
|
||||
|
|
|
|||
|
|
@ -8,10 +8,27 @@ ifeq ($(CONFIG_BSP_USING_LWIP),y)
|
|||
SRC_DIR += ethernet
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_I2C),y)
|
||||
SRC_DIR += i2c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_ADC),y)
|
||||
SRC_DIR += adc
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_SPI),y)
|
||||
SRC_DIR += spi
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_SEMC),y)
|
||||
SRC_DIR += semc
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_RTC),y)
|
||||
SRC_DIR += rtc
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_SDIO),y)
|
||||
SRC_DIR += sdio
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -749,6 +749,115 @@ BOARD_InitPins:
|
|||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
|
||||
void BOARD_InitSPIPins ( void )
|
||||
{
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK, /* GPIO_AD_B0_00 is configured as LPSPI3_SCK */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, /* GPIO_AD_B0_01 is configured as LPSPI3_SDO */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, /* GPIO_AD_B0_02 is configured as LPSPI3_SDI */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0, /* GPIO_AD_B0_03 is configured as LPSPI3_PCS0 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_SD_B0_00 is configured as LPSPI1_SCK */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0, /* GPIO_SD_B0_01 is configured as LPSPI1_PCS0 */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO, /* GPIO_SD_B0_02 is configured as LPSPI1_SDO */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI, /* GPIO_SD_B0_03 is configured as LPSPI1_SDI */
|
||||
0U ); /* Software Input On Field: Input Path is determined by functionality */
|
||||
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_AD_B0_00 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, /* GPIO_AD_B0_01 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, /* GPIO_AD_B0_02 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0, /* GPIO_AD_B0_03 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_SD_B0_00 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0, /* GPIO_SD_B0_01 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO, /* GPIO_SD_B0_02 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI, /* GPIO_SD_B0_03 PAD functional properties : */
|
||||
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
}
|
||||
void BOARD_InitPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
|
||||
|
||||
|
|
@ -964,6 +1073,36 @@ void BOARD_InitPins(void) {
|
|||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
}
|
||||
|
||||
void BOARD_InitI2C1Pins ( void )
|
||||
{
|
||||
CLOCK_EnableClock ( kCLOCK_Iomuxc ); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */
|
||||
1U ); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */
|
||||
IOMUXC_SetPinMux (
|
||||
IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */
|
||||
1U ); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 PAD functional properties : */
|
||||
0xD8B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Enabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 22K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig (
|
||||
IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 PAD functional properties : */
|
||||
0xD8B0u ); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Enabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 22K Ohm Pull Up
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@
|
|||
#ifndef CONNECT_SPI_H
|
||||
#define CONNECT_SPI_H
|
||||
|
||||
#include <xiuos.h>
|
||||
#include <device.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
|
|
@ -205,6 +205,7 @@ KERNELPATHS :=-I$(BSP_ROOT) \
|
|||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/priv \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/prot \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/arch \
|
||||
-I$(KERNEL_ROOT)/resources/include \
|
||||
-I$(BSP_ROOT)/include #
|
||||
endif
|
||||
|
||||
|
|
@ -291,6 +292,8 @@ endif
|
|||
ifeq ($(CONFIG_SUPPORT_CONTROL_FRAMEWORK), y)
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control #
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control/plc/interoperability/opcua #
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control/plc/shared #
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/lib/cJSON
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_CRYPTO), y)
|
||||
|
|
|
|||
|
|
@ -29,17 +29,6 @@
|
|||
* Author: Simon Goldschmidt
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file sys_arch.c
|
||||
|
|
@ -463,9 +452,9 @@ void lwip_input_thread(void *param)
|
|||
|
||||
void lwip_config_input(struct netif *net)
|
||||
{
|
||||
pthread_t th_id = 0;
|
||||
sys_thread_t th_id = 0;
|
||||
|
||||
th_id = sys_thread_new("eth_input", lwip_input_thread, net, 4096, 15);
|
||||
th_id = sys_thread_new("eth_input", lwip_input_thread, net, LWIP_TASK_STACK_SIZE, 15);
|
||||
|
||||
if (th_id >= 0) {
|
||||
lw_print("%s %d successfully!\n", __func__, th_id);
|
||||
|
|
@ -489,6 +478,8 @@ void lwip_config_net(char *ip, char *mask, char *gw)
|
|||
#endif /* FSL_FEATURE_SOC_LPC_ENET_COUNT */
|
||||
};
|
||||
|
||||
ETH_BSP_Config();
|
||||
|
||||
if(chk_lwip_bit(LWIP_INIT_FLAG))
|
||||
{
|
||||
lw_print("lw: [%s] already ...\n", __func__);
|
||||
|
|
@ -551,6 +542,8 @@ void lwip_config_tcp(char *ip, char *mask, char *gw)
|
|||
#endif /* FSL_FEATURE_SOC_LPC_ENET_COUNT */
|
||||
};
|
||||
|
||||
ETH_BSP_Config();
|
||||
|
||||
if(chk_lwip_bit(LWIP_INIT_FLAG))
|
||||
{
|
||||
lw_print("lw: [%s] already ...\n", __func__);
|
||||
|
|
|
|||
|
|
@ -29,17 +29,6 @@
|
|||
* Author: Simon Goldschmidt
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file sys_arch.h
|
||||
|
|
|
|||
|
|
@ -25,31 +25,17 @@
|
|||
#include "lwip/sys.h"
|
||||
#include "tcpecho_raw.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define MSG_SIZE 128
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
// this is for test in shell, in fact, shell restrict the length of input string, which is less then 128
|
||||
char tcp_send_msg[MSG_SIZE] = {0};
|
||||
char tcp_target[] = {192, 168, 250, 252};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/******************************************************************************/
|
||||
|
||||
static void lwip_tcp_send_thread(void *arg)
|
||||
static void LwipTcpSendTask(void *arg)
|
||||
{
|
||||
lw_print("lwip_tcp_send_thread start.\n");
|
||||
lw_print("LwipTcpSendTask start.\n");
|
||||
|
||||
int fd = -1;
|
||||
fd = socket(AF_INET, SOCK_STREAM, 0);
|
||||
|
|
@ -85,7 +71,7 @@ __exit:
|
|||
return;
|
||||
}
|
||||
|
||||
void lwip_tcp_send_run(int argc, char *argv[])
|
||||
void LwipTcpSendTest(int argc, char *argv[])
|
||||
{
|
||||
memset(tcp_send_msg, 0, MSG_SIZE);
|
||||
if(argc >= 2)
|
||||
|
|
@ -103,21 +89,19 @@ void lwip_tcp_send_run(int argc, char *argv[])
|
|||
sscanf(argv[2], "%d.%d.%d.%d", &tcp_target[0], &tcp_target[1], &tcp_target[2], &tcp_target[3]);
|
||||
}
|
||||
|
||||
ETH_BSP_Config();
|
||||
lwip_config_tcp(lwip_ipaddr, lwip_netmask, lwip_gwaddr);
|
||||
sys_thread_new("tcp send", lwip_tcp_send_thread, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO);
|
||||
sys_thread_new("tcp send", LwipTcpSendTask, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO);
|
||||
}
|
||||
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
|
||||
TCPSend, lwip_tcp_send_run, TCP Send message);
|
||||
TCPSend, LwipTcpSendTest, TCP Send message);
|
||||
|
||||
void lwip_tcp_recv_run(void)
|
||||
void LwipTcpRecvTest(void)
|
||||
{
|
||||
ETH_BSP_Config();
|
||||
lwip_config_net(lwip_ipaddr, lwip_netmask, lwip_gwaddr);
|
||||
tcpecho_raw_init();
|
||||
}
|
||||
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0),
|
||||
TCPRecv, lwip_tcp_recv_run, TCP Recv message);
|
||||
TCPRecv, LwipTcpRecvTest, TCP Recv message);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* Copyright (c) 2021 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
|
|
@ -11,7 +11,7 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @file tcp_echo_socket_demo.c
|
||||
* @file lwip_udp_demo.c
|
||||
* @brief One UDP demo based on LwIP
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
|
|
@ -25,33 +25,18 @@
|
|||
#include <lwip/sockets.h>
|
||||
#include "lwip/sys.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define UDP_TASK_STACK_SIZE 4096
|
||||
#define UDP_TASK_PRIO 15
|
||||
#define PBUF_SIZE 27
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
static struct udp_pcb *udpecho_raw_pcb;
|
||||
char udp_target[] = {192, 168, 250, 252};
|
||||
char hello_str[] = {"hello world\r\n"};
|
||||
char udp_send_msg[] = "\n\nThis one is UDP pkg. Congratulations on you.\n\n";
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/******************************************************************************/
|
||||
|
||||
static void lwip_udp_send(void *arg)
|
||||
static void LwipUDPSendTask(void *arg)
|
||||
{
|
||||
int cnt = LWIP_DEMO_TIMES;
|
||||
|
||||
|
|
@ -92,11 +77,10 @@ __exit:
|
|||
return;
|
||||
}
|
||||
|
||||
void *lwip_udp_send_run(int argc, char *argv[])
|
||||
void *LwipUdpSendTest(int argc, char *argv[])
|
||||
{
|
||||
int result = 0;
|
||||
pthread_t th_id;
|
||||
pthread_attr_t attr;
|
||||
sys_thread_t th_id;
|
||||
|
||||
memset(udp_send_msg, 0, sizeof(udp_send_msg));
|
||||
|
||||
|
|
@ -116,15 +100,14 @@ void *lwip_udp_send_run(int argc, char *argv[])
|
|||
}
|
||||
lw_print("lw: [%s] gw %d.%d.%d.%d\n", __func__, udp_target[0], udp_target[1], udp_target[2], udp_target[3]);
|
||||
|
||||
ETH_BSP_Config();
|
||||
lwip_config_tcp(lwip_ipaddr, lwip_netmask, lwip_gwaddr);
|
||||
sys_thread_new("udp socket send", lwip_udp_send, NULL, 4096, 25);
|
||||
sys_thread_new("udp socket send", LwipUDPSendTask, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO);
|
||||
}
|
||||
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
|
||||
UDPSend, lwip_udp_send_run, UDP send echo);
|
||||
UDPSend, LwipUdpSendTest, UDP send echo);
|
||||
|
||||
static void udpecho_raw_recv(void *arg, struct udp_pcb *upcb, struct pbuf *p,
|
||||
static void LwipUdpRecvTask(void *arg, struct udp_pcb *upcb, struct pbuf *p,
|
||||
const ip_addr_t *addr, u16_t port)
|
||||
{
|
||||
int udp_len;
|
||||
|
|
@ -159,10 +142,11 @@ static void udpecho_raw_recv(void *arg, struct udp_pcb *upcb, struct pbuf *p,
|
|||
pbuf_free(udp_buf);
|
||||
}
|
||||
|
||||
void udpecho_raw_init(void)
|
||||
void LwipUdpRecvTest(void)
|
||||
{
|
||||
err_t err;
|
||||
lw_print("udpecho_raw_init\r\n");
|
||||
|
||||
lwip_config_net(lwip_ipaddr, lwip_netmask, lwip_gwaddr);
|
||||
|
||||
udpecho_raw_pcb = udp_new_ip_type(IPADDR_TYPE_ANY);
|
||||
if (udpecho_raw_pcb == NULL)
|
||||
|
|
@ -173,18 +157,10 @@ void udpecho_raw_init(void)
|
|||
err = udp_bind(udpecho_raw_pcb, IP_ANY_TYPE, LWIP_LOCAL_PORT);
|
||||
if (err == ERR_OK)
|
||||
{
|
||||
udp_recv(udpecho_raw_pcb, udpecho_raw_recv, NULL);
|
||||
udp_recv(udpecho_raw_pcb, LwipUdpRecvTask, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
void lwip_udp_server(void)
|
||||
{
|
||||
lw_print("lwip_udp_server\r\n");
|
||||
ETH_BSP_Config();
|
||||
lwip_config_net(lwip_ipaddr, lwip_netmask, lwip_gwaddr);
|
||||
udpecho_raw_init();
|
||||
}
|
||||
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0),
|
||||
UDPRecv, lwip_udp_server, UDP server echo);
|
||||
UDPRecv, LwipUdpRecvTest, UDP server echo);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue