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support spi module

This commit is contained in:
wlyu 2022-02-23 17:11:08 +08:00
parent f942af6c43
commit eb4538e331
9 changed files with 1383 additions and 2401 deletions
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7
Ubiquitous/XiUOS/board/ok1052-c/board.c
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@ -35,6 +35,7 @@ extern int ExtSramInit(void);
#include <connect_ethernet.h>
#include <connect_uart.h>
#include <connect_adc.h>
#include <connect_spi.h>
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
4 bits for subpriority */
@ -634,8 +635,10 @@ void InitBoardHardware()
Imrt1052HwAdcInit();
#endif
#ifdef BSP_USING_SPI
Imrt1052HwSpiInit();
#endif
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
}

4
Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/Kconfig
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@ -44,6 +44,10 @@ menuconfig BSP_USING_SPI
default y
select RESOURCES_SPI
if BSP_USING_SPI
source "$BSP_DIR/third_party_driver/spi/Kconfig"
endif
menuconfig BSP_USING_SEMC
bool "Using SEMC device"
default y

617
Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/common/pin_mux.c
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56
Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/include/connect_spi.h Executable file
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@ -0,0 +1,56 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_spi.h
* @brief define stm32f407-st-discovery-board spi function and struct
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
#ifndef CONNECT_SPI_H
#define CONNECT_SPI_H
#include <xiuos.h>
#include <device.h>
#ifdef __cplusplus
extern "C" {
#endif
#define SPI_USING_RX_DMA_FLAG (1<<0)
#define SPI_USING_TX_DMA_FLAG (1<<1)
struct Stm32HwSpi
{
LPSPI_Type *base;
uint8_t irq;
uint8_t mode;
void *priv_data;
};
struct Stm32Spi
{
LPSPI_Type *instance;
char *bus_name;
struct SpiBus spi_bus;
};
int Imrt1052HwSpiInit(void);
x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name);
#ifdef __cplusplus
}
#endif
#endif

45
Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/spi/Kconfig Executable file
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@ -0,0 +1,45 @@
config BSP_USING_SPI1
bool "Enable SPI1"
default y
if BSP_USING_SPI1
config SPI_1_BUS_NAME
string "spi1 bus name"
default "spi1"
config SPI_1_DRV_NAME
string "spi bus 1 driver name"
default "spi1_drv"
config SPI_1_DEV_NAME_0
string "spi bus 1 device name"
default "spi1_dev"
endif
config BSP_USING_SPI2
bool "Enable SPI2"
default y
if BSP_USING_SPI2
config SPI_2_BUS_NAME
string "spi2 bus name"
default "spi2"
config SPI_2_DRV_NAME
string "spi bus 2 driver name"
default "spi2_drv"
config SPI_2_DEV_NAME_0
string "spi bus 2 device name"
default "spi2_dev"
endif
config BSP_USING_SPI3
bool "Enable SPI3"
default y
if BSP_USING_SPI3
config SPI_3_BUS_NAME
string "spi3 bus name"
default "spi3"
config SPI_3_DRV_NAME
string "spi bus 3 driver name"
default "spi3_drv"
config SPI_3_DEV_NAME_0
string "spi bus 3 device name"
default "spi3_dev"
endif

2
Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/spi/Makefile
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@ -1,3 +1,3 @@
SRC_FILES := fsl_lpspi.c lpspi_interrupt.c connect_flash_spi.c flexspi_nor_flash_ops.c flexspi_nor_polling_transfer.c fsl_flexspi.c
SRC_FILES := fsl_lpspi.c connect_spi.c connect_flash_spi.c flexspi_nor_flash_ops.c flexspi_nor_polling_transfer.c fsl_flexspi.c
include $(KERNEL_ROOT)/compiler.mk

1791
Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/spi/connect_spi.c
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492
Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/spi/lpspi_interrupt.c
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@ -1,492 +0,0 @@
/*
* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/**
* @file lpspi_interrupt.c
* @brief Demo for SPI function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.1.18
*/
#include "fsl_device_registers.h"
#include "fsl_debug_console.h"
#include "fsl_lpspi.h"
#include "board.h"
#include "fsl_common.h"
#include "pin_mux.h"
#if ((defined FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT))
#include "fsl_intmux.h"
#endif
/*******************************************************************************
* Definitions
******************************************************************************/
/* Master related */
#define EXAMPLE_LPSPI_MASTER_BASEADDR (LPSPI3)
#define EXAMPLE_LPSPI_MASTER_IRQN (LPSPI3_IRQn)
#define EXAMPLE_LPSPI_MASTER_IRQHandler (LPSPI3_IRQHandler)
#define EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT (kLPSPI_Pcs0)
#define EXAMPLE_LPSPI_MASTER_PCS_FOR_TRANSFER (kLPSPI_MasterPcs0)
/* Slave related */
#define EXAMPLE_LPSPI_SLAVE_BASEADDR (LPSPI1)
#define EXAMPLE_LPSPI_SLAVE_IRQN (LPSPI1_IRQn)
#define EXAMPLE_LPSPI_SLAVE_IRQHandler (LPSPI1_IRQHandler)
#define EXAMPLE_LPSPI_SLAVE_PCS_FOR_INIT (kLPSPI_Pcs0)
#define EXAMPLE_LPSPI_SLAVE_PCS_FOR_TRANSFER (kLPSPI_SlavePcs0)
/* Select USB1 PLL PFD0 (720 MHz) as lpspi clock source */
#define EXAMPLE_LPSPI_CLOCK_SOURCE_SELECT (1U)
/* Clock divider for master lpspi clock source */
#define EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER (7U)
#define EXAMPLE_LPSPI_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER + 1U))
#define EXAMPLE_LPSPI_MASTER_CLOCK_FREQ EXAMPLE_LPSPI_CLOCK_FREQ
#define EXAMPLE_LPSPI_SLAVE_CLOCK_FREQ EXAMPLE_LPSPI_CLOCK_FREQ
#define TRANSFER_SIZE (512U) /*! Transfer dataSize .*/
#define TRANSFER_BAUDRATE (500000U) /*! Transfer baudrate - 500k */
#define spi_print KPrintf
#define spi_trace() KPrintf("lw: [%s][%d] passed!\n", __func__, __LINE__)
/*******************************************************************************
* Prototypes
******************************************************************************/
/* LPSPI user callback */
void LPSPI_SlaveUserCallback(LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData);
void LPSPI_MasterUserCallback(LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData);
/*******************************************************************************
* Variables
******************************************************************************/
uint8_t masterRxData[TRANSFER_SIZE] = {0};
uint8_t masterTxData[TRANSFER_SIZE] = {0};
uint8_t slaveRxData[TRANSFER_SIZE] = {0};
uint8_t slaveTxData[TRANSFER_SIZE] = {0};
volatile uint32_t slaveTxCount;
volatile uint32_t slaveRxCount;
uint8_t g_slaveRxWatermark;
uint8_t g_slaveFifoSize;
volatile uint32_t masterTxCount;
volatile uint32_t masterRxCount;
uint8_t g_masterRxWatermark;
uint8_t g_masterFifoSize;
volatile bool isSlaveTransferCompleted = false;
volatile bool isMasterTransferCompleted = false;
/*******************************************************************************
* Code
******************************************************************************/
void LPSPI_SlaveUserCallback(LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData)
{
if (status == kStatus_Success)
{
spi_print("This is LPSPI slave transfer completed callback. \r\n");
spi_print("It's a successful transfer. \r\n\r\n");
}
else if (status == kStatus_LPSPI_Error)
{
spi_print("This is LPSPI slave transfer completed callback. \r\n");
spi_print("Error occurred in this transfer. \r\n\r\n");
}
else
{
__NOP();
}
isSlaveTransferCompleted = true;
}
void LPSPI_MasterUserCallback(LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData)
{
isMasterTransferCompleted = true;
}
void EXAMPLE_LPSPI_SLAVE_IRQHandler(int vector, void *param)
{
if (slaveRxCount < TRANSFER_SIZE)
{
while (LPSPI_GetRxFifoCount(EXAMPLE_LPSPI_SLAVE_BASEADDR))
{
slaveRxData[slaveRxCount] = LPSPI_ReadData(EXAMPLE_LPSPI_SLAVE_BASEADDR);
slaveRxCount++;
if (slaveTxCount < TRANSFER_SIZE)
{
LPSPI_WriteData(EXAMPLE_LPSPI_SLAVE_BASEADDR, slaveTxData[slaveTxCount]);
slaveTxCount++;
}
if (slaveRxCount == TRANSFER_SIZE)
{
break;
}
}
}
/*Update rxWatermark. There isn't RX interrupt for the last datas if the RX count is not greater than rxWatermark.*/
if ((TRANSFER_SIZE - slaveRxCount) <= g_slaveRxWatermark)
{
EXAMPLE_LPSPI_SLAVE_BASEADDR->FCR =
(EXAMPLE_LPSPI_SLAVE_BASEADDR->FCR & (~LPSPI_FCR_RXWATER_MASK)) |
LPSPI_FCR_RXWATER(((TRANSFER_SIZE - slaveRxCount) > 1) ? ((TRANSFER_SIZE - slaveRxCount) - 1U) : (0U));
}
/* Check if remaining receive byte count matches user request */
if ((slaveRxCount == TRANSFER_SIZE) && (slaveTxCount == TRANSFER_SIZE))
{
isSlaveTransferCompleted = true;
/* Disable interrupt requests */
LPSPI_DisableInterrupts(EXAMPLE_LPSPI_SLAVE_BASEADDR, kLPSPI_RxInterruptEnable);
}
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
exception return operation might vector to incorrect interrupt */
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
}
DECLARE_HW_IRQ(EXAMPLE_LPSPI_SLAVE_IRQN, EXAMPLE_LPSPI_SLAVE_IRQHandler, NONE);
void EXAMPLE_LPSPI_MASTER_IRQHandler(int vector, void *param)
{
if (masterRxCount < TRANSFER_SIZE)
{
/* First, disable the interrupts to avoid potentially triggering another interrupt
* while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll
* re-enable the interrupts EXAMPLE_LPSPI_MASTER_BASEADDRd on the LPSPI state after reading out the FIFO.
*/
LPSPI_DisableInterrupts(EXAMPLE_LPSPI_MASTER_BASEADDR, kLPSPI_RxInterruptEnable);
while (LPSPI_GetRxFifoCount(EXAMPLE_LPSPI_MASTER_BASEADDR))
{
/*Read out the data*/
masterRxData[masterRxCount] = LPSPI_ReadData(EXAMPLE_LPSPI_MASTER_BASEADDR);
masterRxCount++;
if (masterRxCount == TRANSFER_SIZE)
{
break;
}
}
/* Re-enable the interrupts only if rxCount indicates there is more data to receive,
* else we may get a spurious interrupt.
* */
if (masterRxCount < TRANSFER_SIZE)
{
/* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */
LPSPI_EnableInterrupts(EXAMPLE_LPSPI_MASTER_BASEADDR, kLPSPI_RxInterruptEnable);
}
}
/*Update rxWatermark. There isn't RX interrupt for the last datas if the RX count is not greater than rxWatermark.*/
if ((TRANSFER_SIZE - masterRxCount) <= g_masterRxWatermark)
{
EXAMPLE_LPSPI_MASTER_BASEADDR->FCR =
(EXAMPLE_LPSPI_MASTER_BASEADDR->FCR & (~LPSPI_FCR_RXWATER_MASK)) |
LPSPI_FCR_RXWATER(((TRANSFER_SIZE - masterRxCount) > 1) ? ((TRANSFER_SIZE - masterRxCount) - 1U) : (0U));
}
if (masterTxCount < TRANSFER_SIZE)
{
while ((LPSPI_GetTxFifoCount(EXAMPLE_LPSPI_MASTER_BASEADDR) < g_masterFifoSize) &&
(masterTxCount - masterRxCount < g_masterFifoSize))
{
/*Write the word to TX register*/
LPSPI_WriteData(EXAMPLE_LPSPI_MASTER_BASEADDR, masterTxData[masterTxCount]);
++masterTxCount;
if (masterTxCount == TRANSFER_SIZE)
{
break;
}
}
}
/* Check if we're done with this transfer.*/
if ((masterTxCount == TRANSFER_SIZE) && (masterRxCount == TRANSFER_SIZE))
{
isMasterTransferCompleted = true;
/* Complete the transfer and disable the interrupts */
LPSPI_DisableInterrupts(EXAMPLE_LPSPI_MASTER_BASEADDR, kLPSPI_AllInterruptEnable);
}
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
exception return operation might vector to incorrect interrupt */
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
}
DECLARE_HW_IRQ(EXAMPLE_LPSPI_MASTER_IRQN, EXAMPLE_LPSPI_MASTER_IRQHandler, NONE);
void lpspi_config_init(void)
{
lpspi_master_config_t masterConfig;
lpspi_slave_config_t slaveConfig;
/*Master config*/
masterConfig.baudRate = TRANSFER_BAUDRATE;
masterConfig.bitsPerFrame = 8;
masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
masterConfig.direction = kLPSPI_MsbFirst;
masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate;
masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate;
masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate;
masterConfig.whichPcs = EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT;
masterConfig.pcsActiveHighOrLow = kLPSPI_PcsActiveLow;
masterConfig.pinCfg = kLPSPI_SdiInSdoOut;
masterConfig.dataOutConfig = kLpspiDataOutRetained;
LPSPI_MasterInit(EXAMPLE_LPSPI_MASTER_BASEADDR, &masterConfig, EXAMPLE_LPSPI_MASTER_CLOCK_FREQ);
/*Slave config*/
slaveConfig.bitsPerFrame = masterConfig.bitsPerFrame;
slaveConfig.cpol = masterConfig.cpol;
slaveConfig.cpha = masterConfig.cpha;
slaveConfig.direction = masterConfig.direction;
slaveConfig.whichPcs = EXAMPLE_LPSPI_SLAVE_PCS_FOR_INIT;
slaveConfig.pcsActiveHighOrLow = masterConfig.pcsActiveHighOrLow;
slaveConfig.pinCfg = kLPSPI_SdiInSdoOut;
slaveConfig.dataOutConfig = kLpspiDataOutRetained;
LPSPI_SlaveInit(EXAMPLE_LPSPI_SLAVE_BASEADDR, &slaveConfig);
}
/*!
* @brief Main function
*/
int test_spi(void)
{
/*Set clock source for LPSPI*/
CLOCK_SetMux(kCLOCK_LpspiMux, EXAMPLE_LPSPI_CLOCK_SOURCE_SELECT);
CLOCK_SetDiv(kCLOCK_LpspiDiv, EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER);
spi_print("LPSPI functional interrupt example start.\r\n");
spi_print("This example use one lpspi instance as master and another as slave on one board.\r\n");
spi_print("Master uses interrupt way and slave uses interrupt way.\r\n");
spi_print(
"Note that some LPSPI instances interrupt is in INTMUX ,"
"you should set the intmux when you porting this example accordingly \r\n");
spi_print("Please make sure you make the correct line connection. Basically, the connection is: \r\n");
spi_print("LPSPI_master -- LPSPI_slave \r\n");
spi_print(" CLK -- CLK \r\n");
spi_print(" PCS -- PCS \r\n");
spi_print(" SOUT -- SIN \r\n");
spi_print(" SIN -- SOUT \r\n");
uint32_t errorCount;
uint32_t i;
uint32_t whichPcs;
uint8_t txWatermark;
/*Set up the transfer data*/
for (i = 0; i < TRANSFER_SIZE; i++)
{
masterTxData[i] = i % 256;
masterRxData[i] = 0;
slaveTxData[i] = ~masterTxData[i];
slaveRxData[i] = 0;
}
lpspi_config_init();
/******************Set up slave first ******************/
isSlaveTransferCompleted = false;
slaveTxCount = 0;
slaveRxCount = 0;
whichPcs = EXAMPLE_LPSPI_SLAVE_PCS_FOR_INIT;
/*The TX and RX FIFO sizes are always the same*/
g_slaveFifoSize = LPSPI_GetRxFifoSize(EXAMPLE_LPSPI_SLAVE_BASEADDR);
/*Set the RX and TX watermarks to reduce the ISR times.*/
if (g_slaveFifoSize > 1)
{
txWatermark = 1;
g_slaveRxWatermark = g_slaveFifoSize - 2;
}
else
{
txWatermark = 0;
g_slaveRxWatermark = 0;
}
LPSPI_SetFifoWatermarks(EXAMPLE_LPSPI_SLAVE_BASEADDR, txWatermark, g_slaveRxWatermark);
LPSPI_Enable(EXAMPLE_LPSPI_SLAVE_BASEADDR, false);
EXAMPLE_LPSPI_SLAVE_BASEADDR->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK);
LPSPI_Enable(EXAMPLE_LPSPI_SLAVE_BASEADDR, true);
/*Flush FIFO , clear status , disable all the interrupts.*/
LPSPI_FlushFifo(EXAMPLE_LPSPI_SLAVE_BASEADDR, true, true);
LPSPI_ClearStatusFlags(EXAMPLE_LPSPI_SLAVE_BASEADDR, kLPSPI_AllStatusFlag);
LPSPI_DisableInterrupts(EXAMPLE_LPSPI_SLAVE_BASEADDR, kLPSPI_AllInterruptEnable);
EXAMPLE_LPSPI_SLAVE_BASEADDR->TCR =
(EXAMPLE_LPSPI_SLAVE_BASEADDR->TCR &
~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) |
LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(0) | LPSPI_TCR_TXMSK(0) | LPSPI_TCR_PCS(whichPcs);
/* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX ,
* and you should also enable the INTMUX interrupt in your application.
*/
EnableIRQ(EXAMPLE_LPSPI_SLAVE_IRQN);
/*TCR is also shared the FIFO , so wait for TCR written.*/
while (LPSPI_GetTxFifoCount(EXAMPLE_LPSPI_SLAVE_BASEADDR) != 0)
{
}
spi_trace();
/*Fill up the TX data in FIFO */
while (LPSPI_GetTxFifoCount(EXAMPLE_LPSPI_SLAVE_BASEADDR) < g_slaveFifoSize)
{
/*Write the word to TX register*/
LPSPI_WriteData(EXAMPLE_LPSPI_SLAVE_BASEADDR, slaveTxData[slaveTxCount]);
++slaveTxCount;
if (slaveTxCount == TRANSFER_SIZE)
{
break;
}
}
spi_trace();
LPSPI_EnableInterrupts(EXAMPLE_LPSPI_SLAVE_BASEADDR, kLPSPI_RxInterruptEnable);
/******************Set up master transfer******************/
isMasterTransferCompleted = false;
masterTxCount = 0;
masterRxCount = 0;
whichPcs = EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT;
/*The TX and RX FIFO sizes are always the same*/
g_masterFifoSize = LPSPI_GetRxFifoSize(EXAMPLE_LPSPI_MASTER_BASEADDR);
/*Set the RX and TX watermarks to reduce the ISR times.*/
if (g_masterFifoSize > 1)
{
txWatermark = 1;
g_masterRxWatermark = g_masterFifoSize - 2;
}
else
{
txWatermark = 0;
g_masterRxWatermark = 0;
}
LPSPI_SetFifoWatermarks(EXAMPLE_LPSPI_MASTER_BASEADDR, txWatermark, g_masterRxWatermark);
LPSPI_Enable(EXAMPLE_LPSPI_MASTER_BASEADDR, false);
EXAMPLE_LPSPI_MASTER_BASEADDR->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK);
LPSPI_Enable(EXAMPLE_LPSPI_MASTER_BASEADDR, true);
/*Flush FIFO , clear status , disable all the inerrupts.*/
LPSPI_FlushFifo(EXAMPLE_LPSPI_MASTER_BASEADDR, true, true);
LPSPI_ClearStatusFlags(EXAMPLE_LPSPI_MASTER_BASEADDR, kLPSPI_AllStatusFlag);
LPSPI_DisableInterrupts(EXAMPLE_LPSPI_MASTER_BASEADDR, kLPSPI_AllInterruptEnable);
EXAMPLE_LPSPI_MASTER_BASEADDR->TCR =
(EXAMPLE_LPSPI_MASTER_BASEADDR->TCR &
~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) |
LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(0) | LPSPI_TCR_TXMSK(0) | LPSPI_TCR_PCS(whichPcs);
/* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX ,
* and you should also enable the INTMUX interupt in your application.
*/
EnableIRQ(EXAMPLE_LPSPI_MASTER_IRQN);
/*TCR is also shared the FIFO , so wait for TCR written.*/
while (LPSPI_GetTxFifoCount(EXAMPLE_LPSPI_MASTER_BASEADDR) != 0)
{
}
spi_trace();
/*Fill up the TX data in FIFO */
while ((LPSPI_GetTxFifoCount(EXAMPLE_LPSPI_MASTER_BASEADDR) < g_masterFifoSize) &&
(masterTxCount - masterRxCount < g_masterFifoSize))
{
/*Write the word to TX register*/
LPSPI_WriteData(EXAMPLE_LPSPI_MASTER_BASEADDR, masterTxData[masterTxCount]);
++masterTxCount;
spi_trace();
if (masterTxCount == TRANSFER_SIZE)
{
break;
}
}
spi_trace();
LPSPI_EnableInterrupts(EXAMPLE_LPSPI_MASTER_BASEADDR, kLPSPI_RxInterruptEnable);
/******************Wait for master and slave transfer completed.******************/
while ((!isSlaveTransferCompleted) || (!isMasterTransferCompleted))
{
}
spi_trace();
errorCount = 0;
for (i = 0; i < TRANSFER_SIZE; i++)
{
if (masterTxData[i] != slaveRxData[i])
{
errorCount++;
}
if (slaveTxData[i] != masterRxData[i])
{
errorCount++;
}
}
if (errorCount == 0)
{
spi_print("\r\nLPSPI transfer all data matched! \r\n");
}
else
{
spi_print("\r\nError occurred in LPSPI transfer ! \r\n");
}
LPSPI_Deinit(EXAMPLE_LPSPI_MASTER_BASEADDR);
LPSPI_Deinit(EXAMPLE_LPSPI_SLAVE_BASEADDR);
spi_print("End of example. \r\n");
while (1)
{
}
spi_trace();
}
SHELL_EXPORT_CMD (SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0),
spi, test_spi, SPI test );