diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/TLB.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/TLB.c deleted file mode 100755 index 45ce50e3b..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/TLB.c +++ /dev/null @@ -1,56 +0,0 @@ - - -#define CP15_TLBIALLIS(r) _CP15(0, r, c8, c3, 0) /* Invalidate entire unified TLB Inner Shareable */ -#define CP15_TLBIMVAIS(r) _CP15(0, r, c8, c3, 1) /* Invalidate unified TLB entry by MVA and ASID, Inner Shareable */ -#define CP15_TLBIASIDIS(r) _CP15(0, r, c8, c3, 2) /* Invalidate unified TLB by ASID match Inner Shareable */ -#define CP15_TLBIMVAAIS(r) _CP15(0, r, c8, c3, 3) /* Invalidate unified TLB entry by MVA all ASID Inner Shareable */ -#define CP15_TLBIALL(r,c) _CP15(0, r, c8, c, 0) /* Invalidate entire instruction TLB. CRm = c5, c6, or c7 */ -#define CP15_TLBIMVA(r,c) _CP15(0, r, c8, c, 1) /* Invalidate instruction TLB entry by MVA and ASID. CRm = c5, c6, or c7 */ -#define CP15_TLBIASID(r,c) _CP15(0, r, c8, c, 2) /* Invalidate data TLB by ASID match. CRm = c5, c6, or c7 */ -#define CP15_TLBIMVAA(r,c) _CP15(0, r, c8, c, 3) /* Invalidate unified TLB entry by MVA and ASID. CRm = c5, c6, or c7 */ - -void InvalidateTlbsAll(void) -{ - __asm__ __volatile__ - ( - "\tmcr p15, 0, r0, c8, c7, 0\n" /* TLBIALL */ - : - : - : "r0", "memory" - ); -} - -void InvalidateTlbMVA(uint32_t vaddr) -{ - __asm__ __volatile__ - ( - "\tdsb\n" - - "\tmcr p15, 0, %0, c8, c7, 1\n" /* TLBIMVA */ - - "\tdsb\n" - "\tisb\n" - : - : "r" (vaddr) - : "r1", "memory" - ); -} - - -void InvalidateTlbASID(uint32_t vaddr) -{ - __asm__ __volatile__ - ( - "\tdsb\n" - - "\tmcr p15, 0, %0, c8, c7, 2\n" /* TLBIASID */ - - "\tdsb\n" - "\tisb\n" - : - : "r" (vaddr) - : "r1", "memory" - ); -} - - diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c index 6e613f117..42c0d2c72 100755 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c @@ -1,26 +1,24 @@ -/**************************************************************************** - * arch/arm/src/armv7-a/arm_cache.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: cache.c +* @brief: the general management of cache +* @version: 3.0 +* @author: AIIT XUOS Lab +* @date: 2023/4/27 +* +*/ -/**************************************************************************** - * Included Files - ****************************************************************************/ #include "cache.h" diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h index fb42509fa..5a8a84ace 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h @@ -1,25 +1,24 @@ -/**************************************************************************** - * include/nuttx/cache.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: cache.h +* @brief: the general management of cache +* @version: 3.0 +* @author: AIIT XUOS Lab +* @date: 2023/4/27 +* +*/ -#ifndef __INCLUDE_NUTTX_CACHE_H -#define __INCLUDE_NUTTX_CACHE_H #ifndef __ASSEMBLY__ @@ -416,4 +415,4 @@ void coherent_dcache(uintptr_t addr, size_t len); #endif /* __ASSEMBLY__ */ -#endif /* __INCLUDE_NUTTX_CACHE_H */ + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c index 2e2be4d97..b74c0ce69 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c @@ -1,3 +1,24 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: l1cache.c +* @brief: the general management of L1 cache +* @version: 3.0 +* @author: AIIT XUOS Lab +* @date: 2023/4/27 +* +*/ + #include "l1cache.h" #include "cp15_cacheops.h" #include "barriers.h" diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h index 757157cae..7a507457a 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h @@ -1,22 +1,23 @@ /* - * Copyright (c) 2022 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ /** - * @file l1cache.c - * @brief PLC inovance am401 app - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.8.10 - */ +* @file: l1cache.h +* @brief: the general management of L1 cache +* @version: 3.0 +* @author: AIIT XUOS Lab +* @date: 2023/4/27 +* +*/ #include #include diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h index 5b858e3a3..18118e85d 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h @@ -1,25 +1,24 @@ -/**************************************************************************** - * arch/arm/src/armv7-a/l2cc.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ +/* + * Copyright (c) 2022 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file l2cc.h + * @brief the general management of L2 cache + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.8.10 + */ + -#ifndef __ARCH_ARM_SRC_ARMV7_A_L2CC_H -#define __ARCH_ARM_SRC_ARMV7_A_L2CC_H /**************************************************************************** * Included Files @@ -240,4 +239,4 @@ void FlushL2Cache(uint32_t startaddr, uint32_t endaddr); # define FlushL2Cache(s,e) #endif /* CONFIG_ARCH_L2CACHE */ -#endif /* __ARCH_ARM_SRC_ARMV7_A_L2CC_H */ + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c index 0bc4712a1..981657b57 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c @@ -12,7 +12,7 @@ /** * @file l2cc_pl310.c - * @brief PLC inovance am401 app + * @brief the general management of L2 cache * @version 3.0 * @author AIIT XUOS Lab * @date 2023.8.10