From d528464e90a1575880636b41d97e7ea090a0680a Mon Sep 17 00:00:00 2001 From: Wang_Weigen Date: Mon, 14 Mar 2022 17:30:12 +0800 Subject: [PATCH] add aiit-riscv64-board for rt-thread --- Ubiquitous/Nuttx/apps | 1 - Ubiquitous/Nuttx/nuttx | 1 - .../aiit_board/aiit-riscv64-board/.config | 560 +++++++ .../aiit_board/aiit-riscv64-board/.gitignore | 228 +++ .../aiit_board/aiit-riscv64-board/Kconfig | 39 + .../aiit_board/aiit-riscv64-board/README.md | 11 + .../aiit_board/aiit-riscv64-board/SConscript | 13 + .../aiit_board/aiit-riscv64-board/SConstruct | 65 + .../applications/SConscript | 9 + .../aiit-riscv64-board/applications/main.c | 27 + .../aiit-riscv64-board/base-drivers/Kconfig | 284 ++++ .../base-drivers/SConscript | 53 + .../aiit-riscv64-board/base-drivers/board.c | 144 ++ .../aiit-riscv64-board/base-drivers/board.h | 26 + .../aiit-riscv64-board/base-drivers/ch438.c | 471 ++++++ .../aiit-riscv64-board/base-drivers/ch438.h | 251 ++++ .../aiit-riscv64-board/base-drivers/dmalock.c | 90 ++ .../aiit-riscv64-board/base-drivers/dmalock.h | 14 + .../aiit-riscv64-board/base-drivers/drv_dvp.c | 167 +++ .../aiit-riscv64-board/base-drivers/drv_dvp.h | 46 + .../base-drivers/drv_gpio.c | 267 ++++ .../base-drivers/drv_gpio.h | 16 + .../base-drivers/drv_interrupt.c | 27 + .../base-drivers/drv_io_config.c | 219 +++ .../base-drivers/drv_io_config.h | 63 + .../aiit-riscv64-board/base-drivers/drv_lcd.c | 550 +++++++ .../aiit-riscv64-board/base-drivers/drv_lcd.h | 90 ++ .../base-drivers/drv_mpylcd.c | 1297 +++++++++++++++++ .../base-drivers/drv_mpymachine.c | 27 + .../aiit-riscv64-board/base-drivers/drv_spi.c | 301 ++++ .../aiit-riscv64-board/base-drivers/drv_spi.h | 16 + .../aiit-riscv64-board/base-drivers/heap.c | 11 + .../base-drivers/sdcard_port.c | 42 + .../aiit-riscv64-board/kendryte-sdk/Kconfig | 7 + .../kendryte-sdk/SConscript | 37 + .../aiit_board/aiit-riscv64-board/link.lds | 170 +++ .../aiit-riscv64-board/link_stacksize.lds | 1 + .../aiit_board/aiit-riscv64-board/rtconfig.h | 373 +++++ .../aiit_board/aiit-riscv64-board/rtconfig.py | 49 + Ubiquitous/RT_Thread/build.sh | 0 .../arch/risc-v/rv32m1_vega/arch_interrupt.h | 8 + .../third_party_driver/semc/fsl_semc.c | 20 + 42 files changed, 6089 insertions(+), 2 deletions(-) delete mode 160000 Ubiquitous/Nuttx/apps delete mode 160000 Ubiquitous/Nuttx/nuttx create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.config create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.gitignore create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/Kconfig create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/README.md create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/SConscript create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/SConstruct create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/SConscript create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/main.c create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/Kconfig create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/SConscript create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/board.c create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/board.h create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.c create mode 100755 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.h create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/dmalock.c create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/dmalock.h create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_dvp.c create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_dvp.h create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_gpio.c create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_gpio.h create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_interrupt.c create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.c create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.h create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_lcd.c create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_lcd.h create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_mpylcd.c create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_mpymachine.c create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_spi.c create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_spi.h create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/heap.c create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/sdcard_port.c create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/Kconfig create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/SConscript create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/link.lds create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/link_stacksize.lds create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.h create mode 100644 Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.py mode change 100644 => 100755 Ubiquitous/RT_Thread/build.sh diff --git a/Ubiquitous/Nuttx/apps b/Ubiquitous/Nuttx/apps deleted file mode 160000 index 562239ecb..000000000 --- a/Ubiquitous/Nuttx/apps +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 562239ecb2d84dd9de2dd206da41df19602e20cb diff --git a/Ubiquitous/Nuttx/nuttx b/Ubiquitous/Nuttx/nuttx deleted file mode 160000 index 3fede4209..000000000 --- a/Ubiquitous/Nuttx/nuttx +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 3fede42098e5883f336d846ac30edfe749899494 diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.config b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.config new file mode 100644 index 000000000..0ba268d3d --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.config @@ -0,0 +1,560 @@ +# +# Automatically generated file; DO NOT EDIT. +# XIUOS Rt-thread Configuration +# +CONFIG_ROOT_DIR="../../../.." +CONFIG_BSP_DIR="." +CONFIG_RT_Thread_DIR="../.." +CONFIG_RTT_DIR="../../rt-thread" +CONFIG_BOARD_K210_EVB=y + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_BIG_ENDIAN is not set +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMP=y +CONFIG_RT_CPUS_NR=2 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=4096 +CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +CONFIG_RT_DEBUG_INIT_CONFIG=y +CONFIG_RT_DEBUG_INIT=1 +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_SIGNALS=y + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uarths" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +CONFIG_ARCH_CPU_64BIT=y +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV_FPU=y +CONFIG_ARCH_RISCV_FPU_S=y +CONFIG_ARCH_RISCV64=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +CONFIG_RT_USING_CPLUSPLUS=y +# CONFIG_RT_USING_CPLUSPLUS11 is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=16384 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=16 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=16 +CONFIG_DFS_FD_MAX=64 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +CONFIG_RT_USING_SPI_MSD=y +CONFIG_RT_USING_SFUD=y +CONFIG_RT_SFUD_USING_SFDP=y +CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +# CONFIG_RT_SFUD_USING_QSPI is not set +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 +CONFIG_RT_DEBUG_SFUD=y +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +CONFIG_RT_USING_WIFI=y +CONFIG_RT_WLAN_DEVICE_STA_NAME="wlan0" +CONFIG_RT_WLAN_DEVICE_AP_NAME="wlan1" +CONFIG_RT_WLAN_SSID_MAX_LENGTH=32 +CONFIG_RT_WLAN_PASSWORD_MAX_LENGTH=32 +CONFIG_RT_WLAN_DEV_EVENT_NUM=2 +CONFIG_RT_WLAN_MANAGE_ENABLE=y +CONFIG_RT_WLAN_SCAN_WAIT_MS=10000 +CONFIG_RT_WLAN_CONNECT_WAIT_MS=10000 +CONFIG_RT_WLAN_SCAN_SORT=y +CONFIG_RT_WLAN_MSH_CMD_ENABLE=y +CONFIG_RT_WLAN_AUTO_CONNECT_ENABLE=y +CONFIG_AUTO_CONNECTION_PERIOD_MS=2000 +CONFIG_RT_WLAN_CFG_ENABLE=y +CONFIG_RT_WLAN_CFG_INFO_MAX=3 +CONFIG_RT_WLAN_PROT_ENABLE=y +CONFIG_RT_WLAN_PROT_NAME_LEN=8 +CONFIG_RT_WLAN_PROT_MAX=2 +CONFIG_RT_WLAN_DEFAULT_PROT="lwip" +CONFIG_RT_WLAN_PROT_LWIP_ENABLE=y +CONFIG_RT_WLAN_PROT_LWIP_NAME="lwip" +# CONFIG_RT_WLAN_PROT_LWIP_PBUF_FORCE is not set +CONFIG_RT_WLAN_WORK_THREAD_ENABLE=y +CONFIG_RT_WLAN_WORKQUEUE_THREAD_NAME="wlan" +CONFIG_RT_WLAN_WORKQUEUE_THREAD_SIZE=2048 +CONFIG_RT_WLAN_WORKQUEUE_THREAD_PRIO=15 +# CONFIG_RT_WLAN_DEBUG is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +CONFIG_RT_USING_PTHREADS=y +CONFIG_PTHREAD_NUM_MAX=8 +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_LIBC_USING_TIME=y +# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +CONFIG_RT_USING_SAL=y +# CONFIG_SAL_INTERNET_CHECK is not set + +# +# protocol stack implement +# +CONFIG_SAL_USING_LWIP=y +CONFIG_SAL_USING_POSIX=y + +# +# Network interface device +# +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP203 is not set +# CONFIG_RT_USING_LWIP212 is not set +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=8 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=10240 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=10240 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_RT_LWIP_DEBUG is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# Board Drivers Config +# +CONFIG_BSP_USING_UART_HS=y + +# +# General Purpose UARTs +# +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_UART1_TXD_PIN=20 +CONFIG_BSP_UART1_RXD_PIN=21 +CONFIG_BSP_UART1_RTS_PIN=-1 +CONFIG_BSP_UART1_CTS_PIN=-1 +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_I2C1 is not set +CONFIG_BSP_USING_SPI1=y +# CONFIG_BSP_USING_SPI1_AS_QSPI is not set +CONFIG_BSP_SPI1_CLK_PIN=27 +CONFIG_BSP_SPI1_D0_PIN=28 +CONFIG_BSP_SPI1_D1_PIN=26 +CONFIG_BSP_SPI1_USING_SS0=y +CONFIG_BSP_SPI1_SS0_PIN=29 +CONFIG_BSP_SPI1_USING_SS1=y +CONFIG_BSP_SPI1_SS1_PIN=8 +# CONFIG_BSP_SPI1_USING_SS2 is not set +# CONFIG_BSP_SPI1_USING_SS3 is not set +CONFIG_BSP_USING_LCD=y +CONFIG_BSP_LCD_CS_PIN=36 +CONFIG_BSP_LCD_WR_PIN=39 +CONFIG_BSP_LCD_DC_PIN=38 +CONFIG_BSP_LCD_RST_PIN=37 +CONFIG_BSP_LCD_BACKLIGHT_PIN=-1 +CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_LOW=y +# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_HIGH is not set +CONFIG_BSP_LCD_CLK_FREQ=20000000 +# CONFIG_BSP_BOARD_KD233 is not set +# CONFIG_BSP_BOARD_K210_OPENMV_TEST is not set +CONFIG_BSP_BOARD_USER=y +CONFIG_BSP_LCD_X_MAX=240 +CONFIG_BSP_LCD_Y_MAX=320 +CONFIG_BSP_USING_SDCARD=y +CONFIG_BSP_USING_DVP=y + +# +# The default pin assignment is based on the Maix Duino K210 development board +# +CONFIG_BSP_DVP_SCCB_SDA_PIN=40 +CONFIG_BSP_DVP_SCCB_SCLK_PIN=41 +CONFIG_BSP_DVP_CMOS_RST_PIN=42 +CONFIG_BSP_DVP_CMOS_VSYNC_PIN=43 +CONFIG_BSP_DVP_CMOS_PWDN_PIN=44 +CONFIG_BSP_DVP_CMOS_XCLK_PIN=46 +CONFIG_BSP_DVP_CMOS_PCLK_PIN=47 +CONFIG_BSP_DVP_CMOS_HREF_PIN=45 +CONFIG_BSP_USING_CH438=y +CONFIG_BSP_CH438_ALE_PIN=23 +CONFIG_BSP_CH438_NWR_PIN=24 +CONFIG_BSP_CH438_NRD_PIN=25 +CONFIG_BSP_CH438_D0_PIN=27 +CONFIG_BSP_CH438_D1_PIN=28 +CONFIG_BSP_CH438_D2_PIN=29 +CONFIG_BSP_CH438_D3_PIN=30 +CONFIG_BSP_CH438_D4_PIN=31 +CONFIG_BSP_CH438_D5_PIN=32 +CONFIG_BSP_CH438_D6_PIN=33 +CONFIG_BSP_CH438_D7_PIN=34 +CONFIG_BSP_CH438_INT_PIN=35 + +# +# Kendryte SDK Config +# +CONFIG_PKG_KENDRYTE_SDK_VERNUM=0x0055 + +# +# More Drivers +# +# CONFIG_PKG_USING_RW007 is not set +CONFIG_DRV_USING_OV2640=y +CONFIG_OV2640_JPEG_MODE=y +# CONFIG_OV2640_RGB565_MODE is not set +CONFIG_OV2640_X_RESOLUTION_IMAGE_OUTSIZE=240 +CONFIG_OV2640_Y_RESOLUTION_IMAGE_OUTSIZE=240 +CONFIG_OV2640_X_IMAGE_WINDOWS_SIZE=400 + +# +# the value must be greater than OV2640_X_RESOLUTION_IMAGE_OUTSIZE +# +CONFIG_OV2640_Y_IMAGE_WINDOWS_SIZE=400 + +# +# the value must be greater than OV2640_Y_RESOLUTION_IMAGE_OUTSIZE +# + +# +# APP_Framework +# + +# +# Framework +# +CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y +CONFIG_ADD_XIZI_FETURES=y +# CONFIG_ADD_NUTTX_FETURES is not set +# CONFIG_ADD_RTTHREAD_FETURES is not set +# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set +# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set +CONFIG_SUPPORT_KNOWING_FRAMEWORK=y +# CONFIG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_USING_KNOWING_FILTER is not set +# CONFIG_USING_OTA_MODEL is not set +# CONFIG_USING_IMAGE_PROCESSING is not set +# CONFIG_USING_CMSIS_5 is not set +CONFIG_USING_KPU_PROCESSING=y +CONFIG_USING_YOLOV2=y +CONFIG_USING_YOLOV2_JSONPARSER=y +CONFIG_USING_K210_YOLOV2_DETECT=y +# CONFIG_USING_NNOM is not set +# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set + +# +# Security +# +# CONFIG_CRYPTO is not set + +# +# Applications +# + +# +# config stack size and priority of main task +# +CONFIG_MAIN_KTASK_STACK_SIZE=1024 + +# +# ota app +# +# CONFIG_APPLICATION_OTA is not set + +# +# test app +# +# CONFIG_USER_TEST is not set + +# +# connection app +# +# CONFIG_APPLICATION_CONNECTION is not set + +# +# control app +# + +# +# knowing app +# +CONFIG_APPLICATION_KNOWING=y +CONFIG_K210_DETECT_ENTRY=y +# CONFIG_IRIS_ML_DEMO is not set +# CONFIG_K210_FFT_TEST is not set +# CONFIG_USING_IMAGE_PROCESSING_APP is not set + +# +# sensor app +# +CONFIG_APPLICATION_SENSOR=y +# CONFIG_APPLICATION_SENSOR_HCHO is not set +# CONFIG_APPLICATION_SENSOR_TVOC is not set +# CONFIG_APPLICATION_SENSOR_IAQ is not set +# CONFIG_APPLICATION_SENSOR_CH4 is not set +# CONFIG_APPLICATION_SENSOR_CO2 is not set +# CONFIG_APPLICATION_SENSOR_PM1_0 is not set +# CONFIG_APPLICATION_SENSOR_PM2_5 is not set +# CONFIG_APPLICATION_SENSOR_PM10 is not set +# CONFIG_APPLICATION_SENSOR_VOICE is not set +# CONFIG_APPLICATION_SENSOR_TEMPERATURE is not set +# CONFIG_APPLICATION_SENSOR_HUMIDITY is not set + +# +# lib +# +CONFIG_APP_SELECT_NEWLIB=y +# CONFIG_APP_SELECT_OTHER_LIB is not set +CONFIG_LIB_USING_CJSON=y +# CONFIG_LIB_USING_QUEUE is not set +# CONFIG_LIB_LV is not set +CONFIG___STACKSIZE__=4096 diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.gitignore b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.gitignore new file mode 100644 index 000000000..14e2fd4e8 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.gitignore @@ -0,0 +1,228 @@ +# this +*.old +*.dblite +cconfig.h +*.bin +*.map +# rtconfig.h +# .config + +# General +.DS_Store +.AppleDouble +.LSOverride + +# Icon must end with two \r +Icon + + +# Thumbnails +._* + +# Files that might appear in the root of a volume +.DocumentRevisions-V100 +.fseventsd +.Spotlight-V100 +.TemporaryItems +.Trashes +.VolumeIcon.icns +.com.apple.timemachine.donotpresent + +# Directories potentially created on remote AFP share +.AppleDB +.AppleDesktop +Network Trash Folder +Temporary Items +.apdisk + +# Byte-compiled / optimized / DLL files +__pycache__/ +*.py[cod] +*$py.class + +# C extensions +*.so + +# Distribution / packaging +.Python +build/ +develop-eggs/ +dist/ +downloads/ +eggs/ +.eggs/ +lib/ +lib64/ +parts/ +sdist/ +var/ +wheels/ +share/python-wheels/ +*.egg-info/ +.installed.cfg +*.egg +MANIFEST + +# PyInstaller +# Usually these files are written by a python script from a template +# before PyInstaller builds the exe, so as to inject date/other infos into it. +*.manifest +*.spec + +# Installer logs +pip-log.txt +pip-delete-this-directory.txt + +# Unit test / coverage reports +htmlcov/ +.tox/ +.nox/ +.coverage +.coverage.* +.cache +nosetests.xml +coverage.xml +*.cover +*.py,cover +.hypothesis/ +.pytest_cache/ +cover/ + +# Translations +*.mo +*.pot + +# Django stuff: +*.log +local_settings.py +db.sqlite3 +db.sqlite3-journal + +# Flask stuff: +instance/ +.webassets-cache + +# Scrapy stuff: +.scrapy + +# Sphinx documentation +docs/_build/ + +# PyBuilder +.pybuilder/ +target/ + +# Jupyter Notebook +.ipynb_checkpoints + +# IPython +profile_default/ +ipython_config.py + +# pyenv +# For a library or package, you might want to ignore these files since the code is +# intended to run in multiple environments; otherwise, check them in: +# .python-version + +# pipenv +# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control. +# However, in case of collaboration, if having platform-specific dependencies or dependencies +# having no cross-platform support, pipenv may install dependencies that don't work, or not +# install all needed dependencies. +#Pipfile.lock + +# PEP 582; used by e.g. github.com/David-OConnor/pyflow +__pypackages__/ + +# Celery stuff +celerybeat-schedule +celerybeat.pid + +# SageMath parsed files +*.sage.py + +# Environments +.env +.venv +env/ +venv/ +ENV/ +env.bak/ +venv.bak/ + +# Spyder project settings +.spyderproject +.spyproject + +# Rope project settings +.ropeproject + +# mkdocs documentation +/site + +# mypy +.mypy_cache/ +.dmypy.json +dmypy.json + +# Pyre type checker +.pyre/ + +# pytype static type analyzer +.pytype/ + +# Cython debug symbols +cython_debug/ + +# Prerequisites +*.d + +# Object files +*.o +*.ko +*.obj +*.elf + +# Linker output +*.ilk +*.map +*.exp + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +*.su +*.idb +*.pdb + +# Kernel Module Compile Results +*.mod* +*.cmd +.tmp_versions/ +modules.order +Module.symvers +Mkfile.old +dkms.con \ No newline at end of file diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/Kconfig b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/Kconfig new file mode 100644 index 000000000..feab35037 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/Kconfig @@ -0,0 +1,39 @@ +mainmenu "XIUOS Rt-thread Configuration" + +config ROOT_DIR + string + default "../../../.." + +config BSP_DIR + string + default "." + +config RT_Thread_DIR + string + default "../.." + +config RTT_DIR + string + default "../../rt-thread" + +config BOARD_K210_EVB + bool + select ARCH_RISCV64 + select ARCH_RISCV_FPU_S + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config APP_DIR + string + default "../../../../APP_Framework" + +source "$RTT_DIR/Kconfig" +source "base-drivers/Kconfig" +source "kendryte-sdk/Kconfig" +source "$RT_Thread_DIR/app_match_rt-thread/Kconfig" +source "$ROOT_DIR/APP_Framework/Kconfig" + +config __STACKSIZE__ + int "stack size for interrupt" + default 4096 diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/README.md b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/README.md new file mode 100644 index 000000000..710ac9476 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/README.md @@ -0,0 +1,11 @@ +## aiit-riscv64-boar编译说明 + +编译aiit-riscv64-boar，需要有RT-Thread的代码，因为aiit-riscv64-boar的sdk是以软件包方式，更新软件包在""目录执行一下语句： + + +如果在Linux平台下，可以先执行 + + scons --menuconfig + +退出后执行 + scons编译。 \ No newline at end of file diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/SConscript b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/SConscript new file mode 100644 index 000000000..3d15055d6 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/SConscript @@ -0,0 +1,13 @@ +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/SConstruct b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/SConstruct new file mode 100644 index 000000000..5da36ead2 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/SConstruct @@ -0,0 +1,65 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +# use ASPPCOM to replace ASCOM, ASPPCOM will use CFLAGS/CPPFLAGS with AS +env['ASCOM'] = env['ASPPCOM'] + +AddOption('--compiledb', + dest = 'compiledb', + action = 'store_true', + default = False, + help = 'generate compile_commands.json') + +if GetOption('compiledb'): + if int(SCons.__version__.split('.')[0]) >= 4: + env['COMPILATIONDB_USE_ABSPATH'] = True + env.Tool('compilation_db') + env.CompilationDatabase('compile_commands.json') + else: + print('Warning: --compiledb only support on SCons 4.0+') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) + +stack_size = 4096 + +stack_lds = open('link_stacksize.lds', 'w') +if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__') +stack_lds.write('__STACKSIZE__ = %d;' % stack_size) +stack_lds.close() + +# include more drivers +objs.extend(SConscript(os.getcwd() + '/../../app_match_rt-thread/SConscript')) + +# include APP_Framework/Framework +objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Framework/SConscript')) + +# include APP_Framework/Applications +objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SConscript')) + +# include APP_Framework/lib +objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript')) +# make a building +DoBuilding(TARGET, objs) diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/SConscript b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/SConscript new file mode 100644 index 000000000..c583d3016 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/main.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/main.c new file mode 100644 index 000000000..c20e84ef2 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/main.c @@ -0,0 +1,27 @@ +/* + * @Author: your name + * @Date: 2021-10-11 22:04:25 + * @LastEditTime: 2021-10-14 11:12:52 + * @LastEditors: Please set LastEditors + * @Description: In User Settings Edit + * @FilePath: \xiuos\Ubiquitous\RT_Thread\bsp\k210\applications\main.c + */ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. + */ + +#include + +int main(void) +{ + printf("Hello World\n"); + return 0; +} diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/Kconfig b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/Kconfig new file mode 100644 index 000000000..bff414ec8 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/Kconfig @@ -0,0 +1,284 @@ +menu "Board Drivers Config" + +config BSP_USING_UART_HS + bool "Enable High Speed UART" + default y + + +menu "General Purpose UARTs" +menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_TXD_PIN + int "uart1 TXD pin number" + default 20 + config BSP_UART1_RXD_PIN + int "uart1 RXD pin number" + default 21 + config BSP_UART1_RTS_PIN + int "uart1 RTS pin number (-1 for not used)" + default -1 + config BSP_UART1_CTS_PIN + int "uart1 CTS pin number (-1 for not used)" + default -1 + endif + +menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_TXD_PIN + int "uart2 TXD pin number" + default 28 + config BSP_UART2_RXD_PIN + int "uart2 RXD pin number" + default 27 + config BSP_UART2_RTS_PIN + int "uart2 RTS pin number (-1 for not used)" + default -1 + config BSP_UART2_CTS_PIN + int "uart2 CTS pin number (-1 for not used)" + default -1 + endif + +menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_TXD_PIN + int "uart3 TXD pin number" + default 22 + config BSP_UART3_RXD_PIN + int "uart3 RXD pin number" + default 23 + config BSP_UART3_RTS_PIN + int "uart3 RTS pin number (-1 for not used)" + default -1 + config BSP_UART3_CTS_PIN + int "uart3 CTS pin number (-1 for not used)" + default -1 + endif +endmenu + +config BSP_USING_I2C1 + bool "Enable I2C1 (GPIO0/1)" + select RT_USING_I2C + default n + +menuconfig BSP_USING_SPI1 + bool "Enable SPI1" + select RT_USING_SPI + default n +if BSP_USING_SPI1 + config BSP_USING_SPI1_AS_QSPI + bool + default n + config BSP_SPI1_CLK_PIN + int "spi1 clk pin number" + default 27 + config BSP_SPI1_D0_PIN + int "spi1 d0 pin number" + default 28 + config BSP_SPI1_D1_PIN + int "spi1 d1 pin number" + default 26 + if BSP_USING_SPI1_AS_QSPI + config BSP_SPI1_D2_PIN + int "spi1 d2 pin number" + default 32 + config BSP_SPI1_D3_PIN + int "spi1 d3 pin number" + default 33 + endif + menuconfig BSP_SPI1_USING_SS0 + bool "SPI1 Enable SS0(spi10 dev)" + default n + if BSP_SPI1_USING_SS0 + config BSP_SPI1_SS0_PIN + int "spi1 ss0 pin number" + default 29 + endif + menuconfig BSP_SPI1_USING_SS1 + bool "SPI1 Enable SS1(spi11 dev)" + default n + if BSP_SPI1_USING_SS1 + config BSP_SPI1_SS1_PIN + int "spi1 ss1 pin number" + default 8 + endif + menuconfig BSP_SPI1_USING_SS2 + bool "SPI1 Enable SS2(spi12 dev)" + default n + if BSP_SPI1_USING_SS2 + config BSP_SPI1_SS2_PIN + int "spi1 ss2 pin number" + default 26 + endif + menuconfig BSP_SPI1_USING_SS3 + bool "SPI1 Enable SS3(spi13 dev)" + default n + if BSP_SPI1_USING_SS3 + config BSP_SPI1_SS3_PIN + int "spi1 ss3 pin number" + default 27 + endif +endif + +menuconfig BSP_USING_LCD + bool "Enable LCD on SPI0" + default n + +if BSP_USING_LCD + config BSP_LCD_CS_PIN + int "CS pin number of 8080 interface" + default 36 + config BSP_LCD_WR_PIN + int "WR pin number of 8080 interface" + default 39 + config BSP_LCD_DC_PIN + int "DC pin number of 8080 interface" + default 38 + config BSP_LCD_RST_PIN + int "RESET pin number of 8080 interface (-1 for not used)" + default 37 + config BSP_LCD_BACKLIGHT_PIN + int "Backlight control pin number (-1 for not used)" + default -1 + choice + prompt "backlight active polarity" + default BSP_LCD_BACKLIGHT_ACTIVE_LOW + + config BSP_LCD_BACKLIGHT_ACTIVE_LOW + bool "lcd backlight on low level" + config BSP_LCD_BACKLIGHT_ACTIVE_HIGH + bool "lcd_backlight on high level" + endchoice + + config BSP_LCD_CLK_FREQ + int "Lcd max clk frequency" + default 15000000 + + choice + prompt "lcd scan direction" + default BSP_BOARD_KD233 + + config BSP_BOARD_KD233 + bool "board_kd233 lcd scan: DIR_YX_RLUD" + + config BSP_BOARD_K210_OPENMV_TEST + bool "board_k210_openmv lcd scan: DIR_YX_LRUD" + + config BSP_BOARD_USER + bool "board_user: user defined." + endchoice + + config BSP_LCD_X_MAX + int "LCD Height" + default 240 + config BSP_LCD_Y_MAX + int "LCD Width" + default 320 +endif + +menuconfig BSP_USING_SDCARD + bool "Enable SDCARD (spi1(ss0))" + select BSP_USING_SPI1 + select BSP_SPI1_USING_SS0 + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + select RT_USING_SPI_MSD + default n + + +menuconfig BSP_USING_DVP + bool "Enable DVP(camera)" + default n + +if BSP_USING_DVP + comment "The default pin assignment is based on the Maix Duino K210 development board" + config BSP_DVP_SCCB_SDA_PIN + int "SCCB SDA pin number for camera" + default 40 + config BSP_DVP_SCCB_SCLK_PIN + int "SCCB SCLK pin number for camera" + default 41 + config BSP_DVP_CMOS_RST_PIN + int "CMOS RST pin number for camera" + default 42 + config BSP_DVP_CMOS_VSYNC_PIN + int "CMOS VSYNC pin number for camera" + default 43 + config BSP_DVP_CMOS_PWDN_PIN + int "CMOS PWDN pin number for camera" + default 44 + config BSP_DVP_CMOS_XCLK_PIN + int "CMOS XCLK pin number for camera" + default 46 + config BSP_DVP_CMOS_PCLK_PIN + int "CMOS PCLK pin number for camera" + default 47 + config BSP_DVP_CMOS_HREF_PIN + int "CMOS HREF pin number for camera" + default 45 +endif + +if PKG_USING_RW007 + config RW007_SPIDEV_NAME + string "the SPIDEV rw007 driver on" + default "spi11" + config RW007_INT_BUSY_PIN + int "rw007 int pin for rw007" + default 7 + config RW007_RST_PIN + int "rw007 rst pin for rw007" + default 6 +endif + + + + +endmenu + +menuconfig BSP_USING_CH438 + bool "Enable CH438" + default y + +if BSP_USING_CH438 + config BSP_CH438_ALE_PIN + int "ale pin number for ch438" + default 23 + config BSP_CH438_NWR_PIN + int "nwr pin number for ch438" + default 24 + config BSP_CH438_NRD_PIN + int "nrd pin number for ch438" + default 25 + config BSP_CH438_D0_PIN + int "d0 pin number for ch438" + default 27 + config BSP_CH438_D1_PIN + int "d1 pin number for ch438" + default 28 + config BSP_CH438_D2_PIN + int "d2 pin number for ch438" + default 29 + config BSP_CH438_D3_PIN + int "d3 pin number for ch438" + default 30 + config BSP_CH438_D4_PIN + int "d4 pin number for ch438" + default 31 + config BSP_CH438_D5_PIN + int "d5 pin number for ch438" + default 32 + config BSP_CH438_D6_PIN + int "d6 pin number for ch438" + default 33 + config BSP_CH438_D7_PIN + int "d7 pin number for ch438" + default 34 + config BSP_CH438_INT_PIN + int "int pin number for ch438" + default 35 +endif diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/SConscript b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/SConscript new file mode 100644 index 000000000..c8e4768bb --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/SConscript @@ -0,0 +1,53 @@ +import os +import rtconfig +from building import * + +cwd = GetCurrentDir() +drv_path = cwd+"/../../../rt-thread/bsp/k210/driver/" +src = [ + 'board.c', + 'heap.c', + drv_path + 'drv_uart.c', + 'drv_interrupt.c', + 'drv_io_config.c', + 'dmalock.c' +] +CPPPATH = [cwd,drv_path] + +if GetDepend('RT_USING_PIN'): + src += ['drv_gpio.c'] + +if GetDepend('RT_USING_HWTIMER'): + src += [drv_path + 'drv_hw_timer.c'] + +if GetDepend('RT_USING_I2C'): + src += [drv_path + 'drv_i2c.c'] + +if GetDepend('RT_USING_SPI'): + src += ['drv_spi.c'] + +if GetDepend('RT_USING_PWM'): + src += [drv_path + 'drv_pwm.c'] + +if GetDepend('RT_USING_WDT'): + src += [drv_path + 'drv_wdt.c'] + +if GetDepend('BSP_USING_SDCARD'): + src += ['sdcard_port.c'] + +if GetDepend('BSP_USING_DVP'): + src += ['drv_dvp.c'] + +if GetDepend('BSP_USING_LCD'): + src += ['drv_lcd.c'] + src += ['drv_mpylcd.c'] + +if GetDepend('PKG_USING_RW007'): + src += ['rw007_port.c'] + +if GetDepend('BSP_USING_CH438'): + src += ['ch438.c'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/board.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/board.c new file mode 100644 index 000000000..1f258d2db --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/board.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#include + +#include "board.h" +#include "tick.h" + +#include "drv_uart.h" + +#include "encoding.h" +#include "fpioa.h" +#include "dmac.h" +#include "dmalock.h" + +void init_bss(void) +{ + unsigned int *dst; + + dst = &__bss_start; + while (dst < &__bss_end) + { + *dst++ = 0; + } +} + +void primary_cpu_entry(void) +{ + extern void entry(void); + + /* disable global interrupt */ + init_bss(); + rt_hw_interrupt_disable(); + entry(); +} + +#include +#include + +int freq(void) +{ + rt_uint64_t value = 0; + + value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL0); + rt_kprintf("PLL0: %d\n", value); + value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL1); + rt_kprintf("PLL1: %d\n", value); + value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL2); + rt_kprintf("PLL2: %d\n", value); + value = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU); + rt_kprintf("CPU : %d\n", value); + value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0); + rt_kprintf("APB0: %d\n", value); + value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB1); + rt_kprintf("APB1: %d\n", value); + value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB2); + rt_kprintf("APB2: %d\n", value); + value = sysctl_clock_get_freq(SYSCTL_CLOCK_HCLK); + rt_kprintf("HCLK: %d\n", value); + + value = clint_get_time(); + rt_kprintf("mtime: %d\n", value); + + return 0; +} +MSH_CMD_EXPORT(freq, show freq info); + +#ifdef RT_USING_SMP +extern int rt_hw_clint_ipi_enable(void); +#endif + +extern int io_config_init(void); + +void rt_hw_board_init(void) +{ + sysctl_pll_set_freq(SYSCTL_PLL0, 800000000UL); + sysctl_pll_set_freq(SYSCTL_PLL1, 400000000UL); + sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL); + sysctl_clock_set_threshold(SYSCTL_THRESHOLD_APB1, 2); + /* Init FPIOA */ + fpioa_init(); + + io_config_init(); + + /* Dmac init */ + dmac_init(); + dmalock_init(); + + /* initalize interrupt */ + rt_hw_interrupt_init(); + /* initialize hardware interrupt */ + rt_hw_uart_init(); + + rt_hw_tick_init(); + +#ifdef RT_USING_SMP + rt_hw_clint_ipi_enable(); +#endif + +#ifdef RT_USING_CONSOLE + /* set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif /* RT_USING_CONSOLE */ + +#ifdef RT_USING_HEAP + rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) RT_HW_HEAP_BEGIN, (rt_ubase_t) RT_HW_HEAP_END); + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} +void rt_hw_cpu_reset(void) +{ + sysctl->soft_reset.soft_reset = 1; + while(1); +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine); + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t usec) +{ + rt_uint32_t cycle = read_cycle(); + rt_uint32_t nop_all = usec * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / 1000000UL; + while (1) + { + if(read_cycle() - cycle >= nop_all) + break; + } +} diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/board.h b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/board.h new file mode 100644 index 000000000..9349e3586 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/board.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-5-30 Bernard the first version + */ + +#ifndef BOARD_H__ +#define BOARD_H__ + +#include "fpioa.h" +#include "platform.h" +#include + +extern unsigned int __bss_start; +extern unsigned int __bss_end; + +#define RT_HW_HEAP_BEGIN (void*)&__bss_end +#define RT_HW_HEAP_END (void*)(0x80000000 + 6 * 1024 * 1024) + +void rt_hw_board_init(void); + +#endif diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.c new file mode 100644 index 000000000..b080633b0 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.c @@ -0,0 +1,471 @@ +#include +#include +#include +#include +#include "board.h" +#include "ch438.h" +#include "sleep.h" + +static rt_sem_t ch438_sem; + +static rt_uint8_t offsetadd[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* Offset address of serial port number */ +rt_uint8_t RevLen ,Ch438Buff[8][BUFFSIZE],Ch438BuffPtr[8]; + +void CH438_INIT(void) +{ + CH438_set_output(); + gpiohs_set_drive_mode(FPIOA_CH438_NWR, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_NRD, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_ALE, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_485_DIR, GPIO_DM_OUTPUT); + + gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH); +} + +void CH438_PORT_INIT( rt_uint8_t ext_uart_no,rt_uint32_t BaudRate ) +{ + rt_uint32_t div; + rt_uint8_t DLL,DLM,dlab; + rt_uint8_t REG_LCR_ADDR; + rt_uint8_t REG_DLL_ADDR; + rt_uint8_t REG_DLM_ADDR; + rt_uint8_t REG_IER_ADDR; + rt_uint8_t REG_MCR_ADDR; + rt_uint8_t REG_FCR_ADDR; + rt_uint8_t REG_RBR_ADDR; + rt_uint8_t REG_THR_ADDR; + rt_uint8_t REG_IIR_ADDR; + + REG_LCR_ADDR = offsetadd[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offsetadd[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offsetadd[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offsetadd[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offsetadd[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offsetadd[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offsetadd[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data( REG_IER_ADDR, BIT_IER_RESET ); /* Reset the serial port */ + rt_thread_delay(50); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = ( Fpclk >> 4 ) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data( REG_DLL_ADDR, DLL ); /* Set baud rate */ + WriteCH438Data( REG_DLM_ADDR, DLM ); + WriteCH438Data( REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN ); /* Set FIFO mode */ + + WriteCH438Data( REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0 ); + + WriteCH438Data( REG_IER_ADDR, /*BIT_IER_IEMODEM | BIT_IER_IETHRE | BIT_IER_IELINES | */BIT_IER_IERECV ); + + WriteCH438Data( REG_MCR_ADDR, BIT_MCR_OUT2 ); + + WriteCH438Data(REG_FCR_ADDR,ReadCH438Data(REG_FCR_ADDR)| BIT_FCR_RFIFORST | BIT_FCR_TFIFORST); + +} + +static void CH438_set_output(void) +{ + gpiohs_set_drive_mode(FPIOA_CH438_D0, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D1, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D2, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D3, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D4, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D5, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D6, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D7, GPIO_DM_OUTPUT); + +} +static void CH438_set_input(void) +{ + gpiohs_set_drive_mode(FPIOA_CH438_D0, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D1, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D2, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D3, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D4, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D5, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D6, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D7, GPIO_DM_INPUT_PULL_UP); + +} + + +void set_485_input(rt_uint8_t ch_no) +{ + if(ch_no == 1) + gpiohs_set_pin(FPIOA_485_DIR, GPIO_PV_LOW); +} + +void set_485_output(rt_uint8_t ch_no) +{ + if(ch_no == 1) + gpiohs_set_pin(FPIOA_485_DIR, GPIO_PV_HIGH); +} + +rt_uint8_t ReadCH438Data( rt_uint8_t addr ) +{ + rt_uint8_t dat; + + gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH); + + CH438_set_output(); + usleep(1); + + if(addr &0x80) gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_LOW); + if(addr &0x40) gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_LOW); + if(addr &0x20) gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_LOW); + if(addr &0x10) gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_LOW); + if(addr &0x08) gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_LOW); + if(addr &0x04) gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_LOW); + if(addr &0x02) gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_LOW); + if(addr &0x01) gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_LOW); + + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_LOW); + + usleep(1); + + CH438_set_input(); + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_LOW); + + usleep(1); + + dat = 0; + if (gpiohs_get_pin(FPIOA_CH438_D7)) dat |= 0x80; + if (gpiohs_get_pin(FPIOA_CH438_D6)) dat |= 0x40; + if (gpiohs_get_pin(FPIOA_CH438_D5)) dat |= 0x20; + if (gpiohs_get_pin(FPIOA_CH438_D4)) dat |= 0x10; + if (gpiohs_get_pin(FPIOA_CH438_D3)) dat |= 0x08; + if (gpiohs_get_pin(FPIOA_CH438_D2)) dat |= 0x04; + if (gpiohs_get_pin(FPIOA_CH438_D1)) dat |= 0x02; + if (gpiohs_get_pin(FPIOA_CH438_D0)) dat |= 0x01; + + gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH); + + usleep(1); + + return dat; + +} + + +static void WriteCH438Data( rt_uint8_t addr, rt_uint8_t dat) +{ + gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH); + + CH438_set_output(); + usleep(1); + + if(addr &0x80) gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_LOW); + if(addr &0x40) gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_LOW); + if(addr &0x20) gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_LOW); + if(addr &0x10) gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_LOW); + if(addr &0x08) gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_LOW); + if(addr &0x04) gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_LOW); + if(addr &0x02) gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_LOW); + if(addr &0x01) gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_LOW); + + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_LOW); + usleep(1); + + if(dat &0x80) gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_LOW); + if(dat &0x40) gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_LOW); + if(dat &0x20) gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_LOW); + if(dat &0x10) gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_LOW); + if(dat &0x08) gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_LOW); + if(dat &0x04) gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_LOW); + if(dat &0x02) gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_LOW); + if(dat &0x01) gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_LOW); + + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_LOW); + + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH); + + usleep(1); + + CH438_set_input(); + + return; +} + + +static void WriteCH438Block( rt_uint8_t mAddr, rt_uint8_t mLen, rt_uint8_t *mBuf ) +{ + + while ( mLen -- ) + WriteCH438Data( mAddr, *mBuf++ ); + +} + + +// void CH438UARTSend( rt_uint8_t ext_uart_no,rt_uint8_t *Data, rt_uint8_t Num ) +// { +// rt_uint8_t REG_LSR_ADDR,REG_THR_ADDR; + +// REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR; +// REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR; + +// while( 1 ) +// { + +// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_TEMT ) == 0 ); + +// if( Num <= 128 ) +// { + +// WriteCH438Block( REG_THR_ADDR, Num, Data ); + +// break; + +// } + +// else +// { + +// WriteCH438Block( REG_THR_ADDR, 128, Data ); + +// Num -= 128; + +// Data += 128; + +// } + +// } +// } + + + +// rt_uint8_t CH438UARTRcv( rt_uint8_t ext_uart_no, rt_uint8_t* buf ) +// { +// rt_uint8_t RcvNum = 0; +// rt_uint8_t dat = 0; +// rt_uint8_t REG_LSR_ADDR,REG_RBR_ADDR; +// rt_uint8_t *p_rev; + +// p_rev = buf; + +// REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR; +// REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR; + +// { + +// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0 ); + +// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) +// { +// dat = ReadCH438Data( REG_RBR_ADDR ); + +// Ch438Buff[ext_uart_no][Ch438BuffPtr[ext_uart_no]] = dat; + +// Ch438BuffPtr[ext_uart_no] = Ch438BuffPtr[ext_uart_no] + 1; +// if (Ch438BuffPtr[ext_uart_no] == BUFFSIZE) +// Ch438BuffPtr[ext_uart_no] = 0; + +// RcvNum = RcvNum + 1; + +// } +// } +// return( RcvNum ); +// } + +static rt_err_t rt_extuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + + rt_uint32_t baud_rate = cfg->baud_rate; + uint16_t port = cfg->reserved; + CH438_PORT_INIT(port, baud_rate); + +} + +static rt_err_t extuart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + break; + + case RT_DEVICE_CTRL_SET_INT: + break; + } + + return (RT_EOK); +} + +static int drv_extuart_putc(struct rt_serial_device *serial, char c) +{ + uint16_t ext_uart_no = serial->config.reserved; + + rt_uint8_t REG_LSR_ADDR,REG_THR_ADDR; + + REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR; + REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR; + + while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_TEMT ) == 0 ); + + WriteCH438Block( REG_THR_ADDR, 1, &c ); +} + +static int drv_extuart_getc(struct rt_serial_device *serial) +{ + rt_uint8_t dat = 0; + rt_uint8_t REG_LSR_ADDR,REG_RBR_ADDR; + + uint16_t ext_uart_no = serial->config.reserved;///< get extern uart port + + REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR; + REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR; + + while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0 ); + + // while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) + // { + dat = ReadCH438Data( REG_RBR_ADDR ); + // } + + return( dat ); +} + +const struct rt_uart_ops extuart_ops = +{ + rt_extuart_configure, + extuart_control, + drv_extuart_putc, + drv_extuart_getc, + RT_NULL +}; + +static plic_irq_callback_t Ch438Irq(void *parameter) +{ + rt_sem_release(&ch438_sem); +} + +void Ch438InitDefault(void) +{ + xs_uint8 i, dat; + xs_err_t flag; + + flag = rt_sem_init(&ch438_sem, "sem_438",0,RT_IPC_FLAG_FIFO); + if (flag != RT_EOK) + { + rt_kprintf("ch438.drv create sem failed .\n"); + return ; + } + + gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_pin_edge(FPIOA_CH438_INT,GPIO_PE_FALLING); + gpiohs_irq_register(FPIOA_CH438_INT,1,Ch438Irq,0); + + CH438_INIT(); +} + +int rt_hw_ch438_init(void) +{ + struct rt_serial_device *extserial; + struct device_uart *extuart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + +// #ifdef BSP_USING_UART1 + { + static struct rt_serial_device extserial0; + static struct device_uart extuart0; + + extserial = &extserial0; + extuart = &extuart0; + + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = UART_DEFAULT_BAUDRATE; + extserial->config.reserved = 0; ///< extern uart port + + // extuart->hw_base = UART1_BASE_ADDR; + // extuart->irqno = IRQN_UART1_INTERRUPT; + + // _uart_init(UART_DEVICE_1); + + rt_hw_serial_register(extserial, + "extuart_dev0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + } +// #endif + +// #ifdef BSP_USING_UART2 + // { + // static struct rt_serial_device serial2; + // static struct device_uart uart2; + + // serial = &serial2; + // uart = &uart2; + + // serial->ops = &_uart_ops; + // serial->config = config; + // serial->config.baud_rate = UART_DEFAULT_BAUDRATE; + + // uart->hw_base = UART2_BASE_ADDR; + // uart->irqno = IRQN_UART2_INTERRUPT; + + // _uart_init(UART_DEVICE_2); + + // rt_hw_serial_register(serial, + // "uart2", + // RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + // uart); + // } +// #endif + +// #ifdef BSP_USING_UART3 + // { + // static struct rt_serial_device serial3; + // static struct device_uart uart3; + + // serial = &serial3; + // uart = &uart3; + + // serial->ops = &_uart_ops; + // serial->config = config; + // serial->config.baud_rate = UART_DEFAULT_BAUDRATE; + + // uart->hw_base = UART3_BASE_ADDR; + // uart->irqno = IRQN_UART3_INTERRUPT; + + // _uart_init(UART_DEVICE_3); + + // rt_hw_serial_register(serial, + // "uart3", + // RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + // uart); + // } +// #endif + Ch438InitDefault(); + return 0; +} + diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.h b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.h new file mode 100755 index 000000000..a9284d064 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.h @@ -0,0 +1,251 @@ +#ifndef __CH438_H_ +#define __CH438_H_ + +#include "board.h" + +#define BUFFSIZE 255 + +/******************************************************************************************/ + +/* CH438serial port0 register address */ + +#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */ +#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */ +#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */ +#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */ +#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */ +#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */ +#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */ +#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */ +#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */ +#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */ +#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */ + +/* CH438serial port1 register address */ + +#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */ +#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */ +#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */ +#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */ +#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */ +#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */ +#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */ +#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */ +#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */ +#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */ +#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port2 register address */ + +#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */ +#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */ +#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */ +#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */ +#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */ +#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */ +#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */ +#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */ +#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */ +#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */ +#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port3 register address */ + +#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */ +#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */ +#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */ +#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */ +#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */ +#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */ +#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */ +#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */ +#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */ +#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */ +#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port4 register address */ + +#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */ +#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */ +#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */ +#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */ +#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */ +#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */ +#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */ +#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */ +#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */ +#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */ +#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port5 register address */ + +#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */ +#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */ +#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */ +#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */ +#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */ +#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */ +#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */ +#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */ +#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */ +#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */ +#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port6 register address */ + +#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */ +#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */ +#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */ +#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */ +#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */ +#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */ +#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */ +#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */ +#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */ +#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */ +#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port7 register address */ + +#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */ +#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */ +#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */ +#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */ +#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */ +#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */ +#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */ +#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */ +#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */ +#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */ +#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */ + + +#define REG_SSR_ADDR 0x4F /* pecial status register address */ + + +/* IER register bit */ + +#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */ +#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */ +#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */ +#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */ +#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */ +#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */ +#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */ +#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */ + +/* IIR register bit */ + +#define BIT_IIR_FIFOENS1 0x80 +#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */ + +/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted, +1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */ +#define BIT_IIR_IID3 0x08 +#define BIT_IIR_IID2 0x04 +#define BIT_IIR_IID1 0x02 +#define BIT_IIR_NOINT 0x01 + +/* FCR register bit */ + +/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */ +#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ +#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ + +#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */ + +/* LCR register bit */ + +#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */ +#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/ + +/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */ +#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */ +#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */ + +#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */ +#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */ + +/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */ +#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */ +#define BIT_LCR_WORDSZ0 0x01 + +/* MCR register bit */ + +#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */ +#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */ +#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */ +#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */ +#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */ +#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */ + +/* LSR register bit */ + +#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */ +#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */ +#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/ +#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/ +#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */ +#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */ +#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */ +#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */ + +/* MSR register bit */ + +#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */ +#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */ +#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */ +#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */ +#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */ +#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */ +#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */ +#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */ + +/* Interrupt status code */ + +#define INT_NOINT 0x01 /* There is no interruption */ +#define INT_THR_EMPTY 0x02 /* THR empty interruption */ +#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */ +#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */ +#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */ +#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */ + +#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */ + + +#define Fpclk 1843200 /* Define the internal clock frequency */ + + +void CH438_INIT(void); +void CH438_PORT_INIT( rt_uint8_t ext_uart_no,rt_uint32_t BaudRate ); +rt_uint8_t ReadCH438Data( rt_uint8_t addr ); +void CH438UARTSend( rt_uint8_t ext_uart_no,rt_uint8_t *Data, rt_uint8_t Num ); +rt_uint8_t CH438UARTRcv( rt_uint8_t ext_uart_no, rt_uint8_t* buf ); +void set_485_input(rt_uint8_t ch_no); +void set_485_output(rt_uint8_t ch_no); + + +static void CH438_set_output(void); +static void CH438_set_input(void); +static void WriteCH438Data( rt_uint8_t addr, rt_uint8_t dat); +static void WriteCH438Block( rt_uint8_t mAddr, rt_uint8_t mLen, rt_uint8_t *mBuf ); + +#endif diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/dmalock.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/dmalock.c new file mode 100644 index 000000000..880ab7d8f --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/dmalock.c @@ -0,0 +1,90 @@ + +/* Copyright Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "dmalock.h" + +struct dmac_host +{ + struct rt_semaphore sem; + struct rt_mutex mutex; + uint8_t channel_used[DMAC_CHANNEL_COUNT]; + char *channel_name[DMAC_CHANNEL_COUNT]; +}; + +static struct dmac_host _dmac_host; + +void dmalock_init(void) +{ + rt_sem_init(&_dmac_host.sem, "dma_sem", DMAC_CHANNEL_COUNT, RT_IPC_FLAG_FIFO); + rt_mutex_init(&_dmac_host.mutex, "dma_mutex", RT_IPC_FLAG_FIFO); + for (int i = 0; i < DMAC_CHANNEL_COUNT; i++) + { + _dmac_host.channel_used[i] = 0; + _dmac_host.channel_name[i] = NULL; + } +} + +int _dmalock_sync_take(dmac_channel_number_t *chn, int timeout_ms, const char *name) +{ + rt_err_t result; + + *chn = DMAC_CHANNEL_MAX; + result = rt_sem_take(&_dmac_host.sem, timeout_ms); + if (result == RT_EOK) + { + rt_mutex_take(&_dmac_host.mutex, RT_WAITING_FOREVER); + for (int i = 0; i < DMAC_CHANNEL_COUNT; i++) + { + if (_dmac_host.channel_used[i] == 0) + { + _dmac_host.channel_used[i] = 1; + _dmac_host.channel_name[i] = name; + *chn = i; + break; + } + } + rt_mutex_release(&_dmac_host.mutex); + } + return result; +} + +void dmalock_release(dmac_channel_number_t chn) +{ + if (chn >= DMAC_CHANNEL_MAX) + return; + _dmac_host.channel_name[chn] = NULL; + _dmac_host.channel_used[chn] = 0; + rt_sem_release(&_dmac_host.sem); +} + +static void dma_ch_info(int argc, char **argv) +{ + uint32_t cnt = 0; + + for (int i = 0; i < DMAC_CHANNEL_COUNT; i++) + { + if (_dmac_host.channel_used[i] != 0) + { + rt_kprintf("dma_ch%d is using by func [%s]\n", i, _dmac_host.channel_name[i]); + cnt++; + } + } + + if(cnt == 0) + rt_kprintf(" no dma_ch is using.\n"); +} +MSH_CMD_EXPORT(dma_ch_info, list dma channel informationn.); \ No newline at end of file diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/dmalock.h b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/dmalock.h new file mode 100644 index 000000000..bca6a0d24 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/dmalock.h @@ -0,0 +1,14 @@ +#ifndef __DMALOCK_H +#define __DMALOCK_H + +#include +#include +#include + +#define dmalock_sync_take(x,y) _dmalock_sync_take(x, y, __func__) + +void dmalock_init(void); +int _dmalock_sync_take(dmac_channel_number_t *chn, int timeout_ms, const char *name); +void dmalock_release(dmac_channel_number_t chn); + +#endif diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_dvp.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_dvp.c new file mode 100644 index 000000000..6aad225ce --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_dvp.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-27 tianchunyu the first version + */ + + +#include +#include + +#ifdef BSP_USING_DVP +#include +#define DRV_DEBUG +#define LOG_TAG "drv.dvp" +#define DBG_LVL DBG_LOG +#include + +static struct kendryte_dvp rt_dvp = {0}; +static void (*dvp_irq_callback)(void) = NULL; +/* +the camera starts transfering photos +*/ + +static int on_irq_dvp(void* ctx) +{ + if (dvp_get_interrupt(DVP_STS_FRAME_FINISH)) + { + rt_dvp_stop(); + dvp_clear_interrupt(DVP_STS_FRAME_FINISH); + (*dvp_irq_callback)(); + } + return 0; +} + + +void rt_dvp_start(uint32_t pData, uint32_t Length) +{ + dvp_set_display_addr(pData); + dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 1); + dvp_start_convert(); +} + +/* +the camera stops transfering photos +*/ +void rt_dvp_stop(void) +{ + dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 0); +} + + +static rt_err_t rt_dvp_init(rt_device_t dev) +{ + //sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL); + RT_ASSERT(dev != RT_NULL); + rt_err_t result = RT_EOK; + /* Init DVP IO map and function settings io pin serial number depends on schematic diagram + initialize io in io_config_init function*/ + /*ov2640 dvp interface initialize*/ + dvp_init(8); + dvp_set_xclk_rate(24000000); + dvp_enable_burst(); + dvp_set_output_enable(0, 1); + dvp_set_output_enable(1, 1); + dvp_set_image_format(DVP_CFG_RGB_FORMAT);//////////////// + dvp_set_image_size(320, 240); // default + dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 0); + dvp_disable_auto(); + plic_set_priority(IRQN_DVP_INTERRUPT, 1); + plic_irq_register(IRQN_DVP_INTERRUPT, on_irq_dvp, NULL); + plic_irq_enable(IRQN_DVP_INTERRUPT); + dvp_clear_interrupt(DVP_STS_FRAME_FINISH); + LOG_I("dvp initialize success"); + return result; +} + +static rt_err_t rt_dvp_open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_err_t rt_dvp_close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_err_t rt_dvp_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_size_t rt_dvp_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_size_t rt_dvp_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +rt_err_t rt_set_irq_dvp_callback_hander(void (*p)(void)) +{ + if(NULL == p) + { + LOG_E("set irq dcmi callback hander is NULL"); + return RT_ERROR; + } + dvp_irq_callback = p; + return RT_EOK; + +} +int kendryte_dvp_init(void) +{ + int ret = 0; + rt_device_t dvp_dev = RT_NULL; + rt_dvp.dev.parent.type = RT_Device_Class_Miscellaneous; + rt_dvp.dev.parent.init = rt_dvp_init; + rt_dvp.dev.parent.open = rt_dvp_open; + rt_dvp.dev.parent.close = rt_dvp_close; + rt_dvp.dev.parent.read = rt_dvp_read; + rt_dvp.dev.parent.write = rt_dvp_write; + rt_dvp.dev.parent.control = rt_dvp_control; + rt_dvp.dev.parent.user_data = RT_NULL; + ret = rt_device_register(&rt_dvp.dev.parent, "dvp", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + if(ret != RT_EOK) + { + LOG_E("dvp register fail!!\n\r"); + return -RT_ERROR; + } + LOG_I("dvp register successfully"); + dvp_dev = rt_device_find("dvp"); + if (dvp_dev == RT_NULL) + { + LOG_E("can't find dvp device!"); + return RT_ERROR; + } + ret = rt_device_open(dvp_dev, RT_DEVICE_FLAG_RDWR); + if(ret != RT_EOK) + { + LOG_E("can't open dvp device!"); + return RT_ERROR; + } + LOG_I("dvp open successfully"); + return RT_EOK; +} +INIT_BOARD_EXPORT(kendryte_dvp_init); +#endif + + + + + diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_dvp.h b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_dvp.h new file mode 100644 index 000000000..54c4539b4 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_dvp.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-27 tianchunyu the first version +*/ + +#ifndef __DRV_DVP_H__ +#define __DRV_DVP_H__ +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct rt_dvp_device +{ + struct rt_device parent; +}; + +struct kendryte_dvp +{ + struct rt_dvp_device dev; +}; + +extern void rt_dvp_start(uint32_t pData, uint32_t Length); +extern void rt_dvp_stop(void); +extern rt_err_t rt_set_irq_dvp_callback_hander(void (*p)(void)); + + + + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_gpio.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_gpio.c new file mode 100644 index 000000000..3054a5d3b --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_gpio.c @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-19 ZYH first version + */ + +#include +#include +#include +#include +#include "drv_gpio.h" +#include "drv_io_config.h" +#include +#include +#include +#include + +#define DBG_ENABLE +#define DBG_TAG "PIN" +#define DBG_LVL DBG_WARNING +#define DBG_COLOR +#include + +#define FUNC_GPIOHS(n) (FUNC_GPIOHS0 + n) + +static short pin_alloc_table[FPIOA_NUM_IO]; +static uint32_t free_pin = 0; + +static int alloc_pin_channel(rt_base_t pin_index) +{ + if(free_pin == 32) + { + LOG_E("no free gpiohs channel to alloc"); + return -1; + } + + if(pin_alloc_table[pin_index] != -1) + { + LOG_W("already alloc gpiohs channel for pin %d", pin_index); + return pin_alloc_table[pin_index]; + } + + pin_alloc_table[pin_index] = free_pin; + free_pin++; + + fpioa_set_function(pin_index, FUNC_GPIOHS(pin_alloc_table[pin_index])); + return pin_alloc_table[pin_index]; +} + +int get_pin_channel(rt_base_t pin_index) +{ + return pin_alloc_table[pin_index]; +} + +static void free_pin_channel(rt_base_t pin_index) +{ + if(pin_alloc_table[pin_index] == -1) + { + LOG_W("free error:not alloc gpiohs channel for pin %d", pin_index); + return; + } + pin_alloc_table[pin_index] = -1; + free_pin--; +} + + +static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode) +{ + int pin_channel = get_pin_channel(pin); + if(pin_channel == -1) + { + pin_channel = alloc_pin_channel(pin); + if(pin_channel == -1) + { + return; + } + } + + switch (mode) + { + case PIN_MODE_OUTPUT: + gpiohs_set_drive_mode(pin_channel, GPIO_DM_OUTPUT); + break; + case PIN_MODE_INPUT: + gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT); + break; + case PIN_MODE_INPUT_PULLUP: + gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT_PULL_UP); + break; + case PIN_MODE_INPUT_PULLDOWN: + gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT_PULL_DOWN); + break; + default: + LOG_E("Not support mode %d", mode); + break; + } +} + +static void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value) +{ + int pin_channel = get_pin_channel(pin); + if(pin_channel == -1) + { + LOG_E("pin %d not set mode", pin); + return; + } + gpiohs_set_pin(pin_channel, value == PIN_HIGH ? GPIO_PV_HIGH : GPIO_PV_LOW); +} + +static int drv_pin_read(struct rt_device *device, rt_base_t pin) +{ + int pin_channel = get_pin_channel(pin); + if(pin_channel == -1) + { + LOG_E("pin %d not set mode", pin); + return -1; + } + return gpiohs_get_pin(pin_channel) == GPIO_PV_HIGH ? PIN_HIGH : PIN_LOW; +} + +static struct +{ + void (*hdr)(void *args); + void* args; + gpio_pin_edge_t edge; +} irq_table[32]; + +static void pin_irq(int vector, void *param) +{ + int pin_channel = vector - IRQN_GPIOHS0_INTERRUPT; + if(irq_table[pin_channel].edge & GPIO_PE_FALLING) + { + set_gpio_bit(gpiohs->fall_ie.u32, pin_channel, 0); + set_gpio_bit(gpiohs->fall_ip.u32, pin_channel, 1); + set_gpio_bit(gpiohs->fall_ie.u32, pin_channel, 1); + } + + if(irq_table[pin_channel].edge & GPIO_PE_RISING) + { + set_gpio_bit(gpiohs->rise_ie.u32, pin_channel, 0); + set_gpio_bit(gpiohs->rise_ip.u32, pin_channel, 1); + set_gpio_bit(gpiohs->rise_ie.u32, pin_channel, 1); + } + + if(irq_table[pin_channel].edge & GPIO_PE_LOW) + { + set_gpio_bit(gpiohs->low_ie.u32, pin_channel, 0); + set_gpio_bit(gpiohs->low_ip.u32, pin_channel, 1); + set_gpio_bit(gpiohs->low_ie.u32, pin_channel, 1); + } + + if(irq_table[pin_channel].edge & GPIO_PE_HIGH) + { + set_gpio_bit(gpiohs->high_ie.u32, pin_channel, 0); + set_gpio_bit(gpiohs->high_ip.u32, pin_channel, 1); + set_gpio_bit(gpiohs->high_ie.u32, pin_channel, 1); + } + if(irq_table[pin_channel].hdr) + { + irq_table[pin_channel].hdr(irq_table[pin_channel].args); + } +} + +static rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + int pin_channel = get_pin_channel(pin); + char irq_name[10]; + if(pin_channel == -1) + { + LOG_E("pin %d not set mode", pin); + return -RT_ERROR; + } + irq_table[pin_channel].hdr = hdr; + irq_table[pin_channel].args = args; + switch (mode) + { + case PIN_IRQ_MODE_RISING: + irq_table[pin_channel].edge = GPIO_PE_RISING; + break; + case PIN_IRQ_MODE_FALLING: + irq_table[pin_channel].edge = GPIO_PE_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + irq_table[pin_channel].edge = GPIO_PE_BOTH; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + irq_table[pin_channel].edge = GPIO_PE_LOW; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + irq_table[pin_channel].edge = GPIO_PE_HIGH; + break; + default: + break; + } + gpiohs_set_pin_edge(pin_channel, irq_table[pin_channel].edge); + rt_snprintf(irq_name, sizeof irq_name, "pin%d", pin); + rt_hw_interrupt_install(IRQN_GPIOHS0_INTERRUPT + pin_channel, pin_irq, RT_NULL, irq_name); + + return RT_EOK; +} + +static rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_err_t ret = RT_EOK; + + int pin_channel = get_pin_channel(pin); + if(pin_channel == -1) + { + LOG_E("pin %d not set mode", pin); + return -RT_ERROR; + } + + irq_table[pin_channel].hdr = RT_NULL; + irq_table[pin_channel].args = RT_NULL; + + return ret; +} + +static rt_err_t drv_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + int pin_channel = get_pin_channel(pin); + + if(pin_channel == -1) + { + LOG_E("pin %d not set mode", pin); + return -RT_ERROR; + } + + if(enabled) + { + rt_hw_interrupt_umask(IRQN_GPIOHS0_INTERRUPT + pin_channel); + } + else + { + rt_hw_interrupt_mask(IRQN_GPIOHS0_INTERRUPT + pin_channel); + } + + return RT_EOK; +} + +const static struct rt_pin_ops drv_pin_ops = +{ + drv_pin_mode, + drv_pin_write, + drv_pin_read, + + drv_pin_attach_irq, + drv_pin_detach_irq, + drv_pin_irq_enable +}; + +int rt_hw_pin_init(void) +{ + rt_err_t ret = RT_EOK; + memset(pin_alloc_table, 0xff, sizeof pin_alloc_table); + free_pin = GPIO_ALLOC_START; + ret = rt_device_pin_register("pin", &drv_pin_ops, RT_NULL); + + return ret; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_gpio.h b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_gpio.h new file mode 100644 index 000000000..1b4cf4e21 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_gpio.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-19 ZYH first version + */ + +#ifndef DRV_GPIO_H__ +#define DRV_GPIO_H__ + +int rt_hw_pin_init(void); + +#endif \ No newline at end of file diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_interrupt.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_interrupt.c new file mode 100644 index 000000000..62e899dba --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_interrupt.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-19 ZYH first version + */ + +#include + +void plic_irq_handle(plic_irq_t irq) +{ + plic_instance_t (*plic_instance)[IRQN_MAX] = plic_get_instance(); + if (plic_instance[0][irq].callback) + { + plic_instance[0][irq].callback( + plic_instance[0][irq].ctx); + } + else if (plic_instance[1][irq].callback) + { + plic_instance[1][irq].callback( + plic_instance[1][irq].ctx); + } +} + diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.c new file mode 100644 index 000000000..b2a0a5a3d --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.c @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-19 ZYH first version + */ + +#include +#include +#include +#include + +#define HS_GPIO(n) (FUNC_GPIOHS0 + n) + +#define IOCONFIG(pin,func) {pin, func, #func} + +static struct io_config +{ + int io_num; + fpioa_function_t func; + const char * func_name; +} io_config[] = +{ +#ifdef BSP_USING_LCD + IOCONFIG(BSP_LCD_CS_PIN, FUNC_SPI0_SS0), /* LCD CS PIN */ + IOCONFIG(BSP_LCD_WR_PIN, FUNC_SPI0_SCLK), /* LCD WR PIN */ + IOCONFIG(BSP_LCD_DC_PIN, HS_GPIO(LCD_DC_PIN)), /* LCD DC PIN */ +#if BSP_LCD_RST_PIN >= 0 + IOCONFIG(BSP_LCD_RST_PIN, HS_GPIO(LCD_RST_PIN)), /* LCD RESET PIN */ +#endif +#if BSP_LCD_BACKLIGHT_PIN >= 0 + IOCONFIG(BSP_LCD_BACKLIGHT_PIN, HS_GPIO(LCD_BACKLIGHT_PIN)), /* LCD BACKLIGHT PIN */ +#endif +#endif + +#ifdef BSP_USING_DVP + IOCONFIG(BSP_DVP_SCCB_SDA_PIN, FUNC_SCCB_SDA), + IOCONFIG(BSP_DVP_SCCB_SCLK_PIN, FUNC_SCCB_SCLK), + IOCONFIG(BSP_DVP_CMOS_RST_PIN, FUNC_CMOS_RST), + IOCONFIG(BSP_DVP_CMOS_VSYNC_PIN, FUNC_CMOS_VSYNC), + IOCONFIG(BSP_DVP_CMOS_PWDN_PIN, FUNC_CMOS_PWDN), + IOCONFIG(BSP_DVP_CMOS_XCLK_PIN, FUNC_CMOS_XCLK), + IOCONFIG(BSP_DVP_CMOS_PCLK_PIN, FUNC_CMOS_PCLK), + IOCONFIG(BSP_DVP_CMOS_HREF_PIN, FUNC_CMOS_HREF), +#endif + +#ifdef BSP_USING_SPI1 + IOCONFIG(BSP_SPI1_CLK_PIN, FUNC_SPI1_SCLK), + IOCONFIG(BSP_SPI1_D0_PIN, FUNC_SPI1_D0), + IOCONFIG(BSP_SPI1_D1_PIN, FUNC_SPI1_D1), +#ifdef BSP_USING_SPI1_AS_QSPI + IOCONFIG(BSP_SPI1_D2_PIN, FUNC_SPI1_D2), + IOCONFIG(BSP_SPI1_D3_PIN, FUNC_SPI1_D3), +#endif +#ifdef BSP_SPI1_USING_SS0 + IOCONFIG(BSP_SPI1_SS0_PIN, HS_GPIO(SPI1_CS0_PIN)), +#endif +#ifdef BSP_SPI1_USING_SS1 + IOCONFIG(BSP_SPI1_SS1_PIN, HS_GPIO(SPI1_CS1_PIN)), +#endif +#ifdef BSP_SPI1_USING_SS2 + IOCONFIG(BSP_SPI1_SS2_PIN, HS_GPIO(SPI1_CS2_PIN)), +#endif +#ifdef BSP_SPI1_USING_SS3 + IOCONFIG(BSP_SPI1_SS3_PIN, HS_GPIO(SPI1_CS3_PIN)), +#endif +#endif + +#ifdef BSP_USING_UART1 + IOCONFIG(BSP_UART1_TXD_PIN, FUNC_UART1_TX), + IOCONFIG(BSP_UART1_RXD_PIN, FUNC_UART1_RX), + #if BSP_UART1_RTS_PIN >= 0 + IOCONFIG(BSP_UART1_RTS_PIN, FUNC_UART1_RTS), + #endif + #if BSP_UART1_CTS_PIN >= 0 + IOCONFIG(BSP_UART1_CTS_PIN, FUNC_UART1_CTS), + #endif +#endif +#ifdef BSP_USING_UART2 + IOCONFIG(BSP_UART2_TXD_PIN, FUNC_UART2_TX), + IOCONFIG(BSP_UART2_RXD_PIN, FUNC_UART2_RX), + #if BSP_UART2_RTS_PIN >= 0 + IOCONFIG(BSP_UART2_RTS_PIN, FUNC_UART2_RTS), + #endif + #if BSP_UART2_CTS_PIN >= 0 + IOCONFIG(BSP_UART2_CTS_PIN, FUNC_UART2_CTS), + #endif +#endif +#ifdef BSP_USING_UART3 + IOCONFIG(BSP_UART3_TXD_PIN, FUNC_UART3_TX), + IOCONFIG(BSP_UART3_RXD_PIN, FUNC_UART3_RX), + #if BSP_UART3_RTS_PIN >= 0 + IOCONFIG(BSP_UART3_RTS_PIN, FUNC_UART3_RTS), + #endif + #if BSP_UART3_CTS_PIN >= 0 + IOCONFIG(BSP_UART3_CTS_PIN, FUNC_UART3_CTS), + #endif +#endif +#ifdef BSP_USING_I2C0 + IOCONFIG(BSP_I2C0_SCL_PIN, FUNC_I2C0_SCLK), + IOCONFIG(BSP_I2C0_SDA_PIN, FUNC_I2C0_SDA), +#endif +#ifdef BSP_USING_I2C1 + IOCONFIG(BSP_I2C1_SCL_PIN, FUNC_I2C1_SCLK), + IOCONFIG(BSP_I2C1_SDA_PIN, FUNC_I2C1_SDA), +#endif +#ifdef BSP_USING_I2C2 + IOCONFIG(BSP_I2C2_SCL_PIN, FUNC_I2C2_SCLK), + IOCONFIG(BSP_I2C2_SDA_PIN, FUNC_I2C2_SDA), +#endif +#ifdef BSP_USING_I2S0 + IOCONFIG(BSP_I2S0_OUT_D1_PIN, FUNC_I2S0_OUT_D1), + IOCONFIG(BSP_I2S0_WS_PIN, FUNC_I2S0_WS), + IOCONFIG(BSP_I2S0_SCLK_PIN, FUNC_I2S0_SCLK), +#endif +#ifdef BSP_USING_I2S1 + IOCONFIG(BSP_I2S1_IN_D0_PIN, FUNC_I2S1_IN_D0), + IOCONFIG(BSP_I2S1_WS_PIN, FUNC_I2S1_WS), + IOCONFIG(BSP_I2S1_SCLK_PIN, FUNC_I2S1_SCLK), +#endif +#ifdef BSP_USING_I2S2 + IOCONFIG(BSP_I2S2_OUT_D1_PIN, FUNC_I2S2_OUT_D1), + IOCONFIG(BSP_I2S2_WS_PIN, FUNC_I2S2_WS), + IOCONFIG(BSP_I2S2_SCLK_PIN, FUNC_I2S2_SCLK), +#endif + +#ifdef BSP_PWM_CHN0_ENABLE + IOCONFIG(BSP_PWM_CHN0_PIN, FUNC_TIMER2_TOGGLE1), +#endif +#ifdef BSP_PWM_CHN1_ENABLE + IOCONFIG(BSP_PWM_CHN1_PIN, FUNC_TIMER2_TOGGLE2), +#endif +#ifdef BSP_PWM_CHN2_ENABLE + IOCONFIG(BSP_PWM_CHN2_PIN, FUNC_TIMER2_TOGGLE3), +#endif +#ifdef BSP_PWM_CHN3_ENABLE + IOCONFIG(BSP_PWM_CHN3_PIN, FUNC_TIMER2_TOGGLE4), +#endif +}; + +static int print_io_config() +{ + int i; + rt_kprintf("IO Configuration Table\n"); + rt_kprintf("┌───────┬────────────────────────┐\n"); + rt_kprintf("│Pin │Function │\n"); + rt_kprintf("├───────┼────────────────────────┤\n"); + for(i = 0; i < sizeof io_config / sizeof io_config[0]; i++) + { + rt_kprintf("│%-2d │%-24.24s│\n", io_config[i].io_num, io_config[i].func_name); + } + rt_kprintf("└───────┴────────────────────────┘\n"); + return 0; +} +MSH_CMD_EXPORT_ALIAS(print_io_config, io, print io config); + +int io_config_init(void) +{ + int count = sizeof(io_config) / sizeof(io_config[0]); + int i; + +/* IO GroupA Power Supply Setting */ +#if defined(BSP_GROUPA_POWER_SUPPLY_3V3) + sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V33); + sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V33); + sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V33); +#else + sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18); + sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18); + sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18); +#endif + +/* IO GroupB Power Supply Setting */ +#if defined(BSP_GROUPB_POWER_SUPPLY_3V3) + sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V33); + sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V33); + sysctl_set_power_mode(SYSCTL_POWER_BANK5, SYSCTL_POWER_V33); +#else + sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V18); + sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V18); + sysctl_set_power_mode(SYSCTL_POWER_BANK5, SYSCTL_POWER_V18); +#endif + +/* IO GroupC Power Supply Setting */ +#if defined(BSP_GROUPC_POWER_SUPPLY_3V3) + sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V33); + sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V33); +#else + sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V18); + sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V18); +#endif + + for(i = 0; i < count; i++) + { + fpioa_set_function(io_config[i].io_num, io_config[i].func); + } + +#if defined(BSP_USING_DVP) || defined(BSP_USING_LCD) + sysctl_set_spi0_dvp_data(1); + sysctl_clock_enable(SYSCTL_CLOCK_AI); +#endif +} + +int io_config_used(int io_num) +{ + int count = sizeof(io_config) / sizeof(io_config[0]); + int i; + + for(i = 0; i < count; i++) + { + if (io_config[i].io_num == io_num) + break; + } + + return (i < count); +} diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.h b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.h new file mode 100644 index 000000000..3fa834b54 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-19 ZYH first version + */ + +#ifndef __DRV_IO_CONFIG_H__ +#define __DRV_IO_CONFIG_H__ + +#include + +enum HS_GPIO_CONFIG +{ +#ifdef BSP_USING_LCD + LCD_DC_PIN = 0, /* LCD DC PIN */ +#if BSP_LCD_RST_PIN >= 0 + LCD_RST_PIN, +#endif +#if BSP_LCD_BACKLIGHT_PIN >= 0 + LCD_BACKLIGHT_PIN, +#endif +#endif +#ifdef BSP_SPI1_USING_SS0 + SPI1_CS0_PIN, +#endif +#ifdef BSP_SPI1_USING_SS1 + SPI1_CS1_PIN, +#endif +#ifdef BSP_SPI1_USING_SS2 + SPI1_CS2_PIN, +#endif +#ifdef BSP_SPI1_USING_SS3 + SPI1_CS3_PIN, +#endif + +#ifdef BSP_USING_BRIDGE + SPI2_INT_PIN, + SPI2_READY_PIN, +#endif + GPIO_ALLOC_START /* index of gpio driver start */ +}; + +#define FPIOA_CH438_ALE 11 +#define FPIOA_CH438_NWR 12 +#define FPIOA_CH438_NRD 13 +#define FPIOA_CH438_D0 14 +#define FPIOA_CH438_D1 15 +#define FPIOA_CH438_D2 16 +#define FPIOA_CH438_D3 17 +#define FPIOA_CH438_D4 18 +#define FPIOA_CH438_D5 19 +#define FPIOA_CH438_D6 20 +#define FPIOA_CH438_D7 21 +#define FPIOA_CH438_INT 22 +#define FPIOA_485_DIR 23 + +extern int io_config_init(void); + +#endif diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_lcd.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_lcd.c new file mode 100644 index 000000000..933bd7290 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_lcd.c @@ -0,0 +1,550 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-12 ZYH first version + */ + + +#include + +#ifdef BSP_USING_LCD +#include +#define DBG_TAG "LCD" +#define DBG_LVL DBG_WARNING +#include + +#define NO_OPERATION 0x00 +#define SOFTWARE_RESET 0x01 +#define READ_ID 0x04 +#define READ_STATUS 0x09 +#define READ_POWER_MODE 0x0A +#define READ_MADCTL 0x0B +#define READ_PIXEL_FORMAT 0x0C +#define READ_IMAGE_FORMAT 0x0D +#define READ_SIGNAL_MODE 0x0E +#define READ_SELT_DIAG_RESULT 0x0F +#define SLEEP_ON 0x10 +#define SLEEP_OFF 0x11 +#define PARTIAL_DISPALY_ON 0x12 +#define NORMAL_DISPALY_ON 0x13 +#define INVERSION_DISPALY_OFF 0x20 +#define INVERSION_DISPALY_ON 0x21 +#define GAMMA_SET 0x26 +#define DISPALY_OFF 0x28 +#define DISPALY_ON 0x29 +#define HORIZONTAL_ADDRESS_SET 0x2A +#define VERTICAL_ADDRESS_SET 0x2B +#define MEMORY_WRITE 0x2C +#define COLOR_SET 0x2D +#define MEMORY_READ 0x2E +#define PARTIAL_AREA 0x30 +#define VERTICAL_SCROL_DEFINE 0x33 +#define TEAR_EFFECT_LINE_OFF 0x34 +#define TEAR_EFFECT_LINE_ON 0x35 +#define MEMORY_ACCESS_CTL 0x36 +#define VERTICAL_SCROL_S_ADD 0x37 +#define IDLE_MODE_OFF 0x38 +#define IDLE_MODE_ON 0x39 +#define PIXEL_FORMAT_SET 0x3A +#define WRITE_MEMORY_CONTINUE 0x3C +#define READ_MEMORY_CONTINUE 0x3E +#define SET_TEAR_SCANLINE 0x44 +#define GET_SCANLINE 0x45 +#define WRITE_BRIGHTNESS 0x51 +#define READ_BRIGHTNESS 0x52 +#define WRITE_CTRL_DISPALY 0x53 +#define READ_CTRL_DISPALY 0x54 +#define WRITE_BRIGHTNESS_CTL 0x55 +#define READ_BRIGHTNESS_CTL 0x56 +#define WRITE_MIN_BRIGHTNESS 0x5E +#define READ_MIN_BRIGHTNESS 0x5F +#define READ_ID1 0xDA +#define READ_ID2 0xDB +#define READ_ID3 0xDC +#define RGB_IF_SIGNAL_CTL 0xB0 +#define NORMAL_FRAME_CTL 0xB1 +#define IDLE_FRAME_CTL 0xB2 +#define PARTIAL_FRAME_CTL 0xB3 +#define INVERSION_CTL 0xB4 +#define BLANK_PORCH_CTL 0xB5 +#define DISPALY_FUNCTION_CTL 0xB6 +#define ENTRY_MODE_SET 0xB7 +#define BACKLIGHT_CTL1 0xB8 +#define BACKLIGHT_CTL2 0xB9 +#define BACKLIGHT_CTL3 0xBA +#define BACKLIGHT_CTL4 0xBB +#define BACKLIGHT_CTL5 0xBC +#define BACKLIGHT_CTL7 0xBE +#define BACKLIGHT_CTL8 0xBF +#define POWER_CTL1 0xC0 +#define POWER_CTL2 0xC1 +#define VCOM_CTL1 0xC5 +#define VCOM_CTL2 0xC7 +#define NV_MEMORY_WRITE 0xD0 +#define NV_MEMORY_PROTECT_KEY 0xD1 +#define NV_MEMORY_STATUS_READ 0xD2 +#define READ_ID4 0xD3 +#define POSITIVE_GAMMA_CORRECT 0xE0 +#define NEGATIVE_GAMMA_CORRECT 0xE1 +#define DIGITAL_GAMMA_CTL1 0xE2 +#define DIGITAL_GAMMA_CTL2 0xE3 +#define INTERFACE_CTL 0xF6 + +#define LCD_SPI_CHANNEL SPI_DEVICE_0 +#define LCD_SPI_CHIP_SELECT SPI_CHIP_SELECT_0 + +#if defined(BSP_BOARD_K210_OPENMV_TEST) +#define LCD_SCAN_DIR DIR_YX_LRUD +#elif defined(BSP_BOARD_KD233) +#define LCD_SCAN_DIR (DIR_YX_RLUD | 0x08) +#elif defined(BSP_BOARD_USER) +/*user define.*/ +#define LCD_SCAN_DIR DIR_YX_RLDU +#endif + + + +static struct lcd_8080_device _lcddev; + +static void drv_lcd_cmd(lcd_8080_device_t lcd, rt_uint8_t cmd) +{ + gpiohs_set_pin(lcd->dc_pin, GPIO_PV_LOW); + spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0); + spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/); + spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, &cmd, 1, SPI_TRANS_CHAR); +} + +static void drv_lcd_data_byte(lcd_8080_device_t lcd, rt_uint8_t *data_buf, rt_uint32_t length) +{ + gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH); + spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0); + spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/); + spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_CHAR); +} + +void drv_lcd_data_half_word(lcd_8080_device_t lcd, rt_uint16_t *data_buf, rt_uint32_t length) +{ + gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH); + spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 16, 0); + spi_init_non_standard(lcd->spi_channel, 16 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/); + spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_SHORT); +} + +void drv_lcd_data_word(lcd_8080_device_t lcd, rt_uint32_t *data_buf, rt_uint32_t length) +{ + gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH); + spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0); + spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/); + spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_INT); +} + +static void drv_lcd_hw_init(lcd_8080_device_t lcd) +{ +#if BSP_LCD_RST_PIN >= 0 + { + gpiohs_set_drive_mode(lcd->rst_pin, GPIO_DM_OUTPUT); + gpiohs_set_pin(lcd->rst_pin, GPIO_PV_LOW); + rt_thread_mdelay(20); + gpiohs_set_pin(lcd->rst_pin, GPIO_PV_HIGH); + rt_thread_mdelay(20); + } +#endif +#if BSP_LCD_BACKLIGHT_PIN >= 0 + { + gpiohs_set_drive_mode(lcd->backlight_pin, GPIO_DM_OUTPUT); +#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW) + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW); +#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH) + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH); +#else + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW); +#endif + } +#endif + + gpiohs_set_drive_mode(lcd->dc_pin, GPIO_DM_OUTPUT); + gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH); + spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0); + spi_set_clk_rate(lcd->spi_channel, BSP_LCD_CLK_FREQ); +} + +static void drv_lcd_set_direction(lcd_8080_device_t lcd, lcd_dir_t dir) +{ + if (dir & DIR_XY_MASK) + { + lcd->lcd_info.width = BSP_LCD_Y_MAX; + lcd->lcd_info.height = BSP_LCD_X_MAX; + } + else + { + lcd->lcd_info.width = BSP_LCD_X_MAX; + lcd->lcd_info.height = BSP_LCD_Y_MAX; + } + rt_kprintf("lcd witdth %d,height %d \n",lcd->lcd_info.width,lcd->lcd_info.height); + drv_lcd_cmd(lcd, MEMORY_ACCESS_CTL); + drv_lcd_data_byte(lcd, (rt_uint8_t *)&dir, 1); +} + + void drv_lcd_set_area(lcd_8080_device_t lcd, rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2) +{ + rt_uint8_t data[4] = {0}; + + data[0] = (rt_uint8_t)(x1 >> 8); + data[1] = (rt_uint8_t)(x1); + data[2] = (rt_uint8_t)(x2 >> 8); + data[3] = (rt_uint8_t)(x2); + drv_lcd_cmd(lcd, HORIZONTAL_ADDRESS_SET); + drv_lcd_data_byte(lcd, data, 4); + + data[0] = (rt_uint8_t)(y1 >> 8); + data[1] = (rt_uint8_t)(y1); + data[2] = (rt_uint8_t)(y2 >> 8); + data[3] = (rt_uint8_t)(y2); + drv_lcd_cmd(lcd, VERTICAL_ADDRESS_SET); + drv_lcd_data_byte(lcd, data, 4); + + drv_lcd_cmd(lcd, MEMORY_WRITE); +} + +static void drv_lcd_set_pixel(lcd_8080_device_t lcd, uint16_t x, uint16_t y, uint16_t color) +{ + drv_lcd_set_area(lcd, x, y, x, y); + drv_lcd_data_half_word(lcd, &color, 1); +} + +static void drv_lcd_clear(lcd_8080_device_t lcd, uint16_t color) +{ + uint32_t data = ((uint32_t)color << 16) | (uint32_t)color; + + drv_lcd_set_area(lcd, 0, 0, lcd->lcd_info.width - 1, lcd->lcd_info.height - 1); + gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH); + spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0); + spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/); + spi_fill_data_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, (const uint32_t *)&data, lcd->lcd_info.width * lcd->lcd_info.height / 2); +} + +static void rt_bitblt(rt_uint16_t * dest, int dest_segment, int dest_common, int dest_x, int dest_y, int width, int height, + rt_uint16_t *src, int src_segment, int src_common, int src_x, int src_y) +{ + int sx0, sx1, sy0, sy1; + int dx0, dx1, dy0, dy1; + rt_uint16_t *buff_src; + rt_uint16_t *buff_dest; + int x, y; + + if (width <= 0) { + return; + } + if (height <= 0) { + return; + } + + sx0 = src_x; + sy0 = src_y; + sx1 = sx0 + width - 1; + sy1 = sy0 + height - 1; + dx0 = dest_x; + dy0 = dest_y; + dx1 = dx0 + width - 1; + dy1 = dy0 + height - 1; + + if (sx0 < 0) { + dx0 -= sx0; + sx0 = 0; + } + if (sy0 < 0) { + dy0 -= sy0; + sy0 = 0; + } + if (sx1 >= src_segment) { + dx1 -= (sx1 - src_segment + 1); + sx1 = src_segment - 1; + } + if (sy1 >= src_common) { + dy1 -= (sy1 - src_common + 1); + sy1 = src_common - 1; + } + + if (dx0 < 0) { + sx0 -= dx0; + dx0 = 0; + } + if (dy0 < 0) { + sy0 -= dy0; + dy0 = 0; + } + if (dx1 >= dest_segment) { + sx1 -= (dx1 - dest_segment + 1); + dx1 = dest_segment - 1; + } + if (dy1 >= dest_common) { + sy1 -= (dy1 - dest_common + 1); + dy1 = dest_common - 1; + } + + if (sx1 < 0 || sx0 >= src_segment) { + return; + } + if (sy1 < 0 || sy0 >= src_common) { + return; + } + if (dx1 < 0 || dx0 >= dest_segment) { + return; + } + if (dy1 < 0 || dy0 >= dest_common) { + return; + } + + if ((rt_ubase_t)dest < (rt_ubase_t)src) { + buff_src = src + (sy0 * src_segment) + sx0; + buff_dest = dest + (dy0 * dest_segment) + dx0; + for (y = sy0; y <= sy1; y++) { + src = buff_src; + dest = buff_dest; + for (x = sx0; x <= sx1; x++) { + *dest++ = *src++; + } + buff_src += src_segment; + buff_dest += dest_segment; + } + } else { + buff_src = src + (sy1 * src_segment) + sx1; + buff_dest = dest + (dy1 * dest_segment) + dx1; + for (y = sy1; y >= sy0; y--) { + src = buff_src; + dest = buff_dest; + for (x = sx1; x >= sx0; x--) { + *dest-- = *src--; + } + buff_src -= src_segment; + buff_dest -= dest_segment; + } + } +} + +static void drv_lcd_rect_update(lcd_8080_device_t lcd, uint16_t x1, uint16_t y1, uint16_t width, uint16_t height) +{ + static rt_uint16_t * rect_buffer = RT_NULL; + if(!rect_buffer) + { + rect_buffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64); + if(!rect_buffer) + { + return; + } + } + if(x1 == 0 && y1 == 0 && width == lcd->lcd_info.width && height == lcd->lcd_info.height) + { + drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1); + drv_lcd_data_half_word(lcd, (rt_uint32_t *)lcd->lcd_info.framebuffer, width * height); + } + else + { + rt_bitblt(rect_buffer, width, height, 0, 0, width, height,(rt_uint16_t *)lcd->lcd_info.framebuffer, lcd->lcd_info.width, lcd->lcd_info.height, x1, y1); + drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1); + drv_lcd_data_half_word(lcd, (rt_uint16_t *)rect_buffer, width * height); + } +} + +static rt_err_t drv_lcd_init(rt_device_t dev) +{ + rt_err_t ret = RT_EOK; + lcd_8080_device_t lcd = (lcd_8080_device_t)dev; + rt_uint8_t data = 0; + + if(!lcd) + { + return RT_ERROR; + } + drv_lcd_hw_init(lcd); + /* reset LCD */ + drv_lcd_cmd(lcd, SOFTWARE_RESET); + rt_thread_mdelay(100); + + /* Enter normal status */ + drv_lcd_cmd(lcd, SLEEP_OFF); + rt_thread_mdelay(100); + + /* pixel format rgb565 */ + drv_lcd_cmd(lcd, PIXEL_FORMAT_SET); + data = 0x55; + drv_lcd_data_byte(lcd, &data, 1); + + /* set direction */ + drv_lcd_set_direction(lcd, LCD_SCAN_DIR); + + lcd->lcd_info.framebuffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64); + RT_ASSERT(lcd->lcd_info.framebuffer); + + uint16_t *framebuffer = (uint16_t *)(lcd->lcd_info.framebuffer); + for(uint32_t i=0; i<(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8))/2; i++) { + framebuffer[i] = BLACK; + } + /*display on*/ + drv_lcd_cmd(lcd, DISPALY_ON); + + /* set to black */ + drv_lcd_clear(lcd, BLACK); + return ret; +} + +static rt_err_t drv_lcd_open(rt_device_t dev, rt_uint16_t oflag) +{ + + /* Not need */ + + return RT_EOK; +} + +static rt_err_t drv_lcd_close(rt_device_t dev) +{ + + /* Not need */ + + return RT_EOK; +} + +static rt_size_t drv_lcd_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + + /* Not need */ + + return 0; +} + +static rt_size_t drv_lcd_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + + /* Not need */ + + return 0; +} + +static rt_err_t drv_lcd_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t ret = RT_EOK; + lcd_8080_device_t lcd = (lcd_8080_device_t)dev; + rt_base_t level; + struct rt_device_rect_info* rect_info = (struct rt_device_rect_info*)args; + + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + if(!rect_info) + { + LOG_E("RTGRAPHIC_CTRL_RECT_UPDATE error args"); + return -RT_ERROR; + } + drv_lcd_rect_update(lcd, rect_info->x, rect_info->y, rect_info->width, rect_info->height); + break; + +#if BSP_LCD_BACKLIGHT_PIN >= 0 + case RTGRAPHIC_CTRL_POWERON: +#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW) + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW); +#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH) + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH); +#else + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW); +#endif + break; + + case RTGRAPHIC_CTRL_POWEROFF: +#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW) + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH); +#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH) + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW); +#else + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH); +#endif + break; +#endif /* BSP_LCD_BACKLIGHT_PIN >= 0 */ + + case RTGRAPHIC_CTRL_GET_INFO: + *(struct rt_device_graphic_info *)args = lcd->lcd_info; + break; + + case RTGRAPHIC_CTRL_SET_MODE: + ret = -RT_ENOSYS; + break; + case RTGRAPHIC_CTRL_GET_EXT: + ret = -RT_ENOSYS; + break; + default: + LOG_E("drv_lcd_control cmd: %d", cmd); + break; + } + + return ret; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops drv_lcd_ops = +{ + drv_lcd_init, + drv_lcd_open, + drv_lcd_close, + drv_lcd_read, + drv_lcd_write, + drv_lcd_control +}; +#endif + + +int rt_hw_lcd_init(void) +{ + rt_err_t ret = RT_EOK; + lcd_8080_device_t lcd_dev = &_lcddev; + + lcd_dev->cs = SPI_CHIP_SELECT_0; + lcd_dev->dc_pin = LCD_DC_PIN; +#if BSP_LCD_RST_PIN >= 0 + lcd_dev->rst_pin = LCD_RST_PIN; +#endif +#if BSP_LCD_BACKLIGHT_PIN >= 0 + lcd_dev->backlight_pin = LCD_BACKLIGHT_PIN; +#endif + dmalock_sync_take(&lcd_dev->dma_channel, RT_WAITING_FOREVER); + lcd_dev->spi_channel = SPI_DEVICE_0; + lcd_dev->lcd_info.bits_per_pixel = 16; + lcd_dev->lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; + + lcd_dev->parent.type = RT_Device_Class_Graphic; + lcd_dev->parent.rx_indicate = RT_NULL; + lcd_dev->parent.tx_complete = RT_NULL; + +#ifdef RT_USING_DEVICE_OPS + lcd_dev->parent.ops = &drv_lcd_ops; +#else + lcd_dev->parent.init = drv_lcd_init; + lcd_dev->parent.open = drv_lcd_open; + lcd_dev->parent.close = drv_lcd_close; + lcd_dev->parent.read = drv_lcd_read; + lcd_dev->parent.write = drv_lcd_write; + lcd_dev->parent.control = drv_lcd_control; +#endif + + lcd_dev->parent.user_data = RT_NULL; + + ret = rt_device_register(&lcd_dev->parent, "lcd", RT_DEVICE_FLAG_RDWR); + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_lcd_init); + +void lcd_set_direction(lcd_dir_t dir) +{ + drv_lcd_set_direction(&_lcddev, dir); +} +#endif diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_lcd.h b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_lcd.h new file mode 100644 index 000000000..868c528ff --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_lcd.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-07 ZYH first version + */ + +#ifndef DRV_LCD_H__ +#define DRV_LCD_H__ +#include +#include +#include +#include +#include +#include +#include "dmalock.h" + + +//POINT_COLOR +#define WHITE 0xFFFF +#define BLACK 0x0000 +#define BLUE 0x001F +#define BRED 0XF81F +#define GRED 0XFFE0 +#define GBLUE 0X07FF +#define RED 0xF800 +#define MAGENTA 0xF81F +#define GREEN 0x07E0 +#define CYAN 0x7FFF +#define YELLOW 0xFFE0 +#define BROWN 0XBC40 +#define BRRED 0XFC07 +#define GRAY 0X8430 +#define GRAY175 0XAD75 +#define GRAY151 0X94B2 +#define GRAY187 0XBDD7 +#define GRAY240 0XF79E + +typedef enum _lcd_dir +{ + DIR_XY_RLUD = 0x00, + DIR_YX_RLUD = 0x20, + DIR_XY_LRUD = 0x40, + DIR_YX_LRUD = 0x60, + DIR_XY_RLDU = 0x80, + DIR_YX_RLDU = 0xA0, + DIR_XY_LRDU = 0xC0, + DIR_YX_LRDU = 0xE0, + DIR_XY_MASK = 0x20, + DIR_MASK = 0xE0, +} lcd_dir_t; + +typedef struct lcd_8080_device +{ + struct rt_device parent; + struct rt_device_graphic_info lcd_info; + int spi_channel; + int cs; + int dc_pin; +#if BSP_LCD_RST_PIN >= 0 + int rst_pin; +#endif +#if BSP_LCD_BACKLIGHT_PIN >= 0 + int backlight_pin; +#endif + int dma_channel; +} * lcd_8080_device_t; + +int rt_hw_lcd_init(void); +void drv_lcd_set_area(lcd_8080_device_t lcd, rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2); +void drv_lcd_data_word(lcd_8080_device_t lcd, rt_uint32_t *data_buf, rt_uint32_t length); +void drv_lcd_data_half_word(lcd_8080_device_t lcd, rt_uint16_t *data_buf, rt_uint32_t length); + +/* for mpy machine.lcd */ +void lcd_display_on(void); +void lcd_display_off(void); +void lcd_clear(int color); +void lcd_draw_point_color(int x, int y, int color); +void lcd_show_string(int x, int y, int size, const char *data); +void lcd_draw_line(int x1, int y1, int x2, int y2); +void lcd_draw_rectangle(int x1, int y1, int x2, int y2); +void lcd_draw_circle(int x1, int y1, int r); +void lcd_set_color(int back, int fore); +void lcd_show_image(int x, int y, int length, int wide, const unsigned char *buf); +void lcd_set_direction(lcd_dir_t dir); + +#endif diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_mpylcd.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_mpylcd.c new file mode 100644 index 000000000..ff7e96ce0 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_mpylcd.c @@ -0,0 +1,1297 @@ +#include +#include +#include +#include + +static const uint8_t asc2_1608[]; +static const uint8_t asc2_2412[]; +static const uint8_t asc2_3216[]; + +static rt_device_t dev = 0; +static struct rt_device_graphic_info info; +static uint16_t fcolor = WHITE; +static int bcolor = BLACK; + +static int lcd_init(void) +{ + int result; + + if (dev) + return 0; + + dev = rt_device_find("lcd"); + if (!dev) + return -1; + + if (rt_device_open(dev, 0) != 0) + { + dev = 0; + return -1; + } + + result = rt_device_control(dev, RTGRAPHIC_CTRL_GET_INFO, &info); + if (result != 0) + { + rt_device_close(dev); + dev = 0; + return result; + } + + return 0; +} + +static int lcd_fill_point(int x, int y, uint16_t c) +{ + uint16_t *fb = (uint16_t *)info.framebuffer; + + if ((x < 0) || (y < 0) || (x >= info.width) || (y >= info.height)) + return -1; + + fb += x; + fb += (y * info.width); + + *fb = c; + + return 0; +} + +static void lcd_fill_char1608(int x, int y, char c, uint16_t color, int bc) +{ + uint8_t pos = 0; + uint8_t t = 0; + uint8_t data, temp; + int size = 16; + + data = c - ' '; + + for (pos = 0; pos < size; pos++) + { + temp = asc2_1608[(uint16_t)data * size + pos]; + for (t = 0; t < 8; t++) + { + if (temp & 0x80) + lcd_fill_point(x + t, y, color); + else if (bc != -1) + lcd_fill_point(x + t, y, (uint16_t)bc); + + temp <<= 1; + } + y++; + } +} + +static void lcd_fill_char2412(int x, int y, char c, uint16_t color, int bc) +{ + uint8_t pos = 0; + uint8_t t = 0; + uint8_t data, temp; + int size = 24; + int num; + int x0; + + data = c - ' '; + + for (pos = 0; pos < (size * 16) / 8; pos++) + { + temp = asc2_2412[(uint16_t)data * (size * 16) / 8 + pos]; + if (pos % 2 == 0) + { + num = 8; + x0 = x; + } + else + { + num = 4; + } + + for (t = 0; t < num; t++) + { + if (temp & 0x80) + lcd_fill_point(x0, y, color); + else if (bc != -1) + lcd_fill_point(x0, y, (uint16_t)bc); + + temp <<= 1; + x0++; + } + + if (pos % 2 != 0) + y++; + } +} + +static void lcd_fill_char3216(int x, int y, char c, uint16_t color, int bc) +{ + uint8_t pos = 0; + uint8_t t = 0; + uint8_t data, temp; + int size = 32; + int x0; + + data = c - ' '; + + for (pos = 0; pos < size * (size / 2) / 8; pos++) + { + temp = asc2_3216[(uint16_t)data * size * (size / 2) / 8 + pos]; + if (pos % 2 == 0) + { + x0 = x; + } + + for (t = 0; t < 8; t++) + { + if (temp & 0x80) + lcd_fill_point(x0, y, color); + else if (bc != -1) + lcd_fill_point(x0, y, (uint16_t)bc); + + temp <<= 1; + x0++; + } + + if (pos % 2 != 0) + y++; + } +} + +static void lcd_update(int x, int y, int w, int h) +{ + struct rt_device_rect_info rect; + + if (x < 0) + { + w += x; + x = 0; + } + if (y < 0) + { + h += y; + y = 0; + } + if ((x > info.width) || (y > info.height)) + return; + + if ((x + w) > info.width) + w = info.width - x; + if ((y + h) > info.height) + h = info.height - h; + + if ((w < 1) || (h < 1)) + return; + + rect.x = x; + rect.y = y; + rect.width = w; + rect.height = h; + + rt_device_control(dev, RTGRAPHIC_CTRL_RECT_UPDATE, &rect); +} + +static void _draw_ellipse(int16_t x, int16_t y, int16_t rx, int16_t ry) +{ + int ix, iy; + int h, i, j, k; + int oh, oi, oj, ok; + int xmh, xph, ypk, ymk; + int xmi, xpi, ymj, ypj; + int xmj, xpj, ymi, ypi; + int xmk, xpk, ymh, yph; + uint16_t color = fcolor; + + /* + * Sanity check radii + */ + if ((rx <= 0) || (ry <= 0)) + return; + + /* + * Init vars + */ + oh = oi = oj = ok = 0xFFFF; + + if (rx > ry) + { + ix = 0; + iy = rx * 64; + + do + { + h = (ix + 32) >> 6; + i = (iy + 32) >> 6; + j = (h * ry) / rx; + k = (i * ry) / rx; + + if (((ok != k) && (oj != k)) || ((oj != j) && (ok != j)) || (k != j)) + { + xph = x + h; + xmh = x - h; + if (k > 0) + { + ypk = y + k; + ymk = y - k; + lcd_fill_point(xmh, ypk, color); + lcd_fill_point(xph, ypk, color); + lcd_fill_point(xmh, ymk, color); + lcd_fill_point(xph, ymk, color); + } + else + { + lcd_fill_point(xmh, y, color); + lcd_fill_point(xph, y, color); + } + ok = k; + xpi = x + i; + xmi = x - i; + if (j > 0) + { + ypj = y + j; + ymj = y - j; + lcd_fill_point(xmi, ypj, color); + lcd_fill_point(xpi, ypj, color); + lcd_fill_point(xmi, ymj, color); + lcd_fill_point(xpi, ymj, color); + } + else + { + lcd_fill_point(xmi, y, color); + lcd_fill_point(xpi, y, color); + } + oj = j; + } + + ix = ix + iy / rx; + iy = iy - ix / rx; + } while (i > h); + } + else + { + ix = 0; + iy = ry * 64; + + do + { + h = (ix + 32) >> 6; + i = (iy + 32) >> 6; + j = (h * rx) / ry; + k = (i * rx) / ry; + + if (((oi != i) && (oh != i)) || ((oh != h) && (oi != h) && (i != h))) + { + xmj = x - j; + xpj = x + j; + if (i > 0) + { + ypi = y + i; + ymi = y - i; + lcd_fill_point(xmj, ypi, color); + lcd_fill_point(xpj, ypi, color); + lcd_fill_point(xmj, ymi, color); + lcd_fill_point(xpj, ymi, color); + } + else + { + lcd_fill_point(xmj, y, color); + lcd_fill_point(xpj, y, color); + } + oi = i; + xmk = x - k; + xpk = x + k; + if (h > 0) + { + yph = y + h; + ymh = y - h; + lcd_fill_point(xmk, yph, color); + lcd_fill_point(xpk, yph, color); + lcd_fill_point(xmk, ymh, color); + lcd_fill_point(xpk, ymh, color); + } + else + { + lcd_fill_point(xmk, y, color); + lcd_fill_point(xpk, y, color); + } + oh = h; + } + + ix = ix + iy / ry; + iy = iy - ix / ry; + } while (i > h); + } + + x -= rx; + y -= ry; + if (x < 0) + x = 0; + if (y < 0) + y = 0; + + lcd_update(x, y, 2 * rx + 1, 2 * ry + 1); +} + +void lcd_display_on(void) +{ + if (lcd_init() != 0) + return; + + rt_device_control(dev, RTGRAPHIC_CTRL_POWERON, RT_NULL); +} + +void lcd_display_off(void) +{ + if (lcd_init() != 0) + return; + + rt_device_control(dev, RTGRAPHIC_CTRL_POWEROFF, RT_NULL); +} + +void lcd_clear(int color) +{ + int x, y; + + if (lcd_init() != 0) + return; + + for (x = 0; x < info.width; x++) + { + for (y = 0; y < info.height; y++) + { + lcd_fill_point(x, y, (uint16_t)color); + } + } + + lcd_update(0, 0, info.width, info.height); +} + +void lcd_draw_point_color(int x, int y, int color) +{ + if (lcd_init() != 0) + return; + + if (lcd_fill_point(x, y, (uint16_t)color) == 0) + lcd_update(x, y, 1, 1); +} + +void lcd_show_string(int x, int y, int size, const char *str) +{ + uint16_t color = fcolor; + int bc = bcolor; + int x0 = x; + + if (lcd_init() != 0) + return; + + switch (size) + { + case 16: + { + while (*str) + { + lcd_fill_char1608(x, y, *str, color, bc); + str++; + x += 8; + } + + lcd_update(x0, y, x - x0, size); + } + break; + case 24: + { + while (*str) + { + lcd_fill_char2412(x, y, *str, color, bc); + str++; + x += 12; + } + + lcd_update(x0, y, x - x0, size); + } + break; + case 32: + { + while (*str) + { + lcd_fill_char3216(x, y, *str, color, bc); + str++; + x += 16; + } + + lcd_update(x0, y, x - x0, size); + } + break; + } +} + +void lcd_draw_line(int x1, int y1, int x2, int y2) +{ + float k, b; + int y, x; + + if (lcd_init() != 0) + return; + + k = (y2 - y1) / (float)(x2 - x1); + b = y1 - k * x1; + + for (x = x1; x <= x2; x++) + { + y = k * x + b; + lcd_fill_point(x, y, fcolor); + } + + lcd_update(x1, y1, x2 - x1 + 1, y2 - y1 + 1); +} + +void lcd_draw_rectangle(int x1, int y1, int x2, int y2) +{ + int x, y; + uint16_t color = (uint16_t)fcolor; + + if (lcd_init() != 0) + return; + + for (x = x1; x < x2; x++) + { + lcd_fill_point(x, y1, color); + } + + for (x = x1; x < x2; x++) + { + lcd_fill_point(x, y2, color); + } + + for (y = y1; y < y2; y++) + { + lcd_fill_point(x1, y, color); + } + + for (y = y1; y < y2; y++) + { + lcd_fill_point(x2, y, color); + } + + lcd_update(x1, y1, x2 - x1 + 1, y2 - y1 + 1); +} + +void lcd_draw_circle(int x1, int y1, int r) +{ + if (lcd_init() != 0) + return; + + _draw_ellipse(x1, y1, r, r); +} + +void lcd_set_color(int back, int fore) +{ + bcolor = back; + fcolor = (uint16_t)fore; +} + +void lcd_show_image(int x, int y, int wide, int height,const rt_uint8_t *buf) +{ + uint16_t *color = (uint16_t*)buf; + int h, w; + + if (lcd_init() != 0) + return; + + for (h = 0; h < height; h ++) + { + for (w = 0; w < wide; w ++) + { + lcd_fill_point(x + w, y + h, *color); + color ++; + } + } + + lcd_update(x, y, wide, height); +} +//////////////////////////////////////////////////////////////////////////////////////////////// +void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t *ptr) +{ + lcd_8080_device_t lcd = (lcd_8080_device_t)dev; + if (lcd_init() != 0) + return; + drv_lcd_set_area(lcd,x1, y1, x1 + width, y1 + height); + drv_lcd_data_word(lcd,ptr, width * height/2); +} + +void lcd_draw_16_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t *ptr) +{ + lcd_8080_device_t lcd = (lcd_8080_device_t)dev; + if (lcd_init() != 0) + return; + drv_lcd_set_area(lcd,x1, y1, x1 + width, y1 + height); + drv_lcd_data_half_word(lcd,ptr, width * height); + +} + +#define ASC2_1608 +#define ASC2_2412 +#define ASC2_3216 + +#ifdef ASC2_1608 +static const uint8_t asc2_1608[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*" ",0*/ + 0x00, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, /*"!",1*/ + 0x00, 0x00, 0x00, 0x28, 0x28, 0x28, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*""",2*/ + 0x00, 0x00, 0x00, 0x12, 0x12, 0x16, 0x7F, 0x24, 0x24, 0xFE, 0x28, 0x48, 0x48, 0x00, 0x00, 0x00, /*"#",3*/ + 0x00, 0x00, 0x08, 0x08, 0x3E, 0x49, 0x48, 0x68, 0x3E, 0x0B, 0x09, 0x49, 0x3E, 0x08, 0x08, 0x00, /*"$",4*/ + 0x00, 0x00, 0x00, 0x60, 0x90, 0x90, 0x62, 0x0C, 0x30, 0x46, 0x09, 0x09, 0x06, 0x00, 0x00, 0x00, /*"%",5*/ + 0x00, 0x00, 0x00, 0x1C, 0x20, 0x20, 0x30, 0x30, 0x49, 0x45, 0x45, 0x62, 0x3D, 0x00, 0x00, 0x00, /*"&",6*/ + 0x00, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"'",7*/ + 0x00, 0x00, 0x0C, 0x08, 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08, 0x08, 0x04, 0x00, 0x00, /*"(",8*/ + 0x00, 0x00, 0x30, 0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x30, 0x00, 0x00, /*")",9*/ + 0x00, 0x00, 0x00, 0x08, 0x49, 0x3E, 0x1C, 0x6B, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"*",10*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x10, 0x10, 0xFE, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, /*"+",11*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x10, 0x20, 0x00, /*",",12*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"-",13*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, /*".",14*/ + 0x00, 0x00, 0x00, 0x02, 0x04, 0x04, 0x04, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x20, 0x40, 0x00, /*"/",15*/ + 0x00, 0x00, 0x00, 0x1C, 0x22, 0x41, 0x41, 0x49, 0x41, 0x41, 0x41, 0x22, 0x1C, 0x00, 0x00, 0x00, /*"0",16*/ + 0x00, 0x00, 0x00, 0x18, 0x28, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x3E, 0x00, 0x00, 0x00, /*"1",17*/ + 0x00, 0x00, 0x00, 0x3E, 0x43, 0x01, 0x01, 0x02, 0x06, 0x0C, 0x10, 0x20, 0x7F, 0x00, 0x00, 0x00, /*"2",18*/ + 0x00, 0x00, 0x00, 0x3E, 0x41, 0x01, 0x03, 0x1C, 0x03, 0x01, 0x01, 0x43, 0x3E, 0x00, 0x00, 0x00, /*"3",19*/ + 0x00, 0x00, 0x00, 0x06, 0x0A, 0x1A, 0x12, 0x22, 0x42, 0x7F, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*"4",20*/ + 0x00, 0x00, 0x00, 0x7E, 0x40, 0x40, 0x7C, 0x42, 0x01, 0x01, 0x01, 0x42, 0x3C, 0x00, 0x00, 0x00, /*"5",21*/ + 0x00, 0x00, 0x00, 0x1E, 0x31, 0x60, 0x40, 0x5E, 0x63, 0x41, 0x41, 0x23, 0x1E, 0x00, 0x00, 0x00, /*"6",22*/ + 0x00, 0x00, 0x00, 0x7F, 0x03, 0x02, 0x04, 0x04, 0x08, 0x08, 0x10, 0x10, 0x20, 0x00, 0x00, 0x00, /*"7",23*/ + 0x00, 0x00, 0x00, 0x3E, 0x41, 0x41, 0x41, 0x3E, 0x63, 0x41, 0x41, 0x63, 0x3E, 0x00, 0x00, 0x00, /*"8",24*/ + 0x00, 0x00, 0x00, 0x3C, 0x62, 0x41, 0x41, 0x63, 0x3D, 0x01, 0x03, 0x46, 0x3C, 0x00, 0x00, 0x00, /*"9",25*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, /*":",26*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x18, 0x18, 0x10, 0x20, 0x00, /*";",27*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0E, 0x38, 0x40, 0x38, 0x0E, 0x01, 0x00, 0x00, 0x00, 0x00, /*"<",28*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"=",29*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x38, 0x0E, 0x01, 0x0E, 0x38, 0x40, 0x00, 0x00, 0x00, 0x00, /*">",30*/ + 0x00, 0x00, 0x00, 0x38, 0x44, 0x04, 0x0C, 0x18, 0x10, 0x10, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, /*"?",31*/ + 0x00, 0x00, 0x00, 0x1E, 0x33, 0x21, 0x47, 0x49, 0x49, 0x49, 0x49, 0x47, 0x20, 0x30, 0x0E, 0x00, /*"@",32*/ + 0x00, 0x00, 0x00, 0x08, 0x14, 0x14, 0x14, 0x14, 0x22, 0x3E, 0x22, 0x41, 0x41, 0x00, 0x00, 0x00, /*"A",33*/ + 0x00, 0x00, 0x00, 0x7E, 0x41, 0x41, 0x41, 0x7E, 0x43, 0x41, 0x41, 0x43, 0x7E, 0x00, 0x00, 0x00, /*"B",34*/ + 0x00, 0x00, 0x00, 0x1E, 0x21, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x21, 0x1E, 0x00, 0x00, 0x00, /*"C",35*/ + 0x00, 0x00, 0x00, 0x7C, 0x42, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x42, 0x7C, 0x00, 0x00, 0x00, /*"D",36*/ + 0x00, 0x00, 0x00, 0x7F, 0x40, 0x40, 0x40, 0x7F, 0x40, 0x40, 0x40, 0x40, 0x7F, 0x00, 0x00, 0x00, /*"E",37*/ + 0x00, 0x00, 0x00, 0x7F, 0x40, 0x40, 0x40, 0x7F, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, /*"F",38*/ + 0x00, 0x00, 0x00, 0x1E, 0x21, 0x40, 0x40, 0x40, 0x43, 0x41, 0x41, 0x21, 0x1E, 0x00, 0x00, 0x00, /*"G",39*/ + 0x00, 0x00, 0x00, 0x41, 0x41, 0x41, 0x41, 0x7F, 0x41, 0x41, 0x41, 0x41, 0x41, 0x00, 0x00, 0x00, /*"H",40*/ + 0x00, 0x00, 0x00, 0x7C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x7C, 0x00, 0x00, 0x00, /*"I",41*/ + 0x00, 0x00, 0x00, 0x1C, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x44, 0x38, 0x00, 0x00, 0x00, /*"J",42*/ + 0x00, 0x00, 0x00, 0x42, 0x44, 0x48, 0x50, 0x70, 0x78, 0x48, 0x44, 0x46, 0x42, 0x00, 0x00, 0x00, /*"K",43*/ + 0x00, 0x00, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x7F, 0x00, 0x00, 0x00, /*"L",44*/ + 0x00, 0x00, 0x00, 0x63, 0x63, 0x55, 0x55, 0x55, 0x49, 0x41, 0x41, 0x41, 0x41, 0x00, 0x00, 0x00, /*"M",45*/ + 0x00, 0x00, 0x00, 0x61, 0x61, 0x51, 0x51, 0x49, 0x49, 0x45, 0x45, 0x43, 0x43, 0x00, 0x00, 0x00, /*"N",46*/ + 0x00, 0x00, 0x00, 0x1C, 0x22, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x22, 0x1C, 0x00, 0x00, 0x00, /*"O",47*/ + 0x00, 0x00, 0x00, 0x7E, 0x43, 0x41, 0x41, 0x43, 0x7E, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, /*"P",48*/ + 0x00, 0x00, 0x00, 0x1C, 0x22, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x22, 0x1E, 0x06, 0x02, 0x00, /*"Q",49*/ + 0x00, 0x00, 0x00, 0x7E, 0x43, 0x41, 0x41, 0x43, 0x7C, 0x42, 0x41, 0x41, 0x40, 0x00, 0x00, 0x00, /*"R",50*/ + 0x00, 0x00, 0x00, 0x1E, 0x61, 0x40, 0x40, 0x30, 0x0E, 0x01, 0x01, 0x43, 0x3E, 0x00, 0x00, 0x00, /*"S",51*/ + 0x00, 0x00, 0x00, 0xFE, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, /*"T",52*/ + 0x00, 0x00, 0x00, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x63, 0x3E, 0x00, 0x00, 0x00, /*"U",53*/ + 0x00, 0x00, 0x00, 0x41, 0x41, 0x22, 0x22, 0x22, 0x14, 0x14, 0x14, 0x14, 0x08, 0x00, 0x00, 0x00, /*"V",54*/ + 0x00, 0x00, 0x00, 0x81, 0x81, 0x81, 0x5A, 0x5A, 0x5A, 0x66, 0x66, 0x66, 0x66, 0x00, 0x00, 0x00, /*"W",55*/ + 0x00, 0x00, 0x00, 0x41, 0x22, 0x14, 0x14, 0x08, 0x14, 0x14, 0x22, 0x22, 0x41, 0x00, 0x00, 0x00, /*"X",56*/ + 0x00, 0x00, 0x00, 0x82, 0x44, 0x44, 0x28, 0x38, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, /*"Y",57*/ + 0x00, 0x00, 0x00, 0x7F, 0x03, 0x02, 0x04, 0x08, 0x08, 0x10, 0x20, 0x60, 0x7F, 0x00, 0x00, 0x00, /*"Z",58*/ + 0x00, 0x00, 0x1C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1C, 0x00, 0x00, /*"[",59*/ + 0x00, 0x00, 0x00, 0x40, 0x20, 0x20, 0x20, 0x10, 0x10, 0x08, 0x08, 0x04, 0x04, 0x04, 0x02, 0x00, /*"\",60*/ + 0x00, 0x00, 0x38, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x38, 0x00, 0x00, /*"]",61*/ + 0x00, 0x00, 0x00, 0x10, 0x28, 0x44, 0xC6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"^",62*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, /*"_",63*/ + 0x00, 0x30, 0x10, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"`",64*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x22, 0x02, 0x3E, 0x42, 0x42, 0x46, 0x3A, 0x00, 0x00, 0x00, /*"a",65*/ + 0x00, 0x00, 0x40, 0x40, 0x40, 0x7C, 0x64, 0x42, 0x42, 0x42, 0x42, 0x64, 0x5C, 0x00, 0x00, 0x00, /*"b",66*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x22, 0x40, 0x40, 0x40, 0x40, 0x22, 0x1C, 0x00, 0x00, 0x00, /*"c",67*/ + 0x00, 0x00, 0x02, 0x02, 0x02, 0x3E, 0x26, 0x42, 0x42, 0x42, 0x42, 0x26, 0x3A, 0x00, 0x00, 0x00, /*"d",68*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x26, 0x42, 0x7E, 0x40, 0x40, 0x22, 0x1C, 0x00, 0x00, 0x00, /*"e",69*/ + 0x00, 0x00, 0x0C, 0x10, 0x10, 0x7C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, /*"f",70*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x3A, 0x26, 0x42, 0x42, 0x42, 0x42, 0x26, 0x3A, 0x02, 0x22, 0x1C, /*"g",71*/ + 0x00, 0x00, 0x40, 0x40, 0x40, 0x5C, 0x62, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x00, 0x00, 0x00, /*"h",72*/ + 0x00, 0x00, 0x10, 0x10, 0x00, 0x70, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x7C, 0x00, 0x00, 0x00, /*"i",73*/ + 0x00, 0x00, 0x08, 0x08, 0x00, 0x38, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x70, /*"j",74*/ + 0x00, 0x00, 0x40, 0x40, 0x40, 0x44, 0x48, 0x50, 0x70, 0x48, 0x48, 0x44, 0x42, 0x00, 0x00, 0x00, /*"k",75*/ + 0x00, 0x00, 0x70, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x00, 0x00, 0x00, /*"l",76*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x00, 0x00, 0x00, /*"m",77*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x5C, 0x62, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x00, 0x00, 0x00, /*"n",78*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x66, 0x42, 0x42, 0x42, 0x42, 0x66, 0x3C, 0x00, 0x00, 0x00, /*"o",79*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x5C, 0x64, 0x42, 0x42, 0x42, 0x42, 0x64, 0x7C, 0x40, 0x40, 0x40, /*"p",80*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x3A, 0x26, 0x42, 0x42, 0x42, 0x42, 0x26, 0x3A, 0x02, 0x02, 0x02, /*"q",81*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x32, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, /*"r",82*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x42, 0x40, 0x70, 0x0E, 0x02, 0x42, 0x3C, 0x00, 0x00, 0x00, /*"s",83*/ + 0x00, 0x00, 0x00, 0x10, 0x10, 0x7E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x00, 0x00, 0x00, /*"t",84*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x46, 0x3A, 0x00, 0x00, 0x00, /*"u",85*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x42, 0x24, 0x24, 0x24, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, /*"v",86*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x81, 0x5A, 0x5A, 0x5A, 0x5A, 0x24, 0x24, 0x00, 0x00, 0x00, /*"w",87*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x24, 0x18, 0x18, 0x18, 0x24, 0x24, 0x42, 0x00, 0x00, 0x00, /*"x",88*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x22, 0x24, 0x24, 0x14, 0x18, 0x18, 0x08, 0x08, 0x10, 0x30, /*"y",89*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x7E, 0x00, 0x00, 0x00, /*"z",90*/ + 0x00, 0x00, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x60, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0C, 0x00, /*"{",91*/ + 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, /*"|",92*/ + 0x00, 0x00, 0x60, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x60, 0x00, /*"}",93*/ +}; +#endif + +#ifdef ASC2_2412 +static const uint8_t asc2_2412[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*" ",0*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"!",1*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x80, 0x19, 0x80, 0x19, 0x80, 0x19, 0x80, + 0x19, 0x80, 0x19, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*""",2*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x60, 0x04, 0x40, 0x0C, 0xC0, 0x0C, 0xC0, + 0x7F, 0xF0, 0x7F, 0xF0, 0x08, 0x80, 0x19, 0x80, 0x19, 0x80, 0xFF, 0xE0, 0xFF, 0xE0, 0x33, 0x00, + 0x33, 0x00, 0x22, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"#",3*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x0F, 0x80, 0x1F, 0xC0, 0x3A, 0x40, + 0x32, 0x00, 0x32, 0x00, 0x3A, 0x00, 0x1F, 0x00, 0x07, 0xC0, 0x02, 0xE0, 0x02, 0x60, 0x02, 0x60, + 0x22, 0xE0, 0x3F, 0xC0, 0x1F, 0x80, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, /*"$",4*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x48, 0x00, 0xCC, 0x00, 0xCC, 0x00, + 0xCC, 0x00, 0x48, 0x40, 0x79, 0xC0, 0x0E, 0x00, 0x73, 0xC0, 0x02, 0x40, 0x06, 0x60, 0x06, 0x60, + 0x06, 0x60, 0x02, 0x40, 0x03, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"%",5*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x80, 0x1F, 0x80, 0x18, 0x00, 0x18, 0x00, + 0x18, 0x00, 0x0C, 0x00, 0x1E, 0x00, 0x36, 0x30, 0x63, 0x30, 0x63, 0xB0, 0x61, 0xA0, 0x60, 0xE0, + 0x30, 0xC0, 0x3F, 0x60, 0x0E, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"&",6*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"'",7*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x02, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x04, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, + 0x04, 0x00, 0x06, 0x00, 0x06, 0x00, 0x02, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, /*"(",8*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x04, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x02, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, + 0x02, 0x00, 0x06, 0x00, 0x06, 0x00, 0x04, 0x00, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, /*")",9*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00, 0x44, 0x40, 0x35, 0x80, + 0x0E, 0x00, 0x0E, 0x00, 0x35, 0x80, 0x44, 0x40, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"*",10*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x7F, 0xE0, 0x7F, 0xE0, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"+",11*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, /*",",12*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"-",13*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*".",14*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0x80, + 0x01, 0x80, 0x03, 0x00, 0x03, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x0C, 0x00, 0x0C, 0x00, + 0x18, 0x00, 0x18, 0x00, 0x30, 0x00, 0x30, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"/",15*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x3F, 0x80, 0x31, 0x80, 0x71, 0xC0, + 0x60, 0xC0, 0x60, 0xC0, 0x66, 0xC0, 0x66, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x71, 0xC0, + 0x31, 0x80, 0x3F, 0x80, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"0",16*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x1F, 0x00, 0x1B, 0x00, 0x03, 0x00, + 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, + 0x03, 0x00, 0x1F, 0xE0, 0x1F, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"1",17*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x7F, 0x80, 0x41, 0xC0, 0x00, 0xC0, + 0x00, 0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x06, 0x00, 0x0C, 0x00, 0x18, 0x00, + 0x30, 0x00, 0x7F, 0xC0, 0x7F, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"2",18*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x7F, 0x80, 0x41, 0xC0, 0x00, 0xC0, + 0x00, 0xC0, 0x01, 0xC0, 0x0F, 0x80, 0x0F, 0x80, 0x01, 0x80, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, + 0x41, 0xC0, 0x7F, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"3",19*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x80, 0x03, 0x80, 0x07, 0x80, 0x05, 0x80, + 0x0D, 0x80, 0x09, 0x80, 0x19, 0x80, 0x31, 0x80, 0x31, 0x80, 0x61, 0x80, 0x7F, 0xE0, 0x7F, 0xE0, + 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"4",20*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x80, 0x3F, 0x80, 0x30, 0x00, 0x30, 0x00, + 0x30, 0x00, 0x3F, 0x00, 0x3F, 0x80, 0x21, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, + 0x41, 0x80, 0x7F, 0x80, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"5",21*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x1F, 0x80, 0x38, 0x80, 0x30, 0x00, + 0x70, 0x00, 0x60, 0x00, 0x6F, 0x00, 0x7F, 0x80, 0x71, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, + 0x31, 0xC0, 0x3F, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"6",22*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xC0, 0x7F, 0xC0, 0x01, 0x80, 0x01, 0x80, + 0x01, 0x80, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x0C, 0x00, + 0x0C, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"7",23*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x3F, 0x80, 0x71, 0xC0, 0x60, 0xC0, + 0x60, 0xC0, 0x31, 0x80, 0x1F, 0x00, 0x3F, 0x80, 0x31, 0x80, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, + 0x71, 0xC0, 0x3F, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"8",24*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x3F, 0x80, 0x71, 0x80, 0x60, 0xC0, + 0x60, 0xC0, 0x60, 0xC0, 0x71, 0xC0, 0x3F, 0xC0, 0x1E, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0x80, + 0x23, 0x80, 0x3F, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"9",25*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x06, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"a",65*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, + 0x6F, 0x00, 0x7F, 0x80, 0x71, 0x80, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, + 0x71, 0x80, 0x7F, 0x80, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"b",66*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x00, 0x3F, 0x80, 0x30, 0x80, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, + 0x30, 0x80, 0x3F, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"c",67*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, + 0x1E, 0xC0, 0x3F, 0xC0, 0x31, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, + 0x31, 0xC0, 0x3F, 0xC0, 0x1E, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"d",68*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x00, 0x3F, 0x80, 0x31, 0xC0, 0x60, 0xC0, 0x7F, 0xC0, 0x7F, 0xC0, 0x60, 0x00, 0x60, 0x00, + 0x30, 0x40, 0x3F, 0xC0, 0x0F, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"e",69*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xE0, 0x03, 0xE0, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x3F, 0xE0, 0x3F, 0xE0, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"f",70*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1E, 0xC0, 0x3F, 0xC0, 0x31, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, + 0x31, 0xC0, 0x3F, 0xC0, 0x1E, 0xC0, 0x00, 0xC0, 0x21, 0xC0, 0x3F, 0x80, 0x1F, 0x00, 0x00, 0x00, /*"g",71*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, + 0x67, 0x00, 0x7F, 0x80, 0x71, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, + 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"h",72*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x3E, 0x00, 0x3E, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x7F, 0xE0, 0x7F, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"i",73*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x00, 0x1F, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, + 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x3E, 0x00, 0x3C, 0x00, 0x00, 0x00, /*"j",74*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, + 0x61, 0xC0, 0x63, 0x80, 0x67, 0x00, 0x6E, 0x00, 0x7C, 0x00, 0x7C, 0x00, 0x76, 0x00, 0x67, 0x00, + 0x63, 0x00, 0x61, 0x80, 0x61, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"k",75*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, + 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, + 0x0E, 0x00, 0x07, 0xC0, 0x03, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"l",76*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x6D, 0xC0, 0x7F, 0xE0, 0x66, 0x60, 0x66, 0x60, 0x66, 0x60, 0x66, 0x60, 0x66, 0x60, 0x66, 0x60, + 0x66, 0x60, 0x66, 0x60, 0x66, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"m",77*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x67, 0x00, 0x7F, 0x80, 0x71, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, + 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"n",78*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x00, 0x3F, 0x80, 0x31, 0x80, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, + 0x31, 0x80, 0x3F, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"o",79*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x6F, 0x00, 0x7F, 0x80, 0x71, 0x80, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, + 0x71, 0x80, 0x7F, 0x80, 0x6F, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x00, 0x00, /*"p",80*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1E, 0xC0, 0x3F, 0xC0, 0x31, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, + 0x31, 0xC0, 0x3F, 0xC0, 0x1E, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x00, /*"q",81*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0C, 0xE0, 0x0D, 0xF0, 0x0F, 0x10, 0x0E, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, + 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"r",82*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x80, 0x3F, 0xC0, 0x60, 0x40, 0x60, 0x00, 0x7F, 0x00, 0x1F, 0x80, 0x01, 0xC0, 0x00, 0xC0, + 0x41, 0xC0, 0x7F, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"s",83*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, + 0x7F, 0xC0, 0x7F, 0xC0, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, + 0x0C, 0x00, 0x0F, 0xC0, 0x07, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"t",84*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, 0x60, 0xC0, + 0x71, 0xC0, 0x3F, 0xC0, 0x1C, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"u",85*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x60, 0xC0, 0x71, 0xC0, 0x31, 0x80, 0x31, 0x80, 0x3B, 0x80, 0x1B, 0x00, 0x1B, 0x00, 0x1B, 0x00, + 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"v",86*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC0, 0x30, 0xC0, 0x30, 0x60, 0x60, 0x66, 0x60, 0x66, 0x60, 0x66, 0x60, 0x3F, 0xC0, 0x39, 0xC0, + 0x39, 0xC0, 0x39, 0xC0, 0x30, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"w",87*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x71, 0xC0, 0x31, 0x80, 0x1B, 0x00, 0x1F, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x1F, 0x00, + 0x1B, 0x00, 0x31, 0x80, 0x71, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"x",88*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x60, 0xC0, 0x31, 0x80, 0x31, 0x80, 0x31, 0x80, 0x1B, 0x00, 0x1B, 0x00, 0x1F, 0x00, 0x0E, 0x00, + 0x0E, 0x00, 0x06, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x38, 0x00, 0x38, 0x00, 0x00, 0x00, /*"y",89*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x7F, 0xC0, 0x7F, 0xC0, 0x03, 0x80, 0x03, 0x00, 0x07, 0x00, 0x0E, 0x00, 0x1C, 0x00, 0x18, 0x00, + 0x30, 0x00, 0x7F, 0xC0, 0x7F, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"z",90*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xC0, 0x07, 0xC0, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x0E, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x07, 0xC0, 0x03, 0xC0, 0x00, 0x00, 0x00, 0x00, /*"{",91*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, /*"|",92*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x3E, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x03, 0xC0, 0x03, 0xC0, 0x07, 0x00, 0x06, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x3E, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, /*"}",93*/ +}; +#endif + +#ifdef ASC2_3216 +static const uint8_t asc2_3216[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*" ",0*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC0, 0x01, 0xC0, + 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, + 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC0, + 0x01, 0xC0, 0x01, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"!",1*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x30, 0x06, 0x30, + 0x06, 0x30, 0x06, 0x30, 0x06, 0x30, 0x06, 0x30, 0x06, 0x30, 0x06, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*""",2*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x8C, 0x03, 0x8C, 0x03, 0x0C, + 0x03, 0x18, 0x03, 0x18, 0x03, 0x18, 0x7F, 0xFF, 0x7F, 0xFF, 0x06, 0x30, 0x06, 0x30, 0x0E, 0x30, + 0x0C, 0x70, 0x0C, 0x60, 0xFF, 0xFE, 0xFF, 0xFE, 0x18, 0x60, 0x18, 0xC0, 0x18, 0xC0, 0x18, 0xC0, + 0x30, 0xC0, 0x31, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"#",3*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, + 0x03, 0xF0, 0x0F, 0xFC, 0x0E, 0x8C, 0x1C, 0x80, 0x1C, 0x80, 0x1C, 0x80, 0x1C, 0x80, 0x0E, 0x80, + 0x0F, 0xE0, 0x03, 0xF8, 0x00, 0xFC, 0x00, 0x9E, 0x00, 0x8E, 0x00, 0x8E, 0x00, 0x8E, 0x10, 0x9C, + 0x1F, 0xF8, 0x07, 0xF0, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, /*"$",4*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x7E, 0x00, + 0xE7, 0x00, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, 0xE7, 0x00, 0x7E, 0x1C, 0x3C, 0x78, 0x01, 0xC0, + 0x07, 0x00, 0x3C, 0x78, 0x70, 0xFC, 0x01, 0xCE, 0x01, 0x86, 0x01, 0x86, 0x01, 0x86, 0x01, 0xCE, + 0x00, 0xFC, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"%",5*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0, 0x0F, 0xE0, + 0x1E, 0x20, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1E, 0x00, 0x0E, 0x00, 0x0F, 0x00, 0x1F, 0x00, + 0x3F, 0x83, 0x33, 0xC3, 0x71, 0xE3, 0x70, 0xE3, 0x70, 0xF6, 0x70, 0x7E, 0x78, 0x3C, 0x3C, 0x3E, + 0x1F, 0xEE, 0x07, 0xCF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"&",6*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x01, 0x80, + 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"'",7*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x60, 0x00, 0x60, + 0x00, 0xE0, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0x80, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, + 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x01, 0x80, 0x01, 0xC0, + 0x01, 0xC0, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0x60, 0x00, 0x60, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, /*"(",8*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x03, 0x00, 0x03, 0x00, + 0x03, 0x80, 0x01, 0x80, 0x01, 0xC0, 0x01, 0xC0, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, + 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xC0, 0x01, 0xC0, + 0x01, 0xC0, 0x01, 0x80, 0x03, 0x80, 0x03, 0x00, 0x03, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, /*")",9*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x01, 0x80, + 0x21, 0x84, 0x39, 0x9C, 0x0F, 0xF0, 0x03, 0xC0, 0x03, 0xC0, 0x0F, 0xF0, 0x39, 0x9C, 0x21, 0x84, + 0x01, 0x80, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"*",10*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, + 0x7F, 0xFE, 0x7F, 0xFE, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"+",11*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC0, 0x01, 0xC0, + 0x01, 0xC0, 0x01, 0xC0, 0x01, 0x80, 0x03, 0x80, 0x03, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, /*",",12*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xF0, 0x07, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"-",13*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x80, 0x03, 0x80, + 0x03, 0x80, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*".",14*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x38, + 0x00, 0x38, 0x00, 0x70, 0x00, 0x70, 0x00, 0x70, 0x00, 0xE0, 0x00, 0xE0, 0x01, 0xC0, 0x01, 0xC0, + 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x07, 0x00, 0x07, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x1C, 0x00, + 0x1C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x38, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"/",15*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xE0, 0x0F, 0xF8, + 0x0E, 0x38, 0x1C, 0x1C, 0x1C, 0x1C, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x39, 0xCE, 0x39, 0xCE, + 0x39, 0xCE, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x1C, 0x1C, 0x1C, 0x1C, 0x0E, 0x38, + 0x0F, 0xF8, 0x03, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"0",16*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xE0, 0x0F, 0xE0, + 0x0C, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, + 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, + 0x0F, 0xFE, 0x0F, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"1",17*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xE0, 0x3F, 0xF8, + 0x38, 0x3C, 0x20, 0x1E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x1E, 0x00, 0x3C, + 0x00, 0x7C, 0x00, 0xF8, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x1C, 0x00, + 0x3F, 0xFE, 0x3F, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"2",18*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xF0, 0x1F, 0xF8, + 0x18, 0x1C, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x3C, 0x07, 0xF0, 0x07, 0xF0, + 0x00, 0x3C, 0x00, 0x1C, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x1E, 0x30, 0x3C, + 0x3F, 0xF8, 0x0F, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"3",19*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0xF0, + 0x01, 0xF0, 0x01, 0xF0, 0x03, 0x70, 0x07, 0x70, 0x06, 0x70, 0x0C, 0x70, 0x0C, 0x70, 0x18, 0x70, + 0x38, 0x70, 0x30, 0x70, 0x60, 0x70, 0x7F, 0xFE, 0x7F, 0xFE, 0x00, 0x70, 0x00, 0x70, 0x00, 0x70, + 0x00, 0x70, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"4",20*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0xFC, 0x1F, 0xFC, + 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1F, 0xE0, 0x1F, 0xF8, 0x10, 0x3C, 0x00, 0x1C, + 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x1C, 0x20, 0x3C, + 0x3F, 0xF8, 0x1F, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"5",21*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xF8, 0x07, 0xFC, + 0x0F, 0x04, 0x1E, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x39, 0xF0, 0x3B, 0xF8, 0x3E, 0x3C, + 0x3C, 0x1E, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x18, 0x0E, 0x1C, 0x1C, 0x0E, 0x3C, + 0x0F, 0xF8, 0x03, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"6",22*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xFE, 0x3F, 0xFE, + 0x00, 0x1E, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x70, 0x00, 0x70, + 0x00, 0xF0, 0x00, 0xE0, 0x00, 0xE0, 0x01, 0xE0, 0x01, 0xC0, 0x01, 0xC0, 0x03, 0x80, 0x03, 0x80, + 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"7",23*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xF0, 0x1F, 0xFC, + 0x1C, 0x1C, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x1C, 0x1C, 0x07, 0xF0, 0x0F, 0xF8, + 0x1E, 0x3C, 0x1C, 0x1C, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x3C, 0x1E, 0x1E, 0x3C, + 0x0F, 0xF8, 0x07, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"8",24*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xE0, 0x0F, 0xF8, + 0x1E, 0x38, 0x3C, 0x1C, 0x38, 0x0C, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x3C, 0x1E, + 0x1E, 0x3E, 0x0F, 0xEE, 0x07, 0xCE, 0x00, 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0x1C, 0x1C, 0x1C, 0x1C, 0x1C, + 0x1C, 0x1C, 0x1C, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"h",72*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0xC0, 0x1F, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, + 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, + 0x3F, 0xFE, 0x3F, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"i",73*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xE0, 0x0F, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, + 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, + 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x01, 0xC0, 0x1F, 0xC0, 0x1F, 0x00, /*"j",74*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x71, 0xC7, 0x71, 0xC7, 0x71, 0xC7, 0x71, 0xC7, + 0x71, 0xC7, 0x71, 0xC7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"m",77*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0xF0, 0x1D, 0xF8, 0x1E, 0x3C, 0x1E, 0x1C, 0x1C, 0x1C, + 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, + 0x1C, 0x1C, 0x1C, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"n",78*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xE0, 0x0F, 0xF8, 0x1E, 0x3C, 0x1C, 0x1C, 0x38, 0x0E, + 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x1C, 0x1C, 0x1E, 0x3C, + 0x0F, 0xF8, 0x03, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"o",79*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0xF8, 0x1F, 0xFC, 0x1F, 0x1E, 0x1E, 0x0E, 0x1C, 0x07, + 0x1C, 0x07, 0x1C, 0x07, 0x1C, 0x07, 0x1C, 0x07, 0x1C, 0x07, 0x1C, 0x07, 0x1E, 0x0E, 0x1F, 0x1E, + 0x1F, 0xFC, 0x1C, 0xF8, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, /*"p",80*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xCE, 0x0F, 0xFE, 0x1E, 0x3E, 0x1C, 0x1E, 0x38, 0x0E, + 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x38, 0x0E, 0x1C, 0x1E, 0x1E, 0x3E, + 0x0F, 0xFE, 0x07, 0xCE, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, /*"q",81*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3C, 0x07, 0x7E, 0x07, 0xC2, 0x07, 0x80, 0x07, 0x80, + 0x07, 0x00, 0x07, 0x00, 0x07, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, + 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x3C, 0x1E, 0x3C, + 0x0F, 0xDC, 0x07, 0x9C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"u",85*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0E, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x1C, 0x38, + 0x1C, 0x38, 0x1E, 0x78, 0x0E, 0x70, 0x0E, 0x70, 0x0F, 0xF0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, + 0x03, 0xC0, 0x03, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"v",86*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0xE0, 0x07, 0x70, 0x0E, 0x70, 0x0E, 0x71, 0x8E, + 0x71, 0x8E, 0x7B, 0xDE, 0x3B, 0xDC, 0x3A, 0x5C, 0x3A, 0x5C, 0x3E, 0x7C, 0x1E, 0x78, 0x1C, 0x38, + 0x1C, 0x38, 0x1C, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"w",87*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x3C, 0x1E, 0x78, 0x0E, 0x70, 0x0F, 0xF0, 0x07, 0xE0, + 0x03, 0xC0, 0x03, 0xC0, 0x01, 0x80, 0x03, 0xC0, 0x07, 0xE0, 0x0F, 0xF0, 0x0E, 0x70, 0x1E, 0x78, + 0x3C, 0x3C, 0x78, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"x",88*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0E, 0x38, 0x1C, 0x38, 0x1C, 0x3C, 0x3C, 0x1C, 0x38, + 0x1C, 0x38, 0x1E, 0x78, 0x0E, 0x70, 0x0E, 0x70, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x03, 0xC0, + 0x03, 0xC0, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x07, 0x00, 0x0F, 0x00, 0x3E, 0x00, 0x3C, 0x00, /*"y",89*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0xFC, 0x1F, 0xFC, 0x00, 0x3C, 0x00, 0x78, 0x00, 0x70, + 0x00, 0xF0, 0x01, 0xE0, 0x01, 0xC0, 0x03, 0xC0, 0x07, 0x80, 0x07, 0x00, 0x0F, 0x00, 0x1E, 0x00, + 0x1F, 0xFC, 0x1F, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"z",90*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0xFC, 0x01, 0xE0, + 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, + 0x03, 0x80, 0x1F, 0x00, 0x1F, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, + 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xE0, 0x00, 0xFC, 0x00, 0x7C, 0x00, 0x00, /*"{",91*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, + 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, + 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, + 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, /*"|",92*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x1F, 0x80, 0x03, 0xC0, + 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, + 0x00, 0xE0, 0x00, 0x7C, 0x00, 0x7C, 0x00, 0xE0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, + 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x03, 0xC0, 0x1F, 0x80, 0x1F, 0x00, 0x00, 0x00, /*"}",93*/ +}; +#endif \ No newline at end of file diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_mpymachine.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_mpymachine.c new file mode 100644 index 000000000..1cc00e302 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_mpymachine.c @@ -0,0 +1,27 @@ +#include + +int mp_port_get_freq(int clkid, int *freq) +{ + int ret = 0; + uint32_t value; + + switch (clkid) + { + case 0: + value = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU); + break; + case 1: + value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL1); + break; + case 2: + value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL2); + break; + default: + ret = -1; + break; + } + + *freq = (int)value; + + return ret; +} diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_spi.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_spi.c new file mode 100644 index 000000000..0f591e1d3 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_spi.c @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-18 ZYH first version + */ + +#include +#include + +#ifdef RT_USING_SPI +#include "drv_spi.h" +#include +#include +#include "dmalock.h" +#include +#include +#include +#include "utils.h" + +#define DRV_SPI_DEVICE(spi_bus) (struct drv_spi_bus *)(spi_bus) + +#define MAX_CLOCK (40000000UL) + +struct drv_spi_bus +{ + struct rt_spi_bus parent; + spi_device_num_t spi_instance; + dmac_channel_number_t dma_send_channel; + dmac_channel_number_t dma_recv_channel; + struct rt_completion dma_completion; +}; + +struct drv_cs +{ + int cs_index; + int cs_pin; +}; + +static volatile spi_t *const spi_instance[4] = +{ + (volatile spi_t *)SPI0_BASE_ADDR, + (volatile spi_t *)SPI1_BASE_ADDR, + (volatile spi_t *)SPI_SLAVE_BASE_ADDR, + (volatile spi_t *)SPI3_BASE_ADDR +}; + +static rt_err_t drv_spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + rt_err_t ret = RT_EOK; + int freq = 0; + struct drv_spi_bus *bus = DRV_SPI_DEVICE(device->bus); + struct drv_cs * cs = (struct drv_cs *)device->parent.user_data; + RT_ASSERT(bus != RT_NULL); + + gpiohs_set_drive_mode(cs->cs_pin, GPIO_DM_OUTPUT); + gpiohs_set_pin(cs->cs_pin, GPIO_PV_HIGH); + +#ifdef BSP_USING_SPI1_AS_QSPI + /* Todo:QSPI*/ +#else + spi_init(bus->spi_instance, configuration->mode & RT_SPI_MODE_3, SPI_FF_STANDARD, configuration->data_width, 0); +#endif + freq = spi_set_clk_rate(bus->spi_instance, configuration->max_hz > MAX_CLOCK ? MAX_CLOCK : configuration->max_hz); + rt_kprintf("set spi freq %d\n", freq); + return ret; +} + + +void __spi_set_tmod(uint8_t spi_num, uint32_t tmod) +{ + RT_ASSERT(spi_num < SPI_DEVICE_MAX); + volatile spi_t *spi_handle = spi[spi_num]; + uint8_t tmod_offset = 0; + switch(spi_num) + { + case 0: + case 1: + case 2: + tmod_offset = 8; + break; + case 3: + default: + tmod_offset = 10; + break; + } + set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset); +} +int dma_irq_callback(void *ctx) +{ + struct rt_completion * cmp = ctx; + if(cmp) + { + rt_completion_done(cmp); + } +} + +static rt_uint32_t drv_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + struct drv_spi_bus *bus = DRV_SPI_DEVICE(device->bus); + struct drv_cs * cs = (struct drv_cs *)device->parent.user_data; + struct rt_spi_configuration *cfg = &device->config; + uint32_t * tx_buff = RT_NULL; + uint32_t * rx_buff = RT_NULL; + int i; + rt_ubase_t dummy = 0xFFFFFFFFU; + if(cfg->data_width != 8) + { + return 0; + } + + RT_ASSERT(bus != RT_NULL); + + if(message->cs_take) + { + gpiohs_set_pin(cs->cs_pin, GPIO_PV_LOW); + } + if(message->length) + { + bus->dma_send_channel = DMAC_CHANNEL_MAX; + bus->dma_recv_channel = DMAC_CHANNEL_MAX; + + rt_completion_init(&bus->dma_completion); + if(message->recv_buf) + { + dmalock_sync_take(&bus->dma_recv_channel, RT_WAITING_FOREVER); + sysctl_dma_select(bus->dma_recv_channel, SYSCTL_DMA_SELECT_SSI0_RX_REQ + bus->spi_instance * 2); + rx_buff = rt_calloc(message->length * 4, 1); + if(!rx_buff) + { + goto transfer_done; + } + } + + if(message->send_buf) + { + dmalock_sync_take(&bus->dma_send_channel, RT_WAITING_FOREVER); + sysctl_dma_select(bus->dma_send_channel, SYSCTL_DMA_SELECT_SSI0_TX_REQ + bus->spi_instance * 2); + tx_buff = rt_malloc(message->length * 4); + if(!tx_buff) + { + goto transfer_done; + } + for(i = 0; i < message->length; i++) + { + tx_buff[i] = ((uint8_t *)message->send_buf)[i]; + } + } + + if(message->send_buf && message->recv_buf) + { + dmac_irq_register(bus->dma_recv_channel, dma_irq_callback, &bus->dma_completion, 1); + __spi_set_tmod(bus->spi_instance, SPI_TMOD_TRANS_RECV); + spi_instance[bus->spi_instance]->dmacr = 0x3; + spi_instance[bus->spi_instance]->ssienr = 0x01; + dmac_set_single_mode(bus->dma_recv_channel, (void *)(&spi_instance[bus->spi_instance]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, + DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, message->length); + dmac_set_single_mode(bus->dma_send_channel, tx_buff, (void *)(&spi_instance[bus->spi_instance]->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, + DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, message->length); + } + else if(message->send_buf) + { + dmac_irq_register(bus->dma_send_channel, dma_irq_callback, &bus->dma_completion, 1); + __spi_set_tmod(bus->spi_instance, SPI_TMOD_TRANS); + spi_instance[bus->spi_instance]->dmacr = 0x2; + spi_instance[bus->spi_instance]->ssienr = 0x01; + dmac_set_single_mode(bus->dma_send_channel, tx_buff, (void *)(&spi_instance[bus->spi_instance]->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, + DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, message->length); + } + else if(message->recv_buf) + { + dmac_irq_register(bus->dma_recv_channel, dma_irq_callback, &bus->dma_completion, 1); + __spi_set_tmod(bus->spi_instance, SPI_TMOD_RECV); + spi_instance[bus->spi_instance]->ctrlr1 = message->length - 1; + spi_instance[bus->spi_instance]->dmacr = 0x1; + spi_instance[bus->spi_instance]->ssienr = 0x01; + spi_instance[bus->spi_instance]->dr[0] = 0xFF; + dmac_set_single_mode(bus->dma_recv_channel, (void *)(&spi_instance[bus->spi_instance]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, + DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, message->length); + } + else + { + goto transfer_done; + } + spi_instance[bus->spi_instance]->ser = 1U << cs->cs_index; + + rt_completion_wait(&bus->dma_completion, RT_WAITING_FOREVER); + if(message->recv_buf) + dmac_irq_unregister(bus->dma_recv_channel); + else + dmac_irq_unregister(bus->dma_send_channel); + + // wait until all data has been transmitted + while ((spi_instance[bus->spi_instance]->sr & 0x05) != 0x04) + ; + spi_instance[bus->spi_instance]->ser = 0x00; + spi_instance[bus->spi_instance]->ssienr = 0x00; + + if(message->recv_buf) + { + for(i = 0; i < message->length; i++) + { + ((uint8_t *)message->recv_buf)[i] = (uint8_t)rx_buff[i]; + } + } + +transfer_done: + dmalock_release(bus->dma_send_channel); + dmalock_release(bus->dma_recv_channel); + if(tx_buff) + { + rt_free(tx_buff); + } + if(rx_buff) + { + rt_free(rx_buff); + } + } + + if(message->cs_release) + { + gpiohs_set_pin(cs->cs_pin, GPIO_PV_HIGH); + } + + return message->length; +} + +const static struct rt_spi_ops drv_spi_ops = +{ + drv_spi_configure, + drv_spi_xfer +}; + +int rt_hw_spi_init(void) +{ + rt_err_t ret = RT_EOK; + +#ifdef BSP_USING_SPI1 + { + static struct drv_spi_bus spi_bus1; + spi_bus1.spi_instance = SPI_DEVICE_1; + ret = rt_spi_bus_register(&spi_bus1.parent, "spi1", &drv_spi_ops); + +#ifdef BSP_SPI1_USING_SS0 + { + static struct rt_spi_device spi_device10; + static struct drv_cs cs10 = + { + .cs_index = SPI_CHIP_SELECT_0, + .cs_pin = SPI1_CS0_PIN + }; + + rt_spi_bus_attach_device(&spi_device10, "spi10", "spi1", (void *)&cs10); + } +#endif + +#ifdef BSP_SPI1_USING_SS1 + { + static struct rt_spi_device spi_device11; + static struct drv_cs cs11 = + { + .cs_index = SPI_CHIP_SELECT_1, + .cs_pin = SPI1_CS1_PIN + }; + rt_spi_bus_attach_device(&spi_device11, "spi11", "spi1", (void *)&cs11); + } +#endif + +#ifdef BSP_SPI1_USING_SS2 + { + static struct rt_spi_device spi_device12; + static struct drv_cs cs12 = + { + .cs_index = SPI_CHIP_SELECT_2, + .cs_pin = SPI1_CS2_PIN + }; + rt_spi_bus_attach_device(&spi_device12, "spi12", "spi1", (void *)&cs12); + } +#endif + +#ifdef BSP_SPI1_USING_SS3 + { + static struct rt_spi_device spi_device13; + static struct drv_cs cs13 = + { + .cs_index = SPI_CHIP_SELECT_2, + .cs_pin = SPI1_CS2_PIN + }; + rt_spi_bus_attach_device(&spi_device13, "spi13", "spi1", (void *)&cs13); + } +#endif + } +#endif + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_spi_init); +#endif diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_spi.h b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_spi.h new file mode 100644 index 000000000..78c973e0e --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_spi.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-18 ZYH first version + */ + +#ifndef DRV_SPI_H__ +#define DRV_SPI_H__ + +int rt_hw_spi_init(void); + +#endif diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/heap.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/heap.c new file mode 100644 index 000000000..f1d6d2c27 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/heap.c @@ -0,0 +1,11 @@ +#include +#include + +size_t get_free_heap_size(void) +{ + rt_uint32_t total, used, max; + + rt_memory_info(&total, &used, &max); + + return total - used; +} diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/sdcard_port.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/sdcard_port.c new file mode 100644 index 000000000..d3ef0652e --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/sdcard_port.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#ifdef BSP_USING_SDCARD +#if defined(RT_USING_SPI_MSD) && defined(RT_USING_DFS_ELMFAT) +#include +#include + +#define DBG_TAG "sdcard" +#define DBG_LVL DBG_INFO +#include + +int sd_mount(void) +{ + int ret = 0; + ret = msd_init("sd0", "spi10"); + if(RT_EOK == ret) + { + if(dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + LOG_I("Mount /sd0 successfully"); + return RT_EOK; + } + else + { + LOG_E("Mount fail !!1"); + return -1; + } + } + LOG_E("msd_init fail !!!"); + return -2; +} +INIT_ENV_EXPORT(sd_mount); +#endif +#endif diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/Kconfig b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/Kconfig new file mode 100644 index 000000000..fb10c827c --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/Kconfig @@ -0,0 +1,7 @@ +menu "Kendryte SDK Config" + +config PKG_KENDRYTE_SDK_VERNUM + hex "Kendryte SDK Version" + default 0x0055 + +endmenu diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/SConscript b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/SConscript new file mode 100644 index 000000000..a4b1cce5c --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/SConscript @@ -0,0 +1,37 @@ +from building import * + +cwd = GetCurrentDir() +src = Split(''' +kendryte-sdk-source/lib/bsp/entry.c +kendryte-sdk-source/lib/bsp/entry_user.c +kendryte-sdk-source/lib/drivers/aes.c +kendryte-sdk-source/lib/drivers/clint.c +kendryte-sdk-source/lib/drivers/dmac.c +kendryte-sdk-source/lib/drivers/dvp.c +kendryte-sdk-source/lib/drivers/fft.c +kendryte-sdk-source/lib/drivers/fpioa.c +kendryte-sdk-source/lib/drivers/gpio.c +kendryte-sdk-source/lib/drivers/gpiohs.c +kendryte-sdk-source/lib/drivers/i2c.c +kendryte-sdk-source/lib/drivers/i2s.c +kendryte-sdk-source/lib/drivers/kpu.c +kendryte-sdk-source/lib/drivers/plic.c +kendryte-sdk-source/lib/drivers/pwm.c +kendryte-sdk-source/lib/drivers/rtc.c +kendryte-sdk-source/lib/drivers/sha256.c +kendryte-sdk-source/lib/drivers/spi.c +kendryte-sdk-source/lib/drivers/sysctl.c +kendryte-sdk-source/lib/drivers/timer.c +kendryte-sdk-source/lib/drivers/uart.c +kendryte-sdk-source/lib/drivers/uarths.c +kendryte-sdk-source/lib/drivers/utils.c +kendryte-sdk-source/lib/drivers/wdt.c +''') +CPPPATH = [cwd + '/kendryte-sdk-source/lib/drivers/include', +cwd + '/kendryte-sdk-source/lib/bsp/include', +cwd + '/kendryte-sdk-source/lib/utils/include'] +CPPDEFINES = ['CONFIG_LOG_COLORS', 'CONFIG_LOG_ENABLE', 'CONFIG_LOG_LEVEL=LOG_VERBOSE', 'FPGA_PLL', 'LOG_KERNEL', '__riscv64'] + +group = DefineGroup('SDK', src, depend = [''], CPPPATH = CPPPATH, LOCAL_CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/link.lds b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/link.lds new file mode 100644 index 000000000..b09f56d6a --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/link.lds @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +INCLUDE "link_stacksize.lds" + +/* + * The OUTPUT_ARCH command specifies the machine architecture where the + * argument is one of the names used in the Kendryte library. + */ +OUTPUT_ARCH( "riscv" ) + +MEMORY +{ + /* 6M SRAM */ + SRAM : ORIGIN = 0x80000000, LENGTH = 0x600000 +} + +ENTRY(_start) +SECTIONS +{ + . = 0x80000000 ; + + /* __STACKSIZE__ = 4096; */ + + .start : + { + *(.start); + } > SRAM + + . = ALIGN(8); + + .text : + { + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(8); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(8); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(8); + + /* section information for initial. */ + . = ALIGN(8); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(8); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + . = ALIGN(8); + + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + . = ALIGN(8); + _etext = .; + } > SRAM + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + *(.eh_frame_entry) + } > SRAM + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM + + . = ALIGN(8); + + .data : + { + *(.data) + *(.data.*) + + *(.data1) + *(.data1.*) + + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.sdata) + *(.sdata.*) + } > SRAM + + /* stack for dual core */ + .stack : + { + . = ALIGN(64); + __stack_start__ = .; + + . += __STACKSIZE__; + __stack_cpu0 = .; + + . += __STACKSIZE__; + __stack_cpu1 = .; + } > SRAM + + .sbss : + { + __bss_start = .; + *(.sbss) + *(.sbss.*) + *(.dynsbss) + *(.scommon) + } > SRAM + + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + __bss_end = .; + } > SRAM + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/link_stacksize.lds b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/link_stacksize.lds new file mode 100644 index 000000000..1dd893422 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/link_stacksize.lds @@ -0,0 +1 @@ +__STACKSIZE__ = 4096; \ No newline at end of file diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.h b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.h new file mode 100644 index 000000000..ae69bd39a --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.h @@ -0,0 +1,373 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* XIUOS Rt-thread Configuration */ + +#define ROOT_DIR "../../../.." +#define BSP_DIR "." +#define RT_Thread_DIR "../.." +#define RTT_DIR "../../rt-thread" +#define BOARD_K210_EVB + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_USING_SMP +#define RT_CPUS_NR 2 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 4096 +#define SYSTEM_THREAD_STACK_SIZE 4096 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR +#define RT_DEBUG_INIT_CONFIG +#define RT_DEBUG_INIT 1 + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_SLAB +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uarths" +#define RT_VER_NUM 0x40004 +#define ARCH_CPU_64BIT +#define ARCH_RISCV +#define ARCH_RISCV_FPU +#define ARCH_RISCV_FPU_S +#define ARCH_RISCV64 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 8192 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +#define RT_USING_CPLUSPLUS + +/* Command shell */ + +#define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 16384 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 16 +#define DFS_FILESYSTEM_TYPES_MAX 16 +#define DFS_FD_MAX 64 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_RTC +#define RT_USING_SPI +#define RT_USING_SPI_MSD +#define RT_USING_SFUD +#define RT_SFUD_USING_SFDP +#define RT_SFUD_USING_FLASH_INFO_TABLE +#define RT_SFUD_SPI_MAX_HZ 50000000 +#define RT_DEBUG_SFUD +#define RT_USING_WIFI +#define RT_WLAN_DEVICE_STA_NAME "wlan0" +#define RT_WLAN_DEVICE_AP_NAME "wlan1" +#define RT_WLAN_SSID_MAX_LENGTH 32 +#define RT_WLAN_PASSWORD_MAX_LENGTH 32 +#define RT_WLAN_DEV_EVENT_NUM 2 +#define RT_WLAN_MANAGE_ENABLE +#define RT_WLAN_SCAN_WAIT_MS 10000 +#define RT_WLAN_CONNECT_WAIT_MS 10000 +#define RT_WLAN_SCAN_SORT +#define RT_WLAN_MSH_CMD_ENABLE +#define RT_WLAN_AUTO_CONNECT_ENABLE +#define AUTO_CONNECTION_PERIOD_MS 2000 +#define RT_WLAN_CFG_ENABLE +#define RT_WLAN_CFG_INFO_MAX 3 +#define RT_WLAN_PROT_ENABLE +#define RT_WLAN_PROT_NAME_LEN 8 +#define RT_WLAN_PROT_MAX 2 +#define RT_WLAN_DEFAULT_PROT "lwip" +#define RT_WLAN_PROT_LWIP_ENABLE +#define RT_WLAN_PROT_LWIP_NAME "lwip" +#define RT_WLAN_WORK_THREAD_ENABLE +#define RT_WLAN_WORKQUEUE_THREAD_NAME "wlan" +#define RT_WLAN_WORKQUEUE_THREAD_SIZE 2048 +#define RT_WLAN_WORKQUEUE_THREAD_PRIO 15 + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_PTHREADS +#define PTHREAD_NUM_MAX 8 +#define RT_USING_POSIX +#define RT_LIBC_USING_TIME +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + +#define RT_USING_SAL + +/* protocol stack implement */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX + +/* Network interface device */ + +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 + +/* light weight TCP/IP stack */ + +#define RT_USING_LWIP +#define RT_USING_LWIP202 +#define RT_LWIP_MEM_ALIGNMENT 8 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 10240 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 10240 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* Board Drivers Config */ + +#define BSP_USING_UART_HS + +/* General Purpose UARTs */ + +#define BSP_USING_UART1 +#define BSP_UART1_TXD_PIN 20 +#define BSP_UART1_RXD_PIN 21 +#define BSP_UART1_RTS_PIN -1 +#define BSP_UART1_CTS_PIN -1 +#define BSP_USING_SPI1 +#define BSP_SPI1_CLK_PIN 27 +#define BSP_SPI1_D0_PIN 28 +#define BSP_SPI1_D1_PIN 26 +#define BSP_SPI1_USING_SS0 +#define BSP_SPI1_SS0_PIN 29 +#define BSP_SPI1_USING_SS1 +#define BSP_SPI1_SS1_PIN 8 +#define BSP_USING_LCD +#define BSP_LCD_CS_PIN 36 +#define BSP_LCD_WR_PIN 39 +#define BSP_LCD_DC_PIN 38 +#define BSP_LCD_RST_PIN 37 +#define BSP_LCD_BACKLIGHT_PIN -1 +#define BSP_LCD_BACKLIGHT_ACTIVE_LOW +#define BSP_LCD_CLK_FREQ 20000000 +#define BSP_BOARD_USER +#define BSP_LCD_X_MAX 240 +#define BSP_LCD_Y_MAX 320 +#define BSP_USING_SDCARD +#define BSP_USING_DVP + +/* The default pin assignment is based on the Maix Duino K210 development board */ + +#define BSP_DVP_SCCB_SDA_PIN 40 +#define BSP_DVP_SCCB_SCLK_PIN 41 +#define BSP_DVP_CMOS_RST_PIN 42 +#define BSP_DVP_CMOS_VSYNC_PIN 43 +#define BSP_DVP_CMOS_PWDN_PIN 44 +#define BSP_DVP_CMOS_XCLK_PIN 46 +#define BSP_DVP_CMOS_PCLK_PIN 47 +#define BSP_DVP_CMOS_HREF_PIN 45 +#define BSP_USING_CH438 +#define BSP_CH438_ALE_PIN 23 +#define BSP_CH438_NWR_PIN 24 +#define BSP_CH438_NRD_PIN 25 +#define BSP_CH438_D0_PIN 27 +#define BSP_CH438_D1_PIN 28 +#define BSP_CH438_D2_PIN 29 +#define BSP_CH438_D3_PIN 30 +#define BSP_CH438_D4_PIN 31 +#define BSP_CH438_D5_PIN 32 +#define BSP_CH438_D6_PIN 33 +#define BSP_CH438_D7_PIN 34 +#define BSP_CH438_INT_PIN 35 + +/* Kendryte SDK Config */ + +#define PKG_KENDRYTE_SDK_VERNUM 0x0055 + +/* More Drivers */ + +#define DRV_USING_OV2640 +#define OV2640_JPEG_MODE +#define OV2640_X_RESOLUTION_IMAGE_OUTSIZE 240 +#define OV2640_Y_RESOLUTION_IMAGE_OUTSIZE 240 +#define OV2640_X_IMAGE_WINDOWS_SIZE 400 + +/* the value must be greater than OV2640_X_RESOLUTION_IMAGE_OUTSIZE */ + +#define OV2640_Y_IMAGE_WINDOWS_SIZE 400 + +/* the value must be greater than OV2640_Y_RESOLUTION_IMAGE_OUTSIZE */ + +/* APP_Framework */ + +/* Framework */ + +#define TRANSFORM_LAYER_ATTRIUBUTE +#define ADD_XIZI_FETURES +#define SUPPORT_KNOWING_FRAMEWORK +#define USING_KPU_PROCESSING +#define USING_YOLOV2 +#define USING_YOLOV2_JSONPARSER +#define USING_K210_YOLOV2_DETECT + +/* Security */ + + +/* Applications */ + +/* config stack size and priority of main task */ + +#define MAIN_KTASK_STACK_SIZE 1024 + +/* ota app */ + + +/* test app */ + + +/* connection app */ + + +/* control app */ + +/* knowing app */ + +#define APPLICATION_KNOWING +#define K210_DETECT_ENTRY + +/* sensor app */ + +#define APPLICATION_SENSOR + +/* lib */ + +#define APP_SELECT_NEWLIB +#define LIB_USING_CJSON +#define __STACKSIZE__ 4096 + +#endif diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.py b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.py new file mode 100644 index 000000000..277797109 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.py @@ -0,0 +1,49 @@ +import os + +# toolchains options +ARCH ='risc-v' +CPU ='k210' +CROSS_TOOL ='gcc' + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin' +else: + print('Please make sure your toolchains is GNU GCC!') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + PREFIX = 'riscv-none-embed-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcmodel=medany -march=rv64imafc -mabi=lp64f -fsingle-precision-constant' + CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -ggdb' + AFLAGS += ' -ggdb' + else: + CFLAGS += ' -O2 -Os' + + CXXFLAGS = CFLAGS + # we use c++ 11, but -std=c++11 don't have 'struct siginfo', need gnu++11 + CXXFLAGS += ' -std=gnu++11' + +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/Ubiquitous/RT_Thread/build.sh b/Ubiquitous/RT_Thread/build.sh old mode 100644 new mode 100755 diff --git a/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/arch_interrupt.h b/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/arch_interrupt.h index 3544f8410..4ef8b6353 100755 --- a/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/arch_interrupt.h +++ b/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/arch_interrupt.h @@ -1,3 +1,11 @@ +/** +* @file arch_interrupt.h +* @brief support rv32m1_vega interrupt +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-02-16 +*/ + #ifndef ARCH_INTERRUPT_H__ #define ARCH_INTERRUPT_H__ diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/fsl_semc.c b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/fsl_semc.c index be3f225e7..83ec1ebf7 100644 --- a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/fsl_semc.c +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/fsl_semc.c @@ -5,6 +5,26 @@ * SPDX-License-Identifier: BSD-3-Clause */ +/** + * @file board.c + * @brief relative configure for ok1052-c + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + +/************************************************* +File name: board.c +Description: support imxrt1052-board init function +Others: take SDK_2.6.1_MIMXRT1052xxxxB for references +History: +1. Date: 2022-01-25 +Author: AIIT XUOS Lab +Modification: +1. support imxrt1052-board MPU、clock、memory init +2. support imxrt1052-board uart、semc、sdio driver init +*************************************************/ + #include "fsl_semc.h" /*******************************************************************************