diff --git a/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/startup_RV32M1_zero_riscy.S b/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/startup_RV32M1_zero_riscy.S
index cb180e747..943b5ff63 100644
--- a/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/startup_RV32M1_zero_riscy.S
+++ b/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/startup_RV32M1_zero_riscy.S
@@ -33,7 +33,7 @@ History:
 Author: AIIT XUOS Lab
 Modification:  
 *************************************************/
-
+.extern Rv32m1VgeaStart
 #define EXCEPTION_STACK_SIZE 0x58
 
     .text
@@ -108,7 +108,7 @@ Reset_Handler:
     # Enable global interrupt. */
     csrsi mstatus, 8
 
-    jal main
+    jal Rv32m1VgeaStart
     ebreak
 
     .size Reset_Handler, . - Reset_Handler