From c88dc282fcbfd7f3acee50632dde29cf6c3ade27 Mon Sep 17 00:00:00 2001 From: Wang_Weigen Date: Mon, 17 Jan 2022 15:05:42 +0800 Subject: [PATCH] add semc and extern sram test for ok-1052 --- Ubiquitous/XiUOS/board/ok1052-c/board.c | 27 + .../board/ok1052-c/third_party_driver/Kconfig | 26 +- .../ok1052-c/third_party_driver/Makefile | 4 + .../third_party_driver/common/pin_mux.c | 553 ++++++++- .../ok1052-c/third_party_driver/semc/Kconfig | 9 + .../ok1052-c/third_party_driver/semc/Makefile | 3 + .../third_party_driver/semc/connect_semc.c | 57 + .../third_party_driver/semc/fsl_semc.c | 1066 +++++++++++++++++ .../third_party_driver/semc/fsl_semc.h | 830 +++++++++++++ .../semc/semc_externsdram_test.c | 180 +++ .../XiUOS/kernel/kernel_test/extsram_test.c | 12 +- Ubiquitous/XiUOS/kernel/memory/byte_manage.c | 14 +- 12 files changed, 2762 insertions(+), 19 deletions(-) create mode 100644 Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/Kconfig create mode 100644 Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/Makefile create mode 100644 Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/connect_semc.c create mode 100644 Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/fsl_semc.c create mode 100644 Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/fsl_semc.h create mode 100644 Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/semc_externsdram_test.c diff --git a/Ubiquitous/XiUOS/board/ok1052-c/board.c b/Ubiquitous/XiUOS/board/ok1052-c/board.c index fe07ae869..02fd1cd76 100644 --- a/Ubiquitous/XiUOS/board/ok1052-c/board.c +++ b/Ubiquitous/XiUOS/board/ok1052-c/board.c @@ -29,6 +29,14 @@ #include "board.h" #include "pin_mux.h" + +#ifdef BSP_USING_SEMC +extern status_t BOARD_InitSEMC(void); +#ifdef BSP_USING_EXTSRAM +extern int ExtSramInit(void); +#endif +#endif + #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED #include "fsl_lpi2c.h" #endif /* SDK_I2C_BASED_COMPONENT_USED */ @@ -607,6 +615,23 @@ void InitBoardHardware() #endif InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END); +#ifdef BSP_USING_SEMC + CLOCK_InitSysPfd(kCLOCK_Pfd2, 29); + /* Set semc clock to 163.86 MHz */ + CLOCK_SetMux(kCLOCK_SemcMux, 1); + CLOCK_SetDiv(kCLOCK_SemcDiv, 1); + + if (BOARD_InitSEMC() != kStatus_Success) + { + KPrintf("\r\n SEMC Init Failed\r\n"); + } +#ifdef MEM_EXTERN_SRAM + else + { + ExtSramInit(); + } +#endif +#endif #ifdef BSP_USING_LWIP ETH_BSP_Config(); @@ -616,5 +641,7 @@ void InitBoardHardware() Imrt1052HwUartInit(); #endif InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME); + + } diff --git a/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/Kconfig b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/Kconfig index 8674a2ef6..a0480d689 100644 --- a/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/Kconfig +++ b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/Kconfig @@ -1,12 +1,20 @@ menuconfig BSP_USING_LPUART -bool "Using UART device" -default y -select RESOURCES_SERIAL -if BSP_USING_LPUART -source "$BSP_DIR/third_party_driver/uart/Kconfig" -endif + bool "Using UART device" + default y + select RESOURCES_SERIAL + if BSP_USING_LPUART + source "$BSP_DIR/third_party_driver/uart/Kconfig" + endif menuconfig BSP_USING_LWIP -bool "Using LwIP device" -default n -select RESOURCES_LWIP + bool "Using LwIP device" + default n + select RESOURCES_LWIP + +menuconfig BSP_USING_SEMC + bool "Using SEMC device" + default y + + if BSP_USING_SEMC + source "$BSP_DIR/third_party_driver/semc/Kconfig" + endif diff --git a/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/Makefile b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/Makefile index 71b25e5e8..b55123bc5 100644 --- a/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/Makefile +++ b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/Makefile @@ -8,4 +8,8 @@ ifeq ($(CONFIG_BSP_USING_LWIP),y) SRC_DIR += ethernet endif +ifeq ($(CONFIG_BSP_USING_SEMC),y) + SRC_DIR += semc +endif + include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/common/pin_mux.c b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/common/pin_mux.c index 8d0a4cf50..8504b75df 100755 --- a/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/common/pin_mux.c +++ b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/common/pin_mux.c @@ -46,6 +46,557 @@ void BOARD_InitBootPins(void) { BOARD_InitPins(); } +void SemcPinmuxConfig(void) +{ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 is configured as SEMC_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 is configured as SEMC_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 is configured as SEMC_DATA02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 is configured as SEMC_DATA03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 is configured as SEMC_DATA04 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 is configured as SEMC_DATA05 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 is configured as SEMC_DATA06 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 is configured as SEMC_DATA07 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 is configured as SEMC_DM00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_09_SEMC_ADDR00, /* GPIO_EMC_09 is configured as SEMC_ADDR00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_10_SEMC_ADDR01, /* GPIO_EMC_10 is configured as SEMC_ADDR01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_11_SEMC_ADDR02, /* GPIO_EMC_11 is configured as SEMC_ADDR02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_12_SEMC_ADDR03, /* GPIO_EMC_12 is configured as SEMC_ADDR03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_13_SEMC_ADDR04, /* GPIO_EMC_13 is configured as SEMC_ADDR04 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_14_SEMC_ADDR05, /* GPIO_EMC_14 is configured as SEMC_ADDR05 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_15_SEMC_ADDR06, /* GPIO_EMC_15 is configured as SEMC_ADDR06 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_16_SEMC_ADDR07, /* GPIO_EMC_16 is configured as SEMC_ADDR07 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_17_SEMC_ADDR08, /* GPIO_EMC_17 is configured as SEMC_ADDR08 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_18_SEMC_ADDR09, /* GPIO_EMC_18 is configured as SEMC_ADDR09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_19_SEMC_ADDR11, /* GPIO_EMC_19 is configured as SEMC_ADDR11 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_20_SEMC_ADDR12, /* GPIO_EMC_20 is configured as SEMC_ADDR12 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_21_SEMC_BA0, /* GPIO_EMC_21 is configured as SEMC_BA0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_22_SEMC_BA1, /* GPIO_EMC_22 is configured as SEMC_BA1 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_23_SEMC_ADDR10, /* GPIO_EMC_23 is configured as SEMC_ADDR10 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_24_SEMC_CAS, /* GPIO_EMC_24 is configured as SEMC_CAS */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_25_SEMC_RAS, /* GPIO_EMC_25 is configured as SEMC_RAS */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_26_SEMC_CLK, /* GPIO_EMC_26 is configured as SEMC_CLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_27_SEMC_CKE, /* GPIO_EMC_27 is configured as SEMC_CKE */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_28_SEMC_WE, /* GPIO_EMC_28 is configured as SEMC_WE */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_29_SEMC_CS0, /* GPIO_EMC_29 is configured as SEMC_CS0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_30_SEMC_DATA08, /* GPIO_EMC_30 is configured as SEMC_DATA08 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_31_SEMC_DATA09, /* GPIO_EMC_31 is configured as SEMC_DATA09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_32_SEMC_DATA10, /* GPIO_EMC_32 is configured as SEMC_DATA10 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_33_SEMC_DATA11, /* GPIO_EMC_33 is configured as SEMC_DATA11 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_34_SEMC_DATA12, /* GPIO_EMC_34 is configured as SEMC_DATA12 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_35_SEMC_DATA13, /* GPIO_EMC_35 is configured as SEMC_DATA13 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_36_SEMC_DATA14, /* GPIO_EMC_36 is configured as SEMC_DATA14 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_37_SEMC_DATA15, /* GPIO_EMC_37 is configured as SEMC_DATA15 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_38_SEMC_DM01, /* GPIO_EMC_38 is configured as SEMC_DM01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_39_SEMC_DQS, /* GPIO_EMC_39 is configured as SEMC_DQS */ + 1U); /* Software Input On Field: Force input path of pad GPIO_EMC_39 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_40_SEMC_RDY, /* GPIO_EMC_40 is configured as SEMC_RDY */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_41_SEMC_CSX00, /* GPIO_EMC_41 is configured as SEMC_CSX00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_09_SEMC_ADDR00, /* GPIO_EMC_09 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_10_SEMC_ADDR01, /* GPIO_EMC_10 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_11_SEMC_ADDR02, /* GPIO_EMC_11 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_12_SEMC_ADDR03, /* GPIO_EMC_12 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_13_SEMC_ADDR04, /* GPIO_EMC_13 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_14_SEMC_ADDR05, /* GPIO_EMC_14 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_15_SEMC_ADDR06, /* GPIO_EMC_15 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_16_SEMC_ADDR07, /* GPIO_EMC_16 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_17_SEMC_ADDR08, /* GPIO_EMC_17 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_18_SEMC_ADDR09, /* GPIO_EMC_18 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_19_SEMC_ADDR11, /* GPIO_EMC_19 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_20_SEMC_ADDR12, /* GPIO_EMC_20 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_21_SEMC_BA0, /* GPIO_EMC_21 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_22_SEMC_BA1, /* GPIO_EMC_22 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_23_SEMC_ADDR10, /* GPIO_EMC_23 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_24_SEMC_CAS, /* GPIO_EMC_24 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_25_SEMC_RAS, /* GPIO_EMC_25 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_26_SEMC_CLK, /* GPIO_EMC_26 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_27_SEMC_CKE, /* GPIO_EMC_27 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_28_SEMC_WE, /* GPIO_EMC_28 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_29_SEMC_CS0, /* GPIO_EMC_29 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_30_SEMC_DATA08, /* GPIO_EMC_30 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_31_SEMC_DATA09, /* GPIO_EMC_31 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_32_SEMC_DATA10, /* GPIO_EMC_32 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_33_SEMC_DATA11, /* GPIO_EMC_33 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_34_SEMC_DATA12, /* GPIO_EMC_34 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_35_SEMC_DATA13, /* GPIO_EMC_35 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_36_SEMC_DATA14, /* GPIO_EMC_36 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_37_SEMC_DATA15, /* GPIO_EMC_37 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_38_SEMC_DM01, /* GPIO_EMC_38 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_39_SEMC_DQS, /* GPIO_EMC_39 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_40_SEMC_RDY, /* GPIO_EMC_40 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_41_SEMC_CSX00, /* GPIO_EMC_41 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ +} /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitPins: @@ -94,7 +645,7 @@ void BOARD_InitPins(void) { // IOMUXC_SetPinMux( // IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ // 0U); /* Software Input On Field: Input Path is determined by functionality */ - + SemcPinmuxConfig(); IOMUXC_SetPinMux( IOMUXC_GPIO_AD_B0_03_GPIO1_IO03, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ diff --git a/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/Kconfig b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/Kconfig new file mode 100644 index 000000000..f081299fb --- /dev/null +++ b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/Kconfig @@ -0,0 +1,9 @@ +config BSP_USING_EXTSRAM + bool "config semc extern sram" + default n + select MEM_EXTERN_SRAM + if BSP_USING_EXTSRAM + config EXTSRAM_MAX_NUM + int "config extsram chip num" + default 4 + endif diff --git a/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/Makefile b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/Makefile new file mode 100644 index 000000000..6438aa6ea --- /dev/null +++ b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_semc.c fsl_semc.c semc_externsdram_test.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/connect_semc.c b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/connect_semc.c new file mode 100644 index 000000000..1f05cd4ed --- /dev/null +++ b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/connect_semc.c @@ -0,0 +1,57 @@ +#include "fsl_semc.h" +#include "clock_config.h" +#include + +#define EXAMPLE_SEMC SEMC +#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U) +#define EXAMPLE_SEMC_CLK_FREQ CLOCK_GetFreq(kCLOCK_SemcClk) +#define SEMC_SRAM_SIZE (32 * 1024) + +status_t BOARD_InitSEMC(void) +{ + semc_config_t config; + semc_sdram_config_t sdramconfig; + uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ; + + /* Initializes the MAC configure structure to zero. */ + memset(&config, 0, sizeof(semc_config_t)); + memset(&sdramconfig, 0, sizeof(semc_sdram_config_t)); + + /* Initialize SEMC. */ + SEMC_GetDefaultConfig(&config); + config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */ + SEMC_Init(SEMC, &config); + + /* Configure SDRAM. */ + sdramconfig.csxPinMux = kSEMC_MUXCSX0; + sdramconfig.address = 0x80000000; + sdramconfig.memsize_kbytes = 32 * 1024; /* 32MB = 32*1024*1KBytes*/ + sdramconfig.portSize = kSEMC_PortSize16Bit; + sdramconfig.burstLen = kSEMC_Sdram_BurstLen8; + sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_9bit; + sdramconfig.casLatency = kSEMC_LatencyThree; + sdramconfig.tPrecharge2Act_Ns = 18; /* Trp 18ns */ + sdramconfig.tAct2ReadWrite_Ns = 18; /* Trcd 18ns */ + sdramconfig.tRefreshRecovery_Ns = 67; /* Use the maximum of the (Trfc , Txsr). */ + sdramconfig.tWriteRecovery_Ns = 12; /* 12ns */ + sdramconfig.tCkeOff_Ns = + 42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/ + sdramconfig.tAct2Prechage_Ns = 42; /* Tras 42ns */ + sdramconfig.tSelfRefRecovery_Ns = 67; + sdramconfig.tRefresh2Refresh_Ns = 60; + sdramconfig.tAct2Act_Ns = 60; + sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq); + sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */ + sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow; + sdramconfig.refreshBurstLen = 1; + return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq); +} + +#ifdef BSP_USING_EXTSRAM +int ExtSramInit(void) +{ + extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx); + ExtSramInitBoardMemory((void*)(EXAMPLE_SEMC_START_ADDRESS), (void*)((EXAMPLE_SEMC_START_ADDRESS + SEMC_SRAM_SIZE)), kSEMC_SDRAM_CS0); + return 0; +} +#endif \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/fsl_semc.c b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/fsl_semc.c new file mode 100644 index 000000000..be3f225e7 --- /dev/null +++ b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/fsl_semc.c @@ -0,0 +1,1066 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_semc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.semc" +#endif + +/*! @brief Define macros for SEMC driver. */ +#define SEMC_IPCOMMANDDATASIZEBYTEMAX (4U) +#define SEMC_IPCOMMANDMAGICKEY (0xA55A) +#define SEMC_IOCR_PINMUXBITWIDTH (0x3U) +#define SEMC_IOCR_NAND_CE (4U) +#define SEMC_IOCR_NOR_CE (5U) +#define SEMC_IOCR_NOR_CE_A8 (2U) +#define SEMC_IOCR_PSRAM_CE (6U) +#define SEMC_IOCR_PSRAM_CE_A8 (3U) +#define SEMC_IOCR_DBI_CSX (7U) +#define SEMC_IOCR_DBI_CSX_A8 (4U) +#define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE (24U) +#define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX (28U) +#define SEMC_BMCR0_TYPICAL_WQOS (5U) +#define SEMC_BMCR0_TYPICAL_WAGE (8U) +#define SEMC_BMCR0_TYPICAL_WSH (0x40U) +#define SEMC_BMCR0_TYPICAL_WRWS (0x10U) +#define SEMC_BMCR1_TYPICAL_WQOS (5U) +#define SEMC_BMCR1_TYPICAL_WAGE (8U) +#define SEMC_BMCR1_TYPICAL_WPH (0x60U) +#define SEMC_BMCR1_TYPICAL_WBR (0x40U) +#define SEMC_BMCR1_TYPICAL_WRWS (0x24U) +#define SEMC_STARTADDRESS (0x80000000U) +#define SEMC_ENDADDRESS (0xDFFFFFFFU) +#define SEMC_BR_MEMSIZE_MIN (4) +#define SEMC_BR_MEMSIZE_OFFSET (2) +#define SEMC_BR_MEMSIZE_MAX (4 * 1024 * 1024) +#define SEMC_SDRAM_MODESETCAL_OFFSET (4) +#define SEMC_BR_REG_NUM (9) +#define SEMC_BYTE_NUMBIT (8) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for SEMC module. + * + * @param base SEMC peripheral base address + */ +static uint32_t SEMC_GetInstance(SEMC_Type *base); + +/*! + * @brief Covert the input memory size to internal register set value. + * + * @param base SEMC peripheral base address + * @param size_kbytes SEMC memory size in unit of kbytes. + * @param sizeConverted SEMC converted memory size to 0 ~ 0x1F. + * @return Execution status. + */ +static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted); + +/*! + * @brief Covert the external timing nanosecond to internal clock cycle. + * + * @param time_ns SEMC external time interval in unit of nanosecond. + * @param clkSrc_Hz SEMC clock source frequency. + * @return The changed internal clock cycle. + */ +static uint8_t SEMC_ConvertTiming(uint32_t time_ns, uint32_t clkSrc_Hz); + +/*! + * @brief Configure IP command. + * + * @param base SEMC peripheral base address. + * @param size_bytes SEMC IP command data size. + * @return Execution status. + */ +static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes); + +/*! + * @brief Check if the IP command has finished. + * + * @param base SEMC peripheral base address. + * @return Execution status. + */ +static status_t SEMC_IsIPCommandDone(SEMC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to SEMC clocks for each instance. */ +static const clock_ip_name_t s_semcClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_CLOCKS; +static const clock_ip_name_t s_semcExtClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_EXSC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to SEMC bases for each instance. */ +static SEMC_Type *const s_semcBases[] = SEMC_BASE_PTRS; +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t SEMC_GetInstance(SEMC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_semcBases); instance++) + { + if (s_semcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_semcBases)); + + return instance; +} + +static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted) +{ + assert(sizeConverted); + uint32_t memsize; + + if ((size_kbytes < SEMC_BR_MEMSIZE_MIN) || (size_kbytes > SEMC_BR_MEMSIZE_MAX)) + { + return kStatus_SEMC_InvalidMemorySize; + } + + *sizeConverted = 0; + memsize = size_kbytes / 8; + while (memsize) + { + memsize >>= 1; + (*sizeConverted)++; + } + return kStatus_Success; +} + +static uint8_t SEMC_ConvertTiming(uint32_t time_ns, uint32_t clkSrc_Hz) +{ + assert(clkSrc_Hz); + + uint8_t clockCycles = 0; + uint32_t tClk_us; + + clkSrc_Hz /= 1000000; + tClk_us = 1000000 / clkSrc_Hz; + + while (tClk_us * clockCycles < (time_ns * 1000)) + { + clockCycles++; + } + + return clockCycles; +} + +static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes) +{ + if ((size_bytes > SEMC_IPCOMMANDDATASIZEBYTEMAX) || (!size_bytes)) + { + return kStatus_SEMC_InvalidIpcmdDataSize; + } + + /* Set data size. */ + /* Note: It is better to set data size as the device data port width when transfering + * device command data. but for device memory data transfer, it can be set freely. + * Note: If the data size is greater than data port width, for example, datsz = 4, data port = 16bit, + * then the 4-byte data transfer will be split into two 2-byte transfer, the slave address + * will be switched automatically according to connected device type*/ + base->IPCR1 = SEMC_IPCR1_DATSZ(size_bytes); + /* Clear data size. */ + base->IPCR2 = 0; + /* Set data size. */ + if (size_bytes < 4) + { + base->IPCR2 |= SEMC_IPCR2_BM3_MASK; + } + if (size_bytes < 3) + { + base->IPCR2 |= SEMC_IPCR2_BM2_MASK; + } + if (size_bytes < 2) + { + base->IPCR2 |= SEMC_IPCR2_BM1_MASK; + } + return kStatus_Success; +} + +static status_t SEMC_IsIPCommandDone(SEMC_Type *base) +{ + /* Poll status bit till command is done*/ + while (!(base->INTR & SEMC_INTR_IPCMDDONE_MASK)) + { + }; + + /* Clear status bit */ + base->INTR |= SEMC_INTR_IPCMDDONE_MASK; + + /* Check error status */ + if (base->INTR & SEMC_INTR_IPCMDERR_MASK) + { + base->INTR |= SEMC_INTR_IPCMDERR_MASK; + return kStatus_SEMC_IpCommandExecutionError; + } + + return kStatus_Success; +} + +/*! + * brief Gets the SEMC default basic configuration structure. + * + * The purpose of this API is to get the default SEMC + * configure structure for SEMC_Init(). User may use the initialized + * structure unchanged in SEMC_Init(), or modify some fields of the + * structure before calling SEMC_Init(). + * Example: + code + semc_config_t config; + SEMC_GetDefaultConfig(&config); + endcode + * param config The SEMC configuration structure pointer. + */ +void SEMC_GetDefaultConfig(semc_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + semc_queuea_weight_struct_t *queueaWeight = &(config->queueWeight.queueaWeight.queueaConfig); + semc_queueb_weight_struct_t *queuebWeight = &(config->queueWeight.queuebWeight.queuebConfig); + + /* Get default settings. */ + config->dqsMode = kSEMC_Loopbackinternal; + config->cmdTimeoutCycles = 0; + config->busTimeoutCycles = 0x1F; + + queueaWeight->qos = SEMC_BMCR0_TYPICAL_WQOS; + queueaWeight->aging = SEMC_BMCR0_TYPICAL_WAGE; + queueaWeight->slaveHitSwith = SEMC_BMCR0_TYPICAL_WSH; + queueaWeight->slaveHitNoswitch = SEMC_BMCR0_TYPICAL_WRWS; + queuebWeight->qos = SEMC_BMCR1_TYPICAL_WQOS; + queuebWeight->aging = SEMC_BMCR1_TYPICAL_WAGE; + queuebWeight->slaveHitSwith = SEMC_BMCR1_TYPICAL_WRWS; + queuebWeight->weightPagehit = SEMC_BMCR1_TYPICAL_WPH; + queuebWeight->bankRotation = SEMC_BMCR1_TYPICAL_WBR; +} + +/*! + * brief Initializes SEMC. + * This function ungates the SEMC clock and initializes SEMC. + * This function must be called before calling any other SEMC driver functions. + * + * param base SEMC peripheral base address. + * param configure The SEMC configuration structure pointer. + */ +void SEMC_Init(SEMC_Type *base, semc_config_t *configure) +{ + assert(configure); + + uint8_t index = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Un-gate sdram controller clock. */ + CLOCK_EnableClock(s_semcClock[SEMC_GetInstance(base)]); + CLOCK_EnableClock(s_semcExtClock[SEMC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Initialize all BR to zero due to the default base address set. */ + for (index = 0; index < SEMC_BR_REG_NUM; index++) + { + base->BR[index] = 0; + } + + /* Software reset for SEMC internal logical . */ + base->MCR = SEMC_MCR_SWRST_MASK; + while (base->MCR & SEMC_MCR_SWRST_MASK) + { + } + + /* Configure, disable module first. */ + base->MCR |= SEMC_MCR_MDIS_MASK | SEMC_MCR_BTO(configure->busTimeoutCycles) | + SEMC_MCR_CTO(configure->cmdTimeoutCycles) | SEMC_MCR_DQSMD(configure->dqsMode); + + /* Configure Queue 0/1 for AXI bus. */ + base->BMCR0 = (uint32_t)(configure->queueWeight.queueaWeight.queueaValue); + base->BMCR1 = (uint32_t)(configure->queueWeight.queuebWeight.queuebValue); + + /* Enable SEMC. */ + base->MCR &= ~SEMC_MCR_MDIS_MASK; +} + +/*! + * brief Deinitializes the SEMC module and gates the clock. + * This function gates the SEMC clock. As a result, the SEMC + * module doesn't work after calling this function. + * + * param base SEMC peripheral base address. + */ +void SEMC_Deinit(SEMC_Type *base) +{ + /* Disable module. Check there is no pending command before disable module. */ + while (!(base->STS0 & SEMC_STS0_IDLE_MASK)) + { + ; + } + + base->MCR |= SEMC_MCR_MDIS_MASK | SEMC_MCR_SWRST_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable SDRAM clock. */ + CLOCK_DisableClock(s_semcClock[SEMC_GetInstance(base)]); + CLOCK_DisableClock(s_semcExtClock[SEMC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Configures SDRAM controller in SEMC. + * + * param base SEMC peripheral base address. + * param cs The chip selection. + * param config The sdram configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + assert(clkSrc_Hz); + assert(config->refreshBurstLen); + + uint8_t memsize; + status_t result = kStatus_Success; + uint16_t prescale = config->tPrescalePeriod_Ns / 16 / (1000000000 / clkSrc_Hz); + uint16_t refresh; + uint16_t urgentRef; + uint16_t idle; + uint16_t mode; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + if (config->csxPinMux == kSEMC_MUXA8) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + + if (prescale > 256) + { + return kStatus_SEMC_InvalidTimerSetting; + } + + refresh = config->refreshPeriod_nsPerRow / config->tPrescalePeriod_Ns; + urgentRef = config->refreshUrgThreshold / config->tPrescalePeriod_Ns; + idle = config->tIdleTimeout_Ns / config->tPrescalePeriod_Ns; + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->csxPinMux); + + /* Base control. */ + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + + base->BR[cs] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->SDRAMCR0 = SEMC_SDRAMCR0_PS(config->portSize) | SEMC_SDRAMCR0_BL(config->burstLen) | + SEMC_SDRAMCR0_COL(config->columnAddrBitNum) | SEMC_SDRAMCR0_CL(config->casLatency); + /* IOMUX setting. */ + if (cs) + { + base->IOCR = iocReg | (cs << config->csxPinMux); + } + + base->IOCR &= ~SEMC_IOCR_MUX_A8_MASK; + + /* Timing setting. */ + base->SDRAMCR1 = SEMC_SDRAMCR1_PRE2ACT(SEMC_ConvertTiming(config->tPrecharge2Act_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_ACT2RW(SEMC_ConvertTiming(config->tAct2ReadWrite_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_RFRC(SEMC_ConvertTiming(config->tRefreshRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_WRC(SEMC_ConvertTiming(config->tWriteRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_CKEOFF(SEMC_ConvertTiming(config->tCkeOff_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_ACT2PRE(SEMC_ConvertTiming(config->tAct2Prechage_Ns, clkSrc_Hz) - 1); + base->SDRAMCR2 = + SEMC_SDRAMCR2_SRRC(SEMC_ConvertTiming(config->tSelfRefRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR2_REF2REF( + SEMC_ConvertTiming(config->tRefresh2Refresh_Ns, clkSrc_Hz)) | /* No Minus one to keep with RM */ + SEMC_SDRAMCR2_ACT2ACT(SEMC_ConvertTiming(config->tAct2Act_Ns, clkSrc_Hz)) | /* No Minus one to keep with RM */ + SEMC_SDRAMCR2_ITO(idle); + base->SDRAMCR3 = SEMC_SDRAMCR3_REBL(config->refreshBurstLen - 1) | + /* N * 16 * 1s / clkSrc_Hz = config->tPrescalePeriod_Ns */ + SEMC_SDRAMCR3_PRESCALE(prescale) | SEMC_SDRAMCR3_RT(refresh) | SEMC_SDRAMCR3_UT(urgentRef); + + SEMC->IPCR1 = 0x2; + SEMC->IPCR2 = 0; + + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_Prechargeall, 0, NULL); + if (result != kStatus_Success) + { + return result; + } + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_AutoRefresh, 0, NULL); + if (result != kStatus_Success) + { + return result; + } + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_AutoRefresh, 0, NULL); + if (result != kStatus_Success) + { + return result; + } + /* Mode setting value. */ + mode = (uint16_t)config->burstLen | (uint16_t)(config->casLatency << SEMC_SDRAM_MODESETCAL_OFFSET); + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_Modeset, mode, NULL); + if (result != kStatus_Success) + { + return result; + } + /* Enables refresh */ + base->SDRAMCR3 |= SEMC_SDRAMCR3_REN_MASK; + + return kStatus_Success; +} + +/*! + * brief Configures NAND controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The nand configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + assert(config->timingConfig); + + uint8_t memsize; + status_t result; + + if ((config->axiAddress < SEMC_STARTADDRESS) || (config->axiAddress > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + if (config->cePinMux == kSEMC_MUXRDY) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + + uint32_t iocReg = base->IOCR & ~((SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux) | SEMC_IOCR_MUX_RDY_MASK); + + /* Base control. */ + if (config->rdyactivePolarity == kSEMC_RdyActivehigh) + { + base->MCR |= SEMC_MCR_WPOL1_MASK; + } + else + { + base->MCR &= ~SEMC_MCR_WPOL1_MASK; + } + result = SEMC_CovertMemorySize(base, config->axiMemsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[4] = (config->axiAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + + result = SEMC_CovertMemorySize(base, config->ipgMemsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[8] = (config->ipgAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + + /* IOMUX setting. */ + if (config->cePinMux) + { + base->IOCR = iocReg | (SEMC_IOCR_NAND_CE << config->cePinMux); + } + else + { + base->IOCR = iocReg | (1U << config->cePinMux); + } + + base->NANDCR0 = SEMC_NANDCR0_PS(config->portSize) | SEMC_NANDCR0_BL(config->burstLen) | + SEMC_NANDCR0_EDO(config->edoModeEnabled) | SEMC_NANDCR0_COL(config->columnAddrBitNum); + + /* Timing setting. */ + base->NANDCR1 = SEMC_NANDCR1_CES(SEMC_ConvertTiming(config->timingConfig->tCeSetup_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_CEH(SEMC_ConvertTiming(config->timingConfig->tCeHold_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_WEL(SEMC_ConvertTiming(config->timingConfig->tWeLow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_WEH(SEMC_ConvertTiming(config->timingConfig->tWeHigh_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_REL(SEMC_ConvertTiming(config->timingConfig->tReLow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_REH(SEMC_ConvertTiming(config->timingConfig->tReHigh_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_TA(SEMC_ConvertTiming(config->timingConfig->tTurnAround_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_CEITV(SEMC_ConvertTiming(config->timingConfig->tCeInterval_Ns, clkSrc_Hz) - 1); + base->NANDCR2 = SEMC_NANDCR2_TWHR(SEMC_ConvertTiming(config->timingConfig->tWehigh2Relow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TRHW(SEMC_ConvertTiming(config->timingConfig->tRehigh2Welow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TADL(SEMC_ConvertTiming(config->timingConfig->tAle2WriteStart_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TRR(SEMC_ConvertTiming(config->timingConfig->tReady2Relow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TWB(SEMC_ConvertTiming(config->timingConfig->tWehigh2Busy_Ns, clkSrc_Hz) - 1); + base->NANDCR3 = config->arrayAddrOption; + return kStatus_Success; +} + +/*! + * brief Configures NOR controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The nor configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + + uint8_t memsize; + status_t result; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux); + uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ? + SEMC_IOCR_NOR_CE - 1 : + ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_NOR_CE_A8 : SEMC_IOCR_NOR_CE); + + /* IOMUX setting. */ + base->IOCR = iocReg | (muxCe << config->cePinMux); + /* Address bit setting. */ + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE) + { + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 1) + { + /* Address bit 24 (A24) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX0_MASK; + if (config->cePinMux == kSEMC_MUXCSX0) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 2) + { + /* Address bit 25 (A25) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX1_MASK; + if (config->cePinMux == kSEMC_MUXCSX1) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 3) + { + /* Address bit 26 (A26) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX2_MASK; + if (config->cePinMux == kSEMC_MUXCSX2) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 4) + { + if (config->addr27 == kSEMC_NORA27_MUXCSX3) + { + /* Address bit 27 (A27) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX3_MASK; + } + else if (config->addr27 == kSEMC_NORA27_MUXRDY) + { + base->IOCR |= SEMC_IOCR_MUX_RDY_MASK; + } + else + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + if (config->cePinMux == kSEMC_MUXCSX3) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX) + { + return kStatus_SEMC_InvalidAddressPortWidth; + } + } + + /* Base control. */ + if (config->rdyactivePolarity == kSEMC_RdyActivehigh) + { + base->MCR |= SEMC_MCR_WPOL0_MASK; + } + else + { + base->MCR &= ~SEMC_MCR_WPOL0_MASK; + } + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[5] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->NORCR0 = SEMC_NORCR0_PS(config->portSize) | SEMC_NORCR0_BL(config->burstLen) | + SEMC_NORCR0_AM(config->addrMode) | SEMC_NORCR0_ADVP(config->advActivePolarity) | + SEMC_NORCR0_COL(config->columnAddrBitNum); + + /* Timing setting. */ + base->NORCR1 = SEMC_NORCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz)) | + SEMC_NORCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz)) | + SEMC_NORCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz)) | + SEMC_NORCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz)) | + SEMC_NORCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz)) | + SEMC_NORCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz)) | + SEMC_NORCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz)) | + SEMC_NORCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz)); + base->NORCR2 = +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) + SEMC_NORCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz)) | +#endif /* FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME */ +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) + SEMC_NORCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz)) | +#endif /* FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME */ + SEMC_NORCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) | + SEMC_NORCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 1) | + SEMC_NORCR2_LC(config->latencyCount) | SEMC_NORCR2_RD(config->readCycle) | + SEMC_NORCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz)); + + return SEMC_ConfigureIPCommand(base, (config->portSize + 1)); +} + +/*! + * brief Configures SRAM controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The sram configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + + uint8_t memsize; + status_t result = kStatus_Success; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux); + uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ? + SEMC_IOCR_PSRAM_CE - 1 : + ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_PSRAM_CE_A8 : SEMC_IOCR_PSRAM_CE); + + /* IOMUX setting. */ + base->IOCR = iocReg | (muxCe << config->cePinMux); + /* Address bit setting. */ + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE) + { + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 1) + { + /* Address bit 24 (A24) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX0_MASK; + if (config->cePinMux == kSEMC_MUXCSX0) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 2) + { + /* Address bit 25 (A25) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX1_MASK; + if (config->cePinMux == kSEMC_MUXCSX1) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 3) + { + /* Address bit 26 (A26) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX2_MASK; + if (config->cePinMux == kSEMC_MUXCSX2) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 4) + { + if (config->addr27 == kSEMC_NORA27_MUXCSX3) + { + /* Address bit 27 (A27) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX3_MASK; + } + else if (config->addr27 == kSEMC_NORA27_MUXRDY) + { + base->IOCR |= SEMC_IOCR_MUX_RDY_MASK; + } + else + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + + if (config->cePinMux == kSEMC_MUXCSX3) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX) + { + return kStatus_SEMC_InvalidAddressPortWidth; + } + } + /* Base control. */ + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[6] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->SRAMCR0 = SEMC_SRAMCR0_PS(config->portSize) | SEMC_SRAMCR0_BL(config->burstLen) | + SEMC_SRAMCR0_AM(config->addrMode) | SEMC_SRAMCR0_ADVP(config->advActivePolarity) | + SEMC_SRAMCR0_COL_MASK; + + /* Timing setting. */ + base->SRAMCR1 = SEMC_SRAMCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz)); + + base->SRAMCR2 = SEMC_SRAMCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz)) | + SEMC_SRAMCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz)) | + SEMC_SRAMCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) | + SEMC_SRAMCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 1) | + SEMC_SRAMCR2_LC(config->latencyCount) | SEMC_SRAMCR2_RD(config->readCycle) | + SEMC_SRAMCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz)); + + return result; +} + +/*! + * brief Configures DBI controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The dbi configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + + uint8_t memsize; + status_t result; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->csxPinMux); + uint32_t muxCsx = (config->csxPinMux == kSEMC_MUXRDY) ? + SEMC_IOCR_DBI_CSX - 1 : + ((config->csxPinMux == kSEMC_MUXA8) ? SEMC_IOCR_DBI_CSX_A8 : SEMC_IOCR_DBI_CSX); + + /* IOMUX setting. */ + base->IOCR = iocReg | (muxCsx << config->csxPinMux); + /* Base control. */ + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[7] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->DBICR0 = + SEMC_DBICR0_PS(config->portSize) | SEMC_DBICR0_BL(config->burstLen) | SEMC_DBICR0_COL(config->columnAddrBitNum); + + /* Timing setting. */ + base->DBICR1 = SEMC_DBICR1_CES(SEMC_ConvertTiming(config->tCsxSetup_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_CEH(SEMC_ConvertTiming(config->tCsxHold_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_WEL(SEMC_ConvertTiming(config->tWexLow_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_WEH(SEMC_ConvertTiming(config->tWexHigh_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_REL(SEMC_ConvertTiming(config->tRdxLow_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_REH(SEMC_ConvertTiming(config->tRdxHigh_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_CEITV(SEMC_ConvertTiming(config->tCsxInterval_Ns, clkSrc_Hz) - 1); + return SEMC_ConfigureIPCommand(base, (config->portSize + 1)); +} + +/*! + * brief SEMC IP command access. + * + * param base SEMC peripheral base address. + * param type SEMC memory type. refer to "semc_mem_type_t" + * param address SEMC device address. + * param command SEMC IP command. + * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. + * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". + * For SRAM device, take refer to "semc_ipcmd_sram_t". + * For SDRAM device, take refer to "semc_ipcmd_sdram_t". + * param write Data for write access. + * param read Data pointer for read data out. + */ +status_t SEMC_SendIPCommand( + SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read) +{ + uint32_t cmdMode; + bool readCmd = 0; + bool writeCmd = 0; + status_t result; + + /* Clear status bit */ + base->INTR |= SEMC_INTR_IPCMDDONE_MASK; + /* Set address. */ + base->IPCR0 = address; + + /* Check command mode. */ + cmdMode = command & 0xFU; + switch (type) + { + case kSEMC_MemType_NAND: + readCmd = (cmdMode == kSEMC_NANDCM_CommandAddressRead) || (cmdMode == kSEMC_NANDCM_CommandRead) || + (cmdMode == kSEMC_NANDCM_Read); + writeCmd = (cmdMode == kSEMC_NANDCM_CommandAddressWrite) || (cmdMode == kSEMC_NANDCM_CommandWrite) || + (cmdMode == kSEMC_NANDCM_Write); + break; + case kSEMC_MemType_NOR: + case kSEMC_MemType_8080: + readCmd = (cmdMode == kSEMC_NORDBICM_Read); + writeCmd = (cmdMode == kSEMC_NORDBICM_Write); + break; + case kSEMC_MemType_SRAM: + readCmd = (cmdMode == kSEMC_SRAMCM_ArrayRead) || (cmdMode == kSEMC_SRAMCM_RegRead); + writeCmd = (cmdMode == kSEMC_SRAMCM_ArrayWrite) || (cmdMode == kSEMC_SRAMCM_RegWrite); + break; + case kSEMC_MemType_SDRAM: + readCmd = (cmdMode == kSEMC_SDRAMCM_Read); + writeCmd = (cmdMode == kSEMC_SDRAMCM_Write) || (cmdMode == kSEMC_SDRAMCM_Modeset); + break; + default: + break; + } + + if (writeCmd) + { + /* Set data. */ + base->IPTXDAT = write; + } + + /* Set command code. */ + base->IPCMD = command | SEMC_IPCMD_KEY(SEMC_IPCOMMANDMAGICKEY); + /* Wait for command done. */ + result = SEMC_IsIPCommandDone(base); + if (result != kStatus_Success) + { + return result; + } + + if (readCmd) + { + /* Get the read data */ + *read = base->IPRXDAT; + } + + return kStatus_Success; +} + +/*! + * brief SEMC NAND device memory write through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NAND device address. + * param data Data for write access. + * param size_bytes Data length. + */ +status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + status_t result = kStatus_Success; + uint16_t ipCmd; + uint32_t tempData = 0; + + /* Write command built */ + ipCmd = SEMC_BuildNandIPCommand(0, kSEMC_NANDAM_ColumnRow, kSEMC_NANDCM_Write); + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, *(uint32_t *)data, NULL); + if (result != kStatus_Success) + { + break; + } + + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + + while (size_bytes) + { + tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); + size_bytes--; + } + + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, tempData, NULL); + } + + return result; +} + +/*! + * brief SEMC NAND device memory read through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NAND device address. + * param data Data pointer for data read out. + * param size_bytes Data length. + */ +status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + status_t result = kStatus_Success; + uint16_t ipCmd; + uint32_t tempData = 0; + + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + /* Read command built */ + ipCmd = SEMC_BuildNandIPCommand(0, kSEMC_NANDAM_ColumnRow, kSEMC_NANDCM_Read); + + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, 0, (uint32_t *)data); + if (result != kStatus_Success) + { + break; + } + + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, 0, &tempData); + + while (size_bytes) + { + size_bytes--; + *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU; + } + } + + return result; +} + +/*! + * brief SEMC NOR device memory read through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NOR device address. + * param data Data pointer for data read out. + * param size_bytes Data length. + */ +status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + uint32_t tempData = 0; + status_t result = kStatus_Success; + uint8_t dataSize = base->NORCR0 & SEMC_NORCR0_PS_MASK; + + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Read, 0, (uint32_t *)data); + if (result != kStatus_Success) + { + break; + } + + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Read, 0, &tempData); + while (size_bytes) + { + size_bytes--; + *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU; + } + } + + SEMC_ConfigureIPCommand(base, dataSize); + return result; +} + +/*! + * brief SEMC NOR device memory write through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NOR device address. + * param data Data for write access. + * param size_bytes Data length. + */ +status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + uint32_t tempData = 0; + status_t result = kStatus_Success; + uint8_t dataSize = base->NORCR0 & SEMC_NORCR0_PS_MASK; + + /* Write command built */ + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Write, *(uint32_t *)data, NULL); + if (result != kStatus_Success) + { + break; + } + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + + while (size_bytes) + { + tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); + size_bytes--; + } + + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Write, tempData, NULL); + } + SEMC_ConfigureIPCommand(base, dataSize); + + return result; +} diff --git a/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/fsl_semc.h b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/fsl_semc.h new file mode 100644 index 000000000..75704eadf --- /dev/null +++ b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/fsl_semc.h @@ -0,0 +1,830 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SEMC_H_ +#define _FSL_SEMC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup semc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SEMC driver version 2.0.4. */ +#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +/*! @brief SEMC status. */ +enum _semc_status +{ + kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), + kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), + kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), + kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), + kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), + kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), + kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), + kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), + kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), + kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9), + kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), + kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11), +}; + +/*! @brief SEMC memory device type. */ +typedef enum _semc_mem_type +{ + kSEMC_MemType_SDRAM = 0, /*!< SDRAM */ + kSEMC_MemType_SRAM, /*!< SRAM */ + kSEMC_MemType_NOR, /*!< NOR */ + kSEMC_MemType_NAND, /*!< NAND */ + kSEMC_MemType_8080 /*!< 8080. */ +} semc_mem_type_t; + +/*! @brief SEMC WAIT/RDY polarity. */ +typedef enum _semc_waitready_polarity +{ + kSEMC_LowActive = 0, /*!< Low active. */ + kSEMC_HighActive, /*!< High active. */ +} semc_waitready_polarity_t; + +/*! @brief SEMC SDRAM Chip selection . */ +typedef enum _semc_sdram_cs +{ + kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */ + kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */ + kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */ + kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */ +} semc_sdram_cs_t; + +/*! @brief SEMC NAND device type. */ +typedef enum _semc_nand_access_type +{ + kSEMC_NAND_ACCESS_BY_AXI = 0, + kSEMC_NAND_ACCESS_BY_IPCMD, +} semc_nand_access_type_t; + +/*! @brief SEMC interrupts . */ +typedef enum _semc_interrupt_enable +{ + kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */ + kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */ + kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */ + kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */ +} semc_interrupt_enable_t; + +/*! @brief SEMC IP command data size in bytes. */ +typedef enum _semc_ipcmd_datasize +{ + kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */ + kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */ + kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */ + kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */ +} semc_ipcmd_datasize_t; + +/*! @brief SEMC auto-refresh timing. */ +typedef enum _semc_refresh_time +{ + kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */ + kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */ + kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */ +} semc_refresh_time_t; + +/*! @brief CAS latency */ +typedef enum _semc_caslatency +{ + kSEMC_LatencyOne = 1, /*!< Latency 1. */ + kSEMC_LatencyTwo, /*!< Latency 2. */ + kSEMC_LatencyThree, /*!< Latency 3. */ +} semc_caslatency_t; + +/*! @brief SEMC sdram column address bit number. */ +typedef enum _semc_sdram_column_bit_num +{ + kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_SdramColunm_11bit, /*!< 11 bit. */ + kSEMC_SdramColunm_10bit, /*!< 10 bit. */ + kSEMC_SdramColunm_9bit, /*!< 9 bit. */ +} semc_sdram_column_bit_num_t; + +/*! @brief SEMC sdram burst length. */ +typedef enum _semc_sdram_burst_len +{ + kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/ + kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/ + kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/ +} sem_sdram_burst_len_t; + +/*! @brief SEMC nand column address bit number. */ +typedef enum _semc_nand_column_bit_num +{ + kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */ + kSEMC_NandColum_15bit, /*!< 15 bit. */ + kSEMC_NandColum_14bit, /*!< 14 bit. */ + kSEMC_NandColum_13bit, /*!< 13 bit. */ + kSEMC_NandColum_12bit, /*!< 12 bit. */ + kSEMC_NandColum_11bit, /*!< 11 bit. */ + kSEMC_NandColum_10bit, /*!< 10 bit. */ + kSEMC_NandColum_9bit, /*!< 9 bit. */ +} semc_nand_column_bit_num_t; + +/*! @brief SEMC nand burst length. */ +typedef enum _semc_nand_burst_len +{ + kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Nand_BurstLen2, /*!< Burst length 2*/ + kSEMC_Nand_BurstLen4, /*!< Burst length 4*/ + kSEMC_Nand_BurstLen8, /*!< Burst length 8*/ + kSEMC_Nand_BurstLen16, /*!< Burst length 16*/ + kSEMC_Nand_BurstLen32, /*!< Burst length 32*/ + kSEMC_Nand_BurstLen64 /*!< Burst length 64*/ +} sem_nand_burst_len_t; + +/*! @brief SEMC nor/sram column address bit number. */ +typedef enum _semc_norsram_column_bit_num +{ + kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_NorColum_11bit, /*!< 11 bit. */ + kSEMC_NorColum_10bit, /*!< 10 bit. */ + kSEMC_NorColum_9bit, /*!< 9 bit. */ + kSEMC_NorColum_8bit, /*!< 8 bit. */ + kSEMC_NorColum_7bit, /*!< 7 bit. */ + kSEMC_NorColum_6bit, /*!< 6 bit. */ + kSEMC_NorColum_5bit, /*!< 5 bit. */ + kSEMC_NorColum_4bit, /*!< 4 bit. */ + kSEMC_NorColum_3bit, /*!< 3 bit. */ + kSEMC_NorColum_2bit /*!< 2 bit. */ +} semc_norsram_column_bit_num_t; + +/*! @brief SEMC nor/sram burst length. */ +typedef enum _semc_norsram_burst_len +{ + kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Nor_BurstLen2, /*!< Burst length 2*/ + kSEMC_Nor_BurstLen4, /*!< Burst length 4*/ + kSEMC_Nor_BurstLen8, /*!< Burst length 8*/ + kSEMC_Nor_BurstLen16, /*!< Burst length 16*/ + kSEMC_Nor_BurstLen32, /*!< Burst length 32*/ + kSEMC_Nor_BurstLen64 /*!< Burst length 64*/ +} sem_norsram_burst_len_t; + +/*! @brief SEMC dbi column address bit number. */ +typedef enum _semc_dbi_column_bit_num +{ + kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */ + kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */ + kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */ + kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */ + kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */ + kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */ + kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */ + kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */ + kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */ + kSEMC_Dbi_Colum_2bit /*!< 2 bit. */ +} semc_dbi_column_bit_num_t; + +/*! @brief SEMC dbi burst length. */ +typedef enum _semc_dbi_burst_len +{ + kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/ + kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/ + kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/ + kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/ + kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/ + kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/ +} sem_dbi_burst_len_t; + +/*! @brief SEMC IOMUXC. */ +typedef enum _semc_iomux_pin +{ + kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */ + kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */ + kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/ + kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */ + kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ + kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ +} semc_iomux_pin; + +/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */ +typedef enum _semc_iomux_nora27_pin +{ + kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */ + kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ + kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ +} semc_iomux_nora27_pin; + +/*! @brief SEMC port size. */ +typedef enum _semc_port_size +{ + kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */ + kSEMC_PortSize16Bit /*!< 16-Bit port size. */ +} smec_port_size_t; + +/*! @brief SEMC address mode. */ +typedef enum _semc_addr_mode +{ + kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */ + kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */ + kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */ +} semc_addr_mode_t; + +/*! @brief SEMC DQS read strobe mode. */ +typedef enum _semc_dqs_mode +{ + kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */ + kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */ +} semc_dqs_mode_t; + +/*! @brief SEMC ADV signal active polarity. */ +typedef enum _semc_adv_polarity +{ + kSEMC_AdvActiveLow = 0, /*!< Adv active low. */ + kSEMC_AdvActivehigh, /*!< Adv active low. */ +} semc_adv_polarity_t; + +/*! @brief SEMC RDY signal active polarity. */ +typedef enum _semc_rdy_polarity +{ + kSEMC_RdyActiveLow = 0, /*!< Adv active low. */ + kSEMC_RdyActivehigh, /*!< Adv active low. */ +} semc_rdy_polarity_t; + +/*! @brief SEMC IP command for NAND: address mode. */ +typedef enum _semc_ipcmd_nand_addrmode +{ + kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */ + kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */ + kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */ + kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */ + kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */ + kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */ +} semc_ipcmd_nand_addrmode_t; + +/*! @brief SEMC IP command for NAND： command mode. */ +typedef enum _semc_ipcmd_nand_cmdmode +{ + kSEMC_NANDCM_Command = 0x2U, /*!< command. */ + kSEMC_NANDCM_CommandHold, /*!< Command hold. */ + kSEMC_NANDCM_CommandAddress, /*!< Command address. */ + kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */ + kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */ + kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */ + kSEMC_NANDCM_CommandRead, /*!< Command read. */ + kSEMC_NANDCM_CommandWrite, /*!< Command write. */ + kSEMC_NANDCM_Read, /*!< Read. */ + kSEMC_NANDCM_Write /*!< Write. */ +} semc_ipcmd_nand_cmdmode_t; + +/*! @brief SEMC NAND address option. */ +typedef enum _semc_nand_address_option +{ + kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */ + kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */ + kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */ + kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */ + kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */ + kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */ +} semc_nand_address_option_t; + +/*! @brief SEMC IP command for NOR. */ +typedef enum _semc_ipcmd_nor_dbi +{ + kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */ + kSEMC_NORDBICM_Write /*!< NOR write. */ +} semc_ipcmd_nor_dbi_t; + +/*! @brief SEMC IP command for SRAM. */ +typedef enum _semc_ipcmd_sram +{ + kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */ + kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */ + kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */ + kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */ +} semc_ipcmd_sram_t; + +/*! @brief SEMC IP command for SDARM. */ +typedef enum _semc_ipcmd_sdram +{ + kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */ + kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */ + kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */ + kSEMC_SDRAMCM_Active, /*!< SDRAM active. */ + kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */ + kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */ + kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */ + kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */ +} semc_ipcmd_sdram_t; + +/*! @brief SEMC SDRAM configuration structure. + * + * 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes + * should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. + * Take refer to BR0~BR3 register in RM for details. + * 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, + * it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, + * The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. + * idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are + * similar to prescalePeriod_N16Cycle. + * + */ +typedef struct _semc_sdram_config +{ + semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + smec_port_size_t portSize; /*!< Port size. */ + sem_sdram_burst_len_t burstLen; /*!< Burst length. */ + semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_caslatency_t casLatency; /*!< CAS latency. */ + uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */ + uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */ + uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */ + uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */ + uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */ + uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */ + uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */ + uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */ + uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */ + uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */ + uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */ + uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */ + uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */ + uint8_t refreshBurstLen; /*!< Refresh burst length. */ +} semc_sdram_config_t; + +/*! @brief SEMC NAND device timing configuration structure. */ +typedef struct _semc_nand_timing_config +{ + uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */ + uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */ + uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */ + uint8_t tWeLow_Ns; /*!< WE low time: tWP. */ + uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */ + uint8_t tReLow_Ns; /*!< RE low time: tRP. */ + uint8_t tReHigh_Ns; /*!< RE high time: tREH. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */ + uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */ + uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */ + uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */ + uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */ + uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */ +} semc_nand_timing_config_t; + +/*! @brief SEMC NAND configuration structure. */ +typedef struct _semc_nand_config +{ + semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */ + uint32_t axiAddress; /*!< The base address for AXI nand. */ + uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */ + uint32_t ipgAddress; /*!< The base address for IPG nand . */ + uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */ + semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ + bool edoModeEnabled; /*!< EDO mode enabled. */ + semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_nand_address_option_t arrayAddrOption; /*!< Address option. */ + sem_nand_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */ +} semc_nand_config_t; + +/*! @brief SEMC NOR configuration structure. */ +typedef struct _semc_nor_config +{ + semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ + semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + uint8_t addrPortWidth; /*!< The address port width. */ + semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ + semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */ + semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_addr_mode_t addrMode; /*!< Address mode. */ + sem_norsram_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCeSetup_Ns; /*!< The CE setup time. */ + uint8_t tCeHold_Ns; /*!< The CE hold time. */ + uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ + uint8_t tAddrSetup_Ns; /*!< The address setup time. */ + uint8_t tAddrHold_Ns; /*!< The address hold time. */ + uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ + uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ + uint8_t tReLow_Ns; /*!< RE low time for async mode. */ + uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ + uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) + uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ +#endif +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) + uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ +#endif + uint8_t latencyCount; /*!< Latency count for sync mode. */ + uint8_t readCycle; /*!< Read cycle time for sync mode. */ +} semc_nor_config_t; + +/*! @brief SEMC SRAM configuration structure. */ +typedef struct _semc_sram_config +{ + semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ + semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + uint8_t addrPortWidth; /*!< The address port width. */ + semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */ + semc_addr_mode_t addrMode; /*!< Address mode. */ + sem_norsram_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCeSetup_Ns; /*!< The CE setup time. */ + uint8_t tCeHold_Ns; /*!< The CE hold time. */ + uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ + uint8_t tAddrSetup_Ns; /*!< The address setup time. */ + uint8_t tAddrHold_Ns; /*!< The address hold time. */ + uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ + uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ + uint8_t tReLow_Ns; /*!< RE low time for async mode. */ + uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ + uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ + uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ + uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ + uint8_t latencyCount; /*!< Latency count for sync mode. */ + uint8_t readCycle; /*!< Read cycle time for sync mode. */ +} semc_sram_config_t; + +/*! @brief SEMC DBI configuration structure. */ +typedef struct _semc_dbi_config +{ + semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */ + semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + sem_dbi_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */ + uint8_t tCsxHold_Ns; /*!< The CSX hold time. */ + uint8_t tWexLow_Ns; /*!< WEX low time. */ + uint8_t tWexHigh_Ns; /*!< WEX high time. */ + uint8_t tRdxLow_Ns; /*!< RDX low time. */ + uint8_t tRdxHigh_Ns; /*!< RDX high time. */ + uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/ +} semc_dbi_config_t; + +/*! @brief SEMC AXI queue a weight setting structure. */ +typedef struct _semc_queuea_weight_struct +{ + uint32_t qos : 4; /*!< weight of qos for queue 0 . */ + uint32_t aging : 4; /*!< weight of aging for queue 0.*/ + uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/ + uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/ +} semc_queuea_weight_struct_t; + +/*! @brief SEMC AXI queue a weight setting union. */ +typedef union _semc_queuea_weight +{ + semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */ + uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */ +} semc_queuea_weight_t; + +/*! @brief SEMC AXI queue b weight setting structure. */ +typedef struct _semc_queueb_weight_struct +{ + uint32_t qos : 4; /*!< weight of qos for queue 1. */ + uint32_t aging : 4; /*!< weight of aging for queue 1.*/ + uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/ + uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/ + uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/ +} semc_queueb_weight_struct_t; + +/*! @brief SEMC AXI queue b weight setting union. */ +typedef union _semc_queueb_weight +{ + semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */ + uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */ +} semc_queueb_weight_t; + +/*! @brief SEMC AXI queue weight setting. */ +typedef struct _semc_axi_queueweight +{ + semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */ + semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */ +} semc_axi_queueweight_t; + +/*! + * @brief SEMC configuration structure. + * + * busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is + * 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. + * cmdTimeoutCycles: is used for command execution timeout cycles. it's + * similar to the busTimeoutCycles. + */ +typedef struct _semc_config_t +{ + semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */ + uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */ + uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */ + semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */ +} semc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SEMC Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the SEMC default basic configuration structure. + * + * The purpose of this API is to get the default SEMC + * configure structure for SEMC_Init(). User may use the initialized + * structure unchanged in SEMC_Init(), or modify some fields of the + * structure before calling SEMC_Init(). + * Example: + @code + semc_config_t config; + SEMC_GetDefaultConfig(&config); + @endcode + * @param config The SEMC configuration structure pointer. + */ +void SEMC_GetDefaultConfig(semc_config_t *config); + +/*! + * @brief Initializes SEMC. + * This function ungates the SEMC clock and initializes SEMC. + * This function must be called before calling any other SEMC driver functions. + * + * @param base SEMC peripheral base address. + * @param configure The SEMC configuration structure pointer. + */ +void SEMC_Init(SEMC_Type *base, semc_config_t *configure); + +/*! + * @brief Deinitializes the SEMC module and gates the clock. + * + * This function gates the SEMC clock. As a result, the SEMC module doesn't work after + * calling this function, for some IDE, calling this API may cause the next downloading + * operation failed. so, please call this API cautiously. Additional, users can + * using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control + * operation in drivers. + * + * @param base SEMC peripheral base address. + */ +void SEMC_Deinit(SEMC_Type *base); + +/* @} */ + +/*! + * @name SEMC Configuration Operation For Each Memory Type + * @{ + */ + +/*! + * @brief Configures SDRAM controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param cs The chip selection. + * @param config The sdram configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures NAND controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The nand configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures NOR controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The nor configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures SRAM controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The sram configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures DBI controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The dbi configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz); + +/* @} */ + +/*! + * @name SEMC Interrupt Operation + * @{ + */ + +/*! + * @brief Enables the SEMC interrupt. + * + * This function enables the SEMC interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. + * For example, to enable the IP command done and error interrupt, do the following. + * @code + * SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); + * @endcode + * + * @param base SEMC peripheral base address. + * @param mask SEMC interrupts to enable. This is a logical OR of the + * enumeration :: semc_interrupt_enable_t. + */ +static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask) +{ + base->INTEN |= mask; +} + +/*! + * @brief Disables the SEMC interrupt. + * + * This function disables the SEMC interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. + * For example, to disable the IP command done and error interrupt, do the following. + * @code + * SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); + * @endcode + * + * @param base SEMC peripheral base address. + * @param mask SEMC interrupts to disable. This is a logical OR of the + * enumeration :: semc_interrupt_enable_t. + */ +static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask) +{ + base->INTEN &= ~mask; +} + +/*! + * @brief Gets the SEMC status. + * + * This function gets the SEMC interrupts event status. + * User can use the a logical OR of enumeration member as a mask. + * See @ref semc_interrupt_enable_t. + * + * @param base SEMC peripheral base address. + * @return status flag, use status flag in semc_interrupt_enable_t to get the related status. + */ +static inline bool SEMC_GetStatusFlag(SEMC_Type *base) +{ + return base->INTR; +} + +/*! + * @brief Clears the SEMC status flag state. + * + * The following status register flags can be cleared SEMC interrupt status. + * + * @param base SEMC base pointer + * @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t. + */ +static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask) +{ + base->INTR |= mask; +} + +/* @} */ + +/*! + * @name SEMC Memory Access Operation + * @{ + */ + +/*! + * @brief Check if SEMC is in idle. + * + * @param base SEMC peripheral base address. + * @return True SEMC is in idle, false is not in idle. + */ +static inline bool SEMC_IsInIdle(SEMC_Type *base) +{ + return (base->STS0 & SEMC_STS0_IDLE_MASK) ? true : false; +} + +/*! + * @brief SEMC IP command access. + * + * @param base SEMC peripheral base address. + * @param type SEMC memory type. refer to "semc_mem_type_t" + * @param address SEMC device address. + * @param command SEMC IP command. + * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. + * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". + * For SRAM device, take refer to "semc_ipcmd_sram_t". + * For SDRAM device, take refer to "semc_ipcmd_sdram_t". + * @param write Data for write access. + * @param read Data pointer for read data out. + */ +status_t SEMC_SendIPCommand( + SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read); + +/*! + * @brief Build SEMC IP command for NAND. + * + * This function build SEMC NAND IP command. The command is build of user command code, + * SEMC address mode and SEMC command mode. + * + * @param userCommand NAND device normal command. + * @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t". + * @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t". + */ +static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand, + semc_ipcmd_nand_addrmode_t addrMode, + semc_ipcmd_nand_cmdmode_t cmdMode) +{ + return (uint16_t)((uint16_t)userCommand << 8) | (uint16_t)(addrMode << 4) | ((uint8_t)cmdMode & 0x0Fu); +} + +/*! + * @brief Check if the NAND device is ready. + * + * @param base SEMC peripheral base address. + * @return True NAND is ready, false NAND is not ready. + */ +static inline bool SEMC_IsNandReady(SEMC_Type *base) +{ + return (base->STS0 & SEMC_STS0_NARDY_MASK) ? true : false; +} + +/*! + * @brief SEMC NAND device memory write through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NAND device address. + * @param data Data for write access. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NAND device memory read through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NAND device address. + * @param data Data pointer for data read out. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NOR device memory write through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NOR device address. + * @param data Data for write access. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NOR device memory read through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NOR device address. + * @param data Data pointer for data read out. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SEMC_H_*/ diff --git a/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/semc_externsdram_test.c b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/semc_externsdram_test.c new file mode 100644 index 000000000..c09b6dc27 --- /dev/null +++ b/Ubiquitous/XiUOS/board/ok1052-c/third_party_driver/semc/semc_externsdram_test.c @@ -0,0 +1,180 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "board.h" + +#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U) + +#define SEMC_EXAMPLE_DATALEN (0x1000U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void SEMC_SDRAMReadWrite32Bit(void); +static void SEMC_SDRAMReadWrite16Bit(void); +static void SEMC_SDRAMReadWrite8Bit(void); +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint32_t sdram_writeBuffer[SEMC_EXAMPLE_DATALEN]; +uint32_t sdram_readBuffer[SEMC_EXAMPLE_DATALEN]; + +/*! + * @brief Main function + */ +int semc_externsram_test(void) +{ + KPrintf("\r\n SEMC SDRAM Example Start!\r\n"); + + /* 32Bit data read and write. */ + SEMC_SDRAMReadWrite32Bit(); + /* 16Bit data read and write. */ + SEMC_SDRAMReadWrite16Bit(); + /* 8Bit data read and write. */ + SEMC_SDRAMReadWrite8Bit(); + + KPrintf("\r\n SEMC SDRAM Example End.\r\n"); + +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),semc_externsram_test, semc_externsram_test, semc_externsram_test ); + +void SEMC_SDRAMReadWrite32Bit(void) +{ + uint32_t index; + uint32_t datalen = SEMC_EXAMPLE_DATALEN; + uint32_t *sdram = (uint32_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */ + int result = 0; + + KPrintf("\r\n SEMC SDRAM Memory 32 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Prepare data and write to SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_writeBuffer[index] = index; + sdram[index] = sdram_writeBuffer[index]; + } + + KPrintf("\r\n SEMC SDRAM Read 32 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Read data from the SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_readBuffer[index] = sdram[index]; + } + + KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Start!\r\n"); + /* Compare the two buffers. */ + while (datalen--) + { + if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen]) + { + result = -1; + break; + } + } + + if (result < 0) + { + KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Failed!\r\n"); + } + else + { + KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Succeed!\r\n"); + } +} + +static void SEMC_SDRAMReadWrite16Bit(void) +{ + uint32_t index; + uint32_t datalen = SEMC_EXAMPLE_DATALEN; + uint16_t *sdram = (uint16_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */ + int result = 0; + + KPrintf("\r\n SEMC SDRAM Memory 16 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + + memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer)); + memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer)); + + /* Prepare data and write to SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_writeBuffer[index] = index % 0xFFFF; + sdram[index] = sdram_writeBuffer[index]; + } + + KPrintf("\r\n SEMC SDRAM Read 16 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Read data from the SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_readBuffer[index] = sdram[index]; + } + + KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Start!\r\n"); + /* Compare the two buffers. */ + while (datalen--) + { + if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen]) + { + result = -1; + break; + } + } + + if (result < 0) + { + KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Failed!\r\n"); + } + else + { + KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Succeed!\r\n"); + } +} + +static void SEMC_SDRAMReadWrite8Bit(void) +{ + uint32_t index; + uint32_t datalen = SEMC_EXAMPLE_DATALEN; + uint8_t *sdram = (uint8_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */ + int result = 0; + + KPrintf("\r\n SEMC SDRAM Memory 8 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + + memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer)); + memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer)); + + /* Prepare data and write to SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_writeBuffer[index] = index % 0x100; + sdram[index] = sdram_writeBuffer[index]; + } + + KPrintf("\r\n SEMC SDRAM Read 8 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Read data from the SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_readBuffer[index] = sdram[index]; + } + + KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Start!\r\n"); + /* Compare the two buffers. */ + while (datalen--) + { + if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen]) + { + result = -1; + break; + } + } + + if (result < 0) + { + KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Failed!\r\n"); + } + else + { + KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Succeed!\r\n"); + } +} diff --git a/Ubiquitous/XiUOS/kernel/kernel_test/extsram_test.c b/Ubiquitous/XiUOS/kernel/kernel_test/extsram_test.c index 1e0741430..62402162a 100644 --- a/Ubiquitous/XiUOS/kernel/kernel_test/extsram_test.c +++ b/Ubiquitous/XiUOS/kernel/kernel_test/extsram_test.c @@ -2,12 +2,18 @@ #include /* parameters for sram peripheral */ -/* stm32f4 Bank3:0X68000000 */ -#define SRAM_BANK_ADDR ((uint32_t)0X68000000) +// /* stm32f4 Bank3:0X68000000 */ +// #define SRAM_BANK_ADDR ((uint32_t)0X68000000) + +/* OK-1052 semc:0X80000000 */ +#define SRAM_BANK_ADDR ((uint32_t)0X80000000) /* data width: 8, 16, 32 */ #define SRAM_DATA_WIDTH 16 + +// /* sram size */ +// #define SRAM_SIZE ((uint32_t)0x00100000) /* sram size */ -#define SRAM_SIZE ((uint32_t)0x00100000) +#define SRAM_SIZE ((uint32_t)0x008000) int sram_test(void) { diff --git a/Ubiquitous/XiUOS/kernel/memory/byte_manage.c b/Ubiquitous/XiUOS/kernel/memory/byte_manage.c index 9fda3a1dc..0df9136da 100644 --- a/Ubiquitous/XiUOS/kernel/memory/byte_manage.c +++ b/Ubiquitous/XiUOS/kernel/memory/byte_manage.c @@ -1222,7 +1222,7 @@ void ShowBuddy(void) }; } - KPrintf("\nlist memory information\n\n"); + KPrintf("\n\033[41;1mlist extern memory information\033[0m\n"); #ifdef MEM_EXTERN_SRAM for(i = 0; i < EXTSRAM_MAX_NUM; i++) { if(NONE != ExtByteManager[i].done){ @@ -1230,14 +1230,16 @@ void ShowBuddy(void) for(int lev = 0; lev < MEM_LINKNRS; lev++) { KPrintf("\n %s level [%d],memory size[2^%d] \n",__func__, lev,lev +6); for (debug = & ExtByteManager[i].dynamic_buddy_manager.mm_freenode_list[lev]; ; ) { - if(debug->size > 0) - KPrintf(" [current node %x,next node %x, size %u, flag %x]\n",debug, debug->next,debug->size,debug->flag); - else - KPrintf(" [listhead node %x,next node %x]\n",debug, debug->next); if(debug->next) + { debug = debug->next; - if(debug->size == 0) + if(debug->size > 0) + KPrintf(" [current node %x,next node %x, size %u, flag %x]\n",debug, debug->next,debug->size,debug->flag); + else + KPrintf(" \n"); + } + if(debug->size == 0 || NONE == debug->next) break; } }