diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/config.mk b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/config.mk
index 020fa3ca6..1971aff4c 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/config.mk
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/config.mk
@@ -1,5 +1,5 @@
 export CROSS_COMPILE ?= aarch64-none-elf-
-export DEVICE = -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
+export DEVICE = -mtune=cortex-a55 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
 export CFLAGS := $(DEVICE) -Wall -Werror -O2 -g -fno-omit-frame-pointer -fPIC 
 # export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
 export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds -Wl,--start-group,-lgcc,-lc,--end-group
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds
index 722ddf1e7..7d3e927fd 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds
@@ -45,8 +45,8 @@ ENTRY( _ENTRY )
 ENTRY( _boot_start )
 
 MEMORY {
-  phy_ddr3 (rwx)      : ORIGIN = 0x0000000040000000, LENGTH = 1024M
-  vir_ddr3 (rwx)      : ORIGIN = 0x0000006040635000, LENGTH = 1024M
+  phy_ddr3 (rwx)      : ORIGIN = 0x0000000000A00000, LENGTH = 1024M
+  vir_ddr3 (rwx)      : ORIGIN = 0x0000006041035000, LENGTH = 1024M
 }
 
 
@@ -81,7 +81,7 @@ SECTIONS
 		PROVIDE(boot_end_addr = .);
 	} > phy_ddr3
 
-  .text : AT(0x40635000) {
+  .text : AT(0x1035000) {
     . = ALIGN(0x1000);
     *(.text .text.* .gnu.linkonce.t.*)
   } > vir_ddr3
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap_common.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap_common.c
index 328634f27..624c61445 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap_common.c
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap_common.c
@@ -52,10 +52,10 @@ static void _sys_irq_init(int cpu_id)
     // primary core init intr
     xizi_trap_driver.switch_hw_irqtbl((uintptr_t*)alltraps);
 
-    if (cpu_id == 0) {
-        gic_init();
-    }
-    gicv3inithart(cpu_id);
+    // if (cpu_id == 0) {
+    //     gic_init();
+    // }
+    // gicv3inithart(cpu_id);
 }
 
 static void _cpu_irq_enable(void)
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/ok1028a-c/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/ok1028a-c/memlayout.h
index b916887dd..c206417dd 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/ok1028a-c/memlayout.h
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/ok1028a-c/memlayout.h
@@ -34,10 +34,10 @@ Modification:
 #define ARCH_BIT        64
 
 /* A72 physical memory layout */
-#define PHY_MEM_BASE            (0x0000000040000000ULL)
-#define PHY_USER_FREEMEM_BASE   (0x0000000046000000ULL)
-#define PHY_USER_FREEMEM_TOP    (0x0000000048000000ULL)
-#define PHY_MEM_STOP            (0x0000000048000000ULL)
+#define PHY_MEM_BASE            (0x0000000000A00000ULL)
+#define PHY_USER_FREEMEM_BASE   (0x0000000001A00000ULL)
+#define PHY_USER_FREEMEM_TOP    (0x0000000001A00000ULL)
+#define PHY_MEM_STOP            (0x0000000002000000ULL)
 
 /* PTE-PAGE_SIZE */
 #define LEVEL4_PTE_SHIFT    12
@@ -61,9 +61,9 @@ Modification:
 #define MAX_NR_FREE_PAGES   ((PHY_MEM_STOP - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
 
 /* Deivce memory layout */
-#define DEV_PHYMEM_BASE     (0x0000000000000000ULL)
+#define DEV_PHYMEM_BASE     (0x00000000C0000000ULL)
 #define DEV_VRTMEM_BASE     (0x0000004000000000ULL)
-#define DEV_MEM_SZ          (0x0000000010000000ULL)
+#define DEV_MEM_SZ          (0x0000000040000000ULL)
 
 /* User memory layout */
 #define USER_STACK_SIZE     PAGE_SIZE
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/Makefile
index 7544324de..a8661f85c 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/Makefile
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/Makefile
@@ -1,3 +1,3 @@
-SRC_FILES := uart.c
+SRC_FILES := uart.c ns16550.c
 
 include $(KERNEL_ROOT)/compiler.mk
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/include/ns16550.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/include/ns16550.h
new file mode 100644
index 000000000..8847befca
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/include/ns16550.h
@@ -0,0 +1,198 @@
+/*
+ * NS16550 Serial Port
+ * originally from linux source (arch/powerpc/boot/ns16550.h)
+ *
+ * Cleanup and unification
+ * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
+ *
+ * modified slightly to
+ * have addresses as offsets from CONFIG_SYS_ISA_BASE
+ * added a few more definitions
+ * added prototypes for ns16550.c
+ * reduced no of com ports to 2
+ * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
+ *
+ * added support for port on 64-bit bus
+ * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
+ */
+
+/*
+ * Note that the following macro magic uses the fact that the compiler
+ * will not allocate storage for arrays of size 0
+ */
+
+#include <stdint.h>
+
+/*
+ * For driver model we always use one byte per register, and sort out the
+ * differences in the driver
+ */
+#define CONFIG_SYS_NS16550_REG_SIZE (-1)
+
+#define UART_REG(x)  \
+    unsigned char x; \
+    unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
+
+/**
+ * struct ns16550_platdata - information about a NS16550 port
+ *
+ * @base:		Base register address
+ * @reg_shift:		Shift size of registers (0=byte, 1=16bit, 2=32bit...)
+ * @clock:		UART base clock speed in Hz
+ */
+struct ns16550_platdata {
+    unsigned long base;
+    int reg_shift;
+    int clock;
+    int reg_offset;
+    uint32_t fcr;
+};
+
+struct udevice;
+
+struct NS16550 {
+    UART_REG(rbr); /* 0 */
+    UART_REG(ier); /* 1 */
+    UART_REG(fcr); /* 2 */
+    UART_REG(lcr); /* 3 */
+    UART_REG(mcr); /* 4 */
+    UART_REG(lsr); /* 5 */
+    UART_REG(msr); /* 6 */
+    UART_REG(spr); /* 7 */
+#ifdef CONFIG_SOC_DA8XX
+    UART_REG(reg8); /* 8 */
+    UART_REG(reg9); /* 9 */
+    UART_REG(revid1); /* A */
+    UART_REG(revid2); /* B */
+    UART_REG(pwr_mgmt); /* C */
+    UART_REG(mdr1); /* D */
+#else
+    UART_REG(mdr1); /* 8 */
+    UART_REG(reg9); /* 9 */
+    UART_REG(regA); /* A */
+    UART_REG(regB); /* B */
+    UART_REG(regC); /* C */
+    UART_REG(regD); /* D */
+    UART_REG(regE); /* E */
+    UART_REG(uasr); /* F */
+    UART_REG(scr); /* 10*/
+    UART_REG(ssr); /* 11*/
+#endif
+#ifdef CONFIG_DM_SERIAL
+    struct ns16550_platdata* plat;
+#endif
+};
+
+#define thr rbr
+#define iir fcr
+#define dll rbr
+#define dlm ier
+
+typedef struct NS16550* NS16550_t;
+
+/*
+ * These are the definitions for the FIFO Control Register
+ */
+#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
+#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
+
+#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
+#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
+
+/* Ingenic JZ47xx specific UART-enable bit. */
+#define UART_FCR_UME 0x10
+
+/* Clear & enable FIFOs */
+#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR)
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_DTR 0x01 /* DTR   */
+#define UART_MCR_RTS 0x02 /* RTS   */
+#define UART_MCR_OUT1 0x04 /* Out 1 */
+#define UART_MCR_OUT2 0x08 /* Out 2 */
+#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
+
+#define UART_MCR_DMA_EN 0x04
+#define UART_MCR_TX_DFR 0x08
+
+/*
+ * These are the definitions for the Line Control Register
+ *
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
+#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
+#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
+#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
+#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
+#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
+#define UART_LCR_PEN 0x08 /* Parity eneble */
+#define UART_LCR_EPS 0x10 /* Even Parity Select */
+#define UART_LCR_STKP 0x20 /* Stick Parity */
+#define UART_LCR_SBRK 0x40 /* Set Break */
+#define UART_LCR_BKSE 0x80 /* Bank select enable */
+#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_DR 0x01 /* Data ready */
+#define UART_LSR_OE 0x02 /* Overrun */
+#define UART_LSR_PE 0x04 /* Parity error */
+#define UART_LSR_FE 0x08 /* Framing error */
+#define UART_LSR_BI 0x10 /* Break */
+#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
+#define UART_LSR_TEMT 0x40 /* Xmitter empty */
+#define UART_LSR_ERR 0x80 /* Error */
+
+#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
+#define UART_MSR_RI 0x40 /* Ring Indicator */
+#define UART_MSR_DSR 0x20 /* Data Set Ready */
+#define UART_MSR_CTS 0x10 /* Clear to Send */
+#define UART_MSR_DDCD 0x08 /* Delta DCD */
+#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
+#define UART_MSR_DDSR 0x02 /* Delta DSR */
+#define UART_MSR_DCTS 0x01 /* Delta CTS */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
+#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
+
+#define UART_IIR_MSI 0x00 /* Modem status interrupt */
+#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
+#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
+#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
+#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
+#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
+#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
+
+/* useful defaults for LCR */
+#define UART_LCR_8N1 0x03
+
+void NS16550_init(NS16550_t com_port, int baud_divisor);
+void NS16550_putc(NS16550_t com_port, char c);
+char NS16550_getc(NS16550_t com_port);
+int NS16550_tstc(NS16550_t com_port);
+void NS16550_reinit(NS16550_t com_port, int baud_divisor);
+
+void _debug_uart_init(void);
+void _debug_uart_putc(int ch);
+int _debug_uart_getc(void);
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/ns16550.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/ns16550.c
new file mode 100644
index 000000000..f357c8293
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/ns16550.c
@@ -0,0 +1,98 @@
+/*
+ * COM1 NS16550 support
+ * originally from linux source (arch/powerpc/boot/ns16550.c)
+ * modified to use CONFIG_SYS_ISA_MEM and new defines
+ */
+
+#include <stdint.h>
+
+#include "mmio_access.h"
+#include "ns16550.h"
+
+#define UART_ADDR MMIO_P2V_WO(0xFE660000)
+
+#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
+#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */
+
+#define out_le32(a, v) (*(volatile uint32_t*)(a) = (v))
+#define in_le32(a) (*(volatile uint32_t*)(a))
+
+#ifndef CONFIG_SYS_NS16550_IER
+#define CONFIG_SYS_NS16550_IER 0x00
+#endif /* CONFIG_SYS_NS16550_IER */
+
+#define serial_dout(reg, value)                                                   \
+    serial_out_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \
+        2, value)
+#define serial_din(reg)                                                          \
+    serial_in_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \
+        2)
+
+static inline void serial_out_shift(void* addr, int shift, int value)
+{
+    out_le32(addr, value);
+}
+
+static inline int serial_in_shift(void* addr, int shift)
+{
+    return in_le32(addr);
+}
+
+#ifndef CONFIG_SYS_NS16550_CLK
+#define CONFIG_SYS_NS16550_CLK 0
+#endif
+
+#define DIV_ROUND_CLOSEST(x, divisor) (                                                                                                      \
+    {                                                                                                                                        \
+        typeof(x) __x = x;                                                                                                                   \
+        typeof(divisor) __d = divisor;                                                                                                       \
+        (((typeof(x))-1) > 0 || ((typeof(divisor))-1) > 0 || (__x) > 0) ? (((__x) + ((__d) / 2)) / (__d)) : (((__x) - ((__d) / 2)) / (__d)); \
+    })
+
+int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
+{
+    const unsigned int mode_x_div = 16;
+
+    return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
+}
+
+void _debug_uart_init(void)
+{
+    struct NS16550* com_port = (struct NS16550*)UART_ADDR;
+
+    /*
+     * We copy the code from above because it is already horribly messy.
+     * Trying to refactor to nicely remove the duplication doesn't seem
+     * feasible. The better fix is to move all users of this driver to
+     * driver model.
+     */
+    int baud_divisor = ns16550_calc_divisor(com_port, 24000000,
+        1500000);
+    serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
+    serial_dout(&com_port->mcr, UART_MCRVAL);
+    serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
+
+    serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
+    serial_dout(&com_port->dll, baud_divisor & 0xff);
+    serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
+    serial_dout(&com_port->lcr, UART_LCRVAL);
+}
+
+void _debug_uart_putc(int ch)
+{
+    struct NS16550* com_port = (struct NS16550*)UART_ADDR;
+
+    while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
+        ;
+    serial_dout(&com_port->thr, ch);
+}
+
+int _debug_uart_getc(void)
+{
+    struct NS16550* com_port = (struct NS16550*)UART_ADDR;
+
+    while (!(serial_din(&com_port->lsr) & UART_LSR_DR))
+        ;
+
+    return serial_din(&com_port->rbr);
+}
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/uart.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/uart.c
index 8324eb35e..2fb925ea6 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/uart.c
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/uart.c
@@ -4,6 +4,7 @@
 
 #include "uart.h"
 #include "actracer.h"
+#include "ns16550.h"
 #include "uart_common_ope.h"
 
 // the UART control registers are memory-mapped
@@ -12,28 +13,30 @@
 
 // the transmit output buffer.
 #define UART_TX_BUF_SIZE 32
-static char uart_tx_buf[UART_TX_BUF_SIZE];
+// static char uart_tx_buf[UART_TX_BUF_SIZE];
 uint64_t uart_tx_w; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE]
 uint64_t uart_tx_r; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE]
 
 void uartinit(void)
 {
-    // disable uart
-    UART_WRITE_REG(CR, 0);
+    // // disable uart
+    // UART_WRITE_REG(CR, 0);
 
-    // disable interrupts.
-    UART_WRITE_REG(IMSC, 0);
+    // // disable interrupts.
+    // UART_WRITE_REG(IMSC, 0);
 
-    // in qemu, it is not necessary to set baudrate.
-    // enable FIFOs.
-    // set word length to 8 bits, no parity.
-    UART_WRITE_REG(LCRH, LCRH_FEN | LCRH_WLEN_8BIT);
+    // // in qemu, it is not necessary to set baudrate.
+    // // enable FIFOs.
+    // // set word length to 8 bits, no parity.
+    // UART_WRITE_REG(LCRH, LCRH_FEN | LCRH_WLEN_8BIT);
 
-    // enable RXE, TXE and enable uart.
-    UART_WRITE_REG(CR, 0x301);
+    // // enable RXE, TXE and enable uart.
+    // UART_WRITE_REG(CR, 0x301);
 
-    // enable transmit and receive interrupts.
-    UART_WRITE_REG(IMSC, INT_RX_ENABLE | INT_TX_ENABLE);
+    // // enable transmit and receive interrupts.
+    // UART_WRITE_REG(IMSC, INT_RX_ENABLE | INT_TX_ENABLE);
+
+    _debug_uart_init();
 }
 
 // if the UART is idle, and a character is waiting
@@ -42,71 +45,48 @@ void uartinit(void)
 // called from both the top- and bottom-half.
 void uartstart()
 {
-    while (1) {
-        if (uart_tx_w == uart_tx_r) {
-            // transmit buffer is empty.
-            return;
-        }
+    // while (1) {
+    //     if (uart_tx_w == uart_tx_r) {
+    //         // transmit buffer is empty.
+    //         return;
+    //     }
 
-        if (UART_READ_REG(FR) & FR_TXFF) {
-            // the UART transmit holding register is full,
-            // so we cannot give it another byte.
-            // it will interrupt when it's ready for a new byte.
-            return;
-        }
+    //     if (UART_READ_REG(FR) & FR_TXFF) {
+    //         // the UART transmit holding register is full,
+    //         // so we cannot give it another byte.
+    //         // it will interrupt when it's ready for a new byte.
+    //         return;
+    //     }
 
-        int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE];
-        uart_tx_r += 1;
+    //     int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE];
+    //     uart_tx_r += 1;
 
-        // maybe uartputc() is waiting for space in the buffer.
+    //     // maybe uartputc() is waiting for space in the buffer.
 
-        UART_WRITE_REG(DR, c);
-    }
+    //     UART_WRITE_REG(DR, c);
+    // }
 }
 
-// add a character to the output buffer and tell the
-// UART to start sending if it isn't already.
-// blocks if the output buffer is full.
-// because it may block, it can't be called
-// from interrupts; it's only suitable for use
-// by write().
 void uartputc(uint8_t c)
 {
-    while (uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE)
-        ;
-    uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c;
-    uart_tx_w += 1;
-    uartstart();
-    return;
+    // while (uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE)
+    //     ;
+    // uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c;
+    // uart_tx_w += 1;
+    // uartstart();
+    // return;
+    _debug_uart_putc((int)c);
 }
 
 // read one input character from the UART.
 // return -1 if none is waiting.
 static uint8_t uartgetc(void)
 {
-    if (UART_READ_REG(FR) & FR_RXFE)
-        return 0xFF;
-    else
-        return UART_READ_REG(DR);
-}
-
-// handle a uart interrupt, raised because input has
-// arrived, or the uart is ready for more output, or
-// both. called from trap.c.
-void uartintr(void)
-{
-    // read and process incoming characters.
-    while (1) {
-        int c = uartgetc();
-        if (c == 0xFF)
-            break;
-    }
-
-    // send buffered characters.
-    uartstart();
-
-    // clear transmit and receive interrupts.
-    UART_WRITE_REG(ICR, INT_RX_ENABLE | INT_TX_ENABLE);
+    // if (UART_READ_REG(FR) & FR_RXFE)
+    //     return 0xFF;
+    // else
+    //     return UART_READ_REG(DR);
+    return 0xFF;
 }
 
 static uint32_t UartGetIrqnum()