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Start support ok1028a-c.

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This commit is contained in:
liuqh
2024-05-10 15:42:29 +08:00
parent 361ea2b53e
commit a836b7f5c8
41 changed files with 1072 additions and 489 deletions
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Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/Makefile
+6
View File
@@ -1,4 +1,10 @@
ifneq ($(findstring $(BOARD), ok1028a-c), )
SRC_DIR := armv8-a
endif
ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )
SRC_DIR := armv7-a
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/bootmmu.c
+14 -15
View File
@@ -40,9 +40,9 @@ extern uint64_t kernel_data_begin[];
#define NR_PDE_ENTRIES 512
#define L1_TYPE_SEC (2 << 0)
#define L1_SECT_DEV ((0B00)<<2) //Device memory
#define L1_SECT_AP0 (1 << 6) //Data Access Permissions
uint64_t boot_ptable[NR_PTE_ENTRIES] __attribute__((aligned(0x4000))) = { 0 };
#define L1_SECT_DEV ((0B00) << 2) // Device memory
#define L1_SECT_AP0 (1 << 6) // Data Access Permissions
uint64_t boot_pgdir[NR_PDE_ENTRIES] __attribute__((aligned(0x4000))) = { 0 };
static void build_boot_pgdir()
{
@@ -68,24 +68,23 @@ static void build_boot_pgdir()
}
}
static void load_boot_pgdir()
{
uint64_t val;
// DACR_W(0x55555555); // set domain access control as client
TTBCR_W(0x0);
TTBR0_W((uint64_t)boot_pgdir);
// DACR_W(0x55555555); // set domain access control as client
// TTBCR_W(0x0);
// TTBR0_W((uint64_t)boot_pgdir);
TTBR0_W(0x0);
TTBR1_W((uint64_t)boot_pgdir);
// Enable paging using read/modify/write
SCTLR_R(val);
val |= (1 << 0); //EL1 and EL0 stage 1 address translation enabled.
val |= (1 << 1); //Alignment check enable
val |= (1 << 2); // Cacheability control, for data caching.
val |= (1 << 12); // Instruction access Cacheability control
val |= (1 << 19); //forced to XN for the EL1&0 translation regime.
val |= (1 << 0); // EL1 and EL0 stage 1 address translation enabled.
val |= (1 << 1); // Alignment check enable
val |= (1 << 2); // Cacheability control, for data caching.
val |= (1 << 12); // Instruction access Cacheability control
val |= (1 << 19); // forced to XN for the EL1&0 translation regime.
SCTLR_W(val);
// flush all TLB
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/include/mmu.h
+17 -23
View File
@@ -33,7 +33,6 @@ Modification:
#include "memlayout.h"
#include "page_table_entry.h"
#define TCR_IPS (0 << 32)
#define TCR_TG1_4K (0b10 << 30)
#define TCR_SH1_INNER (0b11 << 28)
@@ -41,16 +40,14 @@ Modification:
#define TCR_TG0_4K (0 << 14)
#define TCR_SH0_INNER (0b11 << 12)
#define TCR_ORGN0_IRGN0_WRITEBACK_WRITEALLOC ((0b01 << 10) | (0b01 << 8))
#define TCR_VALUE \
(TCR_IPS | \
TCR_TG1_4K | TCR_SH1_INNER | TCR_ORGN1_IRGN1_WRITEBACK_WRITEALLOC | \
TCR_TG0_4K | TCR_SH0_INNER | TCR_ORGN0_IRGN0_WRITEBACK_WRITEALLOC)
#define TCR_VALUE \
(TCR_IPS | TCR_TG1_4K | TCR_SH1_INNER | TCR_ORGN1_IRGN1_WRITEBACK_WRITEALLOC | TCR_TG0_4K | TCR_SH0_INNER | TCR_ORGN0_IRGN0_WRITEBACK_WRITEALLOC)
enum AccessPermission {
AccessPermission_NoAccess = 0,
AccessPermission_KernelOnly = 1, //EL1
AccessPermission_KernelOnly = 1, // EL1
AccessPermission_Reserved = 2,
AccessPermission_KernelUser = 3, //EL1&EL0
AccessPermission_KernelUser = 3, // EL1&EL0
};
void GetDevPteAttr(uintptr_t* attr);
@@ -59,32 +56,37 @@ void GetUsrDevPteAttr(uintptr_t* attr);
void GetKernPteAttr(uintptr_t* attr);
void GetPdeAttr(uintptr_t* attr);
/*
Enable MMU, cache, write buffer, etc.
*/
#define SCTLR_R(val) __asm__ volatile("mrs %0, sctlr_el1" : "=r"(val))
#define SCTLR_W(val) __asm__ volatile("msr sctlr_el1, %0" :: "r"(val))
#define SCTLR_W(val) __asm__ volatile("msr sctlr_el1, %0" ::"r"(val))
/*
Read and write mmu pagetable register base addr
*/
#define TTBR0_R(val) __asm__ volatile("mrs %0, ttbr0_el1" : "=r"(val))
#define TTBR0_W(val) __asm__ volatile("msr ttbr0_el1, %0" :: "r"(val))
#define TTBR0_W(val) __asm__ volatile("msr ttbr0_el1, %0" ::"r"(val))
/*
Read and write mmu pagetable register base addr
*/
#define TTBR1_R(val) __asm__ volatile("mrs %0, ttbr1_el1" : "=r"(val))
#define TTBR1_W(val) __asm__ volatile("msr ttbr1_el1, %0" ::"r"(val))
/*
TTBCR is used for choosing TTBR0 and TTBR1 as page table register.
When TTBCR is set to 0, TTBR0 is selected by default.
*/
#define TTBCR_R(val) __asm__ volatile("mrs %0, ttbcr_el1" : "=r"(val))
#define TTBCR_W(val) __asm__ volatile("msr ttbcr_el1, %0" :: "r"(val))
// #define TTBCR_R(val) __asm__ volatile("mrs %0, ttbcr_el1" : "=r"(val))
// #define TTBCR_W(val) __asm__ volatile("msr ttbcr_el1, %0" ::"r"(val))
/*
DACR registers are used to control memory privilage.
The domain value is usually 0x01. The memory privilage will be controled by pte AP/APX
*/
//#define DACR_R(val) __asm__ volatile("mrs %0, dacr_el1" : "=r"(val))
//#define DACR_W(val) __asm__ volatile("msr dacr_el1, %0" :: "r"(val))
// #define DACR_R(val) __asm__ volatile("mrs %0, dacr_el1" : "=r"(val))
// #define DACR_W(val) __asm__ volatile("msr dacr_el1, %0" :: "r"(val))
/*
Flush TLB when loading a new page table.
@@ -97,15 +99,7 @@ When nG is set in the pte attribute, the process is assigned an ASID, which is s
When the process switches, the flush TLB is no longer required anymore.
*/
#define CONTEXTIDR_R(val) __asm__ volatile("mrs %0, contextidr_el1" : "=r"(val))
#define CONTEXTIDR_W(val) __asm__ volatile("msr contextidr_el1, %0" :: "r"(val))
/* virtual and physical addr translate */
#define V2P(a) ((uint64_t)((uint64_t)(a)-KERN_OFFSET))
#define P2V(a) ((void*)((void*)(a) + KERN_OFFSET))
#define V2P_WO(x) ((x)-KERN_OFFSET) // same as V2P, but without casts
#define P2V_WO(x) ((x) + KERN_OFFSET) // same as V2P, but without casts
#define CONTEXTIDR_W(val) __asm__ volatile("msr contextidr_el1, %0" ::"r"(val))
#ifndef __ASSEMBLER__
#include <stdint.h>
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/mmu.c
+1 -20
View File
@@ -38,24 +38,6 @@ Modification:
// extern struct MmuCommonDone mmu_common_done;
static struct MmuDriverRightGroup right_group;
void load_pgdir_critical(uintptr_t pgdir_paddr, struct TraceTag* intr_driver_tag)
{
/* get cache driver */
struct ICacheDone* p_icache_done = AchieveResource(&right_group.icache_driver_tag);
struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag);
/* get intr driver */
struct XiziTrapDriver* p_intr_driver = AchieveResource(intr_driver_tag);
p_intr_driver->cpu_irq_disable();
TTBR0_W((uint64_t)pgdir_paddr);
CLEARTLB(0);
p_icache_done->invalidateall();
p_dcache_done->flushall();
p_intr_driver->cpu_irq_enable();
}
void load_pgdir(uintptr_t pgdir_paddr)
{
/* get cache driver */
@@ -70,7 +52,7 @@ void load_pgdir(uintptr_t pgdir_paddr)
__attribute__((always_inline)) inline static void _tlb_flush(uintptr_t va)
{
__asm__ volatile("tlbi vae1is, %0" :: "r"(va) );
__asm__ volatile("tlbi vae1is, %0" ::"r"(va));
}
static void tlb_flush_range(uintptr_t vstart, int len)
@@ -94,7 +76,6 @@ static struct MmuCommonDone mmu_common_done = {
.MmuUsrDevPteAttr = GetUsrDevPteAttr,
.MmuKernPteAttr = GetKernPteAttr,
.LoadPgdirCrit = load_pgdir_critical,
.LoadPgdir = load_pgdir,
.TlbFlushAll = tlb_flush_all,
.TlbFlush = tlb_flush_range,
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/ok1028a-c/memlayout.h
+2 -2
View File
@@ -72,10 +72,10 @@ Modification:
#define USER_IPC_SPACE_TOP (USER_MEM_TOP - USER_STACK_SIZE)
/* Kernel memory layout */
#define KERN_MEM_BASE (0xffff000000000000) // First kernel virtual address
#define KERN_MEM_BASE (0xffff000000000000ULL) // First kernel virtual address
#define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE)
#define V2P(a) (((uint64)(a)) - KERN_MEM_BASE)
#define V2P(a) (((uint64_t)(a)) - KERN_MEM_BASE)
#define P2V(a) ((void *)(((char *)(a)) + KERN_MEM_BASE))
#define V2P_WO(x) ((x) - KERN_MEM_BASE) // same as V2P, but without casts
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/pagetable_attr.c
+43 -43
View File
@@ -31,67 +31,67 @@ Modification:
void GetUsrPteAttr(uintptr_t* attr)
{
static char init = 0;
static PageTblEntry usr_pte_attr;
if (init == 0) {
init = 1;
// static char init = 0;
// static PageTblEntry usr_pte_attr;
// if (init == 0) {
// init = 1;
usr_pte_attr.entry = 0;
usr_pte_attr.desc_type = PAGE_4K;
usr_pte_attr.B = 1;
usr_pte_attr.C = 1;
usr_pte_attr.S = 1;
usr_pte_attr.AP1_0 = AccessPermission_KernelUser;
}
*attr = usr_pte_attr.entry;
// usr_pte_attr.entry = 0;
// usr_pte_attr.desc_type = PAGE_4K;
// usr_pte_attr.B = 1;
// usr_pte_attr.C = 1;
// usr_pte_attr.S = 1;
// usr_pte_attr.AP1_0 = AccessPermission_KernelUser;
// }
// *attr = usr_pte_attr.entry;
}
void GetUsrDevPteAttr(uintptr_t* attr)
{
static char init = 0;
static PageTblEntry usr_pte_attr;
if (init == 0) {
init = 1;
// static char init = 0;
// static PageTblEntry usr_pte_attr;
// if (init == 0) {
// init = 1;
usr_pte_attr.entry = 0;
usr_pte_attr.desc_type = PAGE_4K;
usr_pte_attr.AP1_0 = AccessPermission_KernelUser;
}
*attr = usr_pte_attr.entry;
// usr_pte_attr.entry = 0;
// usr_pte_attr.desc_type = PAGE_4K;
// usr_pte_attr.AP1_0 = AccessPermission_KernelUser;
// }
// *attr = usr_pte_attr.entry;
}
void GetDevPteAttr(uintptr_t* attr)
{
static char init = 0;
static PageTblEntry dev_pte_attr;
if (init == 0) {
init = 1;
// static char init = 0;
// static PageTblEntry dev_pte_attr;
// if (init == 0) {
// init = 1;
dev_pte_attr.entry = 0;
dev_pte_attr.desc_type = PAGE_4K;
dev_pte_attr.AP1_0 = AccessPermission_KernelOnly;
}
*attr = dev_pte_attr.entry;
// dev_pte_attr.entry = 0;
// dev_pte_attr.desc_type = PAGE_4K;
// dev_pte_attr.AP1_0 = AccessPermission_KernelOnly;
// }
// *attr = dev_pte_attr.entry;
}
void GetKernPteAttr(uintptr_t* attr)
{
static char init = 0;
static PageTblEntry kern_pte_attr;
if (init == 0) {
init = 1;
// static char init = 0;
// static PageTblEntry kern_pte_attr;
// if (init == 0) {
// init = 1;
kern_pte_attr.entry = 0;
kern_pte_attr.desc_type = PAGE_4K;
kern_pte_attr.B = 1;
kern_pte_attr.C = 1;
kern_pte_attr.S = 1;
kern_pte_attr.AP1_0 = AccessPermission_KernelOnly;
}
*attr = kern_pte_attr.entry;
// kern_pte_attr.entry = 0;
// kern_pte_attr.desc_type = PAGE_4K;
// kern_pte_attr.B = 1;
// kern_pte_attr.C = 1;
// kern_pte_attr.S = 1;
// kern_pte_attr.AP1_0 = AccessPermission_KernelOnly;
// }
// *attr = kern_pte_attr.entry;
}
void GetPdeAttr(uintptr_t* attr)
{
*attr = PAGE_DIR_COARSE;
// *attr = PAGE_DIR_COARSE;
}