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format the codes with ok1052-c board

This commit is contained in:
wlyu 2022-03-21 14:48:57 +08:00
parent c61c6dafea 9ffd8fcbbb
commit a52854efb6
685 changed files with 203920 additions and 2293 deletions
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3
.gitmodules vendored
View File

@ -10,3 +10,6 @@
[submodule "Ubiquitous/Nuttx/nuttx"]
path = Ubiquitous/Nuttx/nuttx
url = https://gitlink.org.cn/wgzAIIT/incubator-nuttx.git
[submodule "Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/kendryte-sdk-source"]
path = Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/kendryte-sdk-source
url = https://code.gitlink.org.cn/chunyexixiaoyu/kendryte-sdk-source.git

1
APP_Framework/Framework/transform_layer/rtthread/transform.c
View File

@ -141,6 +141,7 @@ static int PrivSerialIoctl(int fd, int cmd, void *args)
config.bufsz = RT_SERIAL_RB_BUFSZ;
config.parity = serial_cfg->serial_parity_mode;
config.invert = serial_cfg->serial_invert_mode;
config.reserved = serial_cfg->ext_uart_no; ///< using extuart port number
rt_fd = fd_get(fd);
ret = rt_fd->fops->ioctl(rt_fd, RT_DEVICE_CTRL_CONFIG, &config);
return ret;

410
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.config Normal file
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@ -0,0 +1,410 @@
#
# Automatically generated file; DO NOT EDIT.
# XIUOS Rt-thread Configuration
#
CONFIG_ROOT_DIR="../../../.."
CONFIG_BSP_DIR="."
CONFIG_RT_Thread_DIR="../.."
CONFIG_RTT_DIR="../../rt-thread"
CONFIG_BOARD_K210_EVB=y
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_BIG_ENDIAN is not set
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=8
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=4096
CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
CONFIG_RT_DEBUG_INIT_CONFIG=y
CONFIG_RT_DEBUG_INIT=1
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
CONFIG_RT_USING_SIGNALS=y
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uarths"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_ARCH_CPU_64BIT=y
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_RISCV_FPU=y
CONFIG_ARCH_RISCV_FPU_S=y
CONFIG_ARCH_RISCV64=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
CONFIG_RT_USING_CPLUSPLUS=y
# CONFIG_RT_USING_CPLUSPLUS11 is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=16384
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=16
CONFIG_DFS_FILESYSTEM_TYPES_MAX=16
CONFIG_DFS_FD_MAX=64
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
CONFIG_RT_USING_SPI_MSD=y
CONFIG_RT_USING_SFUD=y
CONFIG_RT_SFUD_USING_SFDP=y
CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
# CONFIG_RT_SFUD_USING_QSPI is not set
CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
CONFIG_RT_DEBUG_SFUD=y
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
CONFIG_RT_USING_PTHREADS=y
CONFIG_PTHREAD_NUM_MAX=8
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# Board Drivers Config
#
CONFIG_BSP_USING_UART_HS=y
#
# General Purpose UARTs
#
CONFIG_BSP_USING_UART1=y
CONFIG_BSP_UART1_TXD_PIN=20
CONFIG_BSP_UART1_RXD_PIN=21
CONFIG_BSP_UART1_RTS_PIN=-1
CONFIG_BSP_UART1_CTS_PIN=-1
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_USING_LCD is not set
# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_LOW is not set
# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_HIGH is not set
# CONFIG_BSP_BOARD_KD233 is not set
# CONFIG_BSP_BOARD_K210_OPENMV_TEST is not set
# CONFIG_BSP_BOARD_USER is not set
# CONFIG_BSP_USING_SDCARD is not set
# CONFIG_BSP_USING_DVP is not set
CONFIG_BSP_USING_CH438=y
CONFIG_BSP_CH438_ALE_PIN=23
CONFIG_BSP_CH438_NWR_PIN=24
CONFIG_BSP_CH438_NRD_PIN=25
CONFIG_BSP_CH438_D0_PIN=27
CONFIG_BSP_CH438_D1_PIN=28
CONFIG_BSP_CH438_D2_PIN=29
CONFIG_BSP_CH438_D3_PIN=30
CONFIG_BSP_CH438_D4_PIN=31
CONFIG_BSP_CH438_D5_PIN=32
CONFIG_BSP_CH438_D6_PIN=33
CONFIG_BSP_CH438_D7_PIN=34
CONFIG_BSP_CH438_INT_PIN=35
#
# Kendryte SDK Config
#
CONFIG_PKG_KENDRYTE_SDK_VERNUM=0x0055
#
# More Drivers
#
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_DRV_USING_OV2640 is not set
#
# APP_Framework
#
#
# Framework
#
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
CONFIG_ADD_XIZI_FETURES=y
# CONFIG_ADD_NUTTX_FETURES is not set
# CONFIG_ADD_RTTHREAD_FETURES is not set
# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
# CONFIG_SUPPORT_KNOWING_FRAMEWORK is not set
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
#
# Security
#
# CONFIG_CRYPTO is not set
#
# Applications
#
#
# config stack size and priority of main task
#
CONFIG_MAIN_KTASK_STACK_SIZE=1024
#
# ota app
#
# CONFIG_APPLICATION_OTA is not set
#
# test app
#
# CONFIG_USER_TEST is not set
#
# connection app
#
# CONFIG_APPLICATION_CONNECTION is not set
#
# control app
#
#
# knowing app
#
# CONFIG_APPLICATION_KNOWING is not set
#
# sensor app
#
CONFIG_APPLICATION_SENSOR=y
# CONFIG_APPLICATION_SENSOR_HCHO is not set
# CONFIG_APPLICATION_SENSOR_TVOC is not set
# CONFIG_APPLICATION_SENSOR_IAQ is not set
# CONFIG_APPLICATION_SENSOR_CH4 is not set
# CONFIG_APPLICATION_SENSOR_CO2 is not set
# CONFIG_APPLICATION_SENSOR_PM1_0 is not set
# CONFIG_APPLICATION_SENSOR_PM2_5 is not set
# CONFIG_APPLICATION_SENSOR_PM10 is not set
# CONFIG_APPLICATION_SENSOR_VOICE is not set
# CONFIG_APPLICATION_SENSOR_TEMPERATURE is not set
# CONFIG_APPLICATION_SENSOR_HUMIDITY is not set
# CONFIG_APPLICATION_SENSOR_WINDDIRECTION is not set
# CONFIG_APPLICATION_SENSOR_WINDSPEED is not set
# CONFIG_APPLICATION_SENSOR_ALTITUDE is not set
# CONFIG_USING_EMBEDDED_DATABASE_APP is not set
#
# lib
#
CONFIG_APP_SELECT_NEWLIB=y
# CONFIG_APP_SELECT_OTHER_LIB is not set
CONFIG_LIB_USING_CJSON=y
# CONFIG_LIB_USING_QUEUE is not set
# CONFIG_LIB_LV is not set
# CONFIG_USING_EMBEDDED_DATABASE is not set
CONFIG___STACKSIZE__=4096

228
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.gitignore vendored Normal file
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@ -0,0 +1,228 @@
# this
*.old
*.dblite
cconfig.h
*.bin
*.map
# rtconfig.h
# .config
# General
.DS_Store
.AppleDouble
.LSOverride
# Icon must end with two \r
Icon
# Thumbnails
._*
# Files that might appear in the root of a volume
.DocumentRevisions-V100
.fseventsd
.Spotlight-V100
.TemporaryItems
.Trashes
.VolumeIcon.icns
.com.apple.timemachine.donotpresent
# Directories potentially created on remote AFP share
.AppleDB
.AppleDesktop
Network Trash Folder
Temporary Items
.apdisk
# Byte-compiled / optimized / DLL files
__pycache__/
*.py[cod]
*$py.class
# C extensions
*.so
# Distribution / packaging
.Python
build/
develop-eggs/
dist/
downloads/
eggs/
.eggs/
lib/
lib64/
parts/
sdist/
var/
wheels/
share/python-wheels/
*.egg-info/
.installed.cfg
*.egg
MANIFEST
# PyInstaller
# Usually these files are written by a python script from a template
# before PyInstaller builds the exe, so as to inject date/other infos into it.
*.manifest
*.spec
# Installer logs
pip-log.txt
pip-delete-this-directory.txt
# Unit test / coverage reports
htmlcov/
.tox/
.nox/
.coverage
.coverage.*
.cache
nosetests.xml
coverage.xml
*.cover
*.py,cover
.hypothesis/
.pytest_cache/
cover/
# Translations
*.mo
*.pot
# Django stuff:
*.log
local_settings.py
db.sqlite3
db.sqlite3-journal
# Flask stuff:
instance/
.webassets-cache
# Scrapy stuff:
.scrapy
# Sphinx documentation
docs/_build/
# PyBuilder
.pybuilder/
target/
# Jupyter Notebook
.ipynb_checkpoints
# IPython
profile_default/
ipython_config.py
# pyenv
# For a library or package, you might want to ignore these files since the code is
# intended to run in multiple environments; otherwise, check them in:
# .python-version
# pipenv
# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
# However, in case of collaboration, if having platform-specific dependencies or dependencies
# having no cross-platform support, pipenv may install dependencies that don't work, or not
# install all needed dependencies.
#Pipfile.lock
# PEP 582; used by e.g. github.com/David-OConnor/pyflow
__pypackages__/
# Celery stuff
celerybeat-schedule
celerybeat.pid
# SageMath parsed files
*.sage.py
# Environments
.env
.venv
env/
venv/
ENV/
env.bak/
venv.bak/
# Spyder project settings
.spyderproject
.spyproject
# Rope project settings
.ropeproject
# mkdocs documentation
/site
# mypy
.mypy_cache/
.dmypy.json
dmypy.json
# Pyre type checker
.pyre/
# pytype static type analyzer
.pytype/
# Cython debug symbols
cython_debug/
# Prerequisites
*.d
# Object files
*.o
*.ko
*.obj
*.elf
# Linker output
*.ilk
*.map
*.exp
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
# Debug files
*.dSYM/
*.su
*.idb
*.pdb
# Kernel Module Compile Results
*.mod*
*.cmd
.tmp_versions/
modules.order
Module.symvers
Mkfile.old
dkms.con

39
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/Kconfig Normal file
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@ -0,0 +1,39 @@
mainmenu "XIUOS Rt-thread Configuration"
config ROOT_DIR
string
default "../../../.."
config BSP_DIR
string
default "."
config RT_Thread_DIR
string
default "../.."
config RTT_DIR
string
default "../../rt-thread"
config BOARD_K210_EVB
bool
select ARCH_RISCV64
select ARCH_RISCV_FPU_S
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
config APP_DIR
string
default "../../../../APP_Framework"
source "$RTT_DIR/Kconfig"
source "base-drivers/Kconfig"
source "kendryte-sdk/Kconfig"
source "$RT_Thread_DIR/app_match_rt-thread/Kconfig"
source "$ROOT_DIR/APP_Framework/Kconfig"
config __STACKSIZE__
int "stack size for interrupt"
default 4096

17
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/README.md Normal file
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@ -0,0 +1,17 @@
## aiit-riscv64-board编译说明
编译aiit-riscv64-board，需要有RT-Thread的代码，因为aiit-riscv64-boar的sdk是以软件包方式，更新软件包在~/yourdir/xiuos/目录执行以下语句：
git submodule init
git submodule update Ubiquitous/RT_Thread/rt-thread
git submodule update Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/kendryte-sdk-source
如果在Linux平台下，可以先执行
scons --menuconfig
退出后执行编译：
scons
编译工具链安装参考：xiuos/Ubiquitous/XiZi/board/aiit-riscv64-board/README.md

13
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/SConscript Normal file
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@ -0,0 +1,13 @@
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

65
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/SConstruct Normal file
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@ -0,0 +1,65 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../rt-thread')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
# use ASPPCOM to replace ASCOM, ASPPCOM will use CFLAGS/CPPFLAGS with AS
env['ASCOM'] = env['ASPPCOM']
AddOption('--compiledb',
dest = 'compiledb',
action = 'store_true',
default = False,
help = 'generate compile_commands.json')
if GetOption('compiledb'):
if int(SCons.__version__.split('.')[0]) >= 4:
env['COMPILATIONDB_USE_ABSPATH'] = True
env.Tool('compilation_db')
env.CompilationDatabase('compile_commands.json')
else:
print('Warning: --compiledb only support on SCons 4.0+')
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
stack_size = 4096
stack_lds = open('link_stacksize.lds', 'w')
if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__')
stack_lds.write('__STACKSIZE__ = %d;' % stack_size)
stack_lds.close()
# include more drivers
objs.extend(SConscript(os.getcwd() + '/../../app_match_rt-thread/SConscript'))
# include APP_Framework/Framework
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Framework/SConscript'))
# include APP_Framework/Applications
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SConscript'))
# include APP_Framework/lib
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript'))
# make a building
DoBuilding(TARGET, objs)

9
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/SConscript Normal file
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@ -0,0 +1,9 @@
from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

28
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/main.c Normal file
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@ -0,0 +1,28 @@
/*
* @Author: your name
* @Date: 2021-10-11 22:04:25
* @LastEditTime: 2021-10-14 11:12:52
* @LastEditors: Please set LastEditors
* @Description: In User Settings Edit
* @FilePath: \xiuos\Ubiquitous\RT_Thread\bsp\k210\applications\main.c
*/
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include <rtthread.h>
#include <stdio.h>
int main(void)
{
printf("Hello World\n");
return 0;
}

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Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/Kconfig Normal file
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menu "Board Drivers Config"
config BSP_USING_UART_HS
bool "Enable High Speed UART"
default y
menu "General Purpose UARTs"
menuconfig BSP_USING_UART1
bool "Enable UART1"
default n
if BSP_USING_UART1
config BSP_UART1_TXD_PIN
int "uart1 TXD pin number"
default 20
config BSP_UART1_RXD_PIN
int "uart1 RXD pin number"
default 21
config BSP_UART1_RTS_PIN
int "uart1 RTS pin number (-1 for not used)"
default -1
config BSP_UART1_CTS_PIN
int "uart1 CTS pin number (-1 for not used)"
default -1
endif
menuconfig BSP_USING_UART2
bool "Enable UART2"
default n
if BSP_USING_UART2
config BSP_UART2_TXD_PIN
int "uart2 TXD pin number"
default 28
config BSP_UART2_RXD_PIN
int "uart2 RXD pin number"
default 27
config BSP_UART2_RTS_PIN
int "uart2 RTS pin number (-1 for not used)"
default -1
config BSP_UART2_CTS_PIN
int "uart2 CTS pin number (-1 for not used)"
default -1
endif
menuconfig BSP_USING_UART3
bool "Enable UART3"
default n
if BSP_USING_UART3
config BSP_UART3_TXD_PIN
int "uart3 TXD pin number"
default 22
config BSP_UART3_RXD_PIN
int "uart3 RXD pin number"
default 23
config BSP_UART3_RTS_PIN
int "uart3 RTS pin number (-1 for not used)"
default -1
config BSP_UART3_CTS_PIN
int "uart3 CTS pin number (-1 for not used)"
default -1
endif
endmenu
config BSP_USING_I2C1
bool "Enable I2C1 (GPIO0/1)"
select RT_USING_I2C
default n
menuconfig BSP_USING_SPI1
bool "Enable SPI1"
select RT_USING_SPI
default n
if BSP_USING_SPI1
config BSP_USING_SPI1_AS_QSPI
bool
default n
config BSP_SPI1_CLK_PIN
int "spi1 clk pin number"
default 27
config BSP_SPI1_D0_PIN
int "spi1 d0 pin number"
default 28
config BSP_SPI1_D1_PIN
int "spi1 d1 pin number"
default 26
if BSP_USING_SPI1_AS_QSPI
config BSP_SPI1_D2_PIN
int "spi1 d2 pin number"
default 32
config BSP_SPI1_D3_PIN
int "spi1 d3 pin number"
default 33
endif
menuconfig BSP_SPI1_USING_SS0
bool "SPI1 Enable SS0(spi10 dev)"
default n
if BSP_SPI1_USING_SS0
config BSP_SPI1_SS0_PIN
int "spi1 ss0 pin number"
default 29
endif
menuconfig BSP_SPI1_USING_SS1
bool "SPI1 Enable SS1(spi11 dev)"
default n
if BSP_SPI1_USING_SS1
config BSP_SPI1_SS1_PIN
int "spi1 ss1 pin number"
default 8
endif
menuconfig BSP_SPI1_USING_SS2
bool "SPI1 Enable SS2(spi12 dev)"
default n
if BSP_SPI1_USING_SS2
config BSP_SPI1_SS2_PIN
int "spi1 ss2 pin number"
default 26
endif
menuconfig BSP_SPI1_USING_SS3
bool "SPI1 Enable SS3(spi13 dev)"
default n
if BSP_SPI1_USING_SS3
config BSP_SPI1_SS3_PIN
int "spi1 ss3 pin number"
default 27
endif
endif
menuconfig BSP_USING_LCD
bool "Enable LCD on SPI0"
default n
if BSP_USING_LCD
config BSP_LCD_CS_PIN
int "CS pin number of 8080 interface"
default 36
config BSP_LCD_WR_PIN
int "WR pin number of 8080 interface"
default 39
config BSP_LCD_DC_PIN
int "DC pin number of 8080 interface"
default 38
config BSP_LCD_RST_PIN
int "RESET pin number of 8080 interface (-1 for not used)"
default 37
config BSP_LCD_BACKLIGHT_PIN
int "Backlight control pin number (-1 for not used)"
default -1
choice
prompt "backlight active polarity"
default BSP_LCD_BACKLIGHT_ACTIVE_LOW
config BSP_LCD_BACKLIGHT_ACTIVE_LOW
bool "lcd backlight on low level"
config BSP_LCD_BACKLIGHT_ACTIVE_HIGH
bool "lcd_backlight on high level"
endchoice
config BSP_LCD_CLK_FREQ
int "Lcd max clk frequency"
default 15000000
choice
prompt "lcd scan direction"
default BSP_BOARD_KD233
config BSP_BOARD_KD233
bool "board_kd233 lcd scan: DIR_YX_RLUD"
config BSP_BOARD_K210_OPENMV_TEST
bool "board_k210_openmv lcd scan: DIR_YX_LRUD"
config BSP_BOARD_USER
bool "board_user: user defined."
endchoice
config BSP_LCD_X_MAX
int "LCD Height"
default 240
config BSP_LCD_Y_MAX
int "LCD Width"
default 320
endif
menuconfig BSP_USING_SDCARD
bool "Enable SDCARD (spi1(ss0))"
select BSP_USING_SPI1
select BSP_SPI1_USING_SS0
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
select RT_USING_SPI_MSD
default n
menuconfig BSP_USING_DVP
bool "Enable DVP(camera)"
default n
if BSP_USING_DVP
comment "The default pin assignment is based on the Maix Duino K210 development board"
config BSP_DVP_SCCB_SDA_PIN
int "SCCB SDA pin number for camera"
default 40
config BSP_DVP_SCCB_SCLK_PIN
int "SCCB SCLK pin number for camera"
default 41
config BSP_DVP_CMOS_RST_PIN
int "CMOS RST pin number for camera"
default 42
config BSP_DVP_CMOS_VSYNC_PIN
int "CMOS VSYNC pin number for camera"
default 43
config BSP_DVP_CMOS_PWDN_PIN
int "CMOS PWDN pin number for camera"
default 44
config BSP_DVP_CMOS_XCLK_PIN
int "CMOS XCLK pin number for camera"
default 46
config BSP_DVP_CMOS_PCLK_PIN
int "CMOS PCLK pin number for camera"
default 47
config BSP_DVP_CMOS_HREF_PIN
int "CMOS HREF pin number for camera"
default 45
endif
if PKG_USING_RW007
config RW007_SPIDEV_NAME
string "the SPIDEV rw007 driver on"
default "spi11"
config RW007_INT_BUSY_PIN
int "rw007 int pin for rw007"
default 7
config RW007_RST_PIN
int "rw007 rst pin for rw007"
default 6
endif
endmenu
menuconfig BSP_USING_CH438
bool "Enable CH438"
default y
if BSP_USING_CH438
config BSP_CH438_ALE_PIN
int "ale pin number for ch438"
default 23
config BSP_CH438_NWR_PIN
int "nwr pin number for ch438"
default 24
config BSP_CH438_NRD_PIN
int "nrd pin number for ch438"
default 25
config BSP_CH438_D0_PIN
int "d0 pin number for ch438"
default 27
config BSP_CH438_D1_PIN
int "d1 pin number for ch438"
default 28
config BSP_CH438_D2_PIN
int "d2 pin number for ch438"
default 29
config BSP_CH438_D3_PIN
int "d3 pin number for ch438"
default 30
config BSP_CH438_D4_PIN
int "d4 pin number for ch438"
default 31
config BSP_CH438_D5_PIN
int "d5 pin number for ch438"
default 32
config BSP_CH438_D6_PIN
int "d6 pin number for ch438"
default 33
config BSP_CH438_D7_PIN
int "d7 pin number for ch438"
default 34
config BSP_CH438_INT_PIN
int "int pin number for ch438"
default 35
endif

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Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/SConscript Normal file
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import os
import rtconfig
from building import *
cwd = GetCurrentDir()
drv_path = cwd+"/../../../rt-thread/bsp/k210/driver/"
src = [
'board.c',
'heap.c',
drv_path + 'drv_uart.c',
'drv_interrupt.c',
'drv_io_config.c',
'dmalock.c'
]
CPPPATH = [cwd,drv_path]
if GetDepend('RT_USING_PIN'):
src += ['drv_gpio.c']
if GetDepend('RT_USING_HWTIMER'):
src += [drv_path + 'drv_hw_timer.c']
if GetDepend('RT_USING_I2C'):
src += [drv_path + 'drv_i2c.c']
if GetDepend('RT_USING_SPI'):
src += ['drv_spi.c']
if GetDepend('RT_USING_PWM'):
src += [drv_path + 'drv_pwm.c']
if GetDepend('RT_USING_WDT'):
src += [drv_path + 'drv_wdt.c']
# if GetDepend('BSP_USING_SDCARD'):
# src += ['sdcard_port.c']
# if GetDepend('BSP_USING_DVP'):
# src += ['drv_dvp.c']
# if GetDepend('BSP_USING_LCD'):
# src += ['drv_lcd.c']
# src += ['drv_mpylcd.c']
if GetDepend('BSP_USING_CH438'):
src += ['ch438.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/board.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "tick.h"
#include "drv_uart.h"
#include "encoding.h"
#include "fpioa.h"
#include "dmac.h"
#include "dmalock.h"
void init_bss(void)
{
unsigned int *dst;
dst = &__bss_start;
while (dst < &__bss_end)
{
*dst++ = 0;
}
}
void primary_cpu_entry(void)
{
extern void entry(void);
/* disable global interrupt */
init_bss();
rt_hw_interrupt_disable();
entry();
}
#include <clint.h>
#include <sysctl.h>
int freq(void)
{
rt_uint64_t value = 0;
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL0);
rt_kprintf("PLL0: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL1);
rt_kprintf("PLL1: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL2);
rt_kprintf("PLL2: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
rt_kprintf("CPU : %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0);
rt_kprintf("APB0: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB1);
rt_kprintf("APB1: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB2);
rt_kprintf("APB2: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_HCLK);
rt_kprintf("HCLK: %d\n", value);
value = clint_get_time();
rt_kprintf("mtime: %d\n", value);
return 0;
}
MSH_CMD_EXPORT(freq, show freq info);
#ifdef RT_USING_SMP
extern int rt_hw_clint_ipi_enable(void);
#endif
extern int io_config_init(void);
void rt_hw_board_init(void)
{
sysctl_pll_set_freq(SYSCTL_PLL0, 800000000UL);
sysctl_pll_set_freq(SYSCTL_PLL1, 400000000UL);
sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL);
sysctl_clock_set_threshold(SYSCTL_THRESHOLD_APB1, 2);
/* Init FPIOA */
fpioa_init();
io_config_init();
/* Dmac init */
dmac_init();
dmalock_init();
/* initalize interrupt */
rt_hw_interrupt_init();
/* initialize hardware interrupt */
rt_hw_uart_init();
rt_hw_tick_init();
#ifdef RT_USING_SMP
rt_hw_clint_ipi_enable();
#endif
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif /* RT_USING_CONSOLE */
#ifdef RT_USING_HEAP
rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) RT_HW_HEAP_BEGIN, (rt_ubase_t) RT_HW_HEAP_END);
/* initialize memory system */
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}
void rt_hw_cpu_reset(void)
{
sysctl->soft_reset.soft_reset = 1;
while(1);
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
/**
* This function will delay for some us.
*
* @param us the delay time of us
*/
void rt_hw_us_delay(rt_uint32_t usec)
{
rt_uint32_t cycle = read_cycle();
rt_uint32_t nop_all = usec * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / 1000000UL;
while (1)
{
if(read_cycle() - cycle >= nop_all)
break;
}
}

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Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/board.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef BOARD_H__
#define BOARD_H__
#include "fpioa.h"
#include "platform.h"
#include <rtconfig.h>
extern unsigned int __bss_start;
extern unsigned int __bss_end;
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_END (void*)(0x80000000 + 6 * 1024 * 1024)
void rt_hw_board_init(void);
#endif

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Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.c Normal file
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#include <rtthread.h>
#include <rtdevice.h>
#include <drv_io_config.h>
#include <gpiohs.h>
#include "board.h"
#include "ch438.h"
#include "sleep.h"
static struct rt_semaphore ch438_sem;
static rt_uint8_t offsetadd[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* Offset address of serial port number */
rt_uint8_t RevLen ,Ch438Buff[8][BUFFSIZE],Ch438BuffPtr[8];
void CH438_INIT(void)
{
CH438_set_output();
gpiohs_set_drive_mode(FPIOA_CH438_NWR, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_NRD, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_ALE, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_485_DIR, GPIO_DM_OUTPUT);
gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH);
}
void CH438_PORT_INIT( rt_uint8_t ext_uart_no,rt_uint32_t BaudRate )
{
rt_uint32_t div;
rt_uint8_t DLL,DLM,dlab;
rt_uint8_t REG_LCR_ADDR;
rt_uint8_t REG_DLL_ADDR;
rt_uint8_t REG_DLM_ADDR;
rt_uint8_t REG_IER_ADDR;
rt_uint8_t REG_MCR_ADDR;
rt_uint8_t REG_FCR_ADDR;
rt_uint8_t REG_RBR_ADDR;
rt_uint8_t REG_THR_ADDR;
rt_uint8_t REG_IIR_ADDR;
REG_LCR_ADDR = offsetadd[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offsetadd[ext_uart_no] | REG_IIR0_ADDR;
WriteCH438Data( REG_IER_ADDR, BIT_IER_RESET ); /* Reset the serial port */
rt_thread_delay(50);
dlab = ReadCH438Data(REG_IER_ADDR);
dlab &= 0xDF;
WriteCH438Data(REG_IER_ADDR, dlab);
dlab = ReadCH438Data(REG_LCR_ADDR);
dlab |= 0x80;
WriteCH438Data(REG_LCR_ADDR, dlab);
div = ( Fpclk >> 4 ) / BaudRate;
DLM = div >> 8;
DLL = div & 0xff;
WriteCH438Data( REG_DLL_ADDR, DLL ); /* Set baud rate */
WriteCH438Data( REG_DLM_ADDR, DLM );
WriteCH438Data( REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN ); /* Set FIFO mode */
WriteCH438Data( REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0 );
WriteCH438Data( REG_IER_ADDR, /*BIT_IER_IEMODEM | BIT_IER_IETHRE | BIT_IER_IELINES | */BIT_IER_IERECV );
WriteCH438Data( REG_MCR_ADDR, BIT_MCR_OUT2 );
WriteCH438Data(REG_FCR_ADDR,ReadCH438Data(REG_FCR_ADDR)| BIT_FCR_RFIFORST | BIT_FCR_TFIFORST);
}
static void CH438_set_output(void)
{
gpiohs_set_drive_mode(FPIOA_CH438_D0, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D1, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D2, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D3, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D4, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D5, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D6, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D7, GPIO_DM_OUTPUT);
}
static void CH438_set_input(void)
{
gpiohs_set_drive_mode(FPIOA_CH438_D0, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D1, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D2, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D3, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D4, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D5, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D6, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D7, GPIO_DM_INPUT_PULL_UP);
}
void set_485_input(rt_uint8_t ch_no)
{
if(ch_no == 1)
gpiohs_set_pin(FPIOA_485_DIR, GPIO_PV_LOW);
}
void set_485_output(rt_uint8_t ch_no)
{
if(ch_no == 1)
gpiohs_set_pin(FPIOA_485_DIR, GPIO_PV_HIGH);
}
rt_uint8_t ReadCH438Data( rt_uint8_t addr )
{
rt_uint8_t dat;
gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH);
CH438_set_output();
usleep(1);
if(addr &0x80) gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_LOW);
if(addr &0x40) gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_LOW);
if(addr &0x20) gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_LOW);
if(addr &0x10) gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_LOW);
if(addr &0x08) gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_LOW);
if(addr &0x04) gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_LOW);
if(addr &0x02) gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_LOW);
if(addr &0x01) gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_LOW);
usleep(1);
gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_LOW);
usleep(1);
CH438_set_input();
usleep(1);
gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_LOW);
usleep(1);
dat = 0;
if (gpiohs_get_pin(FPIOA_CH438_D7)) dat |= 0x80;
if (gpiohs_get_pin(FPIOA_CH438_D6)) dat |= 0x40;
if (gpiohs_get_pin(FPIOA_CH438_D5)) dat |= 0x20;
if (gpiohs_get_pin(FPIOA_CH438_D4)) dat |= 0x10;
if (gpiohs_get_pin(FPIOA_CH438_D3)) dat |= 0x08;
if (gpiohs_get_pin(FPIOA_CH438_D2)) dat |= 0x04;
if (gpiohs_get_pin(FPIOA_CH438_D1)) dat |= 0x02;
if (gpiohs_get_pin(FPIOA_CH438_D0)) dat |= 0x01;
gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH);
usleep(1);
return dat;
}
static void WriteCH438Data( rt_uint8_t addr, rt_uint8_t dat)
{
gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH);
CH438_set_output();
usleep(1);
if(addr &0x80) gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_LOW);
if(addr &0x40) gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_LOW);
if(addr &0x20) gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_LOW);
if(addr &0x10) gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_LOW);
if(addr &0x08) gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_LOW);
if(addr &0x04) gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_LOW);
if(addr &0x02) gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_LOW);
if(addr &0x01) gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_LOW);
usleep(1);
gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_LOW);
usleep(1);
if(dat &0x80) gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_LOW);
if(dat &0x40) gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_LOW);
if(dat &0x20) gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_LOW);
if(dat &0x10) gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_LOW);
if(dat &0x08) gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_LOW);
if(dat &0x04) gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_LOW);
if(dat &0x02) gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_LOW);
if(dat &0x01) gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_LOW);
usleep(1);
gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_LOW);
usleep(1);
gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH);
usleep(1);
CH438_set_input();
return;
}
static void WriteCH438Block( rt_uint8_t mAddr, rt_uint8_t mLen, rt_uint8_t *mBuf )
{
while ( mLen -- )
WriteCH438Data( mAddr, *mBuf++ );
}
// void CH438UARTSend( rt_uint8_t ext_uart_no,rt_uint8_t *Data, rt_uint8_t Num )
// {
// rt_uint8_t REG_LSR_ADDR,REG_THR_ADDR;
// REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
// REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
// while( 1 )
// {
// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_TEMT ) == 0 );
// if( Num <= 128 )
// {
// WriteCH438Block( REG_THR_ADDR, Num, Data );
// break;
// }
// else
// {
// WriteCH438Block( REG_THR_ADDR, 128, Data );
// Num -= 128;
// Data += 128;
// }
// }
// }
// rt_uint8_t CH438UARTRcv( rt_uint8_t ext_uart_no, rt_uint8_t* buf )
// {
// rt_uint8_t RcvNum = 0;
// rt_uint8_t dat = 0;
// rt_uint8_t REG_LSR_ADDR,REG_RBR_ADDR;
// rt_uint8_t *p_rev;
// p_rev = buf;
// REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
// REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
// {
// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0 );
// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
// {
// dat = ReadCH438Data( REG_RBR_ADDR );
// Ch438Buff[ext_uart_no][Ch438BuffPtr[ext_uart_no]] = dat;
// Ch438BuffPtr[ext_uart_no] = Ch438BuffPtr[ext_uart_no] + 1;
// if (Ch438BuffPtr[ext_uart_no] == BUFFSIZE)
// Ch438BuffPtr[ext_uart_no] = 0;
// RcvNum = RcvNum + 1;
// }
// }
// return( RcvNum );
// }
static rt_err_t rt_extuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
rt_uint32_t baud_rate = cfg->baud_rate;
uint16_t port = cfg->reserved;
CH438_PORT_INIT(port, baud_rate);
}
static rt_err_t extuart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
break;
case RT_DEVICE_CTRL_SET_INT:
break;
}
return (RT_EOK);
}
static int drv_extuart_putc(struct rt_serial_device *serial, char c)
{
uint16_t ext_uart_no = serial->config.reserved;
rt_uint8_t REG_LSR_ADDR,REG_THR_ADDR;
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_TEMT ) == 0 );
WriteCH438Block( REG_THR_ADDR, 1, &c );
}
static int drv_extuart_getc(struct rt_serial_device *serial)
{
rt_uint8_t dat = 0;
rt_uint8_t REG_LSR_ADDR,REG_RBR_ADDR;
uint16_t ext_uart_no = serial->config.reserved;///< get extern uart port
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0 );
// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
// {
dat = ReadCH438Data( REG_RBR_ADDR );
// }
return( dat );
}
const struct rt_uart_ops extuart_ops =
{
rt_extuart_configure,
extuart_control,
drv_extuart_putc,
drv_extuart_getc,
RT_NULL
};
static int Ch438Irq(void *parameter)
{
rt_sem_release(&ch438_sem);
}
int Ch438InitDefault(void)
{
rt_err_t flag;
flag = rt_sem_init(&ch438_sem, "sem_438",0,RT_IPC_FLAG_FIFO);
if (flag != RT_EOK)
{
rt_kprintf("ch438.drv create sem failed .\n");
return -1;
}
gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_pin_edge(FPIOA_CH438_INT,GPIO_PE_FALLING);
gpiohs_irq_register(FPIOA_CH438_INT, 1, Ch438Irq, 0);
CH438_INIT();
return 0;
}
INIT_APP_EXPORT(Ch438InitDefault);
int rt_hw_ch438_init(void)
{
struct rt_serial_device *extserial;
struct device_uart *extuart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
// #ifdef BSP_USING_UART1
{
static struct rt_serial_device extserial0;
// static struct device_uart extuart0;
extserial = &extserial0;
// extuart = &extuart0;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 115200;
extserial->config.reserved = 0; ///< extern uart port
// extuart->hw_base = UART1_BASE_ADDR;
// extuart->irqno = IRQN_UART1_INTERRUPT;
// _uart_init(UART_DEVICE_1);
rt_hw_serial_register(extserial,
"extuart_dev0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
}
// #endif
// #ifdef BSP_USING_UART2
// {
// static struct rt_serial_device serial2;
// static struct device_uart uart2;
// serial = &serial2;
// uart = &uart2;
// serial->ops = &_uart_ops;
// serial->config = config;
// serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
// uart->hw_base = UART2_BASE_ADDR;
// uart->irqno = IRQN_UART2_INTERRUPT;
// _uart_init(UART_DEVICE_2);
// rt_hw_serial_register(serial,
// "uart2",
// RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
// uart);
// }
// #endif
// #ifdef BSP_USING_UART3
// {
// static struct rt_serial_device serial3;
// static struct device_uart uart3;
// serial = &serial3;
// uart = &uart3;
// serial->ops = &_uart_ops;
// serial->config = config;
// serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
// uart->hw_base = UART3_BASE_ADDR;
// uart->irqno = IRQN_UART3_INTERRUPT;
// _uart_init(UART_DEVICE_3);
// rt_hw_serial_register(serial,
// "uart3",
// RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
// uart);
// }
// #endif
// Ch438InitDefault();
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_ch438_init);

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Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.h Executable file
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#ifndef __CH438_H_
#define __CH438_H_
#include "board.h"
#define BUFFSIZE 255
/******************************************************************************************/
/* CH438serial port0 register address */
#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */
#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */
#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */
#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */
#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */
#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */
#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */
#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */
#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */
#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */
#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port1 register address */
#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */
#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */
#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */
#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */
#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */
#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */
#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */
#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */
#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */
#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */
#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port2 register address */
#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */
#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */
#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */
#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */
#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */
#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */
#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */
#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */
#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */
#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */
#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port3 register address */
#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */
#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */
#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */
#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */
#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */
#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */
#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */
#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */
#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */
#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */
#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port4 register address */
#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */
#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */
#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */
#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */
#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */
#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */
#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */
#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */
#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */
#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */
#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port5 register address */
#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */
#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */
#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */
#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */
#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */
#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */
#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */
#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */
#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */
#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */
#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port6 register address */
#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */
#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */
#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */
#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */
#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */
#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */
#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */
#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */
#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */
#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */
#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port7 register address */
#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */
#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */
#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */
#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */
#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */
#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */
#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */
#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */
#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */
#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */
#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */
#define REG_SSR_ADDR 0x4F /* pecial status register address */
/* IER register bit */
#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */
#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */
#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */
#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */
#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */
#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */
#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */
/* IIR register bit */
#define BIT_IIR_FIFOENS1 0x80
#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */
/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted,
1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */
#define BIT_IIR_IID3 0x08
#define BIT_IIR_IID2 0x04
#define BIT_IIR_IID1 0x02
#define BIT_IIR_NOINT 0x01
/* FCR register bit */
/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */
#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */
#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */
#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */
/* LCR register bit */
#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */
#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/
/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */
#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */
#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */
#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */
/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */
#define BIT_LCR_WORDSZ0 0x01
/* MCR register bit */
#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */
#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */
#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */
#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */
#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */
#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */
/* LSR register bit */
#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */
#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */
#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/
#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/
#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */
#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */
#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */
#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */
/* MSR register bit */
#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */
#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */
#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */
#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */
#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */
#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */
#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */
#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */
/* Interrupt status code */
#define INT_NOINT 0x01 /* There is no interruption */
#define INT_THR_EMPTY 0x02 /* THR empty interruption */
#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */
#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */
#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */
#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */
#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */
#define Fpclk 1843200 /* Define the internal clock frequency */
void CH438_INIT(void);
void CH438_PORT_INIT( rt_uint8_t ext_uart_no,rt_uint32_t BaudRate );
rt_uint8_t ReadCH438Data( rt_uint8_t addr );
void CH438UARTSend( rt_uint8_t ext_uart_no,rt_uint8_t *Data, rt_uint8_t Num );
rt_uint8_t CH438UARTRcv( rt_uint8_t ext_uart_no, rt_uint8_t* buf );
void set_485_input(rt_uint8_t ch_no);
void set_485_output(rt_uint8_t ch_no);
static void CH438_set_output(void);
static void CH438_set_input(void);
static void WriteCH438Data( rt_uint8_t addr, rt_uint8_t dat);
static void WriteCH438Block( rt_uint8_t mAddr, rt_uint8_t mLen, rt_uint8_t *mBuf );
#endif

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Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/dmalock.c Normal file
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/* Copyright Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <rtthread.h>
#include "dmalock.h"
struct dmac_host
{
struct rt_semaphore sem;
struct rt_mutex mutex;
uint8_t channel_used[DMAC_CHANNEL_COUNT];
char *channel_name[DMAC_CHANNEL_COUNT];
};
static struct dmac_host _dmac_host;
void dmalock_init(void)
{
rt_sem_init(&_dmac_host.sem, "dma_sem", DMAC_CHANNEL_COUNT, RT_IPC_FLAG_FIFO);
rt_mutex_init(&_dmac_host.mutex, "dma_mutex", RT_IPC_FLAG_FIFO);
for (int i = 0; i < DMAC_CHANNEL_COUNT; i++)
{
_dmac_host.channel_used[i] = 0;
_dmac_host.channel_name[i] = NULL;
}
}
int _dmalock_sync_take(dmac_channel_number_t *chn, int timeout_ms, const char *name)
{
rt_err_t result;
*chn = DMAC_CHANNEL_MAX;
result = rt_sem_take(&_dmac_host.sem, timeout_ms);
if (result == RT_EOK)
{
rt_mutex_take(&_dmac_host.mutex, RT_WAITING_FOREVER);
for (int i = 0; i < DMAC_CHANNEL_COUNT; i++)
{
if (_dmac_host.channel_used[i] == 0)
{
_dmac_host.channel_used[i] = 1;
_dmac_host.channel_name[i] = name;
*chn = i;
break;
}
}
rt_mutex_release(&_dmac_host.mutex);
}
return result;
}
void dmalock_release(dmac_channel_number_t chn)
{
if (chn >= DMAC_CHANNEL_MAX)
return;
_dmac_host.channel_name[chn] = NULL;
_dmac_host.channel_used[chn] = 0;
rt_sem_release(&_dmac_host.sem);
}
static void dma_ch_info(int argc, char **argv)
{
uint32_t cnt = 0;
for (int i = 0; i < DMAC_CHANNEL_COUNT; i++)
{
if (_dmac_host.channel_used[i] != 0)
{
rt_kprintf("dma_ch%d is using by func [%s]\n", i, _dmac_host.channel_name[i]);
cnt++;
}
}
if(cnt == 0)
rt_kprintf(" no dma_ch is using.\n");
}
MSH_CMD_EXPORT(dma_ch_info, list dma channel informationn.);

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#ifndef __DMALOCK_H
#define __DMALOCK_H
#include <stdint.h>
#include <rtdef.h>
#include <dmac.h>
#define dmalock_sync_take(x,y) _dmalock_sync_take(x, y, __func__)
void dmalock_init(void);
int _dmalock_sync_take(dmac_channel_number_t *chn, int timeout_ms, const char *name);
void dmalock_release(dmac_channel_number_t chn);
#endif

167
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_dvp.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-27 tianchunyu the first version
*/
#include <rtthread.h>
#include <stdio.h>
#ifdef BSP_USING_DVP
#include <drv_dvp.h>
#define DRV_DEBUG
#define LOG_TAG "drv.dvp"
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
static struct kendryte_dvp rt_dvp = {0};
static void (*dvp_irq_callback)(void) = NULL;
/*
the camera starts transfering photos
*/
static int on_irq_dvp(void* ctx)
{
if (dvp_get_interrupt(DVP_STS_FRAME_FINISH))
{
rt_dvp_stop();
dvp_clear_interrupt(DVP_STS_FRAME_FINISH);
(*dvp_irq_callback)();
}
return 0;
}
void rt_dvp_start(uint32_t pData, uint32_t Length)
{
dvp_set_display_addr(pData);
dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 1);
dvp_start_convert();
}
/*
the camera stops transfering photos
*/
void rt_dvp_stop(void)
{
dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 0);
}
static rt_err_t rt_dvp_init(rt_device_t dev)
{
//sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL);
RT_ASSERT(dev != RT_NULL);
rt_err_t result = RT_EOK;
/* Init DVP IO map and function settings io pin serial number depends on schematic diagram
initialize io in io_config_init function*/
/*ov2640 dvp interface initialize*/
dvp_init(8);
dvp_set_xclk_rate(24000000);
dvp_enable_burst();
dvp_set_output_enable(0, 1);
dvp_set_output_enable(1, 1);
dvp_set_image_format(DVP_CFG_RGB_FORMAT);////////////////
dvp_set_image_size(320, 240); // default
dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 0);
dvp_disable_auto();
plic_set_priority(IRQN_DVP_INTERRUPT, 1);
plic_irq_register(IRQN_DVP_INTERRUPT, on_irq_dvp, NULL);
plic_irq_enable(IRQN_DVP_INTERRUPT);
dvp_clear_interrupt(DVP_STS_FRAME_FINISH);
LOG_I("dvp initialize success");
return result;
}
static rt_err_t rt_dvp_open(rt_device_t dev, rt_uint16_t oflag)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_dvp_close(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_dvp_control(rt_device_t dev, int cmd, void *args)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_size_t rt_dvp_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_size_t rt_dvp_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
rt_err_t rt_set_irq_dvp_callback_hander(void (*p)(void))
{
if(NULL == p)
{
LOG_E("set irq dcmi callback hander is NULL");
return RT_ERROR;
}
dvp_irq_callback = p;
return RT_EOK;
}
int kendryte_dvp_init(void)
{
int ret = 0;
rt_device_t dvp_dev = RT_NULL;
rt_dvp.dev.parent.type = RT_Device_Class_Miscellaneous;
rt_dvp.dev.parent.init = rt_dvp_init;
rt_dvp.dev.parent.open = rt_dvp_open;
rt_dvp.dev.parent.close = rt_dvp_close;
rt_dvp.dev.parent.read = rt_dvp_read;
rt_dvp.dev.parent.write = rt_dvp_write;
rt_dvp.dev.parent.control = rt_dvp_control;
rt_dvp.dev.parent.user_data = RT_NULL;
ret = rt_device_register(&rt_dvp.dev.parent, "dvp", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
if(ret != RT_EOK)
{
LOG_E("dvp register fail!!\n\r");
return -RT_ERROR;
}
LOG_I("dvp register successfully");
dvp_dev = rt_device_find("dvp");
if (dvp_dev == RT_NULL)
{
LOG_E("can't find dvp device!");
return RT_ERROR;
}
ret = rt_device_open(dvp_dev, RT_DEVICE_FLAG_RDWR);
if(ret != RT_EOK)
{
LOG_E("can't open dvp device!");
return RT_ERROR;
}
LOG_I("dvp open successfully");
return RT_EOK;
}
INIT_BOARD_EXPORT(kendryte_dvp_init);
#endif

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-27 tianchunyu the first version
*/
#ifndef __DRV_DVP_H__
#define __DRV_DVP_H__
#include <dvp.h>
#include <fpioa.h>
#include <sysctl.h>
#include <plic.h>
#include <sysctl.h>
#ifdef __cplusplus
extern "C" {
#endif
struct rt_dvp_device
{
struct rt_device parent;
};
struct kendryte_dvp
{
struct rt_dvp_device dev;
};
extern void rt_dvp_start(uint32_t pData, uint32_t Length);
extern void rt_dvp_stop(void);
extern rt_err_t rt_set_irq_dvp_callback_hander(void (*p)(void));
#ifdef __cplusplus
}
#endif
#endif

267
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_gpio.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <fpioa.h>
#include <gpiohs.h>
#include "drv_gpio.h"
#include "drv_io_config.h"
#include <plic.h>
#include <rthw.h>
#include <utils.h>
#include <string.h>
#define DBG_ENABLE
#define DBG_TAG "PIN"
#define DBG_LVL DBG_WARNING
#define DBG_COLOR
#include <rtdbg.h>
#define FUNC_GPIOHS(n) (FUNC_GPIOHS0 + n)
static short pin_alloc_table[FPIOA_NUM_IO];
static uint32_t free_pin = 0;
static int alloc_pin_channel(rt_base_t pin_index)
{
if(free_pin == 32)
{
LOG_E("no free gpiohs channel to alloc");
return -1;
}
if(pin_alloc_table[pin_index] != -1)
{
LOG_W("already alloc gpiohs channel for pin %d", pin_index);
return pin_alloc_table[pin_index];
}
pin_alloc_table[pin_index] = free_pin;
free_pin++;
fpioa_set_function(pin_index, FUNC_GPIOHS(pin_alloc_table[pin_index]));
return pin_alloc_table[pin_index];
}
int get_pin_channel(rt_base_t pin_index)
{
return pin_alloc_table[pin_index];
}
static void free_pin_channel(rt_base_t pin_index)
{
if(pin_alloc_table[pin_index] == -1)
{
LOG_W("free error:not alloc gpiohs channel for pin %d", pin_index);
return;
}
pin_alloc_table[pin_index] = -1;
free_pin--;
}
static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
pin_channel = alloc_pin_channel(pin);
if(pin_channel == -1)
{
return;
}
}
switch (mode)
{
case PIN_MODE_OUTPUT:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_OUTPUT);
break;
case PIN_MODE_INPUT:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT);
break;
case PIN_MODE_INPUT_PULLUP:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT_PULL_UP);
break;
case PIN_MODE_INPUT_PULLDOWN:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT_PULL_DOWN);
break;
default:
LOG_E("Not support mode %d", mode);
break;
}
}
static void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return;
}
gpiohs_set_pin(pin_channel, value == PIN_HIGH ? GPIO_PV_HIGH : GPIO_PV_LOW);
}
static int drv_pin_read(struct rt_device *device, rt_base_t pin)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -1;
}
return gpiohs_get_pin(pin_channel) == GPIO_PV_HIGH ? PIN_HIGH : PIN_LOW;
}
static struct
{
void (*hdr)(void *args);
void* args;
gpio_pin_edge_t edge;
} irq_table[32];
static void pin_irq(int vector, void *param)
{
int pin_channel = vector - IRQN_GPIOHS0_INTERRUPT;
if(irq_table[pin_channel].edge & GPIO_PE_FALLING)
{
set_gpio_bit(gpiohs->fall_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->fall_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->fall_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].edge & GPIO_PE_RISING)
{
set_gpio_bit(gpiohs->rise_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->rise_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->rise_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].edge & GPIO_PE_LOW)
{
set_gpio_bit(gpiohs->low_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->low_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->low_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].edge & GPIO_PE_HIGH)
{
set_gpio_bit(gpiohs->high_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->high_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->high_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].hdr)
{
irq_table[pin_channel].hdr(irq_table[pin_channel].args);
}
}
static rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
int pin_channel = get_pin_channel(pin);
char irq_name[10];
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -RT_ERROR;
}
irq_table[pin_channel].hdr = hdr;
irq_table[pin_channel].args = args;
switch (mode)
{
case PIN_IRQ_MODE_RISING:
irq_table[pin_channel].edge = GPIO_PE_RISING;
break;
case PIN_IRQ_MODE_FALLING:
irq_table[pin_channel].edge = GPIO_PE_FALLING;
break;
case PIN_IRQ_MODE_RISING_FALLING:
irq_table[pin_channel].edge = GPIO_PE_BOTH;
break;
case PIN_IRQ_MODE_HIGH_LEVEL:
irq_table[pin_channel].edge = GPIO_PE_LOW;
break;
case PIN_IRQ_MODE_LOW_LEVEL:
irq_table[pin_channel].edge = GPIO_PE_HIGH;
break;
default:
break;
}
gpiohs_set_pin_edge(pin_channel, irq_table[pin_channel].edge);
rt_snprintf(irq_name, sizeof irq_name, "pin%d", pin);
rt_hw_interrupt_install(IRQN_GPIOHS0_INTERRUPT + pin_channel, pin_irq, RT_NULL, irq_name);
return RT_EOK;
}
static rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
rt_err_t ret = RT_EOK;
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -RT_ERROR;
}
irq_table[pin_channel].hdr = RT_NULL;
irq_table[pin_channel].args = RT_NULL;
return ret;
}
static rt_err_t drv_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -RT_ERROR;
}
if(enabled)
{
rt_hw_interrupt_umask(IRQN_GPIOHS0_INTERRUPT + pin_channel);
}
else
{
rt_hw_interrupt_mask(IRQN_GPIOHS0_INTERRUPT + pin_channel);
}
return RT_EOK;
}
const static struct rt_pin_ops drv_pin_ops =
{
drv_pin_mode,
drv_pin_write,
drv_pin_read,
drv_pin_attach_irq,
drv_pin_detach_irq,
drv_pin_irq_enable
};
int rt_hw_pin_init(void)
{
rt_err_t ret = RT_EOK;
memset(pin_alloc_table, 0xff, sizeof pin_alloc_table);
free_pin = GPIO_ALLOC_START;
ret = rt_device_pin_register("pin", &drv_pin_ops, RT_NULL);
return ret;
}
INIT_BOARD_EXPORT(rt_hw_pin_init);

16
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_gpio.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#ifndef DRV_GPIO_H__
#define DRV_GPIO_H__
int rt_hw_pin_init(void);
#endif

27
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_interrupt.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#include <plic.h>
void plic_irq_handle(plic_irq_t irq)
{
plic_instance_t (*plic_instance)[IRQN_MAX] = plic_get_instance();
if (plic_instance[0][irq].callback)
{
plic_instance[0][irq].callback(
plic_instance[0][irq].ctx);
}
else if (plic_instance[1][irq].callback)
{
plic_instance[1][irq].callback(
plic_instance[1][irq].ctx);
}
}

233
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#include <rtthread.h>
#include <fpioa.h>
#include <drv_io_config.h>
#include <sysctl.h>
#define HS_GPIO(n) (FUNC_GPIOHS0 + n)
#define IOCONFIG(pin,func) {pin, func, #func}
static struct io_config
{
int io_num;
fpioa_function_t func;
const char * func_name;
} io_config[] =
{
#ifdef BSP_USING_LCD
IOCONFIG(BSP_LCD_CS_PIN, FUNC_SPI0_SS0), /* LCD CS PIN */
IOCONFIG(BSP_LCD_WR_PIN, FUNC_SPI0_SCLK), /* LCD WR PIN */
IOCONFIG(BSP_LCD_DC_PIN, HS_GPIO(LCD_DC_PIN)), /* LCD DC PIN */
#if BSP_LCD_RST_PIN >= 0
IOCONFIG(BSP_LCD_RST_PIN, HS_GPIO(LCD_RST_PIN)), /* LCD RESET PIN */
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
IOCONFIG(BSP_LCD_BACKLIGHT_PIN, HS_GPIO(LCD_BACKLIGHT_PIN)), /* LCD BACKLIGHT PIN */
#endif
#endif
#ifdef BSP_USING_DVP
IOCONFIG(BSP_DVP_SCCB_SDA_PIN, FUNC_SCCB_SDA),
IOCONFIG(BSP_DVP_SCCB_SCLK_PIN, FUNC_SCCB_SCLK),
IOCONFIG(BSP_DVP_CMOS_RST_PIN, FUNC_CMOS_RST),
IOCONFIG(BSP_DVP_CMOS_VSYNC_PIN, FUNC_CMOS_VSYNC),
IOCONFIG(BSP_DVP_CMOS_PWDN_PIN, FUNC_CMOS_PWDN),
IOCONFIG(BSP_DVP_CMOS_XCLK_PIN, FUNC_CMOS_XCLK),
IOCONFIG(BSP_DVP_CMOS_PCLK_PIN, FUNC_CMOS_PCLK),
IOCONFIG(BSP_DVP_CMOS_HREF_PIN, FUNC_CMOS_HREF),
#endif
#ifdef BSP_USING_SPI1
IOCONFIG(BSP_SPI1_CLK_PIN, FUNC_SPI1_SCLK),
IOCONFIG(BSP_SPI1_D0_PIN, FUNC_SPI1_D0),
IOCONFIG(BSP_SPI1_D1_PIN, FUNC_SPI1_D1),
#ifdef BSP_USING_SPI1_AS_QSPI
IOCONFIG(BSP_SPI1_D2_PIN, FUNC_SPI1_D2),
IOCONFIG(BSP_SPI1_D3_PIN, FUNC_SPI1_D3),
#endif
#ifdef BSP_SPI1_USING_SS0
IOCONFIG(BSP_SPI1_SS0_PIN, HS_GPIO(SPI1_CS0_PIN)),
#endif
#ifdef BSP_SPI1_USING_SS1
IOCONFIG(BSP_SPI1_SS1_PIN, HS_GPIO(SPI1_CS1_PIN)),
#endif
#ifdef BSP_SPI1_USING_SS2
IOCONFIG(BSP_SPI1_SS2_PIN, HS_GPIO(SPI1_CS2_PIN)),
#endif
#ifdef BSP_SPI1_USING_SS3
IOCONFIG(BSP_SPI1_SS3_PIN, HS_GPIO(SPI1_CS3_PIN)),
#endif
#endif
#ifdef BSP_USING_UART1
IOCONFIG(BSP_UART1_TXD_PIN, FUNC_UART1_TX),
IOCONFIG(BSP_UART1_RXD_PIN, FUNC_UART1_RX),
#if BSP_UART1_RTS_PIN >= 0
IOCONFIG(BSP_UART1_RTS_PIN, FUNC_UART1_RTS),
#endif
#if BSP_UART1_CTS_PIN >= 0
IOCONFIG(BSP_UART1_CTS_PIN, FUNC_UART1_CTS),
#endif
#endif
#ifdef BSP_USING_UART2
IOCONFIG(BSP_UART2_TXD_PIN, FUNC_UART2_TX),
IOCONFIG(BSP_UART2_RXD_PIN, FUNC_UART2_RX),
#if BSP_UART2_RTS_PIN >= 0
IOCONFIG(BSP_UART2_RTS_PIN, FUNC_UART2_RTS),
#endif
#if BSP_UART2_CTS_PIN >= 0
IOCONFIG(BSP_UART2_CTS_PIN, FUNC_UART2_CTS),
#endif
#endif
#ifdef BSP_USING_UART3
IOCONFIG(BSP_UART3_TXD_PIN, FUNC_UART3_TX),
IOCONFIG(BSP_UART3_RXD_PIN, FUNC_UART3_RX),
#if BSP_UART3_RTS_PIN >= 0
IOCONFIG(BSP_UART3_RTS_PIN, FUNC_UART3_RTS),
#endif
#if BSP_UART3_CTS_PIN >= 0
IOCONFIG(BSP_UART3_CTS_PIN, FUNC_UART3_CTS),
#endif
#endif
#ifdef BSP_USING_I2C0
IOCONFIG(BSP_I2C0_SCL_PIN, FUNC_I2C0_SCLK),
IOCONFIG(BSP_I2C0_SDA_PIN, FUNC_I2C0_SDA),
#endif
#ifdef BSP_USING_I2C1
IOCONFIG(BSP_I2C1_SCL_PIN, FUNC_I2C1_SCLK),
IOCONFIG(BSP_I2C1_SDA_PIN, FUNC_I2C1_SDA),
#endif
#ifdef BSP_USING_I2C2
IOCONFIG(BSP_I2C2_SCL_PIN, FUNC_I2C2_SCLK),
IOCONFIG(BSP_I2C2_SDA_PIN, FUNC_I2C2_SDA),
#endif
#ifdef BSP_USING_I2S0
IOCONFIG(BSP_I2S0_OUT_D1_PIN, FUNC_I2S0_OUT_D1),
IOCONFIG(BSP_I2S0_WS_PIN, FUNC_I2S0_WS),
IOCONFIG(BSP_I2S0_SCLK_PIN, FUNC_I2S0_SCLK),
#endif
#ifdef BSP_USING_I2S1
IOCONFIG(BSP_I2S1_IN_D0_PIN, FUNC_I2S1_IN_D0),
IOCONFIG(BSP_I2S1_WS_PIN, FUNC_I2S1_WS),
IOCONFIG(BSP_I2S1_SCLK_PIN, FUNC_I2S1_SCLK),
#endif
#ifdef BSP_USING_I2S2
IOCONFIG(BSP_I2S2_OUT_D1_PIN, FUNC_I2S2_OUT_D1),
IOCONFIG(BSP_I2S2_WS_PIN, FUNC_I2S2_WS),
IOCONFIG(BSP_I2S2_SCLK_PIN, FUNC_I2S2_SCLK),
#endif
#ifdef BSP_PWM_CHN0_ENABLE
IOCONFIG(BSP_PWM_CHN0_PIN, FUNC_TIMER2_TOGGLE1),
#endif
#ifdef BSP_PWM_CHN1_ENABLE
IOCONFIG(BSP_PWM_CHN1_PIN, FUNC_TIMER2_TOGGLE2),
#endif
#ifdef BSP_PWM_CHN2_ENABLE
IOCONFIG(BSP_PWM_CHN2_PIN, FUNC_TIMER2_TOGGLE3),
#endif
#ifdef BSP_PWM_CHN3_ENABLE
IOCONFIG(BSP_PWM_CHN3_PIN, FUNC_TIMER2_TOGGLE4),
#endif
IOCONFIG(BSP_CH438_ALE_PIN, HS_GPIO(FPIOA_CH438_ALE)),
IOCONFIG(BSP_CH438_NWR_PIN, HS_GPIO(FPIOA_CH438_NWR)),
IOCONFIG(BSP_CH438_NRD_PIN, HS_GPIO(FPIOA_CH438_NRD)),
IOCONFIG(BSP_CH438_INT_PIN, HS_GPIO(FPIOA_CH438_INT)),
IOCONFIG(BSP_CH438_D0_PIN, HS_GPIO(FPIOA_CH438_D0)),
IOCONFIG(BSP_CH438_D1_PIN, HS_GPIO(FPIOA_CH438_D1)),
IOCONFIG(BSP_CH438_D2_PIN, HS_GPIO(FPIOA_CH438_D2)),
IOCONFIG(BSP_CH438_D3_PIN, HS_GPIO(FPIOA_CH438_D3)),
IOCONFIG(BSP_CH438_D4_PIN, HS_GPIO(FPIOA_CH438_D4)),
IOCONFIG(BSP_CH438_D5_PIN, HS_GPIO(FPIOA_CH438_D5)),
IOCONFIG(BSP_CH438_D6_PIN, HS_GPIO(FPIOA_CH438_D6)),
IOCONFIG(BSP_CH438_D7_PIN, HS_GPIO(FPIOA_CH438_D7)),
};
static int print_io_config()
{
int i;
rt_kprintf("IO Configuration Table\n");
rt_kprintf("┌───────┬────────────────────────┐\n");
rt_kprintf("│Pin │Function │\n");
rt_kprintf("├───────┼────────────────────────┤\n");
for(i = 0; i < sizeof io_config / sizeof io_config[0]; i++)
{
rt_kprintf("│%-2d │%-24.24s│\n", io_config[i].io_num, io_config[i].func_name);
}
rt_kprintf("└───────┴────────────────────────┘\n");
return 0;
}
MSH_CMD_EXPORT_ALIAS(print_io_config, io, print io config);
int io_config_init(void)
{
int count = sizeof(io_config) / sizeof(io_config[0]);
int i;
/* IO GroupA Power Supply Setting */
#if defined(BSP_GROUPA_POWER_SUPPLY_3V3)
sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V33);
#else
sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18);
#endif
/* IO GroupB Power Supply Setting */
#if defined(BSP_GROUPB_POWER_SUPPLY_3V3)
sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK5, SYSCTL_POWER_V33);
#else
sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK5, SYSCTL_POWER_V18);
#endif
/* IO GroupC Power Supply Setting */
#if defined(BSP_GROUPC_POWER_SUPPLY_3V3)
sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V33);
#else
sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V18);
#endif
for(i = 0; i < count; i++)
{
fpioa_set_function(io_config[i].io_num, io_config[i].func);
}
#if defined(BSP_USING_DVP) || defined(BSP_USING_LCD)
sysctl_set_spi0_dvp_data(1);
sysctl_clock_enable(SYSCTL_CLOCK_AI);
#endif
}
int io_config_used(int io_num)
{
int count = sizeof(io_config) / sizeof(io_config[0]);
int i;
for(i = 0; i < count; i++)
{
if (io_config[i].io_num == io_num)
break;
}
return (i < count);
}

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#ifndef __DRV_IO_CONFIG_H__
#define __DRV_IO_CONFIG_H__
#include <rtconfig.h>
enum HS_GPIO_CONFIG
{
#ifdef BSP_USING_LCD
LCD_DC_PIN = 0, /* LCD DC PIN */
#if BSP_LCD_RST_PIN >= 0
LCD_RST_PIN,
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
LCD_BACKLIGHT_PIN,
#endif
#endif
#ifdef BSP_SPI1_USING_SS0
SPI1_CS0_PIN,
#endif
#ifdef BSP_SPI1_USING_SS1
SPI1_CS1_PIN,
#endif
#ifdef BSP_SPI1_USING_SS2
SPI1_CS2_PIN,
#endif
#ifdef BSP_SPI1_USING_SS3
SPI1_CS3_PIN,
#endif
#ifdef BSP_USING_BRIDGE
SPI2_INT_PIN,
SPI2_READY_PIN,
#endif
GPIO_ALLOC_START /* index of gpio driver start */
};
#define FPIOA_CH438_ALE 11
#define FPIOA_CH438_NWR 12
#define FPIOA_CH438_NRD 13
#define FPIOA_CH438_D0 14
#define FPIOA_CH438_D1 15
#define FPIOA_CH438_D2 16
#define FPIOA_CH438_D3 17
#define FPIOA_CH438_D4 18
#define FPIOA_CH438_D5 19
#define FPIOA_CH438_D6 20
#define FPIOA_CH438_D7 21
#define FPIOA_CH438_INT 22
#define FPIOA_485_DIR 23
//PIN.define
#define BSP_CH438_ALE_PIN 23
#define BSP_CH438_NWR_PIN 24
#define BSP_CH438_NRD_PIN 25
#define BSP_CH438_D0_PIN 27
#define BSP_CH438_D1_PIN 28
#define BSP_CH438_D2_PIN 29
#define BSP_CH438_D3_PIN 30
#define BSP_CH438_D4_PIN 31
#define BSP_CH438_D5_PIN 32
#define BSP_CH438_D6_PIN 33
#define BSP_CH438_D7_PIN 34
#define BSP_CH438_INT_PIN 35
extern int io_config_init(void);
#endif

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-12 ZYH first version
*/
#include <rtthread.h>
#ifdef BSP_USING_LCD
#include <drv_lcd.h>
#define DBG_TAG "LCD"
#define DBG_LVL DBG_WARNING
#include <rtdbg.h>
#define NO_OPERATION 0x00
#define SOFTWARE_RESET 0x01
#define READ_ID 0x04
#define READ_STATUS 0x09
#define READ_POWER_MODE 0x0A
#define READ_MADCTL 0x0B
#define READ_PIXEL_FORMAT 0x0C
#define READ_IMAGE_FORMAT 0x0D
#define READ_SIGNAL_MODE 0x0E
#define READ_SELT_DIAG_RESULT 0x0F
#define SLEEP_ON 0x10
#define SLEEP_OFF 0x11
#define PARTIAL_DISPALY_ON 0x12
#define NORMAL_DISPALY_ON 0x13
#define INVERSION_DISPALY_OFF 0x20
#define INVERSION_DISPALY_ON 0x21
#define GAMMA_SET 0x26
#define DISPALY_OFF 0x28
#define DISPALY_ON 0x29
#define HORIZONTAL_ADDRESS_SET 0x2A
#define VERTICAL_ADDRESS_SET 0x2B
#define MEMORY_WRITE 0x2C
#define COLOR_SET 0x2D
#define MEMORY_READ 0x2E
#define PARTIAL_AREA 0x30
#define VERTICAL_SCROL_DEFINE 0x33
#define TEAR_EFFECT_LINE_OFF 0x34
#define TEAR_EFFECT_LINE_ON 0x35
#define MEMORY_ACCESS_CTL 0x36
#define VERTICAL_SCROL_S_ADD 0x37
#define IDLE_MODE_OFF 0x38
#define IDLE_MODE_ON 0x39
#define PIXEL_FORMAT_SET 0x3A
#define WRITE_MEMORY_CONTINUE 0x3C
#define READ_MEMORY_CONTINUE 0x3E
#define SET_TEAR_SCANLINE 0x44
#define GET_SCANLINE 0x45
#define WRITE_BRIGHTNESS 0x51
#define READ_BRIGHTNESS 0x52
#define WRITE_CTRL_DISPALY 0x53
#define READ_CTRL_DISPALY 0x54
#define WRITE_BRIGHTNESS_CTL 0x55
#define READ_BRIGHTNESS_CTL 0x56
#define WRITE_MIN_BRIGHTNESS 0x5E
#define READ_MIN_BRIGHTNESS 0x5F
#define READ_ID1 0xDA
#define READ_ID2 0xDB
#define READ_ID3 0xDC
#define RGB_IF_SIGNAL_CTL 0xB0
#define NORMAL_FRAME_CTL 0xB1
#define IDLE_FRAME_CTL 0xB2
#define PARTIAL_FRAME_CTL 0xB3
#define INVERSION_CTL 0xB4
#define BLANK_PORCH_CTL 0xB5
#define DISPALY_FUNCTION_CTL 0xB6
#define ENTRY_MODE_SET 0xB7
#define BACKLIGHT_CTL1 0xB8
#define BACKLIGHT_CTL2 0xB9
#define BACKLIGHT_CTL3 0xBA
#define BACKLIGHT_CTL4 0xBB
#define BACKLIGHT_CTL5 0xBC
#define BACKLIGHT_CTL7 0xBE
#define BACKLIGHT_CTL8 0xBF
#define POWER_CTL1 0xC0
#define POWER_CTL2 0xC1
#define VCOM_CTL1 0xC5
#define VCOM_CTL2 0xC7
#define NV_MEMORY_WRITE 0xD0
#define NV_MEMORY_PROTECT_KEY 0xD1
#define NV_MEMORY_STATUS_READ 0xD2
#define READ_ID4 0xD3
#define POSITIVE_GAMMA_CORRECT 0xE0
#define NEGATIVE_GAMMA_CORRECT 0xE1
#define DIGITAL_GAMMA_CTL1 0xE2
#define DIGITAL_GAMMA_CTL2 0xE3
#define INTERFACE_CTL 0xF6
#define LCD_SPI_CHANNEL SPI_DEVICE_0
#define LCD_SPI_CHIP_SELECT SPI_CHIP_SELECT_0
#if defined(BSP_BOARD_K210_OPENMV_TEST)
#define LCD_SCAN_DIR DIR_YX_LRUD
#elif defined(BSP_BOARD_KD233)
#define LCD_SCAN_DIR (DIR_YX_RLUD | 0x08)
#elif defined(BSP_BOARD_USER)
/*user define.*/
#define LCD_SCAN_DIR DIR_YX_RLDU
#endif
static struct lcd_8080_device _lcddev;
static void drv_lcd_cmd(lcd_8080_device_t lcd, rt_uint8_t cmd)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_LOW);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, &cmd, 1, SPI_TRANS_CHAR);
}
static void drv_lcd_data_byte(lcd_8080_device_t lcd, rt_uint8_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_CHAR);
}
void drv_lcd_data_half_word(lcd_8080_device_t lcd, rt_uint16_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 16, 0);
spi_init_non_standard(lcd->spi_channel, 16 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_SHORT);
}
void drv_lcd_data_word(lcd_8080_device_t lcd, rt_uint32_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0);
spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_INT);
}
static void drv_lcd_hw_init(lcd_8080_device_t lcd)
{
#if BSP_LCD_RST_PIN >= 0
{
gpiohs_set_drive_mode(lcd->rst_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(lcd->rst_pin, GPIO_PV_LOW);
rt_thread_mdelay(20);
gpiohs_set_pin(lcd->rst_pin, GPIO_PV_HIGH);
rt_thread_mdelay(20);
}
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
{
gpiohs_set_drive_mode(lcd->backlight_pin, GPIO_DM_OUTPUT);
#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#else
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#endif
}
#endif
gpiohs_set_drive_mode(lcd->dc_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_set_clk_rate(lcd->spi_channel, BSP_LCD_CLK_FREQ);
}
static void drv_lcd_set_direction(lcd_8080_device_t lcd, lcd_dir_t dir)
{
if (dir & DIR_XY_MASK)
{
lcd->lcd_info.width = BSP_LCD_Y_MAX;
lcd->lcd_info.height = BSP_LCD_X_MAX;
}
else
{
lcd->lcd_info.width = BSP_LCD_X_MAX;
lcd->lcd_info.height = BSP_LCD_Y_MAX;
}
rt_kprintf("lcd witdth %d,height %d \n",lcd->lcd_info.width,lcd->lcd_info.height);
drv_lcd_cmd(lcd, MEMORY_ACCESS_CTL);
drv_lcd_data_byte(lcd, (rt_uint8_t *)&dir, 1);
}
void drv_lcd_set_area(lcd_8080_device_t lcd, rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2)
{
rt_uint8_t data[4] = {0};
data[0] = (rt_uint8_t)(x1 >> 8);
data[1] = (rt_uint8_t)(x1);
data[2] = (rt_uint8_t)(x2 >> 8);
data[3] = (rt_uint8_t)(x2);
drv_lcd_cmd(lcd, HORIZONTAL_ADDRESS_SET);
drv_lcd_data_byte(lcd, data, 4);
data[0] = (rt_uint8_t)(y1 >> 8);
data[1] = (rt_uint8_t)(y1);
data[2] = (rt_uint8_t)(y2 >> 8);
data[3] = (rt_uint8_t)(y2);
drv_lcd_cmd(lcd, VERTICAL_ADDRESS_SET);
drv_lcd_data_byte(lcd, data, 4);
drv_lcd_cmd(lcd, MEMORY_WRITE);
}
static void drv_lcd_set_pixel(lcd_8080_device_t lcd, uint16_t x, uint16_t y, uint16_t color)
{
drv_lcd_set_area(lcd, x, y, x, y);
drv_lcd_data_half_word(lcd, &color, 1);
}
static void drv_lcd_clear(lcd_8080_device_t lcd, uint16_t color)
{
uint32_t data = ((uint32_t)color << 16) | (uint32_t)color;
drv_lcd_set_area(lcd, 0, 0, lcd->lcd_info.width - 1, lcd->lcd_info.height - 1);
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0);
spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_fill_data_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, (const uint32_t *)&data, lcd->lcd_info.width * lcd->lcd_info.height / 2);
}
static void rt_bitblt(rt_uint16_t * dest, int dest_segment, int dest_common, int dest_x, int dest_y, int width, int height,
rt_uint16_t *src, int src_segment, int src_common, int src_x, int src_y)
{
int sx0, sx1, sy0, sy1;
int dx0, dx1, dy0, dy1;
rt_uint16_t *buff_src;
rt_uint16_t *buff_dest;
int x, y;
if (width <= 0) {
return;
}
if (height <= 0) {
return;
}
sx0 = src_x;
sy0 = src_y;
sx1 = sx0 + width - 1;
sy1 = sy0 + height - 1;
dx0 = dest_x;
dy0 = dest_y;
dx1 = dx0 + width - 1;
dy1 = dy0 + height - 1;
if (sx0 < 0) {
dx0 -= sx0;
sx0 = 0;
}
if (sy0 < 0) {
dy0 -= sy0;
sy0 = 0;
}
if (sx1 >= src_segment) {
dx1 -= (sx1 - src_segment + 1);
sx1 = src_segment - 1;
}
if (sy1 >= src_common) {
dy1 -= (sy1 - src_common + 1);
sy1 = src_common - 1;
}
if (dx0 < 0) {
sx0 -= dx0;
dx0 = 0;
}
if (dy0 < 0) {
sy0 -= dy0;
dy0 = 0;
}
if (dx1 >= dest_segment) {
sx1 -= (dx1 - dest_segment + 1);
dx1 = dest_segment - 1;
}
if (dy1 >= dest_common) {
sy1 -= (dy1 - dest_common + 1);
dy1 = dest_common - 1;
}
if (sx1 < 0 || sx0 >= src_segment) {
return;
}
if (sy1 < 0 || sy0 >= src_common) {
return;
}
if (dx1 < 0 || dx0 >= dest_segment) {
return;
}
if (dy1 < 0 || dy0 >= dest_common) {
return;
}
if ((rt_ubase_t)dest < (rt_ubase_t)src) {
buff_src = src + (sy0 * src_segment) + sx0;
buff_dest = dest + (dy0 * dest_segment) + dx0;
for (y = sy0; y <= sy1; y++) {
src = buff_src;
dest = buff_dest;
for (x = sx0; x <= sx1; x++) {
*dest++ = *src++;
}
buff_src += src_segment;
buff_dest += dest_segment;
}
} else {
buff_src = src + (sy1 * src_segment) + sx1;
buff_dest = dest + (dy1 * dest_segment) + dx1;
for (y = sy1; y >= sy0; y--) {
src = buff_src;
dest = buff_dest;
for (x = sx1; x >= sx0; x--) {
*dest-- = *src--;
}
buff_src -= src_segment;
buff_dest -= dest_segment;
}
}
}
static void drv_lcd_rect_update(lcd_8080_device_t lcd, uint16_t x1, uint16_t y1, uint16_t width, uint16_t height)
{
static rt_uint16_t * rect_buffer = RT_NULL;
if(!rect_buffer)
{
rect_buffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64);
if(!rect_buffer)
{
return;
}
}
if(x1 == 0 && y1 == 0 && width == lcd->lcd_info.width && height == lcd->lcd_info.height)
{
drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1);
drv_lcd_data_half_word(lcd, (rt_uint32_t *)lcd->lcd_info.framebuffer, width * height);
}
else
{
rt_bitblt(rect_buffer, width, height, 0, 0, width, height,(rt_uint16_t *)lcd->lcd_info.framebuffer, lcd->lcd_info.width, lcd->lcd_info.height, x1, y1);
drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1);
drv_lcd_data_half_word(lcd, (rt_uint16_t *)rect_buffer, width * height);
}
}
static rt_err_t drv_lcd_init(rt_device_t dev)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd = (lcd_8080_device_t)dev;
rt_uint8_t data = 0;
if(!lcd)
{
return RT_ERROR;
}
drv_lcd_hw_init(lcd);
/* reset LCD */
drv_lcd_cmd(lcd, SOFTWARE_RESET);
rt_thread_mdelay(100);
/* Enter normal status */
drv_lcd_cmd(lcd, SLEEP_OFF);
rt_thread_mdelay(100);
/* pixel format rgb565 */
drv_lcd_cmd(lcd, PIXEL_FORMAT_SET);
data = 0x55;
drv_lcd_data_byte(lcd, &data, 1);
/* set direction */
drv_lcd_set_direction(lcd, LCD_SCAN_DIR);
lcd->lcd_info.framebuffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64);
RT_ASSERT(lcd->lcd_info.framebuffer);
uint16_t *framebuffer = (uint16_t *)(lcd->lcd_info.framebuffer);
for(uint32_t i=0; i<(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8))/2; i++) {
framebuffer[i] = BLACK;
}
/*display on*/
drv_lcd_cmd(lcd, DISPALY_ON);
/* set to black */
drv_lcd_clear(lcd, BLACK);
return ret;
}
static rt_err_t drv_lcd_open(rt_device_t dev, rt_uint16_t oflag)
{
/* Not need */
return RT_EOK;
}
static rt_err_t drv_lcd_close(rt_device_t dev)
{
/* Not need */
return RT_EOK;
}
static rt_size_t drv_lcd_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
/* Not need */
return 0;
}
static rt_size_t drv_lcd_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
/* Not need */
return 0;
}
static rt_err_t drv_lcd_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd = (lcd_8080_device_t)dev;
rt_base_t level;
struct rt_device_rect_info* rect_info = (struct rt_device_rect_info*)args;
RT_ASSERT(dev != RT_NULL);
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
if(!rect_info)
{
LOG_E("RTGRAPHIC_CTRL_RECT_UPDATE error args");
return -RT_ERROR;
}
drv_lcd_rect_update(lcd, rect_info->x, rect_info->y, rect_info->width, rect_info->height);
break;
#if BSP_LCD_BACKLIGHT_PIN >= 0
case RTGRAPHIC_CTRL_POWERON:
#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#else
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#endif
break;
case RTGRAPHIC_CTRL_POWEROFF:
#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#else
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#endif
break;
#endif /* BSP_LCD_BACKLIGHT_PIN >= 0 */
case RTGRAPHIC_CTRL_GET_INFO:
*(struct rt_device_graphic_info *)args = lcd->lcd_info;
break;
case RTGRAPHIC_CTRL_SET_MODE:
ret = -RT_ENOSYS;
break;
case RTGRAPHIC_CTRL_GET_EXT:
ret = -RT_ENOSYS;
break;
default:
LOG_E("drv_lcd_control cmd: %d", cmd);
break;
}
return ret;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops drv_lcd_ops =
{
drv_lcd_init,
drv_lcd_open,
drv_lcd_close,
drv_lcd_read,
drv_lcd_write,
drv_lcd_control
};
#endif
int rt_hw_lcd_init(void)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd_dev = &_lcddev;
lcd_dev->cs = SPI_CHIP_SELECT_0;
lcd_dev->dc_pin = LCD_DC_PIN;
#if BSP_LCD_RST_PIN >= 0
lcd_dev->rst_pin = LCD_RST_PIN;
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
lcd_dev->backlight_pin = LCD_BACKLIGHT_PIN;
#endif
dmalock_sync_take(&lcd_dev->dma_channel, RT_WAITING_FOREVER);
lcd_dev->spi_channel = SPI_DEVICE_0;
lcd_dev->lcd_info.bits_per_pixel = 16;
lcd_dev->lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
lcd_dev->parent.type = RT_Device_Class_Graphic;
lcd_dev->parent.rx_indicate = RT_NULL;
lcd_dev->parent.tx_complete = RT_NULL;
#ifdef RT_USING_DEVICE_OPS
lcd_dev->parent.ops = &drv_lcd_ops;
#else
lcd_dev->parent.init = drv_lcd_init;
lcd_dev->parent.open = drv_lcd_open;
lcd_dev->parent.close = drv_lcd_close;
lcd_dev->parent.read = drv_lcd_read;
lcd_dev->parent.write = drv_lcd_write;
lcd_dev->parent.control = drv_lcd_control;
#endif
lcd_dev->parent.user_data = RT_NULL;
ret = rt_device_register(&lcd_dev->parent, "lcd", RT_DEVICE_FLAG_RDWR);
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_lcd_init);
void lcd_set_direction(lcd_dir_t dir)
{
drv_lcd_set_direction(&_lcddev, dir);
}
#endif

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-07 ZYH first version
*/
#ifndef DRV_LCD_H__
#define DRV_LCD_H__
#include <rtdevice.h>
#include <board.h>
#include <gpiohs.h>
#include <spi.h>
#include <drv_io_config.h>
#include <rthw.h>
#include "dmalock.h"
//POINT_COLOR
#define WHITE 0xFFFF
#define BLACK 0x0000
#define BLUE 0x001F
#define BRED 0XF81F
#define GRED 0XFFE0
#define GBLUE 0X07FF
#define RED 0xF800
#define MAGENTA 0xF81F
#define GREEN 0x07E0
#define CYAN 0x7FFF
#define YELLOW 0xFFE0
#define BROWN 0XBC40
#define BRRED 0XFC07
#define GRAY 0X8430
#define GRAY175 0XAD75
#define GRAY151 0X94B2
#define GRAY187 0XBDD7
#define GRAY240 0XF79E
typedef enum _lcd_dir
{
DIR_XY_RLUD = 0x00,
DIR_YX_RLUD = 0x20,
DIR_XY_LRUD = 0x40,
DIR_YX_LRUD = 0x60,
DIR_XY_RLDU = 0x80,
DIR_YX_RLDU = 0xA0,
DIR_XY_LRDU = 0xC0,
DIR_YX_LRDU = 0xE0,
DIR_XY_MASK = 0x20,
DIR_MASK = 0xE0,
} lcd_dir_t;
typedef struct lcd_8080_device
{
struct rt_device parent;
struct rt_device_graphic_info lcd_info;
int spi_channel;
int cs;
int dc_pin;
#if BSP_LCD_RST_PIN >= 0
int rst_pin;
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
int backlight_pin;
#endif
int dma_channel;
} * lcd_8080_device_t;
int rt_hw_lcd_init(void);
void drv_lcd_set_area(lcd_8080_device_t lcd, rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2);
void drv_lcd_data_word(lcd_8080_device_t lcd, rt_uint32_t *data_buf, rt_uint32_t length);
void drv_lcd_data_half_word(lcd_8080_device_t lcd, rt_uint16_t *data_buf, rt_uint32_t length);
/* for mpy machine.lcd */
void lcd_display_on(void);
void lcd_display_off(void);
void lcd_clear(int color);
void lcd_draw_point_color(int x, int y, int color);
void lcd_show_string(int x, int y, int size, const char *data);
void lcd_draw_line(int x1, int y1, int x2, int y2);
void lcd_draw_rectangle(int x1, int y1, int x2, int y2);
void lcd_draw_circle(int x1, int y1, int r);
void lcd_set_color(int back, int fore);
void lcd_show_image(int x, int y, int length, int wide, const unsigned char *buf);
void lcd_set_direction(lcd_dir_t dir);
#endif

1297
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_mpylcd.c Normal file
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27
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_mpymachine.c Normal file
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#include <sysctl.h>
int mp_port_get_freq(int clkid, int *freq)
{
int ret = 0;
uint32_t value;
switch (clkid)
{
case 0:
value = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
break;
case 1:
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL1);
break;
case 2:
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL2);
break;
default:
ret = -1;
break;
}
*freq = (int)value;
return ret;
}

301
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_spi.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-18 ZYH first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#ifdef RT_USING_SPI
#include "drv_spi.h"
#include <drv_io_config.h>
#include <spi.h>
#include "dmalock.h"
#include <sysctl.h>
#include <gpiohs.h>
#include <string.h>
#include "utils.h"
#define DRV_SPI_DEVICE(spi_bus) (struct drv_spi_bus *)(spi_bus)
#define MAX_CLOCK (40000000UL)
struct drv_spi_bus
{
struct rt_spi_bus parent;
spi_device_num_t spi_instance;
dmac_channel_number_t dma_send_channel;
dmac_channel_number_t dma_recv_channel;
struct rt_completion dma_completion;
};
struct drv_cs
{
int cs_index;
int cs_pin;
};
static volatile spi_t *const spi_instance[4] =
{
(volatile spi_t *)SPI0_BASE_ADDR,
(volatile spi_t *)SPI1_BASE_ADDR,
(volatile spi_t *)SPI_SLAVE_BASE_ADDR,
(volatile spi_t *)SPI3_BASE_ADDR
};
static rt_err_t drv_spi_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
rt_err_t ret = RT_EOK;
int freq = 0;
struct drv_spi_bus *bus = DRV_SPI_DEVICE(device->bus);
struct drv_cs * cs = (struct drv_cs *)device->parent.user_data;
RT_ASSERT(bus != RT_NULL);
gpiohs_set_drive_mode(cs->cs_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(cs->cs_pin, GPIO_PV_HIGH);
#ifdef BSP_USING_SPI1_AS_QSPI
/* Todo:QSPI*/
#else
spi_init(bus->spi_instance, configuration->mode & RT_SPI_MODE_3, SPI_FF_STANDARD, configuration->data_width, 0);
#endif
freq = spi_set_clk_rate(bus->spi_instance, configuration->max_hz > MAX_CLOCK ? MAX_CLOCK : configuration->max_hz);
rt_kprintf("set spi freq %d\n", freq);
return ret;
}
void __spi_set_tmod(uint8_t spi_num, uint32_t tmod)
{
RT_ASSERT(spi_num < SPI_DEVICE_MAX);
volatile spi_t *spi_handle = spi[spi_num];
uint8_t tmod_offset = 0;
switch(spi_num)
{
case 0:
case 1:
case 2:
tmod_offset = 8;
break;
case 3:
default:
tmod_offset = 10;
break;
}
set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset);
}
int dma_irq_callback(void *ctx)
{
struct rt_completion * cmp = ctx;
if(cmp)
{
rt_completion_done(cmp);
}
}
static rt_uint32_t drv_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
struct drv_spi_bus *bus = DRV_SPI_DEVICE(device->bus);
struct drv_cs * cs = (struct drv_cs *)device->parent.user_data;
struct rt_spi_configuration *cfg = &device->config;
uint32_t * tx_buff = RT_NULL;
uint32_t * rx_buff = RT_NULL;
int i;
rt_ubase_t dummy = 0xFFFFFFFFU;
if(cfg->data_width != 8)
{
return 0;
}
RT_ASSERT(bus != RT_NULL);
if(message->cs_take)
{
gpiohs_set_pin(cs->cs_pin, GPIO_PV_LOW);
}
if(message->length)
{
bus->dma_send_channel = DMAC_CHANNEL_MAX;
bus->dma_recv_channel = DMAC_CHANNEL_MAX;
rt_completion_init(&bus->dma_completion);
if(message->recv_buf)
{
dmalock_sync_take(&bus->dma_recv_channel, RT_WAITING_FOREVER);
sysctl_dma_select(bus->dma_recv_channel, SYSCTL_DMA_SELECT_SSI0_RX_REQ + bus->spi_instance * 2);
rx_buff = rt_calloc(message->length * 4, 1);
if(!rx_buff)
{
goto transfer_done;
}
}
if(message->send_buf)
{
dmalock_sync_take(&bus->dma_send_channel, RT_WAITING_FOREVER);
sysctl_dma_select(bus->dma_send_channel, SYSCTL_DMA_SELECT_SSI0_TX_REQ + bus->spi_instance * 2);
tx_buff = rt_malloc(message->length * 4);
if(!tx_buff)
{
goto transfer_done;
}
for(i = 0; i < message->length; i++)
{
tx_buff[i] = ((uint8_t *)message->send_buf)[i];
}
}
if(message->send_buf && message->recv_buf)
{
dmac_irq_register(bus->dma_recv_channel, dma_irq_callback, &bus->dma_completion, 1);
__spi_set_tmod(bus->spi_instance, SPI_TMOD_TRANS_RECV);
spi_instance[bus->spi_instance]->dmacr = 0x3;
spi_instance[bus->spi_instance]->ssienr = 0x01;
dmac_set_single_mode(bus->dma_recv_channel, (void *)(&spi_instance[bus->spi_instance]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, message->length);
dmac_set_single_mode(bus->dma_send_channel, tx_buff, (void *)(&spi_instance[bus->spi_instance]->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, message->length);
}
else if(message->send_buf)
{
dmac_irq_register(bus->dma_send_channel, dma_irq_callback, &bus->dma_completion, 1);
__spi_set_tmod(bus->spi_instance, SPI_TMOD_TRANS);
spi_instance[bus->spi_instance]->dmacr = 0x2;
spi_instance[bus->spi_instance]->ssienr = 0x01;
dmac_set_single_mode(bus->dma_send_channel, tx_buff, (void *)(&spi_instance[bus->spi_instance]->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, message->length);
}
else if(message->recv_buf)
{
dmac_irq_register(bus->dma_recv_channel, dma_irq_callback, &bus->dma_completion, 1);
__spi_set_tmod(bus->spi_instance, SPI_TMOD_RECV);
spi_instance[bus->spi_instance]->ctrlr1 = message->length - 1;
spi_instance[bus->spi_instance]->dmacr = 0x1;
spi_instance[bus->spi_instance]->ssienr = 0x01;
spi_instance[bus->spi_instance]->dr[0] = 0xFF;
dmac_set_single_mode(bus->dma_recv_channel, (void *)(&spi_instance[bus->spi_instance]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, message->length);
}
else
{
goto transfer_done;
}
spi_instance[bus->spi_instance]->ser = 1U << cs->cs_index;
rt_completion_wait(&bus->dma_completion, RT_WAITING_FOREVER);
if(message->recv_buf)
dmac_irq_unregister(bus->dma_recv_channel);
else
dmac_irq_unregister(bus->dma_send_channel);
// wait until all data has been transmitted
while ((spi_instance[bus->spi_instance]->sr & 0x05) != 0x04)
;
spi_instance[bus->spi_instance]->ser = 0x00;
spi_instance[bus->spi_instance]->ssienr = 0x00;
if(message->recv_buf)
{
for(i = 0; i < message->length; i++)
{
((uint8_t *)message->recv_buf)[i] = (uint8_t)rx_buff[i];
}
}
transfer_done:
dmalock_release(bus->dma_send_channel);
dmalock_release(bus->dma_recv_channel);
if(tx_buff)
{
rt_free(tx_buff);
}
if(rx_buff)
{
rt_free(rx_buff);
}
}
if(message->cs_release)
{
gpiohs_set_pin(cs->cs_pin, GPIO_PV_HIGH);
}
return message->length;
}
const static struct rt_spi_ops drv_spi_ops =
{
drv_spi_configure,
drv_spi_xfer
};
int rt_hw_spi_init(void)
{
rt_err_t ret = RT_EOK;
#ifdef BSP_USING_SPI1
{
static struct drv_spi_bus spi_bus1;
spi_bus1.spi_instance = SPI_DEVICE_1;
ret = rt_spi_bus_register(&spi_bus1.parent, "spi1", &drv_spi_ops);
#ifdef BSP_SPI1_USING_SS0
{
static struct rt_spi_device spi_device10;
static struct drv_cs cs10 =
{
.cs_index = SPI_CHIP_SELECT_0,
.cs_pin = SPI1_CS0_PIN
};
rt_spi_bus_attach_device(&spi_device10, "spi10", "spi1", (void *)&cs10);
}
#endif
#ifdef BSP_SPI1_USING_SS1
{
static struct rt_spi_device spi_device11;
static struct drv_cs cs11 =
{
.cs_index = SPI_CHIP_SELECT_1,
.cs_pin = SPI1_CS1_PIN
};
rt_spi_bus_attach_device(&spi_device11, "spi11", "spi1", (void *)&cs11);
}
#endif
#ifdef BSP_SPI1_USING_SS2
{
static struct rt_spi_device spi_device12;
static struct drv_cs cs12 =
{
.cs_index = SPI_CHIP_SELECT_2,
.cs_pin = SPI1_CS2_PIN
};
rt_spi_bus_attach_device(&spi_device12, "spi12", "spi1", (void *)&cs12);
}
#endif
#ifdef BSP_SPI1_USING_SS3
{
static struct rt_spi_device spi_device13;
static struct drv_cs cs13 =
{
.cs_index = SPI_CHIP_SELECT_2,
.cs_pin = SPI1_CS2_PIN
};
rt_spi_bus_attach_device(&spi_device13, "spi13", "spi1", (void *)&cs13);
}
#endif
}
#endif
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_spi_init);
#endif

16
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_spi.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-18 ZYH first version
*/
#ifndef DRV_SPI_H__
#define DRV_SPI_H__
int rt_hw_spi_init(void);
#endif

11
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/heap.c Normal file
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#include <rtthread.h>
#include <stdlib.h>
size_t get_free_heap_size(void)
{
rt_uint32_t total, used, max;
rt_memory_info(&total, &used, &max);
return total - used;
}

42
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/sdcard_port.c Normal file
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@ -0,0 +1,42 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#ifdef BSP_USING_SDCARD
#if defined(RT_USING_SPI_MSD) && defined(RT_USING_DFS_ELMFAT)
#include <spi_msd.h>
#include <dfs_fs.h>
#define DBG_TAG "sdcard"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
int sd_mount(void)
{
int ret = 0;
ret = msd_init("sd0", "spi10");
if(RT_EOK == ret)
{
if(dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
LOG_I("Mount /sd0 successfully");
return RT_EOK;
}
else
{
LOG_E("Mount fail !!1");
return -1;
}
}
LOG_E("msd_init fail !!!");
return -2;
}
INIT_ENV_EXPORT(sd_mount);
#endif
#endif

7
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/Kconfig Normal file
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@ -0,0 +1,7 @@
menu "Kendryte SDK Config"
config PKG_KENDRYTE_SDK_VERNUM
hex "Kendryte SDK Version"
default 0x0055
endmenu

38
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/SConscript Normal file
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@ -0,0 +1,38 @@
from building import *
cwd = GetCurrentDir()
src = Split('''
kendryte-sdk-source/lib/bsp/entry.c
kendryte-sdk-source/lib/bsp/entry_user.c
kendryte-sdk-source/lib/drivers/aes.c
kendryte-sdk-source/lib/drivers/clint.c
kendryte-sdk-source/lib/drivers/dmac.c
kendryte-sdk-source/lib/drivers/dvp.c
kendryte-sdk-source/lib/drivers/fft.c
kendryte-sdk-source/lib/drivers/fpioa.c
kendryte-sdk-source/lib/drivers/gpio.c
kendryte-sdk-source/lib/drivers/gpiohs.c
kendryte-sdk-source/lib/drivers/i2c.c
kendryte-sdk-source/lib/drivers/i2s.c
kendryte-sdk-source/lib/drivers/kpu.c
kendryte-sdk-source/lib/drivers/plic.c
kendryte-sdk-source/lib/drivers/pwm.c
kendryte-sdk-source/lib/drivers/rtc.c
kendryte-sdk-source/lib/drivers/sha256.c
kendryte-sdk-source/lib/drivers/spi.c
kendryte-sdk-source/lib/drivers/sysctl.c
kendryte-sdk-source/lib/drivers/timer.c
kendryte-sdk-source/lib/drivers/uart.c
kendryte-sdk-source/lib/drivers/uarths.c
kendryte-sdk-source/lib/drivers/utils.c
kendryte-sdk-source/lib/drivers/wdt.c
''')
CPPPATH = [cwd + '/kendryte-sdk-source/lib/drivers/include',
cwd + '/kendryte-sdk-source/lib/nncase/include',
cwd + '/kendryte-sdk-source/lib/bsp/include',
cwd + '/kendryte-sdk-source/lib/utils/include']
CPPDEFINES = ['CONFIG_LOG_COLORS', 'CONFIG_LOG_ENABLE', 'CONFIG_LOG_LEVEL=LOG_VERBOSE', 'FPGA_PLL', 'LOG_KERNEL', '__riscv64']
group = DefineGroup('SDK', src, depend = [''], CPPPATH = CPPPATH, LOCAL_CPPDEFINES = CPPDEFINES)
Return('group')

1
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/kendryte-sdk-source Submodule

@ -0,0 +1 @@
Subproject commit 77d9df93ba7c2c886967995425638477cd139c4f

170
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/link.lds Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
INCLUDE "link_stacksize.lds"
/*
* The OUTPUT_ARCH command specifies the machine architecture where the
* argument is one of the names used in the Kendryte library.
*/
OUTPUT_ARCH( "riscv" )
MEMORY
{
/* 6M SRAM */
SRAM : ORIGIN = 0x80000000, LENGTH = 0x600000
}
ENTRY(_start)
SECTIONS
{
. = 0x80000000 ;
/* __STACKSIZE__ = 4096; */
.start :
{
*(.start);
} > SRAM
. = ALIGN(8);
.text :
{
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(8);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(8);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(8);
/* section information for initial. */
. = ALIGN(8);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(8);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(8);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
. = ALIGN(8);
_etext = .;
} > SRAM
.eh_frame_hdr :
{
*(.eh_frame_hdr)
*(.eh_frame_entry)
} > SRAM
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
. = ALIGN(8);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata)
*(.sdata.*)
} > SRAM
/* stack for dual core */
.stack :
{
. = ALIGN(64);
__stack_start__ = .;
. += __STACKSIZE__;
__stack_cpu0 = .;
. += __STACKSIZE__;
__stack_cpu1 = .;
} > SRAM
.sbss :
{
__bss_start = .;
*(.sbss)
*(.sbss.*)
*(.dynsbss)
*(.scommon)
} > SRAM
.bss :
{
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
__bss_end = .;
} > SRAM
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

1
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/link_stacksize.lds Normal file
View File

@ -0,0 +1 @@
__STACKSIZE__ = 4096;

244
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.h Normal file
View File

@ -0,0 +1,244 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XIUOS Rt-thread Configuration */
#define ROOT_DIR "../../../.."
#define BSP_DIR "."
#define RT_Thread_DIR "../.."
#define RTT_DIR "../../rt-thread"
#define BOARD_K210_EVB
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
#define RT_DEBUG_INIT_CONFIG
#define RT_DEBUG_INIT 1
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_SIGNALS
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_USING_SLAB
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uarths"
#define RT_VER_NUM 0x40004
#define ARCH_CPU_64BIT
#define ARCH_RISCV
#define ARCH_RISCV_FPU
#define ARCH_RISCV_FPU_S
#define ARCH_RISCV64
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
#define RT_USING_CPLUSPLUS
/* Command shell */
#define RT_USING_FINSH
#define RT_USING_MSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 16384
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 16
#define DFS_FILESYSTEM_TYPES_MAX 16
#define DFS_FD_MAX 64
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_RTC
#define RT_USING_SPI
#define RT_USING_SPI_MSD
#define RT_USING_SFUD
#define RT_SFUD_USING_SFDP
#define RT_SFUD_USING_FLASH_INFO_TABLE
#define RT_SFUD_SPI_MAX_HZ 50000000
#define RT_DEBUG_SFUD
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_PTHREADS
#define PTHREAD_NUM_MAX 8
#define RT_USING_POSIX
#define RT_LIBC_USING_TIME
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread Utestcases */
/* Board Drivers Config */
#define BSP_USING_UART_HS
/* General Purpose UARTs */
#define BSP_USING_UART1
#define BSP_UART1_TXD_PIN 20
#define BSP_UART1_RXD_PIN 21
#define BSP_UART1_RTS_PIN -1
#define BSP_UART1_CTS_PIN -1
#define BSP_USING_CH438
#define BSP_CH438_ALE_PIN 23
#define BSP_CH438_NWR_PIN 24
#define BSP_CH438_NRD_PIN 25
#define BSP_CH438_D0_PIN 27
#define BSP_CH438_D1_PIN 28
#define BSP_CH438_D2_PIN 29
#define BSP_CH438_D3_PIN 30
#define BSP_CH438_D4_PIN 31
#define BSP_CH438_D5_PIN 32
#define BSP_CH438_D6_PIN 33
#define BSP_CH438_D7_PIN 34
#define BSP_CH438_INT_PIN 35
/* Kendryte SDK Config */
#define PKG_KENDRYTE_SDK_VERNUM 0x0055
/* More Drivers */
/* APP_Framework */
/* Framework */
#define TRANSFORM_LAYER_ATTRIUBUTE
#define ADD_XIZI_FETURES
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 1024
/* ota app */
/* test app */
/* connection app */
/* control app */
/* knowing app */
/* sensor app */
#define APPLICATION_SENSOR
/* lib */
#define APP_SELECT_NEWLIB
#define LIB_USING_CJSON
#define __STACKSIZE__ 4096
#endif

49
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.py Normal file
View File

@ -0,0 +1,49 @@
import os
# toolchains options
ARCH ='risc-v'
CPU ='k210'
CROSS_TOOL ='gcc'
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin'
else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
PREFIX = 'riscv-none-embed-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcmodel=medany -march=rv64imafc -mabi=lp64f -fsingle-precision-constant'
CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -ggdb'
AFLAGS += ' -ggdb'
else:
CFLAGS += ' -O2 -Os'
CXXFLAGS = CFLAGS
# we use c++ 11, but -std=c++11 don't have 'struct siginfo', need gnu++11
CXXFLAGS += ' -std=gnu++11'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

85
Ubiquitous/RT_Thread/aiit_board/k210/.config
View File

@ -432,16 +432,62 @@ CONFIG_BSP_DVP_CMOS_HREF_PIN=45
#
CONFIG_PKG_KENDRYTE_SDK_VERNUM=0x0055
#
# MicroPython
#
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# More Drivers
#
# CONFIG_PKG_USING_RW007 is not set
CONFIG_DRV_USING_OV2640=y
CONFIG_OV2640_JPEG_MODE=y
# CONFIG_OV2640_RGB565_MODE is not set
CONFIG_OV2640_X_RESOLUTION_IMAGE_OUTSIZE=240
CONFIG_OV2640_Y_RESOLUTION_IMAGE_OUTSIZE=240
CONFIG_OV2640_X_IMAGE_WINDOWS_SIZE=400
#
# the value must be greater than OV2640_X_RESOLUTION_IMAGE_OUTSIZE
#
CONFIG_OV2640_Y_IMAGE_WINDOWS_SIZE=400
#
# the value must be greater than OV2640_Y_RESOLUTION_IMAGE_OUTSIZE
#
#
# APP_Framework
#
#
# Framework
#
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
CONFIG_ADD_XIZI_FETURES=y
# CONFIG_ADD_NUTTX_FETURES is not set
# CONFIG_ADD_RTTHREAD_FETURES is not set
# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
CONFIG_SUPPORT_KNOWING_FRAMEWORK=y
# CONFIG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_USING_KNOWING_FILTER is not set
# CONFIG_USING_OTA_MODEL is not set
# CONFIG_USING_IMAGE_PROCESSING is not set
# CONFIG_USING_CMSIS_5 is not set
CONFIG_USING_KPU_PROCESSING=y
CONFIG_USING_YOLOV2=y
CONFIG_USING_YOLOV2_JSONPARSER=y
CONFIG_USING_K210_YOLOV2_DETECT=y
# CONFIG_USING_NNOM is not set
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
#
# Security
#
# CONFIG_CRYPTO is not set
#
# Applications
#
@ -464,11 +510,11 @@ CONFIG_MAIN_KTASK_STACK_SIZE=1024
#
# connection app
#
# CONFIG_APPLICATION_CONNECTION is not set
#
# control app
#
# CONFIG_APPLICATION_CONTROL is not set
#
# knowing app
@ -483,37 +529,18 @@ CONFIG_K210_DETECT_ENTRY=y
# sensor app
#
CONFIG_APPLICATION_SENSOR=y
# CONFIG_APPLICATION_SENSOR_HCHO is not set
# CONFIG_APPLICATION_SENSOR_TVOC is not set
# CONFIG_APPLICATION_SENSOR_IAQ is not set
# CONFIG_APPLICATION_SENSOR_CH4 is not set
# CONFIG_APPLICATION_SENSOR_CO2 is not set
# CONFIG_APPLICATION_SENSOR_PM1_0 is not set
# CONFIG_APPLICATION_SENSOR_PM2_5 is not set
# CONFIG_APPLICATION_SENSOR_PM10 is not set
# CONFIG_APPLICATION_SENSOR_VOICE is not set
# CONFIG_APPLICATION_SENSOR_HUMIDITY is not set
# CONFIG_APPLICATION_SENSOR_TEMPERATURE is not set
#
# Framework
#
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
CONFIG_ADD_XIZI_FETURES=y
# CONFIG_ADD_NUTTX_FETURES is not set
# CONFIG_ADD_RTTHREAD_FETURES is not set
# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
CONFIG_SUPPORT_KNOWING_FRAMEWORK=y
# CONFIG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_USING_KNOWING_FILTER is not set
# CONFIG_USING_OTA_MODEL is not set
# CONFIG_USING_IMAGE_PROCESSING is not set
# CONFIG_USING_CMSIS_5 is not set
CONFIG_USING_KPU_PROCESSING=y
CONFIG_USING_YOLOV2=y
CONFIG_USING_YOLOV2_JSONPARSER=y
CONFIG_USING_K210_YOLOV2_DETECT=y
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
#
# Security
#
# CONFIG_CRYPTO is not set
# CONFIG_APPLICATION_SENSOR_HUMIDITY is not set
# CONFIG_USING_EMBEDDED_DATABASE_APP is not set
#
# lib
@ -522,4 +549,6 @@ CONFIG_APP_SELECT_NEWLIB=y
# CONFIG_APP_SELECT_OTHER_LIB is not set
CONFIG_LIB_USING_CJSON=y
# CONFIG_LIB_USING_QUEUE is not set
# CONFIG_LIB_LV is not set
# CONFIG_USING_EMBEDDED_DATABASE is not set
CONFIG___STACKSIZE__=4096

1
Ubiquitous/RT_Thread/aiit_board/k210/Kconfig
View File

@ -31,6 +31,7 @@ config APP_DIR
source "$RTT_DIR/Kconfig"
source "base-drivers/Kconfig"
source "kendryte-sdk/Kconfig"
source "$RT_Thread_DIR/micropython/Kconfig"
source "$RT_Thread_DIR/app_match_rt-thread/Kconfig"
source "$ROOT_DIR/APP_Framework/Kconfig"

4
Ubiquitous/RT_Thread/aiit_board/k210/SConstruct
View File

@ -61,5 +61,9 @@ objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SC
# include APP_Framework/lib
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript'))
# include Ubiquitous/RT-Thread/micropython
objs.extend(SConscript(os.getcwd() + '/../../micropython/SConscript'))
# make a building
DoBuilding(TARGET, objs)

41
Ubiquitous/RT_Thread/aiit_board/k210/rtconfig.h
View File

@ -296,12 +296,38 @@
#define PKG_KENDRYTE_SDK_VERNUM 0x0055
/* MicroPython */
/* More Drivers */
#define DRV_USING_OV2640
#define OV2640_JPEG_MODE
#define OV2640_X_RESOLUTION_IMAGE_OUTSIZE 240
#define OV2640_Y_RESOLUTION_IMAGE_OUTSIZE 240
#define OV2640_X_IMAGE_WINDOWS_SIZE 400
/* the value must be greater than OV2640_X_RESOLUTION_IMAGE_OUTSIZE */
#define OV2640_Y_IMAGE_WINDOWS_SIZE 400
/* the value must be greater than OV2640_Y_RESOLUTION_IMAGE_OUTSIZE */
/* APP_Framework */
/* Framework */
#define TRANSFORM_LAYER_ATTRIUBUTE
#define ADD_XIZI_FETURES
#define SUPPORT_KNOWING_FRAMEWORK
#define USING_KPU_PROCESSING
#define USING_YOLOV2
#define USING_YOLOV2_JSONPARSER
#define USING_K210_YOLOV2_DETECT
/* Security */
/* Applications */
/* config stack size and priority of main task */
@ -316,8 +342,8 @@
/* connection app */
/* control app */
/* control app */
/* knowing app */
@ -328,19 +354,6 @@
#define APPLICATION_SENSOR
/* Framework */
#define TRANSFORM_LAYER_ATTRIUBUTE
#define ADD_XIZI_FETURES
#define SUPPORT_KNOWING_FRAMEWORK
#define USING_KPU_PROCESSING
#define USING_YOLOV2
#define USING_YOLOV2_JSONPARSER
#define USING_K210_YOLOV2_DETECT
/* Security */
/* lib */
#define APP_SELECT_NEWLIB

117
Ubiquitous/RT_Thread/aiit_board/stm32f407_core/.config
View File

@ -186,7 +186,9 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
@ -269,8 +271,7 @@ CONFIG_SAL_INTERNET_CHECK=y
# protocol stack implement
#
CONFIG_SAL_USING_LWIP=y
# CONFIG_SAL_USING_POSIX is not set
CONFIG_SAL_SOCKETS_NUM=16
CONFIG_SAL_USING_POSIX=y
#
# Network interface device
@ -384,6 +385,7 @@ CONFIG_BSP_USING_USB_TO_USART=y
# CONFIG_BSP_USING_COM2 is not set
# CONFIG_BSP_USING_COM3 is not set
CONFIG_BSP_USING_SRAM=y
# CONFIG_BSP_USING_MCU_LCD is not set
CONFIG_BSP_USING_SPI_FLASH=y
# CONFIG_BSP_USING_EEPROM is not set
CONFIG_BSP_USING_OV2640=y
@ -438,6 +440,11 @@ CONFIG_BSP_USING_FMC=y
# Board extended module Drivers
#
#
# MicroPython
#
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# More Drivers
#
@ -452,11 +459,66 @@ CONFIG_RW007_BOOT1_PIN=86
CONFIG_RW007_INT_BUSY_PIN=87
CONFIG_RW007_RST_PIN=88
CONFIG_DRV_USING_OV2640=y
CONFIG_OV2640_JPEG_MODE=y
# CONFIG_OV2640_RGB565_MODE is not set
CONFIG_OV2640_X_RESOLUTION_IMAGE_OUTSIZE=240
CONFIG_OV2640_Y_RESOLUTION_IMAGE_OUTSIZE=240
CONFIG_OV2640_X_IMAGE_WINDOWS_SIZE=400
#
# the value must be greater than OV2640_X_RESOLUTION_IMAGE_OUTSIZE
#
CONFIG_OV2640_Y_IMAGE_WINDOWS_SIZE=400
#
# the value must be greater than OV2640_Y_RESOLUTION_IMAGE_OUTSIZE
#
#
# APP_Framework
#
#
# Framework
#
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
CONFIG_ADD_XIZI_FETURES=y
# CONFIG_ADD_NUTTX_FETURES is not set
# CONFIG_ADD_RTTHREAD_FETURES is not set
CONFIG_SUPPORT_SENSOR_FRAMEWORK=y
# CONFIG_SENSOR_HCHO is not set
# CONFIG_SENSOR_TVOC is not set
# CONFIG_SENSOR_IAQ is not set
# CONFIG_SENSOR_CH4 is not set
# CONFIG_SENSOR_CO2 is not set
# CONFIG_SENSOR_PM is not set
CONFIG_SENSOR_VOICE=y
CONFIG_SENSOR_D124=y
CONFIG_SENSOR_DEVICE_D124="d124_1"
CONFIG_SENSOR_QUANTITY_D124_VOICE="voice_1"
# CONFIG_SENSOR_D124_DRIVER_EXTUART is not set
CONFIG_SENSOR_DEVICE_D124_DEV="/dev/uart2"
# CONFIG_SENSOR_TEMPERATURE is not set
# CONFIG_SENSOR_HUMIDITY is not set
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
CONFIG_SUPPORT_KNOWING_FRAMEWORK=y
# CONFIG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_USING_KNOWING_FILTER is not set
# CONFIG_USING_OTA_MODEL is not set
# CONFIG_USING_IMAGE_PROCESSING is not set
# CONFIG_USING_CMSIS_5 is not set
CONFIG_USING_KPU_PROCESSING=y
# CONFIG_USING_YOLOV2 is not set
# CONFIG_USING_YOLOV2_JSONPARSER is not set
# CONFIG_USING_K210_YOLOV2_DETECT is not set
# CONFIG_USING_NNOM is not set
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
#
# Security
#
# CONFIG_CRYPTO is not set
#
# Applications
#
@ -479,11 +541,11 @@ CONFIG_MAIN_KTASK_STACK_SIZE=1024
#
# connection app
#
# CONFIG_APPLICATION_CONNECTION is not set
#
# control app
#
# CONFIG_APPLICATION_CONTROL is not set
#
# knowing app
@ -494,48 +556,19 @@ CONFIG_MAIN_KTASK_STACK_SIZE=1024
# sensor app
#
CONFIG_APPLICATION_SENSOR=y
# CONFIG_APPLICATION_SENSOR_HCHO is not set
# CONFIG_APPLICATION_SENSOR_TVOC is not set
# CONFIG_APPLICATION_SENSOR_IAQ is not set
# CONFIG_APPLICATION_SENSOR_CH4 is not set
# CONFIG_APPLICATION_SENSOR_CO2 is not set
# CONFIG_APPLICATION_SENSOR_PM1_0 is not set
# CONFIG_APPLICATION_SENSOR_PM2_5 is not set
# CONFIG_APPLICATION_SENSOR_PM10 is not set
CONFIG_APPLICATION_SENSOR_VOICE=y
CONFIG_APPLICATION_SENSOR_VOICE_D124=y
# CONFIG_APPLICATION_SENSOR_HUMIDITY is not set
# CONFIG_APPLICATION_SENSOR_TEMPERATURE is not set
#
# Framework
#
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
CONFIG_ADD_XIZI_FETURES=y
# CONFIG_ADD_NUTTX_FETURES is not set
# CONFIG_ADD_RTTHREAD_FETURES is not set
CONFIG_SUPPORT_SENSOR_FRAMEWORK=y
# CONFIG_SENSOR_CO2 is not set
# CONFIG_SENSOR_PM is not set
CONFIG_SENSOR_VOICE=y
CONFIG_SENSOR_D124=y
CONFIG_SENSOR_DEVICE_D124="d124_1"
CONFIG_SENSOR_QUANTITY_D124_VOICE="voice_1"
# CONFIG_SENSOR_D124_DRIVER_EXTUART is not set
CONFIG_SENSOR_DEVICE_D124_DEV="/dev/uart2"
# CONFIG_SENSOR_TEMPERATURE is not set
# CONFIG_SENSOR_HUMIDITY is not set
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
CONFIG_SUPPORT_KNOWING_FRAMEWORK=y
# CONFIG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_USING_KNOWING_FILTER is not set
# CONFIG_USING_OTA_MODEL is not set
# CONFIG_USING_IMAGE_PROCESSING is not set
# CONFIG_USING_CMSIS_5 is not set
CONFIG_USING_KPU_PROCESSING=y
# CONFIG_USING_YOLOV2 is not set
# CONFIG_USING_YOLOV2_JSONPARSER is not set
# CONFIG_USING_K210_YOLOV2_DETECT is not set
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
#
# Security
#
# CONFIG_CRYPTO is not set
# CONFIG_APPLICATION_SENSOR_HUMIDITY is not set
# CONFIG_USING_EMBEDDED_DATABASE_APP is not set
#
# lib
@ -544,3 +577,5 @@ CONFIG_APP_SELECT_NEWLIB=y
# CONFIG_APP_SELECT_OTHER_LIB is not set
# CONFIG_LIB_USING_CJSON is not set
# CONFIG_LIB_USING_QUEUE is not set
# CONFIG_LIB_LV is not set
# CONFIG_USING_EMBEDDED_DATABASE is not set

2
Ubiquitous/RT_Thread/aiit_board/stm32f407_core/Kconfig
View File

@ -16,7 +16,6 @@ config RTT_DIR
string
default "../../rt-thread"
config APP_DIR
string
default "../../../../APP_Framework"
@ -24,6 +23,7 @@ config APP_DIR
source "$RTT_DIR/Kconfig"
source "$RTT_DIR/bsp/stm32/libraries/Kconfig"
source "board/Kconfig"
source "$RT_Thread_DIR/micropython/Kconfig"
source "$RT_Thread_DIR/app_match_rt-thread/Kconfig"
source "$ROOT_DIR/APP_Framework/Kconfig"

5
Ubiquitous/RT_Thread/aiit_board/stm32f407_core/SConstruct
View File

@ -81,7 +81,12 @@ objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Framework/SCons
# include APP_Framework/Applications
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SConscript'))
# include APP_Framework/lib
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript'))
# include Ubiquitous/RT-Thread/micropython
objs.extend(SConscript(os.getcwd() + '/../../micropython/SConscript'))
# make a building
DoBuilding(TARGET, objs)

68
Ubiquitous/RT_Thread/aiit_board/stm32f407_core/rtconfig.h
View File

@ -123,6 +123,7 @@
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_PIN
#define RT_USING_RTC
#define RT_USING_SPI
#define RT_USING_SPI_MSD
#define RT_USING_SFUD
@ -177,7 +178,7 @@
/* protocol stack implement */
#define SAL_USING_LWIP
#define SAL_SOCKETS_NUM 16
#define SAL_USING_POSIX
/* Network interface device */
@ -279,6 +280,9 @@
/* Board extended module Drivers */
/* MicroPython */
/* More Drivers */
#define PKG_USING_RW007
@ -291,35 +295,19 @@
#define RW007_INT_BUSY_PIN 87
#define RW007_RST_PIN 88
#define DRV_USING_OV2640
#define OV2640_JPEG_MODE
#define OV2640_X_RESOLUTION_IMAGE_OUTSIZE 240
#define OV2640_Y_RESOLUTION_IMAGE_OUTSIZE 240
#define OV2640_X_IMAGE_WINDOWS_SIZE 400
/* the value must be greater than OV2640_X_RESOLUTION_IMAGE_OUTSIZE */
#define OV2640_Y_IMAGE_WINDOWS_SIZE 400
/* the value must be greater than OV2640_Y_RESOLUTION_IMAGE_OUTSIZE */
/* APP_Framework */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 1024
/* ota app */
/* test app */
/* connection app */
/* control app */
/* knowing app */
/* sensor app */
#define APPLICATION_SENSOR
#define APPLICATION_SENSOR_VOICE
#define APPLICATION_SENSOR_VOICE_D124
/* Framework */
#define TRANSFORM_LAYER_ATTRIUBUTE
@ -336,6 +324,32 @@
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 1024
/* ota app */
/* test app */
/* connection app */
/* control app */
/* knowing app */
/* sensor app */
#define APPLICATION_SENSOR
#define APPLICATION_SENSOR_VOICE
#define APPLICATION_SENSOR_VOICE_D124
/* lib */
#define APP_SELECT_NEWLIB

354
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/.config Normal file
View File

@ -0,0 +1,354 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
CONFIG_ROOT_DIR="../../../.."
CONFIG_BSP_DIR="."
CONFIG_RT_Thread_DIR="../.."
CONFIG_RTT_DIR="../../rt-thread"
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_BIG_ENDIAN is not set
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M7=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
CONFIG_RT_USING_CPLUSPLUS=y
# CONFIG_RT_USING_CPLUSPLUS11 is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
CONFIG_RT_USING_DFS_ROMFS=y
# CONFIG_RT_USING_DFS_RAMFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
CONFIG_RT_USING_PTHREADS=y
CONFIG_PTHREAD_NUM_MAX=8
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32H7=y
#
# Hardware Drivers Config
#
CONFIG_SOC_STM32H743II=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_LPUART1 is not set
CONFIG_BSP_USING_SDRAM=y
# CONFIG_BSP_USING_CRC is not set
# CONFIG_BSP_USING_RNG is not set
# CONFIG_BSP_USING_UDID is not set
#
# More Drivers
#
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_DRV_USING_OV2640 is not set
#
# APP_Framework
#
#
# Framework
#
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
CONFIG_ADD_XIZI_FETURES=y
# CONFIG_ADD_NUTTX_FETURES is not set
# CONFIG_ADD_RTTHREAD_FETURES is not set
# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
# CONFIG_SUPPORT_KNOWING_FRAMEWORK is not set
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
#
# Security
#
# CONFIG_CRYPTO is not set
#
# Applications
#
#
# config stack size and priority of main task
#
CONFIG_MAIN_KTASK_STACK_SIZE=1024
#
# ota app
#
# CONFIG_APPLICATION_OTA is not set
#
# test app
#
# CONFIG_USER_TEST is not set
#
# connection app
#
# CONFIG_APPLICATION_CONNECTION is not set
#
# control app
#
#
# knowing app
#
# CONFIG_APPLICATION_KNOWING is not set
#
# sensor app
#
# CONFIG_APPLICATION_SENSOR is not set
# CONFIG_USING_EMBEDDED_DATABASE_APP is not set
#
# lib
#
CONFIG_APP_SELECT_NEWLIB=y
# CONFIG_APP_SELECT_OTHER_LIB is not set
# CONFIG_LIB_USING_CJSON is not set
# CONFIG_LIB_USING_QUEUE is not set
# CONFIG_LIB_LV is not set
# CONFIG_USING_EMBEDDED_DATABASE is not set

42
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/.gitignore vendored Normal file
View File

@ -0,0 +1,42 @@
*.pyc
*.map
*.dblite
*.elf
*.bin
*.hex
*.axf
*.exe
*.pdb
*.idb
*.ilk
*.old
build
Debug
documentation/html
packages/
*~
*.o
*.obj
*.out
*.bak
*.dep
*.lib
*.i
*.d
.DS_Stor*
.config 3
.config 4
.config 5
Midea-X1
*.uimg
GPATH
GRTAGS
GTAGS
.vscode
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h

29
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/Kconfig Normal file
View File

@ -0,0 +1,29 @@
mainmenu "RT-Thread Configuration"
config ROOT_DIR
string
default "../../../.."
config BSP_DIR
string
default "."
config RT_Thread_DIR
string
default "../.."
config RTT_DIR
string
default "../../rt-thread"
config APP_DIR
string
default "../../../../APP_Framework"
source "$RTT_DIR/Kconfig"
source "$RTT_DIR/bsp/stm32/libraries/Kconfig"
source "board/Kconfig"
source "$RT_Thread_DIR/app_match_rt-thread/Kconfig"
source "$ROOT_DIR/APP_Framework/Kconfig"

85
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/README.md Normal file
View File

@ -0,0 +1,85 @@
# OPENMV4 H7 PLUS说明
## 使用说明
- 使用ST-LINK无法连接OPENMV时，可以尝试连接RST引脚和GND引脚进入RESET后连接。
- 当前串口通信需要使用USB转TTL连接USART1(P1 TX)(P0 RX)。
- 用户RAM空间为512Kb AXI-SRAM，起始地址 0x24000000。
## 以下为引脚硬件的连接表
### GPIO
| 引脚 | 作用 |
| ---- | ----- |
| PC0 | LED_R |
| PC1 | LED_G |
| PC2 | LED_B |
### USART1 串口
| 引脚 | 作用 |
| ---- | --------- |
| PB14 | USART1 TX |
| PB15 | USART1 RX |
### SDRAM (FMC接口) IS42S32800 BANK1
| 引脚 | 作用 |
| ---- | ---------- |
| PF0 | FMC_A0 |
| PF1 | FMC_A1 |
| PF2 | FMC_A2 |
| PF3 | FMC_A3 |
| PF4 | FMC_A4 |
| PF5 | FMC_A5 |
| PF12 | FMC_A6 |
| PF13 | FMC_A7 |
| PF14 | FMC_A8 |
| PF15 | FMC_A9 |
| PG0 | FMC_A10 |
| PG1 | FMC_A11 |
| PG4 | FMC_BA0 |
| PG5 | FMC_BA1 |
| PD14 | FMC_D0 |
| PD15 | FMC_D1 |
| PD0 | FMC_D2 |
| PD1 | FMC_D3 |
| PE7 | FMC_D4 |
| PE8 | FMC_D5 |
| PE9 | FMC_D6 |
| PE10 | FMC_D7 |
| PE11 | FMC_D8 |
| PE12 | FMC_D9 |
| PE13 | FMC_D10 |
| PE14 | FMC_D11 |
| PE15 | FMC_D12 |
| PD8 | FMC_D13 |
| PD9 | FMC_D14 |
| PD10 | FMC_D15 |
| PH8 | FMC_D16 |
| PH9 | FMC_D17 |
| PH10 | FMC_D18 |
| PH11 | FMC_D19 |
| PH12 | FMC_D20 |
| PH13 | FMC_D21 |
| PH14 | FMC_D22 |
| PH15 | FMC_D23 |
| PI0 | FMC_D24 |
| PI1 | FMC_D25 |
| PI2 | FMC_D26 |
| PI3 | FMC_D27 |
| PI6 | FMC_D28 |
| PI7 | FMC_D29 |
| PI9 | FMC_D30 |
| PI10 | FMC_D31 |
| PE0 | FMC_NBL0 |
| PE1 | FMC_NBL1 |
| PI4 | FMC_NBL2 |
| PI5 | FMC_NBL3 |
| PA7 | FMC_SDNWE |
| PC4 | FMC_SDNE0 |
| PC5 | FMC_SDCKE0 |
| PG8 | FMC_SDCLK |
| PG15 | FMC_SDNCAS |
| PF11 | FMC_SDNRAS |

15
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/SConscript Normal file
View File

@ -0,0 +1,15 @@
# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

89
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/SConstruct Normal file
View File

@ -0,0 +1,89 @@
import os
import sys
import rtconfig
import SCons
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../rt-thread')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
AddOption('--compiledb',
dest = 'compiledb',
action = 'store_true',
default = False,
help = 'generate compile_commands.json')
if GetOption('compiledb'):
if int(SCons.__version__.split('.')[0]) >= 4:
env['COMPILATIONDB_USE_ABSPATH'] = True
env.Tool('compilation_db')
env.CompilationDatabase('compile_commands.json')
else:
print('Warning: --compiledb only support on SCons 4.0+')
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
#if os.path.exists(SDK_ROOT + '/libraries'):
# libraries_path_prefix = SDK_ROOT + '/libraries'
#else:
# libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
libraries_path_prefix = RTT_ROOT + '/bsp/stm32/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
stm32_library = 'STM32H7xx_HAL'
rtconfig.BSP_LIBRARY_TYPE = stm32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
# include more drivers
objs.extend(SConscript(os.getcwd() + '/../../app_match_rt-thread/SConscript'))
# include APP_Framework/Framework
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Framework/SConscript'))
# include APP_Framework/Applications
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SConscript'))
# include APP_Framework/lib
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript'))
# make a building
DoBuilding(TARGET, objs)

13
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/applications/SConscript Normal file
View File

@ -0,0 +1,13 @@
import rtconfig
from building import *
cwd = GetCurrentDir()
CPPPATH = [str(Dir('#')), cwd]
src = Split('''
main.c
''')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

44
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/applications/main.c Normal file
View File

@ -0,0 +1,44 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-12-14 supperthomas first version
* 2022-03-14 wwt add xiuos framework
*/
#include <board.h>
#include <stdio.h>
#include <string.h>
#ifdef RT_USING_POSIX
#include <pthread.h>
#include <unistd.h>
#include <stdio.h>
#include <dfs_poll.h>
#include <dfs_posix.h>
#include <dfs.h>
#ifdef RT_USING_POSIX_TERMIOS
#include <posix_termios.h>
#endif
#endif
#define LEDR_PIN GET_PIN(C, 0)
extern int FrameworkInit();
int main(void)
{
rt_pin_mode(LEDR_PIN, PIN_MODE_OUTPUT);
rt_thread_mdelay(100);
FrameworkInit();
printf("XIUOS stm32h7 build %s %s\n",__DATE__,__TIME__);
while (1)
{
rt_pin_write(LEDR_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LEDR_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
#define LED_RED_Pin GPIO_PIN_0
#define LED_RED_GPIO_Port GPIOC
#define LED_GREEN_Pin GPIO_PIN_1
#define LED_GREEN_GPIO_Port GPIOC
#define LED_BLUE_Pin GPIO_PIN_2
#define LED_BLUE_GPIO_Port GPIOC
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h7xx_hal_conf.h
* @author MCD Application Team
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_CONF_H
#define STM32H7xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
/* #define HAL_FDCAN_MODULE_ENABLED */
/* #define HAL_FMAC_MODULE_ENABLED */
/* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_COMP_MODULE_ENABLED */
/* #define HAL_CORDIC_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_DAC_MODULE_ENABLED */
/* #define HAL_DCMI_MODULE_ENABLED */
/* #define HAL_DMA2D_MODULE_ENABLED */
/* #define HAL_ETH_MODULE_ENABLED */
/* #define HAL_NAND_MODULE_ENABLED */
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_OTFDEC_MODULE_ENABLED */
/* #define HAL_SRAM_MODULE_ENABLED */
#define HAL_SDRAM_MODULE_ENABLED
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_HRTIM_MODULE_ENABLED */
/* #define HAL_HSEM_MODULE_ENABLED */
/* #define HAL_GFXMMU_MODULE_ENABLED */
/* #define HAL_JPEG_MODULE_ENABLED */
/* #define HAL_OPAMP_MODULE_ENABLED */
/* #define HAL_OSPI_MODULE_ENABLED */
/* #define HAL_OSPI_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
/* #define HAL_SMBUS_MODULE_ENABLED */
/* #define HAL_IWDG_MODULE_ENABLED */
/* #define HAL_LPTIM_MODULE_ENABLED */
/* #define HAL_LTDC_MODULE_ENABLED */
/* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_RAMECC_MODULE_ENABLED */
/* #define HAL_RNG_MODULE_ENABLED */
/* #define HAL_RTC_MODULE_ENABLED */
/* #define HAL_SAI_MODULE_ENABLED */
/* #define HAL_SD_MODULE_ENABLED */
/* #define HAL_MMC_MODULE_ENABLED */
/* #define HAL_SPDIFRX_MODULE_ENABLED */
/* #define HAL_SPI_MODULE_ENABLED */
/* #define HAL_SWPMI_MODULE_ENABLED */
/* #define HAL_TIM_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED
/* #define HAL_USART_MODULE_ENABLED */
/* #define HAL_IRDA_MODULE_ENABLED */
/* #define HAL_SMARTCARD_MODULE_ENABLED */
/* #define HAL_WWDG_MODULE_ENABLED */
/* #define HAL_PCD_MODULE_ENABLED */
/* #define HAL_HCD_MODULE_ENABLED */
/* #define HAL_DFSDM_MODULE_ENABLED */
/* #define HAL_DSI_MODULE_ENABLED */
/* #define HAL_JPEG_MODULE_ENABLED */
/* #define HAL_MDIOS_MODULE_ENABLED */
/* #define HAL_PSSI_MODULE_ENABLED */
/* #define HAL_DTS_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_MDMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_HSEM_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE (12000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal oscillator (CSI) default value.
* This value is the default CSI value after Reset.
*/
#if !defined (CSI_VALUE)
#define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
#if !defined (LSI_VALUE)
#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */
#define USE_RTOS 0
#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
#define USE_SPI_CRC 0U /*!< use CRC in SPI */
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */
#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */
#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
/* ########################### Ethernet Configuration ######################### */
#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
#define ETH_MAC_ADDR0 (0x02UL)
#define ETH_MAC_ADDR1 (0x00UL)
#define ETH_MAC_ADDR2 (0x00UL)
#define ETH_MAC_ADDR3 (0x00UL)
#define ETH_MAC_ADDR4 (0x00UL)
#define ETH_MAC_ADDR5 (0x00UL)
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32h7xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32h7xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32h7xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_MDMA_MODULE_ENABLED
#include "stm32h7xx_hal_mdma.h"
#endif /* HAL_MDMA_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32h7xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32h7xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32h7xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32h7xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32h7xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_DTS_MODULE_ENABLED
#include "stm32h7xx_hal_dts.h"
#endif /* HAL_DTS_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32h7xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32h7xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32h7xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32h7xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_FDCAN_MODULE_ENABLED
#include "stm32h7xx_hal_fdcan.h"
#endif /* HAL_FDCAN_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32h7xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32h7xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CORDIC_MODULE_ENABLED
#include "stm32h7xx_hal_cordic.h"
#endif /* HAL_CORDIC_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32h7xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32h7xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32h7xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32h7xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_GFXMMU_MODULE_ENABLED
#include "stm32h7xx_hal_gfxmmu.h"
#endif /* HAL_GFXMMU_MODULE_ENABLED */
#ifdef HAL_FMAC_MODULE_ENABLED
#include "stm32h7xx_hal_fmac.h"
#endif /* HAL_FMAC_MODULE_ENABLED */
#ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32h7xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */
#ifdef HAL_HSEM_MODULE_ENABLED
#include "stm32h7xx_hal_hsem.h"
#endif /* HAL_HSEM_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32h7xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32h7xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32h7xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32h7xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32h7xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32h7xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_JPEG_MODULE_ENABLED
#include "stm32h7xx_hal_jpeg.h"
#endif /* HAL_JPEG_MODULE_ENABLED */
#ifdef HAL_MDIOS_MODULE_ENABLED
#include "stm32h7xx_hal_mdios.h"
#endif /* HAL_MDIOS_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32h7xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32h7xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32h7xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32h7xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_OSPI_MODULE_ENABLED
#include "stm32h7xx_hal_ospi.h"
#endif /* HAL_OSPI_MODULE_ENABLED */
#ifdef HAL_OTFDEC_MODULE_ENABLED
#include "stm32h7xx_hal_otfdec.h"
#endif /* HAL_OTFDEC_MODULE_ENABLED */
#ifdef HAL_PSSI_MODULE_ENABLED
#include "stm32h7xx_hal_pssi.h"
#endif /* HAL_PSSI_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32h7xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32h7xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RAMECC_MODULE_ENABLED
#include "stm32h7xx_hal_ramecc.h"
#endif /* HAL_RAMECC_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32h7xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32h7xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32h7xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32h7xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32h7xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32h7xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_SPDIFRX_MODULE_ENABLED
#include "stm32h7xx_hal_spdifrx.h"
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
#ifdef HAL_SWPMI_MODULE_ENABLED
#include "stm32h7xx_hal_swpmi.h"
#endif /* HAL_SWPMI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32h7xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32h7xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32h7xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32h7xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32h7xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32h7xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32h7xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32h7xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32h7xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* STM32H7xx_HAL_CONF_H */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h7xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_IT_H
#define __STM32H7xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_IT_H */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
UART_HandleTypeDef huart1;
SDRAM_HandleTypeDef hsdram1;
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_USART1_UART_Init(void);
static void MX_FMC_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_USART1_UART_Init();
MX_FMC_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** Supply configuration update enable
*/
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 3;
RCC_OscInitStruct.PLL.PLLN = 200;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
/* USER CODE BEGIN USART1_Init 0 */
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
huart1.Init.BaudRate = 115200;
huart1.Init.WordLength = UART_WORDLENGTH_8B;
huart1.Init.StopBits = UART_STOPBITS_1;
huart1.Init.Parity = UART_PARITY_NONE;
huart1.Init.Mode = UART_MODE_TX_RX;
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart1) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
/* FMC initialization function */
static void MX_FMC_Init(void)
{
/* USER CODE BEGIN FMC_Init 0 */
/* USER CODE END FMC_Init 0 */
FMC_SDRAM_TimingTypeDef SdramTiming = {0};
/* USER CODE BEGIN FMC_Init 1 */
/* USER CODE END FMC_Init 1 */
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1.Instance = FMC_SDRAM_DEVICE;
/* hsdram1.Init */
hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32;
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
/* SdramTiming */
SdramTiming.LoadToActiveDelay = 2;
SdramTiming.ExitSelfRefreshDelay = 7;
SdramTiming.SelfRefreshTime = 5;
SdramTiming.RowCycleDelay = 6;
SdramTiming.WriteRecoveryTime = 3;
SdramTiming.RPDelay = 2;
SdramTiming.RCDDelay = 2;
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
{
Error_Handler( );
}
/* USER CODE BEGIN FMC_Init 2 */
/* USER CODE END FMC_Init 2 */
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, LED_RED_Pin|LED_GREEN_Pin|LED_BLUE_Pin, GPIO_PIN_RESET);
/*Configure GPIO pins : LED_RED_Pin LED_GREEN_Pin LED_BLUE_Pin */
GPIO_InitStruct.Pin = LED_RED_Pin|LED_GREEN_Pin|LED_BLUE_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h7xx_hal_msp.c
* @brief This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
#ifdef __RTTHREAD__
#include "drv_common.h"
#endif
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */
/* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN Macro */
/* USER CODE END Macro */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* External functions --------------------------------------------------------*/
/* USER CODE BEGIN ExternalFunctions */
/* USER CODE END ExternalFunctions */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
/**
* @brief UART MSP Initialization
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(huart->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**USART1 GPIO Configuration
PB14 ------> USART1_TX
PB15 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF4_USART1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
/**
* @brief UART MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
{
if(huart->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspDeInit 0 */
/* USER CODE END USART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART1_CLK_DISABLE();
/**USART1 GPIO Configuration
PB14 ------> USART1_TX
PB15 ------> USART1_RX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14|GPIO_PIN_15);
/* USER CODE BEGIN USART1_MspDeInit 1 */
/* USER CODE END USART1_MspDeInit 1 */
}
}
static uint32_t FMC_Initialized = 0;
static void HAL_FMC_MspInit(void){
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct ={0};
if (FMC_Initialized) {
return;
}
FMC_Initialized = 1;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FMC;
PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_D1HCLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE();
/** FMC GPIO Configuration
PE1 ------> FMC_NBL1
PE0 ------> FMC_NBL0
PG15 ------> FMC_SDNCAS
PD0 ------> FMC_D2
PI7 ------> FMC_D29
PI6 ------> FMC_D28
PI5 ------> FMC_NBL3
PD1 ------> FMC_D3
PI3 ------> FMC_D27
PI2 ------> FMC_D26
PI9 ------> FMC_D30
PI4 ------> FMC_NBL2
PH15 ------> FMC_D23
PI1 ------> FMC_D25
PF0 ------> FMC_A0
PI10 ------> FMC_D31
PH13 ------> FMC_D21
PH14 ------> FMC_D22
PI0 ------> FMC_D24
PF2 ------> FMC_A2
PF1 ------> FMC_A1
PG8 ------> FMC_SDCLK
PF3 ------> FMC_A3
PF4 ------> FMC_A4
PF5 ------> FMC_A5
PH12 ------> FMC_D20
PG5 ------> FMC_BA1
PG4 ------> FMC_BA0
PH11 ------> FMC_D19
PH10 ------> FMC_D18
PD15 ------> FMC_D1
PG1 ------> FMC_A11
PH8 ------> FMC_D16
PH9 ------> FMC_D17
PD14 ------> FMC_D0
PC4 ------> FMC_SDNE0
PF13 ------> FMC_A7
PG0 ------> FMC_A10
PE13 ------> FMC_D10
PD10 ------> FMC_D15
PC5 ------> FMC_SDCKE0
PF12 ------> FMC_A6
PF15 ------> FMC_A9
PE8 ------> FMC_D5
PE9 ------> FMC_D6
PE11 ------> FMC_D8
PE14 ------> FMC_D11
PD9 ------> FMC_D14
PD8 ------> FMC_D13
PA7 ------> FMC_SDNWE
PF11 ------> FMC_SDNRAS
PF14 ------> FMC_A8
PE7 ------> FMC_D4
PE10 ------> FMC_D7
PE12 ------> FMC_D9
PE15 ------> FMC_D12
*/
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_13|GPIO_PIN_8
|GPIO_PIN_9|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7
|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_5|GPIO_PIN_4
|GPIO_PIN_1|GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_14
|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_3
|GPIO_PIN_2|GPIO_PIN_9|GPIO_PIN_4|GPIO_PIN_1
|GPIO_PIN_10|GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_12
|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_8|GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_12
|GPIO_PIN_15|GPIO_PIN_11|GPIO_PIN_14;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
/* USER CODE BEGIN SDRAM_MspInit 0 */
/* USER CODE END SDRAM_MspInit 0 */
HAL_FMC_MspInit();
/* USER CODE BEGIN SDRAM_MspInit 1 */
/* USER CODE END SDRAM_MspInit 1 */
}
static uint32_t FMC_DeInitialized = 0;
static void HAL_FMC_MspDeInit(void){
/* USER CODE BEGIN FMC_MspDeInit 0 */
/* USER CODE END FMC_MspDeInit 0 */
if (FMC_DeInitialized) {
return;
}
FMC_DeInitialized = 1;
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_DISABLE();
/** FMC GPIO Configuration
PE1 ------> FMC_NBL1
PE0 ------> FMC_NBL0
PG15 ------> FMC_SDNCAS
PD0 ------> FMC_D2
PI7 ------> FMC_D29
PI6 ------> FMC_D28
PI5 ------> FMC_NBL3
PD1 ------> FMC_D3
PI3 ------> FMC_D27
PI2 ------> FMC_D26
PI9 ------> FMC_D30
PI4 ------> FMC_NBL2
PH15 ------> FMC_D23
PI1 ------> FMC_D25
PF0 ------> FMC_A0
PI10 ------> FMC_D31
PH13 ------> FMC_D21
PH14 ------> FMC_D22
PI0 ------> FMC_D24
PF2 ------> FMC_A2
PF1 ------> FMC_A1
PG8 ------> FMC_SDCLK
PF3 ------> FMC_A3
PF4 ------> FMC_A4
PF5 ------> FMC_A5
PH12 ------> FMC_D20
PG5 ------> FMC_BA1
PG4 ------> FMC_BA0
PH11 ------> FMC_D19
PH10 ------> FMC_D18
PD15 ------> FMC_D1
PG1 ------> FMC_A11
PH8 ------> FMC_D16
PH9 ------> FMC_D17
PD14 ------> FMC_D0
PC4 ------> FMC_SDNE0
PF13 ------> FMC_A7
PG0 ------> FMC_A10
PE13 ------> FMC_D10
PD10 ------> FMC_D15
PC5 ------> FMC_SDCKE0
PF12 ------> FMC_A6
PF15 ------> FMC_A9
PE8 ------> FMC_D5
PE9 ------> FMC_D6
PE11 ------> FMC_D8
PE14 ------> FMC_D11
PD9 ------> FMC_D14
PD8 ------> FMC_D13
PA7 ------> FMC_SDNWE
PF11 ------> FMC_SDNRAS
PF14 ------> FMC_A8
PE7 ------> FMC_D4
PE10 ------> FMC_D7
PE12 ------> FMC_D9
PE15 ------> FMC_D12
*/
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_13|GPIO_PIN_8
|GPIO_PIN_9|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7
|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_15);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_5|GPIO_PIN_4
|GPIO_PIN_1|GPIO_PIN_0);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_14
|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8);
HAL_GPIO_DeInit(GPIOI, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_3
|GPIO_PIN_2|GPIO_PIN_9|GPIO_PIN_4|GPIO_PIN_1
|GPIO_PIN_10|GPIO_PIN_0);
HAL_GPIO_DeInit(GPIOH, GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_12
|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_8|GPIO_PIN_9);
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_12
|GPIO_PIN_15|GPIO_PIN_11|GPIO_PIN_14);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_7);
/* USER CODE BEGIN FMC_MspDeInit 1 */
/* USER CODE END FMC_MspDeInit 1 */
}
void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){
/* USER CODE BEGIN SDRAM_MspDeInit 0 */
/* USER CODE END SDRAM_MspDeInit 0 */
HAL_FMC_MspDeInit();
/* USER CODE BEGIN SDRAM_MspDeInit 1 */
/* USER CODE END SDRAM_MspDeInit 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

526
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/board/CubeMX_Config/CubeMX_Config.ioc Normal file
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@ -0,0 +1,526 @@
#MicroXplorer Configuration settings - do not modify
FMC.BankMapConfig=FMC_SWAPBMAP_DISABLE
FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_2
FMC.ColumnBitsNumber1=FMC_SDRAM_COLUMN_BITS_NUM_9
FMC.ExitSelfRefreshDelay1=7
FMC.IPParameters=ColumnBitsNumber1,CASLatency1,SDClockPeriod1,LoadToActiveDelay1,RCDDelay1,ExitSelfRefreshDelay1,SelfRefreshTime1,RowCycleDelay1,RPDelay1,BankMapConfig,WriteRecoveryTime1,ReadBurst1
FMC.LoadToActiveDelay1=2
FMC.RCDDelay1=2
FMC.RPDelay1=2
FMC.ReadBurst1=FMC_SDRAM_RBURST_ENABLE
FMC.RowCycleDelay1=6
FMC.SDClockPeriod1=FMC_SDRAM_CLOCK_PERIOD_2
FMC.SelfRefreshTime1=5
FMC.WriteRecoveryTime1=3
File.Version=6
GPIO.groupedBy=Group By Peripherals
KeepUserPlacement=false
Mcu.CPN=STM32H743IIK6
Mcu.Family=STM32H7
Mcu.IP0=CORTEX_M7
Mcu.IP1=FMC
Mcu.IP2=NVIC
Mcu.IP3=RCC
Mcu.IP4=SYS
Mcu.IP5=USART1
Mcu.IPNb=6
Mcu.Name=STM32H743IIKx
Mcu.Package=UFBGA176
Mcu.Pin0=PE1
Mcu.Pin1=PE0
Mcu.Pin10=PI9
Mcu.Pin11=PI4
Mcu.Pin12=PH15
Mcu.Pin13=PI1
Mcu.Pin14=PF0
Mcu.Pin15=PI10
Mcu.Pin16=PH13
Mcu.Pin17=PH14
Mcu.Pin18=PI0
Mcu.Pin19=PH0-OSC_IN (PH0)
Mcu.Pin2=PG15
Mcu.Pin20=PH1-OSC_OUT (PH1)
Mcu.Pin21=PF2
Mcu.Pin22=PF1
Mcu.Pin23=PG8
Mcu.Pin24=PF3
Mcu.Pin25=PF4
Mcu.Pin26=PF5
Mcu.Pin27=PH12
Mcu.Pin28=PG5
Mcu.Pin29=PG4
Mcu.Pin3=PD0
Mcu.Pin30=PH11
Mcu.Pin31=PH10
Mcu.Pin32=PD15
Mcu.Pin33=PC0
Mcu.Pin34=PC1
Mcu.Pin35=PC2_C
Mcu.Pin36=PG1
Mcu.Pin37=PH8
Mcu.Pin38=PH9
Mcu.Pin39=PD14
Mcu.Pin4=PI7
Mcu.Pin40=PC4
Mcu.Pin41=PF13
Mcu.Pin42=PG0
Mcu.Pin43=PE13
Mcu.Pin44=PD10
Mcu.Pin45=PC5
Mcu.Pin46=PF12
Mcu.Pin47=PF15
Mcu.Pin48=PE8
Mcu.Pin49=PE9
Mcu.Pin5=PI6
Mcu.Pin50=PE11
Mcu.Pin51=PE14
Mcu.Pin52=PD9
Mcu.Pin53=PD8
Mcu.Pin54=PA7
Mcu.Pin55=PF11
Mcu.Pin56=PF14
Mcu.Pin57=PE7
Mcu.Pin58=PE10
Mcu.Pin59=PE12
Mcu.Pin6=PI5
Mcu.Pin60=PE15
Mcu.Pin61=PB14
Mcu.Pin62=PB15
Mcu.Pin63=VP_SYS_VS_Systick
Mcu.Pin7=PD1
Mcu.Pin8=PI3
Mcu.Pin9=PI2
Mcu.PinsNb=64
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32H743IIKx
MxCube.Version=6.5.0
MxDb.Version=DB.6.0.50
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
PA7.GPIOParameters=GPIO_PuPd
PA7.GPIO_PuPd=GPIO_PULLUP
PA7.Locked=true
PA7.Signal=FMC_SDNWE
PB14.Locked=true
PB14.Mode=Asynchronous
PB14.Signal=USART1_TX
PB15.Locked=true
PB15.Mode=Asynchronous
PB15.Signal=USART1_RX
PC0.GPIOParameters=GPIO_Label
PC0.GPIO_Label=LED_RED
PC0.Locked=true
PC0.Signal=GPIO_Output
PC1.GPIOParameters=GPIO_Label
PC1.GPIO_Label=LED_GREEN
PC1.Locked=true
PC1.Signal=GPIO_Output
PC2_C.GPIOParameters=GPIO_Label
PC2_C.GPIO_Label=LED_BLUE
PC2_C.Locked=true
PC2_C.Signal=GPIO_Output
PC4.GPIOParameters=GPIO_PuPd
PC4.GPIO_PuPd=GPIO_PULLUP
PC4.Locked=true
PC4.Mode=SdramChipSelect1_1
PC4.Signal=FMC_SDNE0
PC5.GPIOParameters=GPIO_PuPd
PC5.GPIO_PuPd=GPIO_PULLUP
PC5.Locked=true
PC5.Mode=SdramChipSelect1_1
PC5.Signal=FMC_SDCKE0
PD0.GPIOParameters=GPIO_PuPd
PD0.GPIO_PuPd=GPIO_PULLUP
PD0.Signal=FMC_D2_DA2
PD1.GPIOParameters=GPIO_PuPd
PD1.GPIO_PuPd=GPIO_PULLUP
PD1.Signal=FMC_D3_DA3
PD10.GPIOParameters=GPIO_PuPd
PD10.GPIO_PuPd=GPIO_PULLUP
PD10.Signal=FMC_D15_DA15
PD14.GPIOParameters=GPIO_PuPd
PD14.GPIO_PuPd=GPIO_PULLUP
PD14.Signal=FMC_D0_DA0
PD15.GPIOParameters=GPIO_PuPd
PD15.GPIO_PuPd=GPIO_PULLUP
PD15.Signal=FMC_D1_DA1
PD8.GPIOParameters=GPIO_PuPd
PD8.GPIO_PuPd=GPIO_PULLUP
PD8.Signal=FMC_D13_DA13
PD9.GPIOParameters=GPIO_PuPd
PD9.GPIO_PuPd=GPIO_PULLUP
PD9.Signal=FMC_D14_DA14
PE0.GPIOParameters=GPIO_PuPd
PE0.GPIO_PuPd=GPIO_PULLUP
PE0.Signal=FMC_NBL0
PE1.GPIOParameters=GPIO_PuPd
PE1.GPIO_PuPd=GPIO_PULLUP
PE1.Signal=FMC_NBL1
PE10.GPIOParameters=GPIO_PuPd
PE10.GPIO_PuPd=GPIO_PULLUP
PE10.Signal=FMC_D7_DA7
PE11.GPIOParameters=GPIO_PuPd
PE11.GPIO_PuPd=GPIO_PULLUP
PE11.Signal=FMC_D8_DA8
PE12.GPIOParameters=GPIO_PuPd
PE12.GPIO_PuPd=GPIO_PULLUP
PE12.Signal=FMC_D9_DA9
PE13.GPIOParameters=GPIO_PuPd
PE13.GPIO_PuPd=GPIO_PULLUP
PE13.Signal=FMC_D10_DA10
PE14.GPIOParameters=GPIO_PuPd
PE14.GPIO_PuPd=GPIO_PULLUP
PE14.Signal=FMC_D11_DA11
PE15.GPIOParameters=GPIO_PuPd
PE15.GPIO_PuPd=GPIO_PULLUP
PE15.Signal=FMC_D12_DA12
PE7.GPIOParameters=GPIO_PuPd
PE7.GPIO_PuPd=GPIO_PULLUP
PE7.Signal=FMC_D4_DA4
PE8.GPIOParameters=GPIO_PuPd
PE8.GPIO_PuPd=GPIO_PULLUP
PE8.Signal=FMC_D5_DA5
PE9.GPIOParameters=GPIO_PuPd
PE9.GPIO_PuPd=GPIO_PULLUP
PE9.Signal=FMC_D6_DA6
PF0.GPIOParameters=GPIO_PuPd
PF0.GPIO_PuPd=GPIO_PULLUP
PF0.Signal=FMC_A0
PF1.GPIOParameters=GPIO_PuPd
PF1.GPIO_PuPd=GPIO_PULLUP
PF1.Signal=FMC_A1
PF11.GPIOParameters=GPIO_PuPd
PF11.GPIO_PuPd=GPIO_PULLUP
PF11.Signal=FMC_SDNRAS
PF12.GPIOParameters=GPIO_PuPd
PF12.GPIO_PuPd=GPIO_PULLUP
PF12.Signal=FMC_A6
PF13.GPIOParameters=GPIO_PuPd
PF13.GPIO_PuPd=GPIO_PULLUP
PF13.Signal=FMC_A7
PF14.GPIOParameters=GPIO_PuPd
PF14.GPIO_PuPd=GPIO_PULLUP
PF14.Signal=FMC_A8
PF15.GPIOParameters=GPIO_PuPd
PF15.GPIO_PuPd=GPIO_PULLUP
PF15.Signal=FMC_A9
PF2.GPIOParameters=GPIO_PuPd
PF2.GPIO_PuPd=GPIO_PULLUP
PF2.Signal=FMC_A2
PF3.GPIOParameters=GPIO_PuPd
PF3.GPIO_PuPd=GPIO_PULLUP
PF3.Signal=FMC_A3
PF4.GPIOParameters=GPIO_PuPd
PF4.GPIO_PuPd=GPIO_PULLUP
PF4.Signal=FMC_A4
PF5.GPIOParameters=GPIO_PuPd
PF5.GPIO_PuPd=GPIO_PULLUP
PF5.Signal=FMC_A5
PG0.GPIOParameters=GPIO_PuPd
PG0.GPIO_PuPd=GPIO_PULLUP
PG0.Signal=FMC_A10
PG1.GPIOParameters=GPIO_PuPd
PG1.GPIO_PuPd=GPIO_PULLUP
PG1.Signal=FMC_A11
PG15.GPIOParameters=GPIO_PuPd
PG15.GPIO_PuPd=GPIO_PULLUP
PG15.Signal=FMC_SDNCAS
PG4.GPIOParameters=GPIO_PuPd
PG4.GPIO_PuPd=GPIO_PULLUP
PG4.Signal=FMC_A14_BA0
PG5.GPIOParameters=GPIO_PuPd
PG5.GPIO_PuPd=GPIO_PULLUP
PG5.Signal=FMC_A15_BA1
PG8.GPIOParameters=GPIO_PuPd
PG8.GPIO_PuPd=GPIO_PULLUP
PG8.Signal=FMC_SDCLK
PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
PH10.GPIOParameters=GPIO_PuPd
PH10.GPIO_PuPd=GPIO_PULLUP
PH10.Signal=FMC_D18
PH11.GPIOParameters=GPIO_PuPd
PH11.GPIO_PuPd=GPIO_PULLUP
PH11.Signal=FMC_D19
PH12.GPIOParameters=GPIO_PuPd
PH12.GPIO_PuPd=GPIO_PULLUP
PH12.Signal=FMC_D20
PH13.GPIOParameters=GPIO_PuPd
PH13.GPIO_PuPd=GPIO_PULLUP
PH13.Signal=FMC_D21
PH14.GPIOParameters=GPIO_PuPd
PH14.GPIO_PuPd=GPIO_PULLUP
PH14.Signal=FMC_D22
PH15.GPIOParameters=GPIO_PuPd
PH15.GPIO_PuPd=GPIO_PULLUP
PH15.Signal=FMC_D23
PH8.GPIOParameters=GPIO_PuPd
PH8.GPIO_PuPd=GPIO_PULLUP
PH8.Signal=FMC_D16
PH9.GPIOParameters=GPIO_PuPd
PH9.GPIO_PuPd=GPIO_PULLUP
PH9.Signal=FMC_D17
PI0.GPIOParameters=GPIO_PuPd
PI0.GPIO_PuPd=GPIO_PULLUP
PI0.Signal=FMC_D24
PI1.GPIOParameters=GPIO_PuPd
PI1.GPIO_PuPd=GPIO_PULLUP
PI1.Signal=FMC_D25
PI10.GPIOParameters=GPIO_PuPd
PI10.GPIO_PuPd=GPIO_PULLUP
PI10.Signal=FMC_D31
PI2.GPIOParameters=GPIO_PuPd
PI2.GPIO_PuPd=GPIO_PULLUP
PI2.Signal=FMC_D26
PI3.GPIOParameters=GPIO_PuPd
PI3.GPIO_PuPd=GPIO_PULLUP
PI3.Signal=FMC_D27
PI4.GPIOParameters=GPIO_PuPd
PI4.GPIO_PuPd=GPIO_PULLUP
PI4.Signal=FMC_NBL2
PI5.GPIOParameters=GPIO_PuPd
PI5.GPIO_PuPd=GPIO_PULLUP
PI5.Signal=FMC_NBL3
PI6.GPIOParameters=GPIO_PuPd
PI6.GPIO_PuPd=GPIO_PULLUP
PI6.Signal=FMC_D28
PI7.GPIOParameters=GPIO_PuPd
PI7.GPIO_PuPd=GPIO_PULLUP
PI7.Signal=FMC_D29
PI9.GPIOParameters=GPIO_PuPd
PI9.GPIO_PuPd=GPIO_PULLUP
PI9.Signal=FMC_D30
PinOutPanel.CurrentBGAView=Top
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32H743IIKx
ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.10.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=CubeMX_Config.ioc
ProjectManager.ProjectName=CubeMX_Config
ProjectManager.RegisterCallBack=
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5.32
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_FMC_Init-FMC-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
RCC.ADCFreq_Value=24187500
RCC.AHB12Freq_Value=200000000
RCC.AHB4Freq_Value=200000000
RCC.APB1Freq_Value=100000000
RCC.APB2Freq_Value=100000000
RCC.APB3Freq_Value=100000000
RCC.APB4Freq_Value=100000000
RCC.AXIClockFreq_Value=200000000
RCC.CECFreq_Value=32000
RCC.CKPERFreq_Value=64000000
RCC.CortexFreq_Value=400000000
RCC.CpuClockFreq_Value=400000000
RCC.D1CPREFreq_Value=400000000
RCC.D1PPRE=RCC_APB3_DIV2
RCC.D2PPRE1=RCC_APB1_DIV2
RCC.D2PPRE2=RCC_APB2_DIV2
RCC.D3PPRE=RCC_APB4_DIV2
RCC.DFSDMACLkFreq_Value=400000000
RCC.DFSDMFreq_Value=100000000
RCC.DIVM1=3
RCC.DIVN1=200
RCC.DIVP1Freq_Value=400000000
RCC.DIVP2Freq_Value=24187500
RCC.DIVP3Freq_Value=24187500
RCC.DIVQ1Freq_Value=400000000
RCC.DIVQ2Freq_Value=24187500
RCC.DIVQ3Freq_Value=24187500
RCC.DIVR1Freq_Value=400000000
RCC.DIVR2Freq_Value=24187500
RCC.DIVR3Freq_Value=24187500
RCC.FDCANFreq_Value=400000000
RCC.FMCFreq_Value=200000000
RCC.FamilyName=M
RCC.HCLK3ClockFreq_Value=200000000
RCC.HCLKFreq_Value=200000000
RCC.HPRE=RCC_HCLK_DIV2
RCC.HRTIMFreq_Value=200000000
RCC.HSE_VALUE=12000000
RCC.I2C123Freq_Value=100000000
RCC.I2C4Freq_Value=100000000
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
RCC.LPTIM1Freq_Value=100000000
RCC.LPTIM2Freq_Value=100000000
RCC.LPTIM345Freq_Value=100000000
RCC.LPUART1Freq_Value=100000000
RCC.LTDCFreq_Value=24187500
RCC.MCO1PinFreq_Value=64000000
RCC.MCO2PinFreq_Value=400000000
RCC.PLL2FRACN=0
RCC.PLL3FRACN=0
RCC.PLLFRACN=0
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.QSPIFreq_Value=200000000
RCC.RNGFreq_Value=48000000
RCC.RTCFreq_Value=32000
RCC.SAI1Freq_Value=400000000
RCC.SAI23Freq_Value=400000000
RCC.SAI4AFreq_Value=400000000
RCC.SAI4BFreq_Value=400000000
RCC.SDMMCFreq_Value=400000000
RCC.SPDIFRXFreq_Value=400000000
RCC.SPI123Freq_Value=400000000
RCC.SPI45Freq_Value=100000000
RCC.SPI6Freq_Value=100000000
RCC.SWPMI1Freq_Value=100000000
RCC.SYSCLKFreq_VALUE=400000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.Tim1OutputFreq_Value=200000000
RCC.Tim2OutputFreq_Value=200000000
RCC.TraceFreq_Value=64000000
RCC.USART16Freq_Value=100000000
RCC.USART234578Freq_Value=100000000
RCC.USBFreq_Value=400000000
RCC.VCO1OutputFreq_Value=800000000
RCC.VCO2OutputFreq_Value=48375000
RCC.VCO3OutputFreq_Value=48375000
RCC.VCOInput1Freq_Value=4000000
RCC.VCOInput2Freq_Value=375000
RCC.VCOInput3Freq_Value=375000
SH.FMC_A0.0=FMC_A0,12b-sda1
SH.FMC_A0.ConfNb=1
SH.FMC_A1.0=FMC_A1,12b-sda1
SH.FMC_A1.ConfNb=1
SH.FMC_A10.0=FMC_A10,12b-sda1
SH.FMC_A10.ConfNb=1
SH.FMC_A11.0=FMC_A11,12b-sda1
SH.FMC_A11.ConfNb=1
SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1
SH.FMC_A14_BA0.ConfNb=1
SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1
SH.FMC_A15_BA1.ConfNb=1
SH.FMC_A2.0=FMC_A2,12b-sda1
SH.FMC_A2.ConfNb=1
SH.FMC_A3.0=FMC_A3,12b-sda1
SH.FMC_A3.ConfNb=1
SH.FMC_A4.0=FMC_A4,12b-sda1
SH.FMC_A4.ConfNb=1
SH.FMC_A5.0=FMC_A5,12b-sda1
SH.FMC_A5.ConfNb=1
SH.FMC_A6.0=FMC_A6,12b-sda1
SH.FMC_A6.ConfNb=1
SH.FMC_A7.0=FMC_A7,12b-sda1
SH.FMC_A7.ConfNb=1
SH.FMC_A8.0=FMC_A8,12b-sda1
SH.FMC_A8.ConfNb=1
SH.FMC_A9.0=FMC_A9,12b-sda1
SH.FMC_A9.ConfNb=1
SH.FMC_D0_DA0.0=FMC_D0,sd-32b-d1
SH.FMC_D0_DA0.ConfNb=1
SH.FMC_D10_DA10.0=FMC_D10,sd-32b-d1
SH.FMC_D10_DA10.ConfNb=1
SH.FMC_D11_DA11.0=FMC_D11,sd-32b-d1
SH.FMC_D11_DA11.ConfNb=1
SH.FMC_D12_DA12.0=FMC_D12,sd-32b-d1
SH.FMC_D12_DA12.ConfNb=1
SH.FMC_D13_DA13.0=FMC_D13,sd-32b-d1
SH.FMC_D13_DA13.ConfNb=1
SH.FMC_D14_DA14.0=FMC_D14,sd-32b-d1
SH.FMC_D14_DA14.ConfNb=1
SH.FMC_D15_DA15.0=FMC_D15,sd-32b-d1
SH.FMC_D15_DA15.ConfNb=1
SH.FMC_D16.0=FMC_D16,sd-32b-d1
SH.FMC_D16.ConfNb=1
SH.FMC_D17.0=FMC_D17,sd-32b-d1
SH.FMC_D17.ConfNb=1
SH.FMC_D18.0=FMC_D18,sd-32b-d1
SH.FMC_D18.ConfNb=1
SH.FMC_D19.0=FMC_D19,sd-32b-d1
SH.FMC_D19.ConfNb=1
SH.FMC_D1_DA1.0=FMC_D1,sd-32b-d1
SH.FMC_D1_DA1.ConfNb=1
SH.FMC_D20.0=FMC_D20,sd-32b-d1
SH.FMC_D20.ConfNb=1
SH.FMC_D21.0=FMC_D21,sd-32b-d1
SH.FMC_D21.ConfNb=1
SH.FMC_D22.0=FMC_D22,sd-32b-d1
SH.FMC_D22.ConfNb=1
SH.FMC_D23.0=FMC_D23,sd-32b-d1
SH.FMC_D23.ConfNb=1
SH.FMC_D24.0=FMC_D24,sd-32b-d1
SH.FMC_D24.ConfNb=1
SH.FMC_D25.0=FMC_D25,sd-32b-d1
SH.FMC_D25.ConfNb=1
SH.FMC_D26.0=FMC_D26,sd-32b-d1
SH.FMC_D26.ConfNb=1
SH.FMC_D27.0=FMC_D27,sd-32b-d1
SH.FMC_D27.ConfNb=1
SH.FMC_D28.0=FMC_D28,sd-32b-d1
SH.FMC_D28.ConfNb=1
SH.FMC_D29.0=FMC_D29,sd-32b-d1
SH.FMC_D29.ConfNb=1
SH.FMC_D2_DA2.0=FMC_D2,sd-32b-d1
SH.FMC_D2_DA2.ConfNb=1
SH.FMC_D30.0=FMC_D30,sd-32b-d1
SH.FMC_D30.ConfNb=1
SH.FMC_D31.0=FMC_D31,sd-32b-d1
SH.FMC_D31.ConfNb=1
SH.FMC_D3_DA3.0=FMC_D3,sd-32b-d1
SH.FMC_D3_DA3.ConfNb=1
SH.FMC_D4_DA4.0=FMC_D4,sd-32b-d1
SH.FMC_D4_DA4.ConfNb=1
SH.FMC_D5_DA5.0=FMC_D5,sd-32b-d1
SH.FMC_D5_DA5.ConfNb=1
SH.FMC_D6_DA6.0=FMC_D6,sd-32b-d1
SH.FMC_D6_DA6.ConfNb=1
SH.FMC_D7_DA7.0=FMC_D7,sd-32b-d1
SH.FMC_D7_DA7.ConfNb=1
SH.FMC_D8_DA8.0=FMC_D8,sd-32b-d1
SH.FMC_D8_DA8.ConfNb=1
SH.FMC_D9_DA9.0=FMC_D9,sd-32b-d1
SH.FMC_D9_DA9.ConfNb=1
SH.FMC_NBL0.0=FMC_NBL0,Sd4ByteEnable1
SH.FMC_NBL0.ConfNb=1
SH.FMC_NBL1.0=FMC_NBL1,Sd4ByteEnable1
SH.FMC_NBL1.ConfNb=1
SH.FMC_NBL2.0=FMC_NBL2,Sd4ByteEnable1
SH.FMC_NBL2.ConfNb=1
SH.FMC_NBL3.0=FMC_NBL3,Sd4ByteEnable1
SH.FMC_NBL3.ConfNb=1
SH.FMC_SDCLK.0=FMC_SDCLK,12b-sda1
SH.FMC_SDCLK.ConfNb=1
SH.FMC_SDNCAS.0=FMC_SDNCAS,12b-sda1
SH.FMC_SDNCAS.ConfNb=1
SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda1
SH.FMC_SDNRAS.ConfNb=1
SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda1
SH.FMC_SDNWE.ConfNb=1
USART1.IPParameters=VirtualMode-Asynchronous
USART1.VirtualMode-Asynchronous=VM_ASYNC
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom

59
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menu "Hardware Drivers Config"
config SOC_STM32H743II
bool
select SOC_SERIES_STM32H7
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_USING_LPUART1
bool "Enable LPUART1"
default n
config BSP_LPUART1_RX_USING_DMA
bool "Enable LPUART1 RX DMA"
depends on BSP_USING_LPUART1 && RT_SERIAL_USING_DMA
default n
endif
config BSP_USING_SDRAM
bool "Enable SDRAM"
default n
source "$RTT_DIR/bsp/stm32/libraries/HAL_Drivers/Kconfig"
endmenu
endmenu

34
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/board/SConscript Normal file
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import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c
''')
if GetDepend(['BSP_USING_SDRAM']):
src += Glob('ports/sdram_test.c')
path = [cwd]
path += [cwd + '/CubeMX_Config/Core/Inc']
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB
if rtconfig.CROSS_TOOL == 'gcc':
src += [startup_path_prefix + '/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += [startup_path_prefix + '/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += [startup_path_prefix + '/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h743xx.s']
CPPDEFINES = ['STM32H743xx']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

65
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/board/board.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-12-14 supperthomas first version
*/
#include <board.h>
#include <rtthread.h>
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** Supply configuration update enable
*/
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 3;
RCC_OscInitStruct.PLL.PLLN = 200;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
Error_Handler();
}
}

57
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/board/board.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-12-14 supperthomas first version
* 2022-03-14 wwt add sram2
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rtthread.h>
#include <stm32h7xx.h>
#include "drv_common.h"
#include "drv_gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (2048 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
#define STM32_SRAM1_SIZE (128)
#define STM32_SRAM1_START (0x20000000)
#define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024)
#define STM32_SRAM2_SIZE (512)
#define STM32_SRAM2_START (0x24000000)
#define STM32_SRAM2_END (STM32_SRAM2_START + STM32_SRAM2_SIZE * 1024)
#if defined(__ARMCC_VERSION)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END STM32_SRAM2_END
void SystemClock_Config(void);
#ifdef __cplusplus
}
#endif
#endif

32
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/board/linker_scripts/link.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM1_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_RAM2_start__ = 0x24000000;
define symbol __ICFEDIT_region_RAM2_end__ = 0x2407FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0400;
define symbol __ICFEDIT_size_heap__ = 0x000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM1_region { section .sram , readwrite, last block CSTACK};

157
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/board/linker_scripts/link.lds Normal file
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/*
* linker script for STM32H7XX with GNU ld
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 2048k /* 2048KB flash */
RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */
RAM2 (rw) : ORIGIN = 0x24000000, LENGTH = 512k /* 512K sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x400;
SECTIONS
{
.text :
{
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
_etext = .;
} > ROM = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > ROM
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM2
.stack :
{
. = ALIGN(4);
_sstack = .;
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >RAM2
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > RAM2
__bss_end = .;
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

19
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/board/linker_scripts/link.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00200000 { ; load region size_region
ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00020000 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 0x24000000 0x0080000 {
.ANY (+RW +ZI)
}
}

68
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/board/ports/sdram_port.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-12-14 supperthomas The first version for STM32H7xx
*/
#ifndef __SDRAM_PORT_H__
#define __SDRAM_PORT_H__
/* parameters for sdram peripheral */
/* Bank1 or Bank2 */
#define SDRAM_TARGET_BANK 1
/* stm32h7 Bank1:0XC0000000 Bank2:0XD0000000 */
#define SDRAM_BANK_ADDR ((uint32_t)0XC0000000)
/* data width: 8, 16, 32 */
#define SDRAM_DATA_WIDTH 32
/* column bit numbers: 8, 9, 10, 11 */
#define SDRAM_COLUMN_BITS 9
/* row bit numbers: 11, 12, 13 */
#define SDRAM_ROW_BITS 12
/* cas latency clock number: 1, 2, 3 */
#define SDRAM_CAS_LATENCY 2
/* read pipe delay: 0, 1, 2 */
#define SDRAM_RPIPE_DELAY 0
/* clock divid: 2, 3 */
#define SDCLOCK_PERIOD 2
/* refresh rate counter */
#define SDRAM_REFRESH_RATE (64) // ms
#define SDRAM_FREQUENCY (100000) // 100 MHz
#define SDRAM_REFRESH_CYCLES 4096
#define SDRAM_REFRESH_COUNT (SDRAM_REFRESH_RATE * SDRAM_FREQUENCY / SDRAM_REFRESH_CYCLES - 20) //((uint32_t)0x02A5)
#define SDRAM_SIZE (32 * 1024 * 1024)
/* Timing configuration for W9825G6KH-6 */
/* 100 MHz of HCKL3 clock frequency (200MHz/2) */
/* TMRD: 2 Clock cycles */
#define LOADTOACTIVEDELAY 2
/* TXSR: 8x10ns */
#define EXITSELFREFRESHDELAY 7
/* TRAS: 5x10ns */
#define SELFREFRESHTIME 5
/* TRC: 7x10ns */
#define ROWCYCLEDELAY 6
/* TWR: 2 Clock cycles */
#define WRITERECOVERYTIME 3
/* TRP: 2x10ns */
#define RPDELAY 2
/* TRCD: 2x10ns */
#define RCDDELAY 2
/* memory mode register */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
#endif

28
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/board/ports/sdram_test.c Normal file
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#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#ifdef BSP_USING_SDRAM
#include <sdram_port.h>
#define DRV_DEBUG
#define LOG_TAG "drv.sram"
#include <drv_log.h>
static void sdram_test2(void)
{
char *p =NULL;
p = rt_malloc(1024 * 1024 * 1);
if(p == NULL)
{
LOG_E("apply for 1MB memory fail ~!!!");
}
else
{
LOG_D("appyle for 1MB memory success!!!");
}
rt_free(p);
}
MSH_CMD_EXPORT(sdram_test2, sdram test2);
#endif

208
Ubiquitous/RT_Thread/aiit_board/stm32h743_openmv_h7plus/rtconfig.h Normal file
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
#define ROOT_DIR "../../../.."
#define BSP_DIR "."
#define RT_Thread_DIR "../.."
#define RTT_DIR "../../rt-thread"
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_USING_MEMHEAP_AUTO_BINDING
#define RT_USING_MEMHEAP_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40004
#define ARCH_ARM
#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M7
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
#define RT_USING_CPLUSPLUS
/* Command shell */
#define RT_USING_FINSH
#define RT_USING_MSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_ROMFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_PTHREADS
#define PTHREAD_NUM_MAX 8
#define RT_USING_POSIX
#define RT_LIBC_USING_TIME
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread Utestcases */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32H7
/* Hardware Drivers Config */
#define SOC_STM32H743II
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
#define BSP_USING_SDRAM
/* More Drivers */
/* APP_Framework */
/* Framework */
#define TRANSFORM_LAYER_ATTRIUBUTE
#define ADD_XIZI_FETURES
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 1024
/* ota app */
/* test app */
/* connection app */
/* control app */
/* knowing app */
/* sensor app */
/* lib */
#define APP_SELECT_NEWLIB
#endif

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import os
SRC_APP_DIR = '../../../../APP_Framework'
# toolchains options
ARCH='arm'
CPU='cortex-m4'
CROSS_TOOL='gcc'
# bsp lib config
BSP_LIBRARY_TYPE = None
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'/opt/gcc-arm-none-eabi-7-2018-q2-update/bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
CXX = PREFIX + 'g++'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 -g'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CXXFLAGS += ' -std=gnu++11'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
CXX = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M4.fp '
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
CFLAGS += ' -D__MICROLIB '
AFLAGS += ' --pd "__MICROLIB SETA 1" '
LFLAGS += ' --library_type=microlib '
EXEC_PATH += '/ARM/ARMCC/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = '-Dewarm'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M4'
CFLAGS += ' -e'
CFLAGS += ' --fpu=VFPv4_sp'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M4'
AFLAGS += ' --fpu VFPv4_sp'
AFLAGS += ' -S'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = ' --config "board/linker_scripts/link.icf"'
LFLAGS += ' --entry __iar_program_start'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

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/.vscode/settings.json

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menu "MicroPython"
config PKG_USING_MICROPYTHON
bool "Enable MicroPython"
select RT_USING_LIBC
select RT_USING_RTC
default n
if PKG_USING_MICROPYTHON
menu "System Module"
config MICROPYTHON_USING_UOS
bool "uos: basic 'operating system' services"
select RT_USING_DFS
default n
if MICROPYTHON_USING_UOS
config MICROPYTHON_USING_FILE_SYNC_VIA_IDE
bool "filesync: sync files through MicroPython IDE"
default y
endif
config MICROPYTHON_USING_THREAD
bool "_thread: multithreading support"
default n
config MICROPYTHON_USING_USELECT
bool "uselect: wait for events on a set of streams"
default n
config MICROPYTHON_USING_UCTYPES
bool "uctypes: create and manipulate C data types in Python"
default n
config MICROPYTHON_USING_UERRNO
bool "uerrno: system error codes"
default n
endmenu
menu "Tools Module"
config MICROPYTHON_USING_CMATH
bool "cmath: mathematical functions for complex numbers"
default n
config MICROPYTHON_USING_UBINASCII
bool "ubinascii: binary/ASCII conversions"
default n
# # Module hashlib conflicts with Kendryte standalone SDK on header
# config MICROPYTHON_USING_UHASHLIB
# bool "uhashlib: hashing algorithms"
# default n
config MICROPYTHON_USING_UHEAPQ
bool "uheapq: heap queue algorithm"
default n
config MICROPYTHON_USING_UJSON
bool "ujson: JSON encoding and decoding"
select MICROPYTHON_USING_UOS
default n
config MICROPYTHON_USING_URE
bool "ure: simple regular expressions"
default n
config MICROPYTHON_USING_UZLIB
bool "uzlib: zlib decompression"
default n
config MICROPYTHON_USING_URANDOM
bool "urandom: random variable generators"
default n
endmenu
menu "Network Module"
config MICROPYTHON_USING_USOCKET
bool "usocket: socket operations and some related functions"
select RT_USING_SAL
select SAL_USING_POSIX
select RT_LWIP_IGMP
default n
endmenu
menu "User Extended Module"
config MICROPYTHON_USING_USEREXTMODS
bool "modules define in your project"
default n
help
You must provide 'qstrdefs.user.extmods.h'
and 'moddefs.user.extmods.h'.
Macro 'MICROPY_USER_MODULES' in
'moddefs.user.extmods.h' to export your modules.
endmenu
config PKG_MICROPYTHON_HEAP_SIZE
int
prompt "Heap size for python run environment"
default 8192
config MICROPYTHON_USING_FLOAT_IMPL_FLOAT
bool "Enable micropython to use float instead of double"
default y
help
In some MCU, using float can accelerate computing-speed because of the FPU.
endif
endmenu

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The MIT License (MIT)
Copyright (c) 2013, 2014 Damien P. George
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.

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# MicroPython
[中文页](README_ZH.md) | English
## 1. Introduction
This is a port of `MicroPython` on RT-Thread, which can run on **RT-Thread 3.0** or higher. This software package can run `MicroPython` on embedded systems equipped with RT-Thread.
If it is the first time to come into contact with RT-Thread MicroPython, it is recommended that you use RT-Thread officially supported development boards to get started quickly. These development boards have complete firmware functions and provide source code, suitable for introductory learning, and officially support development boards [firmware download Please click on me](https://www.rt-thread.org/qa/forum.php?mod=viewthread&tid=12305&extra=page%3D1%26filter%3Dtypeid%26typeid%3D20).
### 1.1 Directory structure
| Name | Description |
| ---- | ---- |
| docs | Document directory, including getting started guide and development manual |
| drivers | MicroPython source code directory |
| extmod | MicroPython Source Code Directory |
| lib | MicroPython source code directory |
| py | MicroPython source code directory |
| port | Porting code directory |
| LICENSE | Micropython MIT License |
### 1.2 License
RT-Thread MicroPython follows the MIT license, see the `LICENSE` file for details.
### 1.3 Dependency
- RT-Thread 3.0+
## 2. How to open RT-Thread MicroPython
To use `MicroPython package`, you need to select it in the RT-Thread package manager. The specific path is as follows:
![elect_micropytho](./docs/assets/select_micropython.png)
Then let the RT-Thread package manager automatically update, or use the `pkgs --update` command to update the package to the BSP.
## 3. Use RT-Thread MicroPython
### 3.1 Add software package to project
After selecting `MicroPython package`, when compiling with `bsp` again, it will be added to the `bsp` project for compilation.
* For firmware development, please refer to [《MicroPython Firmware Development Guide》](./docs/firmware-develop.md)
* For more MicroPython documentation, please visit [RT-Thread Documentation Center](https://www.rt-thread.org/document/site/submodules/micropython/docs/introduction/)
### 3.2 Using MicroPython IDE
[RT-Thread MicroPython IDE](https://marketplace.visualstudio.com/items?itemName=RT-Thread.rt-thread-micropython) provides a powerful development environment for MicroPython, which can be directly searched and downloaded through the VScode application store. Examples are as follows:
![08_direct_run_files](docs/assets/08_direct_run_files.gif)
### 3.3 Add C extension to MicroPython
In order to facilitate users to add their own C functions to MicroPython to be called by Python scripts, RT-Thread provides [MicroPython C binding code automatic generator](https://summerlife.github.io/RT-MicroPython-Generator/) For everyone to use. With this tool, users only need a few simple steps to achieve C function extension. The following figure shows the form of the automatically generated C code.
![08_direct_run_files](docs/assets/c-gen.png)
## 4. Matters needing attention
- Need to use **RT-Thread 3.0** or above
- Select the `latest` version of `Micropython` in the `menuconfig` option
- Currently, the `ffi` module under `System Module` only supports GCC toolchain, and relevant information needs to be added to the link script
## 5. Development resources
* [RT-Thread MicroPython Forum](https://www.rt-thread.org/qa/forum.php)
* [RT-Thread MicroPython Documentation Center](https://www.rt-thread.org/document/site/submodules/micropython/docs/introduction/)
* [Click to join the RT-Thread MicroPython exchange group](https://jq.qq.com/?_wv=1027&k=5EhyEjx)

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# MicroPython
中文页 | [English](README.md)
## 1、介绍
这是一个在 RT-Thread 上的 `MicroPython` 移植，可以运行在 **RT-Thread 3.0** 版本以上。通过该软件包可以在搭载了 RT-Thread 的嵌入式系统上运行 `MicroPython`。
如果是第一次接触 RT-Thread MicroPython，推荐你先通过 RT-Thread 官方支持的开发板来快速上手，这些开发板的固件功能完善并提供源代码，适合入门学习，官方支持开发板 [固件下载请点我](https://www.rt-thread.org/qa/forum.php?mod=viewthread&tid=12305&extra=page%3D1%26filter%3Dtypeid%26typeid%3D20)。
### 1.1 目录结构
| 名称 | 说明 |
| ---- | ---- |
| docs | 文档目录，包括入门指南和开发手册 |
| drivers | MicroPython 源代码目录 |
| extmod | MicroPython 源代码目录 |
| lib | MicroPython 源代码目录 |
| py | MicroPython 源代码目录 |
| port | 移植代码目录 |
| LICENSE | Micropython MIT 许可证 |
### 1.2 许可证
RT-Thread MicroPython 遵循 MIT 许可，详见 `LICENSE` 文件。
### 1.3 依赖
- RT-Thread 3.0+
## 2、如何打开 RT-Thread MicroPython
使用 `MicroPython package` 需要在 RT-Thread 的包管理器中选择它，具体路径如下：
![elect_micropytho](./docs/assets/select_micropython.png)
然后让 RT-Thread 的包管理器自动更新，或者使用 `pkgs --update` 命令更新包到 BSP 中。
## 3、使用 RT-Thread MicroPython
### 3.1 添加软件包到工程
选中 `MicroPython package` 后，再次进行 `bsp` 编译时，它会被加入到 `bsp` 工程中进行编译。
* 固件开发可参考 [《MicroPython 固件开发指南》](./docs/firmware-develop.md)
* 查阅更多 MicroPython 说明文档请访问 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/submodules/micropython/docs/introduction/)
### 3.2 使用 MicroPython IDE
[RT-Thread MicroPython IDE](https://marketplace.visualstudio.com/items?itemName=RT-Thread.rt-thread-micropython) 为 MicroPython 提供了强大的开发环境，可以通过 VScode 应用商店直接查询下载，示例如下所示：
![08_direct_run_files](docs/assets/08_direct_run_files.gif)
### 3.3 向 MicroPython 添加 C 扩展
为了方便用户添加自己编写的 C 函数到 MicroPython 中被 Python 脚本调用，RT-Thread 提供了 [MicroPython C 绑定代码自动生成器](https://summerlife.github.io/RT-MicroPython-Generator/) 供大家使用。通过该工具，用户只需要简单几步，即可实现 C 函数扩展，下图展示了自动生成的 C 代码的形式。
![08_direct_run_files](docs/assets/c-gen.png)
## 4、注意事项
- 需要使用 **RT-Thread 3.0** 以上版本
- 在 `menuconfig` 选项中选择 `Micropython` 的 `latest` 版本
- 目前 `System Module` 下的 `ffi` 模块只支持 GCC 工具链，且需要在链接脚本中添加相关段信息
## 5、开发资源
* [RT-Thread MicroPython 论坛](https://www.rt-thread.org/qa/forum.php)
* [RT-Thread MicroPython 文档中心](https://www.rt-thread.org/document/site/submodules/micropython/docs/introduction/)
* [点击加入 RT-Thread MicroPython 交流群](https://jq.qq.com/?_wv=1027&k=5EhyEjx)

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from building import *
import rtconfig
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Glob('py/*.c')
src += Glob('lib/mp-readline/*.c')
src += Glob('lib/utils/*.c')
src += Glob('extmod/*.c')
src += Glob('port/*.c')
src += Glob('port/modules/*.c')
src += Glob('port/modules/machine/*.c')
src += Glob('port/modules/user/*.c')
src += Glob('lib/netutils/*.c')
src += Glob('lib/timeutils/*.c')
src += Glob('drivers/bus/*.c')
src += Glob('port/native/*.c')
path = [cwd + '/']
path += [cwd + '/port']
path += [cwd + '/port/modules']
path += [cwd + '/port/modules/machine']
LOCAL_CCFLAGS = ''
if rtconfig.CROSS_TOOL == 'gcc':
LOCAL_CCFLAGS += ' -std=gnu99'
elif rtconfig.CROSS_TOOL == 'keil':
LOCAL_CCFLAGS += ' --c99 --gnu'
group = DefineGroup('MicroPython', src, depend = ['PKG_USING_MICROPYTHON'], CPPPATH = path, LOCAL_CCFLAGS = LOCAL_CCFLAGS)
Return('group')

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