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QEMU support for XiUOS based on Cortex-M3

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This commit is contained in:
Huang_Yuqing
2021-05-13 12:33:17 +08:00
parent 9fb9a3a2ec
commit a2d278bb04
46 changed files with 68781 additions and 11 deletions
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3
arch/arm/cortex-m3/Makefile Normal file
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SRC_FILES := boot.c interrupt.c interrupt_vector.S
include $(KERNEL_ROOT)/compiler.mk

28
arch/arm/cortex-m3/arch_interrupt.h Normal file
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#ifndef ARCH_INTERRUPT_H__
#define ARCH_INTERRUPT_H__
#include <xs_base.h>
#define ARCH_MAX_IRQ_NUM (256)
#define ARCH_IRQ_NUM_OFFSET 0
#define SYSTICK_IRQN 15
#define UART1_IRQn 21
int32 ArchEnableHwIrq(uint32 irq_num);
int32 ArchDisableHwIrq(uint32 irq_num);
#endif

97
arch/arm/cortex-m3/boot.c Normal file
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//*****************************************************************************
//
// startup_gcc.c - Startup code for use with GNU tools.
//
// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
/**
* @file boot.c
* @brief derived from Stellaris Firmware Development Package
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-13
*/
/*************************************************
File name: boot.c
Description: Reset and init function
Others:
History:
1. Date: 2021-05-13
Author: AIIT XUOS Lab
Modification:
1. take startup_gcc.c from revision 10636 of the Stellaris Firmware Development Package for XiUOS
*************************************************/
extern unsigned long _sidata;
extern unsigned long _sdata;
extern unsigned long _edata;
extern unsigned long _sbss;
extern unsigned long _ebss;
extern int entry(void);
void
Reset_Handler(void)
{
unsigned long *pulSrc, *pulDest;
//
// Copy the data segment initializers from flash to SRAM.
//
pulSrc = &_sidata;
for(pulDest = &_sdata; pulDest < &_edata; )
{
*pulDest++ = *pulSrc++;
}
//
// Zero fill the bss segment.
//
__asm(" ldr r0, =_sbss\n"
" ldr r1, =_ebss\n"
" mov r2, #0\n"
" .thumb_func\n"
"zero_loop:\n"
" cmp r0, r1\n"
" it lt\n"
" strlt r2, [r0], #4\n"
" blt zero_loop");
//
// Call the application's entry point.
//
entry();
}

84
arch/arm/cortex-m3/interrupt.c Normal file
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file interrupt.c
* @brief support arm cortex-m4 interrupt function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-29
*/
#include <xs_base.h>
#include <xs_isr.h>
x_base __attribute__((naked)) DisableLocalInterrupt()
{
asm volatile ("MRS r0, PRIMASK");
asm volatile ("CPSID I");
asm volatile ("BX LR ");
}
void __attribute__((naked)) EnableLocalInterrupt(x_base level)
{
asm volatile ("MSR PRIMASK, r0");
asm volatile ("BX LR");
}
int32 ArchEnableHwIrq(uint32 irq_num)
{
return EOK;
}
int32 ArchDisableHwIrq(uint32 irq_num)
{
return EOK;
}
extern void KTaskOsAssignAfterIrq(void *context);
void IsrEntry()
{
uint32 ipsr;
__asm__ volatile("MRS %0, IPSR" : "=r"(ipsr));
isrManager.done->incCounter();
isrManager.done->handleIrq(ipsr);
KTaskOsAssignAfterIrq(NONE);
isrManager.done->decCounter();
}
void UsageFault_Handler(int irqn, void *arg)
{
/* Go to infinite loop when Usage Fault exception occurs */
while (1)
{
}
}
void BusFault_Handler(int irqn, void *arg)
{
/* Go to infinite loop when Bus Fault exception occurs */
while (1)
{
}
}
void NMI_Handler(int irqn, void *arg)
{
while (1)
{
}
}

138
arch/arm/cortex-m3/interrupt_vector.S Normal file
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//*****************************************************************************
//
// startup_gcc.c - Startup code for use with GNU tools.
//
// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
/**
* @file interrupt_vector.S
* @brief derived from Stellaris Firmware Development Package
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-13
*/
/*************************************************
File name: interrupt_vector.S
Description: vector table for a Cortex M3
Others:
History:
1. Date: 2021-05-13
Author: AIIT XUOS Lab
Modification:
1. take startup_gcc.c from revision 10636 of the Stellaris Firmware Development Package for XiUOS
*************************************************/
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
//*****************************************************************************
.globl InterruptVectors
/******************************************************************************
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type InterruptVectors, %object
.size InterruptVectors, .-InterruptVectors
InterruptVectors:
.word _sp
.word Reset_Handler
.word NMI_Handler //NMI_Handler
.word HardFaultHandler
.word MemFaultHandler //MemManage_Handler
.word BusFault_Handler //BusFault_Handler
.word UsageFault_Handler //UsageFault_Handler
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry //SVC_Handler
.word IsrEntry //DebugMon_Handler
.word IsrEntry
.word PendSV_Handler
.word IsrEntry //systick
.word IsrEntry // GPIO Port A
.word IsrEntry // GPIO Port B
.word IsrEntry // GPIO Port C
.word IsrEntry // GPIO Port D
.word IsrEntry // GPIO Port E
.word IsrEntry // UART0 Rx and Tx
.word IsrEntry // UART1 Rx and Tx
.word IsrEntry // SSI Rx and Tx
.word IsrEntry // I2C Master and Slave
.word IsrEntry // PWM Fault
.word IsrEntry // PWM Generator 0
.word IsrEntry // PWM Generator 1
.word IsrEntry // PWM Generator 2
.word IsrEntry // Quadrature Encoder
.word IsrEntry // ADC Sequence 0
.word IsrEntry // ADC Sequence 1
.word IsrEntry // ADC Sequence 2
.word IsrEntry // ADC Sequence 3
.word IsrEntry // Watchdog timer
.word IsrEntry // Timer 0 subtimer A
.word IsrEntry // Timer 0 subtimer B
.word IsrEntry // Timer 1 subtimer A
.word IsrEntry // Timer 1 subtimer B
.word IsrEntry // Timer 2 subtimer A
.word IsrEntry // Timer 2 subtimer B
.word IsrEntry // Analog Comparator 0
.word IsrEntry // Analog Comparator 1
.word IsrEntry // Analog Comparator 2
.word IsrEntry // System Control (PLL, OSC,
.word IsrEntry // FLASH Control
.word IsrEntry // GPIO Port F
.word IsrEntry // GPIO Port G
.word IsrEntry // GPIO Port H
.word IsrEntry // UART2 Rx and Tx
.word IsrEntry // SSI1 Rx and Tx
.word IsrEntry // Timer 3 subtimer A
.word IsrEntry // Timer 3 subtimer B
.word IsrEntry // I2C1 Master and Slave
.word IsrEntry // Quadrature Encoder 1
.word IsrEntry // CAN0
.word IsrEntry // CAN1
.word IsrEntry // CAN2
.word IsrEntry // Ethernet
.word IsrEntry // Hibernate
.word IsrEntry // USB0
.word IsrEntry // PWM Generator 3
.word IsrEntry // uDMA Software Transfer
.word IsrEntry // uDMA Error