forked from xuos/xiuos
fixed menu and complilation error
This commit is contained in:
commit
8992dce241
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@ -3,6 +3,7 @@ menu "control app"
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menuconfig APPLICATION_CONTROL
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bool "Using control apps"
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default n
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depends on SUPPORT_CONTROL_FRAMEWORK
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endmenu
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@ -2,9 +2,11 @@ SRC_DIR :=
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ifeq ($(CONFIG_RESOURCES_LWIP),y)
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SRC_DIR += lwip_demo
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endif
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ifeq ($(CONFIG_USING_CONTROL_PLC_OPCUA), y)
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SRC_DIR += opcua_demo
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endif
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endif
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include $(KERNEL_ROOT)/compiler.mk
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@ -1,3 +1,3 @@
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SRC_FILES := ping.c lwip_ping_demo.c
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SRC_FILES := ping.c lwip_ping_demo.c udp_echo.c lwip_udp_demo.c
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include $(KERNEL_ROOT)/compiler.mk
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@ -46,8 +46,6 @@
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#include "pin_mux.h"
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#include "clock_config.h"
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#include "fsl_gpio.h"
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#include "fsl_iomuxc.h"
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#include <transform.h>
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#include <sys_arch.h>
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@ -19,6 +19,7 @@
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*/
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#include <xiuos.h>
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#include "board.h"
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#include "udp_echo.h"
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#include <connect_ethernet.h>
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@ -25,12 +25,9 @@
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#include <stdint.h>
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#include <sys/types.h>
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#include <lwip/altcp.h>
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#include <fsl_gpio.h>
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#include <fsl_iomuxc.h>
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#include "netif/ethernet.h"
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#include "enet_ethernetif.h"
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#include "connect_ethernet.h"
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#include "board.h"
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typedef unsigned int nfds_t;
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#include "../../../../APP_Framework/Framework/control/plc/interoperability/opcua/open62541.h"
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@ -70,14 +67,13 @@ typedef unsigned int nfds_t;
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/* System clock name. */
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#define EXAMPLE_CLOCK_NAME kCLOCK_CoreSysClk
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//#define sourceClock CLOCK_GetFreq(kCLOCK_CoreSysClk)
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const char *test_uri = "opc.tcp://192.168.250.5:4840";
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const char *test_cb_str = "tcp client connected\r\n";
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void ua_ip_init(void)
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{
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#ifdef BOARD_CORTEX_M7_EVB
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struct netif fsl_netif0;
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#if defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
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mem_range_t non_dma_memory[] = NON_DMA_MEMORY_ARRAY;
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@ -92,8 +88,6 @@ void ua_ip_init(void)
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#endif /* FSL_FEATURE_SOC_LPC_ENET_COUNT */
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};
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gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
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ua_print("lw: [%s] start ...\n", __func__);
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IP4_ADDR(&fsl_netif0_ipaddr, configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3);
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@ -107,8 +101,6 @@ void ua_ip_init(void)
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netif_set_default(&fsl_netif0);
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netif_set_up(&fsl_netif0);
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// ping_init(&fsl_netif0_gw);
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ua_print("\r\n************************************************\r\n");
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ua_print(" PING example\r\n");
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ua_print("************************************************\r\n");
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@ -119,7 +111,7 @@ void ua_ip_init(void)
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ua_print(" IPv4 Gateway : %u.%u.%u.%u\r\n", ((u8_t *)&fsl_netif0_gw)[0], ((u8_t *)&fsl_netif0_gw)[1],
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((u8_t *)&fsl_netif0_gw)[2], ((u8_t *)&fsl_netif0_gw)[3]);
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ua_print("************************************************\r\n");
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#endif
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}
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// tcp client callback
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@ -243,4 +235,3 @@ void TestUaConnect(int argc, char *argv[])
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SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0),
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UaConnect, TestUaConnect, TestUaConnect);
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@ -2,4 +2,5 @@
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menuconfig USING_CONTROL_PLC_OPCUA
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bool "PLC support OPCUA"
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default y
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depends on RESOURCES_LWIP
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@ -1,9 +1,13 @@
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SRC_DIR :=
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ifeq ($(CONFIG_RESOURCES_LWIP),y)
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ifeq ($(CONFIG_USING_CONTROL_PLC_OPCUA), y)
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SRC_DIR += opcua
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endif
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endif
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SRC_FILES += interoperability.c
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include $(KERNEL_ROOT)/compiler.mk
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@ -426,8 +426,6 @@ void ENET_Init(ENET_Type *base,
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/* Reset ENET module. */
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ENET_Reset(base);
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lw_print("lw: [%s] config %p %x\n", __func__, config, config->interrupt);
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/* Initializes the ENET transmit buffer descriptors. */
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ENET_SetTxBufferDescriptors(handle, config, bufferConfig);
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@ -504,9 +502,6 @@ static void ENET_SetHandler(ENET_Type *base,
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handle->txBdCurrent[count] = buffCfg->txBdStartAddrAlign;
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handle->txBuffSizeAlign[count] = buffCfg->txBuffSizeAlign;
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lw_print("lw: [%s] %d instance %d ring %d %p IRQ %p %#x\n", __func__,
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count, instance, handle->ringNum, buffCfg->rxBdStartAddrAlign, config, config->interrupt);
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buffCfg++;
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}
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@ -516,19 +511,16 @@ static void ENET_SetHandler(ENET_Type *base,
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/* Set the IRQ handler when the interrupt is enabled. */
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if (config->interrupt & ENET_TX_INTERRUPT)
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{
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lw_trace();
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s_enetTxIsr = ENET_TransmitIRQHandler;
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EnableIRQ(s_enetTxIrqId[instance]);
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}
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if (config->interrupt & ENET_RX_INTERRUPT)
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{
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lw_trace();
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s_enetRxIsr = ENET_ReceiveIRQHandler;
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EnableIRQ(s_enetRxIrqId[instance]);
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}
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if (config->interrupt & ENET_ERR_INTERRUPT)
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{
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lw_trace();
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s_enetErrIsr = ENET_ErrorIRQHandler;
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EnableIRQ(s_enetErrIrqId[instance]);
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}
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@ -921,10 +913,6 @@ static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId)
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/* Ensure previous data update is completed with Data Synchronization Barrier before activing Tx BD. */
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__DSB();
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//tst by wly
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// lw_print("lw: [%s] ring %d\n", __func__, ringId);
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switch (ringId)
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{
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case kENET_Ring0:
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@ -1322,12 +1310,9 @@ status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length)
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}
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/* FCS is removed by MAC. */
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*length = curBuffDescrip->length;
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// lw_print("lw: [%s] %p %p ctrl %#x ok\n", __func__, curBuffDescrip, handle->rxBdCurrent[0], curBuffDescrip->control);
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return kStatus_Success;
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}
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// lw_print("lw: [%s] %p %p ctrl %#x\n", __func__, curBuffDescrip, handle->rxBdCurrent[0], curBuffDescrip->control);
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/* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */
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if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK)
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{
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@ -1396,8 +1381,6 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
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/* For data-NULL input, only update the buffer descriptor. */
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if (!data)
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{
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// lw_print("lw: [%s] data %d ctrl %#x\n", __func__, length, handle->rxBdCurrent[0]->control);
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do
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{
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/* Update the control flag. */
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@ -1418,8 +1401,6 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
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else
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{
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// lw_print("lw: [%s] data len %d ctrl %#x\n", __func__, length, handle->rxBdCurrent[0]->control);
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/* A frame on one buffer or several receive buffers are both considered. */
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#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
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address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local);
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@ -1489,9 +1470,6 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
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/* Get the current buffer descriptor. */
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curBuffDescrip = handle->rxBdCurrent[0];
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// lw_print("lw: [%s] ctrl %#x\n", __func__, handle->rxBdCurrent[0]->control);
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/* Add the cache invalidate maintain. */
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#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
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address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local);
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@ -1517,8 +1495,6 @@ static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint3
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/* Sets the receive buffer descriptor with the empty flag. */
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handle->rxBdCurrent[ringId]->control |= ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK;
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// lw_print("lw: [%s] ring %d ctrl %#x\n", __func__, ringId, handle->rxBdCurrent[ringId]->control);
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/* Increase current buffer descriptor to the next one. */
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if (handle->rxBdCurrent[ringId]->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK)
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{
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@ -1529,8 +1505,6 @@ static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint3
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handle->rxBdCurrent[ringId]++;
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}
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// lw_print("lw: [%s] ring %d changed ctrl %#x\n", __func__, ringId, handle->rxBdCurrent[ringId]->control);
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/* Ensure previous data update is completed with Data Synchronization Barrier before activing Rx BD. */
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__DSB();
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@ -1636,8 +1610,6 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
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handle->txBdCurrent[0]++;
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}
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// lw_print("lw: [%s] ctrl %#x\n", __func__, curBuffDescrip->control);
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/* Active the transmit buffer descriptor. */
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ENET_ActiveSend(base, 0);
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@ -3130,8 +3102,6 @@ void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle)
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assert(handle);
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uint32_t mask = kENET_RxFrameInterrupt | kENET_RxBufferInterrupt;
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lw_print("lw: [%s] input\n", __func__);
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/* Check if the receive interrupt happen. */
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#if FSL_FEATURE_ENET_QUEUE > 1
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switch (ringId)
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@ -1,5 +1,3 @@
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SRC_FILES += sys_arch.c \
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tcp_echo_socket_demo.c \
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udp_echo.c
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SRC_FILES += sys_arch.c
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include $(KERNEL_ROOT)/compiler.mk
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