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add pin config for riscv64 board

This commit is contained in:
Wang_Weigen 2022-03-15 16:04:51 +08:00
parent cb8da02a88
commit 7ebc769017
6 changed files with 45 additions and 77 deletions
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44
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.config
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@ -290,45 +290,15 @@ CONFIG_BSP_UART1_CTS_PIN=-1
# CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_I2C1 is not set
CONFIG_BSP_USING_SPI1=y # CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_USING_SPI1_AS_QSPI is not set # CONFIG_BSP_USING_LCD is not set
CONFIG_BSP_SPI1_CLK_PIN=27 # CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_LOW is not set
CONFIG_BSP_SPI1_D0_PIN=28
CONFIG_BSP_SPI1_D1_PIN=26
CONFIG_BSP_SPI1_USING_SS0=y
CONFIG_BSP_SPI1_SS0_PIN=29
CONFIG_BSP_SPI1_USING_SS1=y
CONFIG_BSP_SPI1_SS1_PIN=8
# CONFIG_BSP_SPI1_USING_SS2 is not set
# CONFIG_BSP_SPI1_USING_SS3 is not set
CONFIG_BSP_USING_LCD=y
CONFIG_BSP_LCD_CS_PIN=36
CONFIG_BSP_LCD_WR_PIN=39
CONFIG_BSP_LCD_DC_PIN=38
CONFIG_BSP_LCD_RST_PIN=37
CONFIG_BSP_LCD_BACKLIGHT_PIN=-1
CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_LOW=y
# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_HIGH is not set # CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_HIGH is not set
CONFIG_BSP_LCD_CLK_FREQ=20000000
# CONFIG_BSP_BOARD_KD233 is not set # CONFIG_BSP_BOARD_KD233 is not set
# CONFIG_BSP_BOARD_K210_OPENMV_TEST is not set # CONFIG_BSP_BOARD_K210_OPENMV_TEST is not set
CONFIG_BSP_BOARD_USER=y # CONFIG_BSP_BOARD_USER is not set
CONFIG_BSP_LCD_X_MAX=240 # CONFIG_BSP_USING_SDCARD is not set
CONFIG_BSP_LCD_Y_MAX=320 # CONFIG_BSP_USING_DVP is not set
CONFIG_BSP_USING_SDCARD=y
CONFIG_BSP_USING_DVP=y
#
# The default pin assignment is based on the Maix Duino K210 development board
#
CONFIG_BSP_DVP_SCCB_SDA_PIN=40
CONFIG_BSP_DVP_SCCB_SCLK_PIN=41
CONFIG_BSP_DVP_CMOS_RST_PIN=42
CONFIG_BSP_DVP_CMOS_VSYNC_PIN=43
CONFIG_BSP_DVP_CMOS_PWDN_PIN=44
CONFIG_BSP_DVP_CMOS_XCLK_PIN=46
CONFIG_BSP_DVP_CMOS_PCLK_PIN=47
CONFIG_BSP_DVP_CMOS_HREF_PIN=45
CONFIG_BSP_USING_CH438=y CONFIG_BSP_USING_CH438=y
CONFIG_BSP_CH438_ALE_PIN=23 CONFIG_BSP_CH438_ALE_PIN=23
CONFIG_BSP_CH438_NWR_PIN=24 CONFIG_BSP_CH438_NWR_PIN=24
@ -353,8 +323,6 @@ CONFIG_PKG_KENDRYTE_SDK_VERNUM=0x0055
# #
# CONFIG_PKG_USING_RW007 is not set # CONFIG_PKG_USING_RW007 is not set
# CONFIG_DRV_USING_OV2640 is not set # CONFIG_DRV_USING_OV2640 is not set
# CONFIG_OV2640_JPEG_MODE is not set
# CONFIG_OV2640_RGB565_MODE is not set
# #
# APP_Framework # APP_Framework

1
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/main.c
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@ -19,6 +19,7 @@
*/ */
#include <rtthread.h> #include <rtthread.h>
#include <stdio.h>
int main(void) int main(void)
{ {

16
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.c
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@ -6,7 +6,7 @@
#include "ch438.h" #include "ch438.h"
#include "sleep.h" #include "sleep.h"
static rt_sem_t ch438_sem; static struct rt_semaphore ch438_sem;
static rt_uint8_t offsetadd[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* Offset address of serial port number */ static rt_uint8_t offsetadd[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* Offset address of serial port number */
rt_uint8_t RevLen ,Ch438Buff[8][BUFFSIZE],Ch438BuffPtr[8]; rt_uint8_t RevLen ,Ch438Buff[8][BUFFSIZE],Ch438BuffPtr[8];
@ -364,18 +364,18 @@ const struct rt_uart_ops extuart_ops =
static int Ch438Irq(void *parameter) static int Ch438Irq(void *parameter)
{ {
rt_sem_release(ch438_sem); rt_sem_release(&ch438_sem);
} }
void Ch438InitDefault(void) int Ch438InitDefault(void)
{ {
rt_err_t flag; rt_err_t flag;
flag = rt_sem_init(ch438_sem, "sem_438",0,RT_IPC_FLAG_FIFO); flag = rt_sem_init(&ch438_sem, "sem_438",0,RT_IPC_FLAG_FIFO);
if (flag != RT_EOK) if (flag != RT_EOK)
{ {
rt_kprintf("ch438.drv create sem failed .\n"); rt_kprintf("ch438.drv create sem failed .\n");
return ; return -1;
} }
gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP); gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP);
@ -383,7 +383,9 @@ void Ch438InitDefault(void)
gpiohs_irq_register(FPIOA_CH438_INT, 1, Ch438Irq, 0); gpiohs_irq_register(FPIOA_CH438_INT, 1, Ch438Irq, 0);
CH438_INIT(); CH438_INIT();
return 0;
} }
INIT_APP_EXPORT(Ch438InitDefault);
int rt_hw_ch438_init(void) int rt_hw_ch438_init(void)
{ {
@ -464,7 +466,7 @@ int rt_hw_ch438_init(void)
// uart); // uart);
// } // }
// #endif // #endif
Ch438InitDefault(); // Ch438InitDefault();
return 0; return 0;
} }
INIT_DEVICE_EXPORT(rt_hw_ch438_init);

14
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.c
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@ -139,6 +139,20 @@ static struct io_config
#ifdef BSP_PWM_CHN3_ENABLE #ifdef BSP_PWM_CHN3_ENABLE
IOCONFIG(BSP_PWM_CHN3_PIN, FUNC_TIMER2_TOGGLE4), IOCONFIG(BSP_PWM_CHN3_PIN, FUNC_TIMER2_TOGGLE4),
#endif #endif
IOCONFIG(BSP_CH438_ALE_PIN, HS_GPIO(FPIOA_CH438_ALE)),
IOCONFIG(BSP_CH438_NWR_PIN, HS_GPIO(FPIOA_CH438_NWR)),
IOCONFIG(BSP_CH438_NRD_PIN, HS_GPIO(FPIOA_CH438_NRD)),
IOCONFIG(BSP_CH438_INT_PIN, HS_GPIO(FPIOA_CH438_INT)),
IOCONFIG(BSP_CH438_D0_PIN, HS_GPIO(FPIOA_CH438_D0)),
IOCONFIG(BSP_CH438_D1_PIN, HS_GPIO(FPIOA_CH438_D1)),
IOCONFIG(BSP_CH438_D2_PIN, HS_GPIO(FPIOA_CH438_D2)),
IOCONFIG(BSP_CH438_D3_PIN, HS_GPIO(FPIOA_CH438_D3)),
IOCONFIG(BSP_CH438_D4_PIN, HS_GPIO(FPIOA_CH438_D4)),
IOCONFIG(BSP_CH438_D5_PIN, HS_GPIO(FPIOA_CH438_D5)),
IOCONFIG(BSP_CH438_D6_PIN, HS_GPIO(FPIOA_CH438_D6)),
IOCONFIG(BSP_CH438_D7_PIN, HS_GPIO(FPIOA_CH438_D7)),
}; };
static int print_io_config() static int print_io_config()

15
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.h
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@ -58,6 +58,21 @@ enum HS_GPIO_CONFIG
#define FPIOA_CH438_INT 22 #define FPIOA_CH438_INT 22
#define FPIOA_485_DIR 23 #define FPIOA_485_DIR 23
//PIN.define
#define BSP_CH438_ALE_PIN 23
#define BSP_CH438_NWR_PIN 24
#define BSP_CH438_NRD_PIN 25
#define BSP_CH438_D0_PIN 27
#define BSP_CH438_D1_PIN 28
#define BSP_CH438_D2_PIN 29
#define BSP_CH438_D3_PIN 30
#define BSP_CH438_D4_PIN 31
#define BSP_CH438_D5_PIN 32
#define BSP_CH438_D6_PIN 33
#define BSP_CH438_D7_PIN 34
#define BSP_CH438_INT_PIN 35
extern int io_config_init(void); extern int io_config_init(void);
#endif #endif

32
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.h
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@ -180,38 +180,6 @@
#define BSP_UART1_RXD_PIN 21 #define BSP_UART1_RXD_PIN 21
#define BSP_UART1_RTS_PIN -1 #define BSP_UART1_RTS_PIN -1
#define BSP_UART1_CTS_PIN -1 #define BSP_UART1_CTS_PIN -1
#define BSP_USING_SPI1
#define BSP_SPI1_CLK_PIN 27
#define BSP_SPI1_D0_PIN 28
#define BSP_SPI1_D1_PIN 26
#define BSP_SPI1_USING_SS0
#define BSP_SPI1_SS0_PIN 29
#define BSP_SPI1_USING_SS1
#define BSP_SPI1_SS1_PIN 8
#define BSP_USING_LCD
#define BSP_LCD_CS_PIN 36
#define BSP_LCD_WR_PIN 39
#define BSP_LCD_DC_PIN 38
#define BSP_LCD_RST_PIN 37
#define BSP_LCD_BACKLIGHT_PIN -1
#define BSP_LCD_BACKLIGHT_ACTIVE_LOW
#define BSP_LCD_CLK_FREQ 20000000
#define BSP_BOARD_USER
#define BSP_LCD_X_MAX 240
#define BSP_LCD_Y_MAX 320
#define BSP_USING_SDCARD
#define BSP_USING_DVP
/* The default pin assignment is based on the Maix Duino K210 development board */
#define BSP_DVP_SCCB_SDA_PIN 40
#define BSP_DVP_SCCB_SCLK_PIN 41
#define BSP_DVP_CMOS_RST_PIN 42
#define BSP_DVP_CMOS_VSYNC_PIN 43
#define BSP_DVP_CMOS_PWDN_PIN 44
#define BSP_DVP_CMOS_XCLK_PIN 46
#define BSP_DVP_CMOS_PCLK_PIN 47
#define BSP_DVP_CMOS_HREF_PIN 45
#define BSP_USING_CH438 #define BSP_USING_CH438
#define BSP_CH438_ALE_PIN 23 #define BSP_CH438_ALE_PIN 23
#define BSP_CH438_NWR_PIN 24 #define BSP_CH438_NWR_PIN 24