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support zynq7000-zc702

This commit is contained in:
TXuian 2024-03-05 16:18:01 +08:00
parent 5f9478251b
commit 6489d94dcd
5 changed files with 4 additions and 10 deletions
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6
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_zynq7000-zc702/boot.S
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@ -140,7 +140,7 @@ OKToRun:
mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */ mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
bl invalidate_dcache /* invalidate dcache */ bl boot_invalidate_dcache /* invalidate dcache */
/* Disable MMU, if enabled */ /* Disable MMU, if enabled */
mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */ mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
@ -193,14 +193,14 @@ OKToRun:
/* /*
************************************************************************* *************************************************************************
* *
* invalidate_dcache - invalidate the entire d-cache by set/way * boot_invalidate_dcache - invalidate the entire d-cache by set/way
* *
* Note: for Cortex-A9, there is no cp instruction for invalidating * Note: for Cortex-A9, there is no cp instruction for invalidating
* the whole D-cache. Need to invalidate each line. * the whole D-cache. Need to invalidate each line.
* *
************************************************************************* *************************************************************************
*/ */
invalidate_dcache: boot_invalidate_dcache:
mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */ mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
ands r3, r0, #0x7000000 ands r3, r0, #0x7000000
mov r3, r3, lsr #23 /* cache level value (naturally aligned) */ mov r3, r3, lsr #23 /* cache level value (naturally aligned) */

2
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_zynq7000-zc702/zynq7000-zc702.lds
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@ -36,8 +36,6 @@ SECTIONS
.start_sec : { .start_sec : {
. = ALIGN(0x1000); . = ALIGN(0x1000);
*(.vectors)
/* read only area. */ /* read only area. */
boot.o(.text) boot.o(.text)
xil-crt0.o(.text .text.*) xil-crt0.o(.text .text.*)

3
Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/xil_uart.c
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@ -50,6 +50,7 @@
*****************************************************************************/ *****************************************************************************/
/***************************** Include Files ********************************/ /***************************** Include Files ********************************/
#include "xparameters.h"
#include "xuartps_hw.h" #include "xuartps_hw.h"
#include "mmio_access.h" #include "mmio_access.h"
@ -176,8 +177,6 @@ void XUartPs_ResetHw(u32 BaseAddress)
((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS | (u32)XUARTPS_CR_STOPBRK)); ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS | (u32)XUARTPS_CR_STOPBRK));
} }
#define STDIN_BASEADDRESS 0xE0001000
#define STDOUT_BASEADDRESS 0xE0001000
void UartPutChar(uint8_t ch) void UartPutChar(uint8_t ch)
{ {
if (ch == '\n') { if (ch == '\n') {

1
Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c
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@ -288,7 +288,6 @@ void load_kern_pgdir(struct TraceTag* mmu_driver_tag, struct TraceTag* intr_driv
uintptr_t dev_attr = 0; uintptr_t dev_attr = 0;
_p_pgtbl_mmu_access->MmuDevPteAttr(&dev_attr); _p_pgtbl_mmu_access->MmuDevPteAttr(&dev_attr);
_map_pages((uintptr_t*)kern_pgdir.pd_addr, PHY_MEM_BASE, PHY_MEM_BASE, (PHY_MEM_STOP - PHY_MEM_BASE), kern_attr);
// kern mem // kern mem
_map_pages((uintptr_t*)kern_pgdir.pd_addr, KERN_MEM_BASE, PHY_MEM_BASE, (PHY_MEM_STOP - PHY_MEM_BASE), kern_attr); _map_pages((uintptr_t*)kern_pgdir.pd_addr, KERN_MEM_BASE, PHY_MEM_BASE, (PHY_MEM_STOP - PHY_MEM_BASE), kern_attr);
// dev mem // dev mem

2
Ubiquitous/XiZi_AIoT/softkernel/task/task.c
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@ -198,9 +198,7 @@ static void _scheduler(struct SchedulerRightGroup right_group)
struct CPU* cpu = cur_cpu(); struct CPU* cpu = cur_cpu();
cpu->task = next_task; cpu->task = next_task;
// DEBUG("%s %d\n", __func__, __LINE__);
context_switch(&cpu->scheduler, next_task->main_thread.context); context_switch(&cpu->scheduler, next_task->main_thread.context);
// DEBUG("%s %d\n", __func__, __LINE__);
} }
} }