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add part of bsp for sabre lite board

This commit is contained in:
Wang_Weigen 2023-04-07 16:23:09 +08:00
parent 419b53594f
commit 60e1c1bf8f
123 changed files with 450231 additions and 21 deletions
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8
Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.c
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@ -118,12 +118,12 @@ static int32_t FreeHwIrq(uint32_t irq_num)
*
* @return 0 on success; -1 on failure
*/
static int32_t EnableHwIrq(uint32_t irq_num)
static int32_t EnableHwIrq(uint32_t irq_num, uint32_t cpu_id)
{
if (irq_num >= ARCH_MAX_IRQ_NUM )
return -1;
return ArchEnableHwIrq(irq_num);
return ArchEnableHwIrq(irq_num, cpu_id);
}
/**
* This function will disable a irq.
@ -133,12 +133,12 @@ static int32_t EnableHwIrq(uint32_t irq_num)
* @return 0 on success; -1 on failure
*/
static int32_t DisableHwIrq(uint32_t irq_num)
static int32_t DisableHwIrq(uint32_t irq_num, uint32_t cpu_id)
{
if (irq_num >= ARCH_MAX_IRQ_NUM )
return -1;
return ArchDisableHwIrq(irq_num);
return ArchDisableHwIrq(irq_num, cpu_id);
}
/* called from arch-specific ISR wrapper */

4
Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.h
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@ -55,8 +55,8 @@ struct IsrDone
bool (*isInIsr)();
int32_t (*registerIrq)(uint32_t irq_num, IsrHandlerType handler, void *arg);
int32_t (*freeIrq)(uint32_t irq_num);
int32_t (*enableIrq)(uint32_t irq_num);
int32_t (*disableIrq)(uint32_t irq_num);
int32_t (*enableIrq)(uint32_t irq_num, uint32_t cpu_id);
int32_t (*disableIrq)(uint32_t irq_num, uint32_t cpu_id);
void (*handleIrq)(uint32_t irq_num);
uint16_t (*getCounter)() ;
void (*incCounter)();

2
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/Makefile
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@ -1,3 +1,3 @@
SRC_FILES := boot.S cache.S exception.S cortexA9.S gic.c interrupt.c
SRC_FILES := boot.S cache.S exception.S cortexA9.S gic.c interrupt.c mmu.c ccm_pll.c
include $(KERNEL_ROOT)/compiler.mk

4
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/arch_interrupt.h
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@ -19,8 +19,8 @@
#define ARCH_MAX_IRQ_NUM PLATFORM_MAX_IRQ_NR
int32_t ArchEnableHwIrq(uint32_t irq_num);
int32_t ArchDisableHwIrq(uint32_t irq_num);
int32_t ArchEnableHwIrq(uint32_t irq_num, uint32_t cpu_id);
int32_t ArchDisableHwIrq(uint32_t irq_num, uint32_t cpu_id);
//! @brief
typedef enum {

85
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/arm_cp_registers.h Normal file
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@ -0,0 +1,85 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//! @addtogroup cortexa9
//! @{
/*!
* @file arm_cp_registers.h
* @brief Definitions for ARM coprocessor registers.
*/
#ifndef __ARM_CP_REGISTERS_H__
#define __ARM_CP_REGISTERS_H__
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! @name ACTLR
//@{
#define BM_ACTLR_SMP (1 << 6)
//@}
//! @name DFSR
//@{
#define BM_DFSR_WNR (1 << 11) //!< Write not Read bit. 0=read, 1=write.
#define BM_DFSR_FS4 (0x400) //!< Fault status bit 4..
#define BP_DFSR_FS4 (10) //!< Bit position for FS[4].
#define BM_DFSR_FS (0xf) //!< Fault status bits [3:0].
//@}
//! @name SCTLR
//@{
#define BM_SCTLR_TE (1 << 30) //!< Thumb exception enable.
#define BM_SCTLR_AFE (1 << 29) //!< Access flag enable.
#define BM_SCTLR_TRE (1 << 28) //!< TEX remap enable.
#define BM_SCTLR_NMFI (1 << 27) //!< Non-maskable FIQ support.
#define BM_SCTLR_EE (1 << 25) //!< Exception endianess.
#define BM_SCTLR_VE (1 << 24) //!< Interrupt vectors enable.
#define BM_SCTLR_FI (1 << 21) //!< Fast interrupt configurable enable.
#define BM_SCTLR_RR (1 << 14) //!< Round Robin
#define BM_SCTLR_V (1 << 13) //!< Vectors
#define BM_SCTLR_I (1 << 12) //!< Instruction cache enable
#define BM_SCTLR_Z (1 << 11) //!< Branch prediction enable
#define BM_SCTLR_SW (1 << 10) //!< SWP and SWPB enable
#define BM_SCTLR_CP15BEN (1 << 5) //!< CP15 barrier enable
#define BM_SCTLR_C (1 << 2) //!< Data cache enable
#define BM_SCTLR_A (1 << 1) //!< Alignment check enable
#define BM_SCTLR_M (1 << 0) //!< MMU enable
//@}
//! @}
#endif // __ARM_CP_REGISTERS_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

9
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/boot.S
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@ -4,7 +4,7 @@
.section ".startup","ax"
.globl _reset
.extern init
_reset:
/* set the cpu to SVC32 mode and disable interrupt */
@ -22,6 +22,11 @@ _reset:
ldr r0, =stack_top
@ get cpu id, and subtract the offset from the stacks base address
mrc p15,0,r2,c0,c0,5 @ read multiprocessor affinity register
and r2, r2, #3 @ mask off, leaving CPU ID field
mov r5, r2 @ save cpu id for later
@ Set the startup stack for svc
mov sp, r0
@ -86,7 +91,7 @@ ctor_loop:
b ctor_loop
ctor_end:
bl start_kernel
bl init
_loop_here:
b _loop_here

442
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/ccm_pll.c Executable file
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@ -0,0 +1,442 @@
/*
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
#include "registers/regsccm.h"
#include "registers/regsccmanalog.h"
#include "registers/regsgpc.h"
#include "registers/regsiomuxc.h"
#include "registers/regsuart.h"
#include "registers/regsssi.h"
#include "registers/regsepit.h"
#include "registers/regsgpt.h"
#include "registers/regsi2c.h"
#include "registers/regsspdif.h"
#include "registers/regsspba.h"
#include "registers/regssdmaarm.h"
#include "registers/regsecspi.h"
#if defined(CHIP_MX6DQ)
#include "registers/regssata.h"
#endif
#if !defined(CHIP_MX6SL)
#include "registers/regsgpmi.h"
#include "registers/regsesai.h"
#endif
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
const uint32_t PLL1_OUTPUT = 792000000;
const uint32_t PLL2_OUTPUT[] = { 528000000, 396000000, 352000000, 198000000, 594000000 };
const uint32_t PLL3_OUTPUT[] = { 480000000, 720000000, 540000000, 508235294, 454736842 };
const uint32_t PLL4_OUTPUT = 650000000;
const uint32_t PLL5_OUTPUT = 650000000;
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
void ccm_init(void)
{
// ETHNET
HW_CCM_ANALOG_PLL_ENET_CLR(BM_CCM_ANALOG_PLL_ENET_POWERDOWN);
HW_CCM_ANALOG_PLL_ENET_SET(BM_CCM_ANALOG_PLL_ENET_ENABLE);
HW_CCM_ANALOG_PLL_ENET_CLR(BM_CCM_ANALOG_PLL_ENET_BYPASS);
#if !defined (CHIP_MX6SL)
HW_CCM_ANALOG_PLL_ENET.B.DIV_SELECT = 0x3;
#else
HW_CCM_ANALOG_PLL_ENET.B.DIV_SELECT = 0x1;
#endif
// Ungate clocks that are not enabled in a driver - need to be updated
HW_CCM_CCGR0_WR(0xffffffff);
HW_CCM_CCGR1_WR(0xFFCF0FFF); // EPIT, ESAI, GPT enabled by driver
HW_CCM_CCGR2_WR(0xFFFFF03F); // I2C enabled by driver
HW_CCM_CCGR3_WR(0xffffffff);
HW_CCM_CCGR4_WR(0x00FFFF03); // GPMI, Perfmon enabled by driver
HW_CCM_CCGR5_WR(0xF0FFFFCF); // UART, SATA enabled by driver
HW_CCM_CCGR6_WR(0xffffffff);
/*
* Keep default settings at reset.
* pre_periph_clk_sel is by default at 0, so the selected output
* of PLL2 is the main output at 528MHz.
* => by default, ahb_podf divides by 4 => AHB_CLK@132MHz.
* => by default, ipg_podf divides by 2 => IPG_CLK@66MHz.
*/
HW_CCM_CBCDR.U = BF_CCM_CBCDR_AHB_PODF(3)
#if !defined (CHIP_MX6SL)
| BF_CCM_CBCDR_AXI_PODF(1)
#endif
| BF_CCM_CBCDR_IPG_PODF(1);
/*
* UART clock tree: PLL3 (480MHz) div-by-6: 80MHz
* 80MHz uart_clk_podf (div-by-1) = 80MHz (UART module clock input)
*/
// writel(readl(CCM_CSCDR1) & 0x0000003F, CCM_CSCDR1);
// HW_CCM_CSCDR1.U =
/* Mask all interrupt sources that could wake up the processor when in
a low power mode. A source is individually masked/unmasked when the
interrupt is enabled/disabled by the GIC/interrupt driver. */
HW_GPC_IMR1_WR(0xFFFFFFFF);
HW_GPC_IMR2_WR(0xFFFFFFFF);
HW_GPC_IMR3_WR(0xFFFFFFFF);
HW_GPC_IMR4_WR(0xFFFFFFFF);
}
uint32_t get_main_clock(main_clocks_t clock)
{
uint32_t ret_val = 0;
uint32_t pre_periph_clk_sel = HW_CCM_CBCMR.B.PRE_PERIPH_CLK_SEL;
switch (clock) {
case CPU_CLK:
ret_val = PLL1_OUTPUT;
break;
#if !defined (CHIP_MX6SL)
case AXI_CLK:
ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AXI_PODF + 1);
break;
case MMDC_CH0_AXI_CLK:
ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.MMDC_CH0_AXI_PODF + 1);
break;
#endif
case AHB_CLK:
ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF + 1);
break;
case IPG_CLK:
ret_val =
PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF +
1) / (HW_CCM_CBCDR.B.IPG_PODF + 1);
break;
case IPG_PER_CLK:
ret_val =
PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF +
1) / (HW_CCM_CBCDR.B.IPG_PODF +
1) / (HW_CCM_CSCMR1.B.PERCLK_PODF + 1);
break;
#if !defined (CHIP_MX6SL)
case MMDC_CH1_AXI_CLK:
ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.MMDC_CH1_AXI_PODF + 1);
break;
#endif
default:
break;
}
return ret_val;
}
uint32_t get_peri_clock(peri_clocks_t clock)
{
uint32_t ret_val = 0;
switch (clock)
{
case UART1_MODULE_CLK:
case UART2_MODULE_CLK:
case UART3_MODULE_CLK:
case UART4_MODULE_CLK:
// UART source clock is a fixed PLL3 / 6
ret_val = PLL3_OUTPUT[0] / 6 / (HW_CCM_CSCDR1.B.UART_CLK_PODF + 1);
break;
// eCSPI clock:
// PLL3(480) -> /8 -> CSCDR2[ECSPI_CLK_PODF]
case SPI_CLK:
ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCDR2.B.ECSPI_CLK_PODF + 1);
break;
#if !defined (CHIP_MX6SL)
case RAWNAND_CLK:
ret_val =
PLL3_OUTPUT[0] / (HW_CCM_CS2CDR.B.ENFC_CLK_PRED + 1) / (HW_CCM_CS2CDR.B.ENFC_CLK_PODF +
1);
break;
case CAN_CLK:
// For i.mx6dq/sdl CAN source clock is a fixed PLL3 / 8
ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCMR2.B.CAN_CLK_PODF + 1);
break;
#endif
default:
break;
}
return ret_val;
}
/*!
* Set/unset clock gating for a peripheral.
* @param ccm_ccgrx Address of the clock gating register: CCM_CCGR1,...
* @param cgx_offset Offset of the clock gating field: CG(x).
* @param gating_mode Clock gating mode: CLOCK_ON or CLOCK_OFF.
*/
void ccm_ccgr_config(uint32_t ccm_ccgrx, uint32_t cgx_offset, uint32_t gating_mode)
{
if (gating_mode == CLOCK_ON)
{
*(volatile uint32_t *)(ccm_ccgrx) |= cgx_offset;
}
else
{
*(volatile uint32_t *)(ccm_ccgrx) &= ~cgx_offset;
}
}
void clock_gating_config(uint32_t base_address, uint32_t gating_mode)
{
uint32_t ccm_ccgrx = 0;
uint32_t cgx_offset = 0;
switch (base_address)
{
case REGS_UART1_BASE:
case REGS_UART2_BASE:
case REGS_UART3_BASE:
case REGS_UART4_BASE:
case REGS_UART5_BASE:
ccm_ccgrx = HW_CCM_CCGR5_ADDR;
cgx_offset = CG(13) | CG(12);
break;
case REGS_SSI3_BASE:
ccm_ccgrx = HW_CCM_CCGR5_ADDR;
cgx_offset = CG(11);
break;
case REGS_SSI2_BASE:
ccm_ccgrx = HW_CCM_CCGR5_ADDR;
cgx_offset = CG(10);
break;
case REGS_SSI1_BASE:
ccm_ccgrx = HW_CCM_CCGR5_ADDR;
cgx_offset = CG(9);
break;
case REGS_SPDIF_BASE:
ccm_ccgrx = HW_CCM_CCGR5_ADDR;
cgx_offset = CG(7);
break;
case REGS_SPBA_BASE:
ccm_ccgrx = HW_CCM_CCGR5_ADDR;
cgx_offset = CG(6);
break;
case REGS_SDMAARM_BASE:
ccm_ccgrx = HW_CCM_CCGR5_ADDR;
cgx_offset = CG(3);
break;
#if CHIP_MX6DQ
case REGS_SATA_BASE:
ccm_ccgrx = HW_CCM_CCGR5_ADDR;
cgx_offset = CG(2);
break;
#endif // CHIP_MX6DQ
case REGS_EPIT1_BASE:
ccm_ccgrx = HW_CCM_CCGR1_ADDR;
cgx_offset = CG(6);
break;
case REGS_EPIT2_BASE:
ccm_ccgrx = HW_CCM_CCGR1_ADDR;
cgx_offset = CG(7);
break;
case REGS_GPT_BASE:
ccm_ccgrx = HW_CCM_CCGR1_ADDR;
cgx_offset = CG(10);
break;
case REGS_I2C1_BASE:
ccm_ccgrx = HW_CCM_CCGR2_ADDR;
cgx_offset = CG(3);
break;
case REGS_I2C2_BASE:
ccm_ccgrx = HW_CCM_CCGR2_ADDR;
cgx_offset = CG(4);
break;
case REGS_I2C3_BASE:
ccm_ccgrx = HW_CCM_CCGR2_ADDR;
cgx_offset = CG(5);
break;
case REGS_ECSPI1_BASE:
ccm_ccgrx = HW_CCM_CCGR1_ADDR;
cgx_offset = CG(0);
break;
case REGS_ECSPI2_BASE:
ccm_ccgrx = HW_CCM_CCGR1_ADDR;
cgx_offset = CG(1);
break;
case REGS_ECSPI3_BASE:
ccm_ccgrx = HW_CCM_CCGR1_ADDR;
cgx_offset = CG(2);
break;
case REGS_ECSPI4_BASE:
ccm_ccgrx = HW_CCM_CCGR1_ADDR;
cgx_offset = CG(3);
break;
#if CHIP_MX6DQ
case REGS_ECSPI5_BASE:
ccm_ccgrx = HW_CCM_CCGR1_ADDR;
cgx_offset = CG(4);
break;
#endif // CHIP_MX6DQ
#if !defined (CHIP_MX6SL)
case REGS_GPMI_BASE:
ccm_ccgrx = HW_CCM_CCGR4_ADDR;
cgx_offset = CG(15) | CG(14) | CG(13) | CG(12);
break;
case REGS_ESAI_BASE:
ccm_ccgrx = HW_CCM_CCGR1_ADDR;
cgx_offset = CG(8);
break;
case CAAM_BASE_ADDR:
ccm_ccgrx = HW_CCM_CCGR0_ADDR;
cgx_offset = CG(6) | CG(5) | CG(4);
break;
#endif // !defined (CHIP_MX6SL)
default:
break;
}
// apply changes only if a valid address was found
if (ccm_ccgrx != 0)
{
ccm_ccgr_config(ccm_ccgrx, cgx_offset, gating_mode);
}
}
void ccm_set_lpm_wakeup_source(uint32_t irq_id, bool doEnable)
{
uint32_t reg_offset = 0;
uint32_t bit_offset = 0;
uint32_t gpc_imr = 0;
// calculate the offset of the register handling that interrupt ID
// ID starts at 32, so for instance ID=89 is handled by IMR2 because
// the integer part of the division is reg_offset = 2
reg_offset = (irq_id / 32);
// and the rest of the previous division is used to calculate the bit
// offset in the register, so for ID=89 this is bit_offset = 25
bit_offset = irq_id - 32 * reg_offset;
// get the current value of the corresponding GPC_IMRx register
gpc_imr = readl(HW_GPC_IMR1_ADDR + (reg_offset - 1) * 4);
if (doEnable) {
// clear the corresponding bit to unmask the interrupt source
gpc_imr &= ~(1 << bit_offset);
// write the new mask
writel(gpc_imr, HW_GPC_IMR1_ADDR + (reg_offset - 1) * 4);
} else {
// set the corresponding bit to mask the interrupt source
gpc_imr |= (1 << bit_offset);
// write the new mask
writel(gpc_imr, HW_GPC_IMR1_ADDR + (reg_offset - 1) * 4);
}
}
void ccm_enter_low_power(lp_modes_t lp_mode)
{
uint32_t ccm_clpcr = 0;
// if MMDC channel 1 is not used, the handshake must be masked
// set disable core clock in wait - set disable oscillator in stop
ccm_clpcr =
#if !defined (CHIP_MX6SL)
BM_CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS |
#endif
BM_CCM_CLPCR_SBYOS | BM_CCM_CLPCR_ARM_CLK_DIS_ON_LPM | lp_mode;
if (lp_mode == STOP_MODE) {
// enable peripherals well-biased
ccm_clpcr |= BM_CCM_CLPCR_WB_PER_AT_LPM;
}
HW_CCM_CLPCR_WR(ccm_clpcr);
__asm(
// data synchronization barrier (caches, TLB maintenance, ...)
"dsb;"
// wait for interrupt instruction
"wfi;"
// instruction synchronization barrier (flush the pipe-line)
"isb;");
return;
}
#if !defined (CHIP_MX6SL)
/*!
* @brief Configure ipu 1 and 2 hsp clk to default 264MHz
*
* ipu_hsp_clk is derived from mmdc_ch0 divided by 2.
*/
void ipu_hsp_clk_config(void)
{
// clk_sel from mmdc_ch0, podf=1
HW_CCM_CSCDR3_WR(BF_CCM_CSCDR3_IPU1_HSP_CLK_SEL(0)
| BF_CCM_CSCDR3_IPU1_HSP_PODF(1)
#if CHIP_MX6DQ
| BF_CCM_CSCDR3_IPU2_HSP_CLK_SEL(0)
| BF_CCM_CSCDR3_IPU2_HSP_PODF(1)
#endif // CHIP_MX6DQ
);
}
void gpu_clock_config(void)
{
HW_CCM_ANALOG_PLL_VIDEO_NUM_WR(0xFF0D6C3);
HW_CCM_ANALOG_PLL_VIDEO_WR(BF_CCM_ANALOG_PLL_VIDEO_DIV_SELECT(2) |
BF_CCM_ANALOG_PLL_VIDEO_ENABLE(1) |
BF_CCM_ANALOG_PLL_VIDEO_BYPASS(1));
while (!HW_CCM_ANALOG_PLL_VIDEO.B.LOCK) ; //waiting for PLL lock
BF_CLR(CCM_ANALOG_PLL_VIDEO, BYPASS);
//ldb_di0_clk select PLL5
HW_CCM_CS2CDR.B.LDB_DI0_CLK_SEL = 0; // PLL5
HW_IOMUXC_GPR3.B.LVDS1_MUX_CTL = 0; // LVDS1 source is IPU1 DI0 port
HW_IOMUXC_GPR3.B.LVDS0_MUX_CTL = 2; // LVDS0 source is IPU2 DI0 port
HW_CCM_CHSCCDR.B.IPU1_DI0_CLK_SEL = 3; // derive clock from ldb_di0_clk
HW_CCM_CSCMR2_SET(BM_CCM_CSCMR2_LDB_DI0_IPU_DIV | BM_CCM_CSCMR2_LDB_DI1_IPU_DIV); // ldb_di0 divided by 3.5
#if CHIP_MX6DQ
HW_CCM_CSCDR2.B.IPU2_DI0_CLK_SEL = 3; // derive clock from ldb_di0_clk
HW_CCM_CSCDR2.B.IPU2_DI1_CLK_SEL = 3; // derive clock from 352M PFD
#endif // CHIP_MX6DQ
}
#endif
////////////////////////////////////////////////////////////////////////////////
// End of file
////////////////////////////////////////////////////////////////////////////////

150
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/ccm_pll.h Normal file
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@ -0,0 +1,150 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CCM_PLL_H_
#define _CCM_PLL_H_
#include "sdk_types.h"
//! @addtogroup diag_clocks
//! @{
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
#define CLK_SRC_32K 32768
//! @brief Create a clock gate bit mask value.
//! @param x 0..15, for CG0 to CG15
#define CG(x) (3 << (x*2))
//! @brief Constants for CCM CCGR register fields.
enum _clock_gate_constants
{
CLOCK_ON = 0x3, //!< Clock always on in both run and stop modes.
CLOCK_ON_RUN = 0x1, //!< Clock on only in run mode.
CLOCK_OFF = 0x0 //!< Clocked gated off.
};
//! @brief Low power mdoes.
typedef enum _lp_modes {
RUN_MODE,
WAIT_MODE,
STOP_MODE,
} lp_modes_t;
//! @brief Main clock sources.
typedef enum _main_clocks {
CPU_CLK,
AXI_CLK,
MMDC_CH0_AXI_CLK,
AHB_CLK,
IPG_CLK,
IPG_PER_CLK,
MMDC_CH1_AXI_CLK,
} main_clocks_t;
//! @brief Peripheral clocks.
typedef enum _peri_clocks {
UART1_MODULE_CLK,
UART2_MODULE_CLK,
UART3_MODULE_CLK,
UART4_MODULE_CLK,
SSI1_BAUD,
SSI2_BAUD,
CSI_BAUD,
MSTICK1_CLK,
MSTICK2_CLK,
RAWNAND_CLK,
USB_CLK,
VPU_CLK,
SPI_CLK,
CAN_CLK
} peri_clocks_t;
//! @brief Available PLLs.
typedef enum plls {
PLL1,
PLL2,
PLL3,
PLL4,
PLL5,
} plls_t;
extern const uint32_t PLL1_OUTPUT;
extern const uint32_t PLL2_OUTPUT[];
extern const uint32_t PLL3_OUTPUT[];
extern const uint32_t PLL4_OUTPUT;
extern const uint32_t PLL5_OUTPUT;
////////////////////////////////////////////////////////////////////////////////
// API
////////////////////////////////////////////////////////////////////////////////
#if defined(__cplusplus)
extern "C" {
#endif
//! @brief Set/unset clock gating for a peripheral.
//! @param base_address configure clock gating for that module from the base address.
//! @param gating_mode clock gating mode: CLOCK_ON or CLOCK_OFF.
void clock_gating_config(uint32_t base_address, uint32_t gating_mode);
//! @brief Returns the frequency of a clock in megahertz.
uint32_t get_main_clock(main_clocks_t clk);
//! @brief Returns the frequency of a clock in megahertz.
uint32_t get_peri_clock(peri_clocks_t clk);
//! @brief Inits clock sources.
void ccm_init(void);
//! @brief Prepare and enter in a low power mode.
//! @param lp_mode low power mode : WAIT_MODE or STOP_MODE.
void ccm_enter_low_power(lp_modes_t lp_mode);
//! @brief Mask/unmask an interrupt source that can wake up the processor when in a
//! low power mode.
//!
//! @param irq_id ID of the interrupt to mask/unmask.
//! @param doEnable Pass true to unmask the source ID.
void ccm_set_lpm_wakeup_source(uint32_t irq_id, bool doEnable);
#if defined(__cplusplus)
}
#endif
//! @}
#endif
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

8
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/interrupt.c
View File

@ -27,19 +27,19 @@ void EnableLocalInterrupt(unsigned long level)
return;
}
int32_t ArchEnableHwIrq(uint32_t irq_num)
int32_t ArchEnableHwIrq(uint32_t irq_num, uint32_t cpu_id)
{
// gic_set_irq_priority(irq_num, priority);
gic_set_irq_security(irq_num, false); // set IRQ as non-secure
// gic_set_cpu_target(irq_num, CPU_0, true);
gic_set_cpu_target(irq_num, cpu_id, true);
gic_enable_irq(irq_num, true);
return 0;
}
int32_t ArchDisableHwIrq(uint32_t irq_num)
int32_t ArchDisableHwIrq(uint32_t irq_num, uint32_t cpu_id)
{
gic_enable_irq(irq_num, false);
// gic_set_cpu_target(irq_num, CPU_0, false);
gic_set_cpu_target(irq_num, cpu_id, false);
return 0;
}

285
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/mmu.c Normal file
View File

@ -0,0 +1,285 @@
/*
* Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!
* @file mmu.c
* @brief System memory arangement.
*/
#include "cortex_a9.h"
#include "mmu.h"
#include "arm_cp_registers.h"
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! @brief Size in bytes of the first-level page table.
#define MMU_L1_PAGE_TABLE_SIZE (16 * 1024)
//! @brief First-level 1MB section descriptor entry.
typedef union mmu_l1_section {
uint32_t u;
struct {
uint32_t id:2; //!< ID
uint32_t b:1; //!< Bufferable
uint32_t c:1; //!< Cacheable
uint32_t xn:1; //!< Execute-not
uint32_t domain:4; //!< Domain
uint32_t _impl_defined:1; //!< Implementation defined, should be zero.
uint32_t ap1_0:2; //!< Access permissions AP[1:0]
uint32_t tex:3; //!< TEX remap
uint32_t ap2:1; //!< Access permissions AP[2]
uint32_t s:1; //!< Shareable
uint32_t ng:1; //!< Not-global
uint32_t _zero:1; //!< Should be zero.
uint32_t ns:1; //!< Non-secure
uint32_t address:12; //!< Physical base address
};
} mmu_l1_section_t;
enum {
kMMU_L1_Section_ID = 2, //!< ID value for a 1MB section first-level entry.
kMMU_L1_Section_Address_Shift = 20 //!< Bit offset of the physical base address field.
};
////////////////////////////////////////////////////////////////////////////////
// Externs
////////////////////////////////////////////////////////////////////////////////
extern char __l1_page_table_start;
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
void mmu_enable()
{
// invalidate all tlb
arm_unified_tlb_invalidate();
// read SCTLR
uint32_t sctlr;
_ARM_MRC(15, 0, sctlr, 1, 0, 0);
// set MMU enable bit
sctlr |= BM_SCTLR_M;
// write modified SCTLR
_ARM_MCR(15, 0, sctlr, 1, 0, 0);
}
void mmu_disable()
{
// read current SCTLR
uint32_t sctlr;
_ARM_MRC(15, 0, sctlr, 1, 0, 0);
// clear MMU enable bit
sctlr &=~ BM_SCTLR_M;
// write modified SCTLR
_ARM_MCR(15, 0, sctlr, 1, 0, 0);
}
void mmu_init()
{
// Get the L1 page table base address.
uint32_t * table = (uint32_t *)&__l1_page_table_start;
uint32_t share_attr = kShareable;
// write table address to TTBR0
_ARM_MCR(15, 0, table, 2, 0, 0);
// set Client mode for all Domains
uint32_t dacr = 0x55555555;
_ARM_MCR(15, 0, dacr, 3, 0, 0); // MCR p15, 0, <Rd>, c3, c0, 0 ; Write DACR
// Clear the L1 table.
bzero(table, MMU_L1_PAGE_TABLE_SIZE);
// Create default mappings.
mmu_map_l1_range(0x00000000, 0x00000000, 0x00900000, kStronglyOrdered, kShareable, kRWAccess); // ROM and peripherals
mmu_map_l1_range(0x00900000, 0x00900000, 0x00100000, kStronglyOrdered, kShareable, kRWAccess); // OCRAM
mmu_map_l1_range(0x00a00000, 0x00a00000, 0x0f600000, kStronglyOrdered, kShareable, kRWAccess); // More peripherals
// Check whether SMP is enabled. If it is not, then we don't want to make SDRAM shareable.
uint32_t actlr = 0x0;
_ARM_MRC(15, 0, actlr, 1, 0, 1);
if (actlr & BM_ACTLR_SMP)
{
share_attr = kShareable;
}
else
{
share_attr = kNonshareable;
}
#if defined(CHIP_MX6DQ) || defined(CHIP_MX6SDL)
mmu_map_l1_range(0x10000000, 0x10000000, 0x80000000, kOuterInner_WB_WA, share_attr, kRWAccess); // 2GB DDR
#elif defined(CHIP_MX6SL)
mmu_map_l1_range(0x80000000, 0x80000000, 0x40000000, kOuterInner_WB_WA, share_attr, kRWAccess); // 1GB DDR
#else
#error Unknown chip type!
#endif
}
void mmu_map_l1_range(uint32_t pa, uint32_t va, uint32_t length, mmu_memory_type_t memoryType, mmu_shareability_t isShareable, mmu_access_t access)
{
register mmu_l1_section_t entry;
entry.u = 0;
// Set constant attributes.
entry.id = kMMU_L1_Section_ID;
entry.xn = 0; // Allow execution
entry.domain = 0; // Domain 0
entry.ng = 0; // Global
entry.ns = 0; // Secure
// Set attributes based on the selected memory type.
switch (memoryType)
{
case kStronglyOrdered:
entry.c = 0;
entry.b = 0;
entry.tex = 0;
entry.s = 1; // Ignored
break;
case kDevice:
if (isShareable)
{
entry.c = 0;
entry.b = 1;
entry.tex = 0;
entry.s = 1; // Ignored
}
else
{
entry.c = 0;
entry.b = 0;
entry.tex = 2;
entry.s = 0; // Ignored
}
break;
case kOuterInner_WB_WA:
entry.c = 1;
entry.b = 1;
entry.tex = 1;
entry.s = isShareable;
break;
case kOuterInner_WT:
entry.c = 1;
entry.b = 0;
entry.tex = 0;
entry.s = isShareable;
break;
case kNoncacheable:
entry.c = 0;
entry.b = 0;
entry.tex = 1;
entry.s = isShareable;
break;
}
// Set attributes from specified access mode.
switch (access)
{
case kNoAccess:
entry.ap2 = 0;
entry.ap1_0 = 0;
break;
case kROAccess:
entry.ap2 = 1;
entry.ap1_0 = 3;
break;
case kRWAccess:
entry.ap2 = 0;
entry.ap1_0 = 3;
break;
}
// Get the L1 page table base address.
uint32_t * table = (uint32_t *)&__l1_page_table_start;
// Convert addresses to 12-bit bases.
uint32_t vbase = va >> kMMU_L1_Section_Address_Shift;
uint32_t pbase = pa >> kMMU_L1_Section_Address_Shift;
uint32_t entries = length >> kMMU_L1_Section_Address_Shift;
// Fill in L1 page table entries.
for (; entries > 0; ++pbase, ++vbase, --entries)
{
entry.address = pbase;
table[vbase] = entry.u;
}
// Invalidate TLB
arm_unified_tlb_invalidate();
}
bool mmu_virtual_to_physical(uint32_t virtualAddress, uint32_t * physicalAddress)
{
uint32_t pa = 0;
// VA to PA translation with privileged read permission check
_ARM_MCR(15, 0, virtualAddress & 0xfffffc00, 7, 8, 0);
// Read PA register
_ARM_MRC(15, 0, pa, 7, 4, 0);
// First bit of returned value is Result of conversion (0 is successful translation)
if (pa & 1)
{
// We can try write permission also
// VA to PA translation with privileged write permission check
_ARM_MCR(15, 0, virtualAddress & 0xfffffc00, 7, 8, 1);
// Read PA register
_ARM_MRC(15, 0, pa, 7, 4, 0);
// First bit of returned value is Result of conversion (0 is successful translation)
if (pa & 1)
{
return false;
}
}
if (physicalAddress)
{
// complete address returning base + offset
pa = (pa & 0xfffff000) | (virtualAddress & 0x00000fff);
*physicalAddress = pa;
}
return true;
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

157
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/mmu.h Normal file
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@ -0,0 +1,157 @@
/*
* Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//! @addtogroup diag_mmu
//! @{
/*!
* @file mmu.h
* @brief System memory arrangement.
*/
#ifndef _MMU_H_
#define _MMU_H_
#include "sdk.h"
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! @brief Memory region attributes.
typedef enum _mmu_memory_type
{
kStronglyOrdered,
kDevice,
kOuterInner_WB_WA,
kOuterInner_WT,
kNoncacheable,
} mmu_memory_type_t;
//! @brief Memory region shareability options.
typedef enum _mmu_shareability
{
kShareable = 1,
kNonshareable = 0
} mmu_shareability_t;
//! @brief Access permissions for a memory region.
typedef enum _mmu_access
{
kNoAccess,
kROAccess,
kRWAccess
} mmu_access_t;
////////////////////////////////////////////////////////////////////////////////
// Prototypes
////////////////////////////////////////////////////////////////////////////////
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Enable the MMU.
*
* The L1 page tables and MMU settings must have already been configured by
* calling mmu_init() before the MMU is enabled.
*/
void mmu_enable();
/*!
* @brief Disable the MMU.
*/
void mmu_disable();
/*!
* @brief Set up the default first-level page table.
*
* Initializes the L1 page table with the following regions:
* - 0x00000000...0x00900000 : ROM and peripherals, strongly-ordered
* - 0x00900000...0x00a00000 : OCRAM, strongly-ordered
* - For MX6DQ or MX6SDL: 0x10000000...0x90000000 : DDR, normal, outer inner, write-back, write-allocate
* - For MX6SL: 0x80000000...0xc0000000 : DDR, normal, outer inner, write-back, write-allocate
*
* If the CPU is participating in SMP, then the DDR regions are made shareable. Otherwise they
* are marked as non-shareable.
*
* The TTBR0 register is set to the base of the L1 table.
*
* All memory domains are configured to allow client access. However, note that only domain 0 is
* used by mmu_map_l1_range().
*/
void mmu_init();
/*!
* @brief Maps a range of memory in the first-level page table.
*
* Entries in the first-level page table are filled in for the range of virtual addresses
* starting at @a va and continuing for @a length bytes. These virtual addreses are mapped
* to the physical addresses starting at @a pa and continuing for @a length bytes. All table
* entries for the range of mapped memory have the same attributes, which are selected with
* the @a memoryType, @a isShareable, and @a access parameters.
*
* @param pa The base physical address of the range to which the virtual address will be mapped.
* @param va The base virtual address of the range.
* @param length The size of the range to be mapped, in bytes. This value must be divisible by 1MB.
* @param memoryType The type of the memory region. This controls caching, buffering, ordering of
* memory accesses, and other attributes of the region.
* @param isShareable The shareability of the physical memory. Ignored for strongly-ordered memory.
* @param access Access permissions.
*/
void mmu_map_l1_range(uint32_t pa, uint32_t va, uint32_t length, mmu_memory_type_t memoryType, mmu_shareability_t isShareable, mmu_access_t access);
/*!
* @brief Convert virtual address to physical.
*
* First attempts a priviledged read translation for the current security mode. If that fails,
* a priviledged write translation, also for the current security mode, is attempted. If this
* second attempt at translation fails, then false will be returned.
*
* @param virtualAddress Virtual address to convert to a physical address.
* @param[out] physicalAddress This parameter is filled in with the physical address corresponding
* to the virtual address passed in @a virtualAddress.
* @retval true The address returned through @a physicalAddress is valid.
* @retval false The conversion failed for some reason.
*/
bool mmu_virtual_to_physical(uint32_t virtualAddress, uint32_t * physicalAddress);
#if defined(__cplusplus)
}
#endif
//! @}
#endif // _MMU_H_
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

1
Ubiquitous/XiZi_AIoT/path_kernel.mk
View File

@ -24,6 +24,7 @@ KERNELPATHS += \
-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9 \
-I$(KERNEL_ROOT)/hardkernel/abstraction \
-I$(KERNEL_ROOT)/include \
-I$(BSP_ROOT)/third_party_driver/include \
-I$(BSP_ROOT)/include
ifeq ($(CONFIG_RESOURCES_LWIP),y)

2
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile
View File

@ -1,6 +1,6 @@
SRC_FILES := board.c ivt.c
SRC_DIR := third_party_driver
SRC_DIR := common third_party_driver

10
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/board.c
View File

@ -1,4 +1,10 @@
void start_kernel()
#include <isr.h>
extern void platform_init(void);
extern void print_version(void);
void init()
{
SysInitIsrManager();
platform_init();
print_version();
}

0
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/common/Kconfig Normal file
View File

4
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/common/Makefile Normal file
View File

@ -0,0 +1,4 @@
SRC_FILES := platform_init.c print_clock_info.c print_version.c
SRC_DIR :=
include $(KERNEL_ROOT)/compiler.mk

83
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/common/platform_init.c Executable file
View File

@ -0,0 +1,83 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
// #include "board_io_expanders.h"
#include "platform_init.h"
#include <cortex_a9.h>
#include <mmu.h>
#include <registers/regsuart.h>
uint32_t g_debug_uart_port = HW_UART4;
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
void platform_init(void)
{
enable_neon_fpu();
disable_strict_align_check();
mmu_init();
// Map some SDRAM for DMA
#if defined(BOARD_EVB)
mmu_map_l1_range(0x30000000, 0x30000000, 0x70000000, kNoncacheable, kShareable, kRWAccess);
#elif defined(BOARD_SMART_DEVICE)
mmu_map_l1_range(0x20000000, 0x20000000, 0x30000000, kNoncacheable, kShareable, kRWAccess);
#endif
// Enable interrupts. Until this point, the startup code has left interrupts disabled.
gic_init();
arm_set_interrupt_state(true);
// Initialize clock sources, dividers, ...
ccm_init();
// Configure the EPIT timer used for system delay function.
system_time_init();
// Initialize the debug/console UART
uart_init(g_debug_uart_port, 115200, PARITY_NONE, STOPBITS_ONE, EIGHTBITS, FLOWCTRL_OFF);
// flush UART RX FIFO
uint8_t c;
do {
c = uart_getchar(g_debug_uart_port);
} while (c != NONE_CHAR);
// Some init for the board
// board_ioexpander_init();
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

55
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/common/platform_init.h Normal file
View File

@ -0,0 +1,55 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__PLATFORM_INIT_H__)
#define __PLATFORM_INIT_H__
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
#if defined(__cplusplus)
extern "C" {
#endif
//! @brief Do basic hardware initialization to make the system usable.
//!
//! Performs minimal initialization to enable most drivers to work. The GIC,
//! CCM, and UART drivers are inited. The systme timer is inited. And
//! board_ioexpander_init() is called.
void platform_init(void);
#if defined(__cplusplus)
}
#endif
#endif // __PLATFORM_INIT_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

129
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/common/print_clock_info.c Normal file
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@ -0,0 +1,129 @@
/*
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "print_clock_info.h"
#include <ccm_pll.h>
#include <registers/regsuart.h>
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
extern uint32_t g_debug_uart_port;
void show_freq(void)
{
printf("========== Clock frequencies ===========\n");
printf("CPU: %ld kHz\n", get_main_clock(CPU_CLK)/1000);
printf("DDR: %ld kHz\n", get_main_clock(MMDC_CH0_AXI_CLK)/1000);
printf("IPG: %ld kHz\n", get_main_clock(IPG_CLK)/1000);
peri_clocks_t clk = UART1_MODULE_CLK + (g_debug_uart_port - HW_UART1);
printf("Debug UART: %ld Hz\n", get_peri_clock(clk));
printf("========================================\n\n");
}
//! @todo Rewrite for MMDC controller. This code is currently for MX53.
void show_ddr_config(void)
{
#if 0
uint32_t temp1, dsiz, row, col, cs_info;
uint32_t temp2, num_banks, ddr_type;
uint32_t density, megabyte;
uint32_t num_rows = 1, num_cols = 1, num_dsiz = 1, i = 1;
printf("========== DDR configuration ===========\n");
megabyte = 1024 * 1024;
/* read ESDCTL and gather information */
temp1 = readl(ESDCTL_REGISTERS_BASE_ADDR + 0x00);
dsiz = ((temp1 & (0x00030000)) >> 16);
/*Calculate dsize */
while (i <= dsiz) {
num_dsiz *= 2;
i++;
}
dsiz = 16 * num_dsiz;
row = ((temp1 & (0x07000000)) >> 24) + 11;
col = ((temp1 & (0x00700000)) >> 20) + 9;
cs_info = (temp1 & (0xC0000000)) >> 30;
/* read ESDMISC to get # of BANK info */
temp2 = readl(ESDCTL_REGISTERS_BASE_ADDR + 0x18);
num_banks = (!((temp2 & (0x00000020)) >> 5)) * 4 + 4;
ddr_type = (temp2 & (0x00000018)) >> 3;
printf("data bits: %d, num_banks: %d \n", dsiz, num_banks);
printf("row: %d, col: %d \n", row, col);
if (ddr_type == 1)
printf("DDR type is DDR2 \n");
else if (ddr_type == 2)
printf("DDR type is LPDDR2\n");
else
printf("DDR type is DDR3 \n");
if (cs_info == 0)
printf("No chip select is enabled \n");
else if (cs_info == 2)
printf("Chip select CSD0 is used \n");
else if (cs_info == 1)
printf("Chip select CSD1 is used \n");
else
printf("Both chip select CSD0 and CSD1 are used \n");
/* Now calculate the DDR density per chip select */
i = 1;
/* First need to calculate the number of rows and cols 2^row and 2^col */
while (i <= row) {
num_rows *= 2;
i++;
}
debug_printf("num_rows= %d\n", num_rows);
i = 1;
while (i <= col) {
num_cols *= 2;
i++;
}
debug_printf("num_cols= %d\n", num_cols);
density = num_rows * num_cols / megabyte;
density = density * dsiz * num_banks / 8;
printf("Density per chip select: %dMB \n", density);
printf("========================================\n\n");
#endif // 0
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

68
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/common/print_clock_info.h Normal file
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@ -0,0 +1,68 @@
/*
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__PRINT_CLOCK_INFO_H__)
#define __PRINT_CLOCK_INFO_H__
#include "sdk.h"
//! @addtogroup app_common
//! @{
////////////////////////////////////////////////////////////////////////////////
// API
////////////////////////////////////////////////////////////////////////////////
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Display module frequency
*/
void show_freq(void);
/*!
* @brief Display the board's DDR configuration
*/
void show_ddr_config(void);
#if defined(__cplusplus)
}
#endif
//! @}
#endif // __PRINT_CLOCK_INFO_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

73
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@ -0,0 +1,73 @@
/*
* Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!
* @file print_version.c
* @brief Contains function to print out the app release version.
*/
#include "sdk.h"
#include "sdk_version.h"
// #include "board_id/board_id.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
/*!
* print out the diag release version info
*
*/
void print_version(void)
{
// char chip_str[64] = { 0 };
// char chip_rev_str[64] = { 0 };
// char board_str[64] = { 0 };
// char board_rev_str[64] = { 0 };
// fsl_board_id_t fsl_board_id = get_board_id();
// chip_name(chip_str, fsl_board_id.B.CHIP_TYPE_ID, false);
// chip_revision(chip_rev_str, fsl_board_id.B.CHIP_REV_MAJOR, fsl_board_id.B.CHIP_REV_MINOR);
// board_name(board_str, BOARD_TYPE);
// board_revision(board_rev_str, BOARD_REVISION);
// printf("\n\n\n\n");
// printf("**************************************************************************\n");
// printf(" Platform SDK (%s) for %s %s %s %s\n", k_sdk_version, chip_str, chip_rev_str,
// board_str, board_rev_str);
// printf(" Build: %s, %s\n", __DATE__, __TIME__);
// printf(" %s\n", k_sdk_copyright);
printf("**************************************************************************\n\n");
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

59
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/common/print_version.h Normal file
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@ -0,0 +1,59 @@
/*
* Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!
* @file print_version.h
* @brief release version define - should be changed for each release
*/
#if !defined(__PRINT_VERSION_H__)
#define __PRINT_VERSION_H__
////////////////////////////////////////////////////////////////////////////////
// Prototypes
////////////////////////////////////////////////////////////////////////////////
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Prints the version header to the console.
*/
void print_version(void);
#if defined(__cplusplus)
}
#endif
#endif // __PRINT_VERSION_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

2
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/config.mk
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@ -15,7 +15,7 @@ endif
# export LINK_LWIP := $(KERNEL_ROOT)/resources/ethernet/LwIP/liblwip.a
# endif
export DEFINES := -DHAVE_CCONFIG_H
export DEFINES := -DHAVE_CCONFIG_H -DCHIP_MX6DQ
export USING_NEWLIB =1
export USING_VFS = 1

90
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/include/buffers.h Executable file
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@ -0,0 +1,90 @@
/*
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!
* @file buffers.h
* @definitions for ALL buffer memory space regions used by sdk drivers
*/
#define IPU_DEFAULT_WORK_CLOCK 264000000
#define IPU_DMA_MEMORY_START 0x40000000
#define IPU_DMA_MEMORY_END 0x43FFFFFF
#define HDMI_AUDIO_BUF_START 0x4fff0000
#define HDMI_AUDIO_BUF_END 0x4fff4000
#define CH23_EBA0 (IPU_DMA_MEMORY_START + 0x00000000)
#define CH23_EBA1 (IPU_DMA_MEMORY_START + 0x00400000)
#define CH27_EBA0 (IPU_DMA_MEMORY_START + 0x00800000)
#define CH27_EBA1 (IPU_DMA_MEMORY_START + 0x00C00000)
#define CH28_EBA0 (IPU_DMA_MEMORY_START + 0x01000000)
#define CH28_EBA1 (IPU_DMA_MEMORY_START + 0x01400000)
#define CH0_EBA0 (IPU_DMA_MEMORY_START + 0x01800000)
#define CH0_EBA1 (IPU_DMA_MEMORY_START + 0x01C00000)
/*for dual video playback*/
#define IPU1_CH23_EBA0 CH23_EBA0
#define IPU1_CH23_EBA1 CH23_EBA1
#define IPU2_CH23_EBA0 CH27_EBA0
#define IPU2_CH23_EBA1 CH27_EBA1
// for video playback after resizing&rotation
#define CH22_EBA0 (IPU_DMA_MEMORY_START + 0x01800000)
#define CH22_EBA1 (IPU_DMA_MEMORY_START + 0x01C00000)
#define CH21_EBA0 (IPU_DMA_MEMORY_START + 0x02000000)
#define CH21_EBA1 (IPU_DMA_MEMORY_START + 0x02400000)
#define CH20_EBA0 (IPU_DMA_MEMORY_START + 0x02800000)
#define CH20_EBA1 (IPU_DMA_MEMORY_START + 0x02C00000)
/* put the TWO video instance on different CS to
improve the performance.
*/
#define VPU_WORK_BUFFERS (0x44100000)
#define VIDEO_BUFFERS_START (0x48000000)
#define VIDEO_BUFFERS_END (0x4FFFFFFF)
/*OCRAM partition table*/
#define VPU_SEC_AXI_START 0x00910000
#define VPU_SEC_AXI_END 0x0091FFFF
/* OCRAM ADMA buffer */
#define USDHC_ADMA_BUFFER1 0x00907000
#define USDHC_ADMA_BUFFER2 0x00908000
#define USDHC_ADMA_BUFFER3 0x00909000
#define USDHC_ADMA_BUFFER4 0x0090A000
// USB buffers
#define QH_BUFFER 0x00908000 // internal RAM
#define TD_BUFFER 0x00908200 // internal RAM
#define SATA_PROTOCOL_BUFFER_BASE 0x0090a000
#define SATA_PROTOCOL_BUFFER_SIZE 0x1000
#define SATA_TRANSFER_BUFFER_BASE 0x0090c000

144
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/include/io.h Executable file
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@ -0,0 +1,144 @@
/*
* Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!
* @file io.h
* @brief Register access macros.
*
* @ingroup diag_init
*/
#ifndef __IO_H__
#define __IO_H__
#include "sdk_types.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "sdk.h"
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! @name Register read functions
//@{
#define reg8_read(addr) *((volatile uint8_t *)(addr))
#define reg16_read(addr) *((volatile uint16_t *)(addr))
#define reg32_read(addr) *((volatile uint32_t *)(addr))
//@}
//! @name Register write functions
//@{
#define reg8_write(addr,val) *((volatile uint8_t *)(addr)) = (val)
#define reg16_write(addr,val) *((volatile uint16_t *)(addr)) = (val)
#define reg32_write(addr,val) *((volatile uint32_t *)(addr)) = (val)
//@}
//! @name Memory read functions
//@{
#define mem8_read(addr) *((volatile uint8_t *)(addr))
#define mem16_read(addr) *((volatile uint16_t *)(addr))
#define mem32_read(addr) *((volatile uint32_t *)(addr))
//@}
//! @name Memory write functions
//@{
#define mem8_write(addr,val) *((volatile uint8_t *)(addr)) = (val)
#define mem16_write(addr,val) *((volatile uint16_t *)(addr)) = (val)
#define mem32_write(addr,val) *((volatile uint32_t *)(addr)) = (val)
//@}
//! @name Read functions
//@{
#define readb(a) reg8_read(a)
#define readw(a) reg16_read(a)
#define readl(a) reg32_read(a)
//@}
//! @name Write functrions
//!
//! The prefered method to access registers.
//@{
#define writeb(v, a) reg8_write(a, v)
#define writew(v, a) reg16_write(a, v)
#define writel(v, a) reg32_write(a, v)
//@}
//! @name Bit set/clear functions
//@{
#define reg8setbit(addr,bitpos) \
reg8_write((addr),(reg8_read((addr)) | (1<<(bitpos))))
#define reg16setbit(addr,bitpos) \
reg16_write((addr),(reg16_read((addr)) | (1<<(bitpos))))
#define reg32setbit(addr,bitpos) \
reg32_write((addr),(reg32_read((addr)) | (1<<(bitpos))))
#define reg8clrbit(addr,bitpos) \
reg8_write((addr),(reg8_read((addr)) & (0xFF ^ (1<<(bitpos)))))
#define reg16clrbit(addr,bitpos) \
reg16_write((addr),(reg16_read((addr)) & (0xFFFF ^ (1<<(bitpos)))))
#define reg32clrbit(addr,bitpos) \
reg32_write((addr),(reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos)))))
//@}
//! @name Masked write functions
//@{
#define reg8_write_mask(addr, data, mask) \
reg8_write((addr),((reg8_read(addr) & (~mask)) | (mask & data)))
#define reg16_write_mask(addr, data, mask) \
reg16_write((addr),((reg16_read(addr) & (~mask)) | (mask & data)))
#define reg32_write_mask(addr, data, mask) \
reg32_write((addr),((reg32_read(addr) & (~mask)) | (mask & data)))
#define gen_msk32(start, end) ((0xFFFFFFFF << (start)) ^ (0xFFFFFFFF << ((end + 1))))
#define reg32_set_field(addr, start, end, val) \
reg32_write_mask(addr, (val) << (start), gen_msk32((start, end)))
//@}
/*!
* This macro is used to get certain bit field from a number
*/
#define GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
/*!
* This macro is used to set certain bit field inside a number
*/
#define SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
#endif // __IO_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

124
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/include/iomux_config.h Normal file
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@ -0,0 +1,124 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: iomux_config.h
/* ------------------------------------------------------------------------------
* <auto-generated>
* This code was generated by a tool.
* Runtime Version:3.4.0.0
*
* Changes to this file may cause incorrect behavior and will be lost if
* the code is regenerated.
* </auto-generated>
* ------------------------------------------------------------------------------
*/
#ifndef _IOMUX_CONFIG_H_
#define _IOMUX_CONFIG_H_
// Board and Module IOMUXC configuration function prototypes.
#if defined(__cplusplus)
extern "C" {
#endif
// Board IOMUXC configuration function.
void iomux_config(void);
// Module IOMUXC configuration functions.
void arm_iomux_config(void);
void asrc_iomux_config(void);
void audmux_iomux_config(void);
void ccm_iomux_config(void);
void dcic_iomux_config(int instance);
void dcic1_iomux_config(void);
void dcic2_iomux_config(void);
void ecspi_iomux_config(int instance);
void ecspi1_iomux_config(void);
void ecspi2_iomux_config(void);
void ecspi3_iomux_config(void);
void ecspi4_iomux_config(void);
void ecspi5_iomux_config(void);
void eim_iomux_config(void);
void enet_iomux_config(void);
void epit_iomux_config(int instance);
void epit1_iomux_config(void);
void epit2_iomux_config(void);
void esai_iomux_config(void);
void flexcan_iomux_config(int instance);
void flexcan1_iomux_config(void);
void flexcan2_iomux_config(void);
void gpio_iomux_config(int instance);
void gpio1_iomux_config(void);
void gpio2_iomux_config(void);
void gpio3_iomux_config(void);
void gpio4_iomux_config(void);
void gpio5_iomux_config(void);
void gpio6_iomux_config(void);
void gpio7_iomux_config(void);
void gpmi_iomux_config(void);
void gpt_iomux_config(void);
void hdmi_iomux_config(void);
void i2c_iomux_config(int instance);
void i2c1_iomux_config(void);
void i2c2_iomux_config(void);
void i2c3_iomux_config(void);
void ipu_iomux_config(int instance);
void ipu1_iomux_config(void);
void ipu2_iomux_config(void);
void kpp_iomux_config(void);
void ldb_iomux_config(void);
void mipi_csi_iomux_config(void);
void mipi_dsi_iomux_config(void);
void mipi_hsi_iomux_config(void);
void mlb_iomux_config(void);
void mmdc_iomux_config(void);
void pcie_iomux_config(void);
void pmu_iomux_config(void);
void pwm_iomux_config(int instance);
void pwm1_iomux_config(void);
void pwm2_iomux_config(void);
void pwm3_iomux_config(void);
void pwm4_iomux_config(void);
void sata_phy_iomux_config(void);
void sdma_iomux_config(void);
void sjc_iomux_config(void);
void snvs_iomux_config(void);
void spdif_iomux_config(void);
void src_iomux_config(void);
void uart_iomux_config(int instance);
void uart1_iomux_config(void);
void uart2_iomux_config(void);
void uart3_iomux_config(void);
void uart4_iomux_config(void);
void uart5_iomux_config(void);
void usb_iomux_config(void);
void usdhc_iomux_config(int instance);
void usdhc1_iomux_config(void);
void usdhc2_iomux_config(void);
void usdhc3_iomux_config(void);
void usdhc4_iomux_config(void);
void wdog_iomux_config(int instance);
void wdog1_iomux_config(void);
void wdog2_iomux_config(void);
void xtalosc_iomux_config(void);
#if defined(__cplusplus)
}
#endif
#endif // _IOMUX_CONFIG_H_

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: iomux_define.h
#ifndef _IOMUX_DEFINE_H_
#define _IOMUX_DEFINE_H_
// IOMUXC_SW_MUX_CTL_PAD_*
// SION
#define SION_DISABLED 0x0
#define SION_ENABLED 0x1
// MUX_MODE
#define ALT0 0x0
#define ALT1 0x1
#define ALT2 0x2
#define ALT3 0x3
#define ALT4 0x4
#define ALT5 0x5
#define ALT6 0x6
#define ALT7 0x7
// IOMUXC_SW_PAD_CTL_PAD_*
// IOMUXC_SW_PAD_CTL_GRP_*
// HYS
#define HYS_DISABLED 0x0
#define HYS_ENABLED 0x1
// PUS
#define PUS_100KOHM_PD 0x0
#define PUS_47KOHM_PU 0x1
#define PUS_100KOHM_PU 0x2
#define PUS_22KOHM_PU 0x3
// PUE
#define PUE_KEEP 0x0
#define PUE_PULL 0x1
// PKE
#define PKE_DISABLED 0x0
#define PKE_ENABLED 0x1
// ODE
#define ODE_DISABLED 0x0
#define ODE_ENABLED 0x1
// SPEED
#define SPD_TBD 0x0
#define SPD_50MHZ 0x1
#define SPD_100MHZ 0x2
#define SPD_200MHZ 0x3
// DSE
#define DSE_DISABLED 0x0
#define DSE_240OHM 0x1
#define DSE_120OHM 0x2
#define DSE_80OHM 0x3
#define DSE_60OHM 0x4
#define DSE_48OHM 0x5
#define DSE_40OHM 0x6
#define DSE_34OHM 0x7
// SRE
#define SRE_SLOW 0x0
#define SRE_FAST 0x1
// ODT
#define ODT_OFF 0x0
#define ODT_120OHM 0x1
#define ODT_60OHM 0x2
#define ODT_40OHM 0x3
#define ODT_30OHM 0x4
#define ODT_RES5 0x5
#define ODT_20OHM 0x6
#define ODT_RES7 0x7
// DDR_INPUT
#define DDR_INPUT_CMOS 0x0
#define DDR_INPUT_DIFF 0x1
// DDR_SEL
#define DDR_SEL_RES0 0x0
#define DDR_SEL_RES1 0x1
#define DDR_SEL_LPDDR2 0x2
#define DDR_SEL_DDR3 0x3
// IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT
// DAISY
#define SEL_KEY_ROW3_ALT1 0x0
#define SEL_GPIO_0_ALT3 0x1
#define SEL_GPIO_18_ALT4 0x2
// IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT
// DAISY
#define SEL_SD2_DAT0_ALT3 0x0
#define SEL_DISP0_DAT23_ALT3 0x1
// IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT
// DAISY
#define SEL_SD2_DAT2_ALT3 0x0
#define SEL_DISP0_DAT21_ALT3 0x1
// IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT
// DAISY
#define SEL_DISP0_DAT19_ALT4 0x0
#define SEL_SD2_CMD_ALT3 0x1
// IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT
// DAISY
#define SEL_DISP0_DAT18_ALT4 0x0
#define SEL_SD2_CLK_ALT3 0x1
// IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT
// DAISY
#define SEL_DISP0_DAT20_ALT3 0x0
#define SEL_SD2_DAT3_ALT3 0x1
// IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT
// DAISY
#define SEL_SD2_DAT1_ALT3 0x0
#define SEL_DISP0_DAT22_ALT3 0x1
// IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT
// DAISY
#define SEL_DISP0_DAT19_ALT3 0x0
#define SEL_KEY_ROW1_ALT2 0x1
// IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT
// DAISY
#define SEL_DISP0_DAT17_ALT3 0x0
#define SEL_KEY_ROW0_ALT2 0x1
// IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT
// DAISY
#define SEL_EIM_D25_ALT6 0x0
#define SEL_DISP0_DAT14_ALT3 0x1
// IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT
// DAISY
#define SEL_EIM_D24_ALT6 0x0
#define SEL_DISP0_DAT13_ALT3 0x1
// IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT
// DAISY
#define SEL_DISP0_DAT16_ALT3 0x0
#define SEL_KEY_COL0_ALT2 0x1
// IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT
// DAISY
#define SEL_DISP0_DAT18_ALT3 0x0
#define SEL_KEY_COL1_ALT2 0x1
// IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT
// DAISY
#define SEL_KEY_ROW2_ALT2 0x0
#define SEL_GPIO_8_ALT3 0x1
#define SEL_SD3_CLK_ALT2 0x2
// IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT
// DAISY
#define SEL_KEY_ROW4_ALT0 0x0
#define SEL_SD3_DAT1_ALT2 0x1
// IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT
// DAISY
#define SEL_EIM_EB2_ALT2 0x0
#define SEL_EIM_DA13_ALT2 0x1
// IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT
// DAISY
#define SEL_EIM_EB0_ALT4 0x0
#define SEL_GPIO_17_ALT2 0x1
// IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT
// DAISY
#define SEL_EIM_D16_ALT1 0x0
#define SEL_DISP0_DAT20_ALT2 0x1
#define SEL_KEY_COL0_ALT0 0x2
#define SEL_CSI0_DAT4_ALT2 0x3
// IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT
// DAISY
#define SEL_EIM_D17_ALT1 0x0
#define SEL_DISP0_DAT22_ALT2 0x1
#define SEL_KEY_COL1_ALT0 0x2
#define SEL_CSI0_DAT6_ALT2 0x3
// IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT
// DAISY
#define SEL_EIM_D18_ALT1 0x0
#define SEL_DISP0_DAT21_ALT2 0x1
#define SEL_KEY_ROW0_ALT0 0x2
#define SEL_CSI0_DAT5_ALT2 0x3
// IOMUXC_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT
// DAISY
#define SEL_EIM_EB2_ALT1 0x0
#define SEL_DISP0_DAT23_ALT2 0x1
#define SEL_KEY_ROW1_ALT0 0x2
#define SEL_CSI0_DAT7_ALT2 0x3
// IOMUXC_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT
// DAISY
#define SEL_EIM_D19_ALT1 0x0
#define SEL_DISP0_DAT15_ALT2 0x1
#define SEL_KEY_COL2_ALT0 0x2
// IOMUXC_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT
// DAISY
#define SEL_EIM_D24_ALT3 0x0
#define SEL_KEY_ROW2_ALT0 0x1
// IOMUXC_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT
// DAISY
#define SEL_EIM_D25_ALT3 0x0
#define SEL_KEY_COL3_ALT0 0x1
// IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT
// DAISY
#define SEL_EIM_CS0_ALT2 0x0
#define SEL_DISP0_DAT19_ALT2 0x1
#define SEL_CSI0_DAT8_ALT2 0x2
// IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT
// DAISY
#define SEL_EIM_OE_ALT2 0x0
#define SEL_DISP0_DAT17_ALT2 0x1
#define SEL_CSI0_DAT10_ALT2 0x2
// IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT
// DAISY
#define SEL_EIM_CS1_ALT2 0x0
#define SEL_DISP0_DAT16_ALT2 0x1
#define SEL_CSI0_DAT9_ALT2 0x2
// IOMUXC_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT
// DAISY
#define SEL_EIM_RW_ALT2 0x0
#define SEL_DISP0_DAT18_ALT2 0x1
#define SEL_CSI0_DAT11_ALT2 0x2
// IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT
// DAISY
#define SEL_EIM_LBA_ALT2 0x0
#define SEL_DISP0_DAT15_ALT3 0x1
// IOMUXC_ECSPI4_IPP_IND_SS_B_0_SELECT_INPUT
// DAISY
#define SEL_EIM_D20_ALT1 0x0
#define SEL_EIM_D29_ALT2 0x1
// IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT
// DAISY
#define SEL_SD1_CLK_ALT1 0x0
#define SEL_SD2_CLK_ALT1 0x1
// IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT
// DAISY
#define SEL_SD2_DAT0_ALT1 0x0
#define SEL_SD1_DAT0_ALT1 0x1
// IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT
// DAISY
#define SEL_SD1_CMD_ALT1 0x0
#define SEL_SD2_CMD_ALT1 0x1
// IOMUXC_ECSPI5_IPP_IND_SS_B_0_SELECT_INPUT
// DAISY
#define SEL_SD2_DAT1_ALT1 0x0
#define SEL_SD1_DAT1_ALT1 0x1
// IOMUXC_ECSPI5_IPP_IND_SS_B_1_SELECT_INPUT
// DAISY
#define SEL_SD2_DAT2_ALT1 0x0
#define SEL_SD1_DAT2_ALT1 0x1
// IOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT
// DAISY
#define SEL_RGMII_TX_CTL_ALT7 0x0
#define SEL_GPIO_16_ALT2 0x1
// IOMUXC_ENET_IPP_IND_MAC0_MDIO_SELECT_INPUT
// DAISY
#define SEL_ENET_MDIO_ALT1 0x0
#define SEL_KEY_COL1_ALT1 0x1
// IOMUXC_ENET_IPP_IND_MAC0_RXCLK_SELECT_INPUT
// DAISY
#define SEL_RGMII_RXC_ALT1 0x0
#define SEL_GPIO_18_ALT1 0x1
// IOMUXC_ENET_IPP_IND_MAC0_RXDATA_0_SELECT_INPUT
// DAISY
#define SEL_RGMII_RD0_ALT1 0x0
#define SEL_ENET_RXD0_ALT1 0x1
// IOMUXC_ENET_IPP_IND_MAC0_RXDATA_1_SELECT_INPUT
// DAISY
#define SEL_RGMII_RD1_ALT1 0x0
#define SEL_ENET_RXD1_ALT1 0x1
// IOMUXC_ENET_IPP_IND_MAC0_RXDATA_2_SELECT_INPUT
// DAISY
#define SEL_RGMII_RD2_ALT1 0x0
#define SEL_KEY_COL2_ALT1 0x1
// IOMUXC_ENET_IPP_IND_MAC0_RXDATA_3_SELECT_INPUT
// DAISY
#define SEL_RGMII_RD3_ALT1 0x0
#define SEL_KEY_COL0_ALT1 0x1
// IOMUXC_ENET_IPP_IND_MAC0_RXEN_SELECT_INPUT
// DAISY
#define SEL_RGMII_RX_CTL_ALT1 0x0
#define SEL_ENET_CRS_DV_ALT1 0x1
// IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT
// DAISY
#define SEL_ENET_REF_CLK_ALT2 0x0
#define SEL_GPIO_9_ALT0 0x1
// IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT
// DAISY
#define SEL_ENET_RXD1_ALT2 0x0
#define SEL_GPIO_2_ALT0 0x1
// IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT
// DAISY
#define SEL_ENET_RX_ER_ALT2 0x0
#define SEL_GPIO_3_ALT0 0x1
// IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT
// DAISY
#define SEL_ENET_RXD0_ALT2 0x0
#define SEL_GPIO_4_ALT0 0x1
// IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT
// DAISY
#define SEL_ENET_MDIO_ALT2 0x0
#define SEL_GPIO_1_ALT0 0x1
// IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT
// DAISY
#define SEL_ENET_CRS_DV_ALT2 0x0
#define SEL_GPIO_6_ALT0 0x1
// IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT
// DAISY
#define SEL_GPIO_17_ALT0 0x0
#define SEL_NANDF_CS2_ALT2 0x1
// IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT
// DAISY
#define SEL_GPIO_18_ALT0 0x0
#define SEL_NANDF_CS3_ALT2 0x1
// IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT
// DAISY
#define SEL_ENET_TXD1_ALT2 0x0
#define SEL_GPIO_5_ALT0 0x1
// IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT
// DAISY
#define SEL_ENET_TX_EN_ALT2 0x0
#define SEL_GPIO_16_ALT0 0x1
// IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT
// DAISY
#define SEL_ENET_TXD0_ALT2 0x0
#define SEL_GPIO_7_ALT0 0x1
// IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT
// DAISY
#define SEL_ENET_MDC_ALT2 0x0
#define SEL_GPIO_8_ALT0 0x1
// IOMUXC_HDMI_TX_ICECIN_SELECT_INPUT
// DAISY
#define SEL_EIM_A25_ALT6 0x0
#define SEL_KEY_ROW2_ALT6 0x1
// IOMUXC_HDMI_TX_II2C_MSTH13TDDC_SCLIN_SELECT_INPUT
// DAISY
#define SEL_EIM_EB2_ALT4 0x0
#define SEL_KEY_COL3_ALT2 0x1
// IOMUXC_HDMI_TX_II2C_MSTH13TDDC_SDAIN_SELECT_INPUT
// DAISY
#define SEL_EIM_D16_ALT4 0x0
#define SEL_KEY_ROW3_ALT2 0x1
// IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT
// DAISY
#define SEL_EIM_D21_ALT6 0x0
#define SEL_CSI0_DAT9_ALT4 0x1
// IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT
// DAISY
#define SEL_EIM_D28_ALT1 0x0
#define SEL_CSI0_DAT8_ALT4 0x1
// IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT
// DAISY
#define SEL_EIM_EB2_ALT6 0x0
#define SEL_KEY_COL3_ALT4 0x1
// IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT
// DAISY
#define SEL_EIM_D16_ALT6 0x0
#define SEL_KEY_ROW3_ALT4 0x1
// IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT
// DAISY
#define SEL_EIM_D17_ALT6 0x0
#define SEL_GPIO_3_ALT2 0x1
#define SEL_GPIO_5_ALT6 0x2
// IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT
// DAISY
#define SEL_EIM_D18_ALT6 0x0
#define SEL_GPIO_6_ALT2 0x1
#define SEL_GPIO_16_ALT6 0x2
// IOMUXC_IPU2_IPP_IND_SENS1_DATA_10_SELECT_INPUT
// DAISY
#define SEL_EIM_D22_ALT3 0x0
#define SEL_EIM_EB1_ALT2 0x1
// IOMUXC_IPU2_IPP_IND_SENS1_DATA_11_SELECT_INPUT
// DAISY
#define SEL_EIM_D21_ALT3 0x0
#define SEL_EIM_EB0_ALT2 0x1
// IOMUXC_IPU2_IPP_IND_SENS1_DATA_12_SELECT_INPUT
// DAISY
#define SEL_EIM_D28_ALT3 0x0
#define SEL_EIM_A17_ALT2 0x1
// IOMUXC_IPU2_IPP_IND_SENS1_DATA_13_SELECT_INPUT
// DAISY
#define SEL_EIM_D27_ALT3 0x0
#define SEL_EIM_A18_ALT2 0x1
// IOMUXC_IPU2_IPP_IND_SENS1_DATA_14_SELECT_INPUT
// DAISY
#define SEL_EIM_D26_ALT3 0x0
#define SEL_EIM_A19_ALT2 0x1
// IOMUXC_IPU2_IPP_IND_SENS1_DATA_15_SELECT_INPUT
// DAISY
#define SEL_EIM_D20_ALT3 0x0
#define SEL_EIM_A20_ALT2 0x1
// IOMUXC_IPU2_IPP_IND_SENS1_DATA_16_SELECT_INPUT
// DAISY
#define SEL_EIM_D19_ALT3 0x0
#define SEL_EIM_A21_ALT2 0x1
// IOMUXC_IPU2_IPP_IND_SENS1_DATA_17_SELECT_INPUT
// DAISY
#define SEL_EIM_D18_ALT3 0x0
#define SEL_EIM_A22_ALT2 0x1
// IOMUXC_IPU2_IPP_IND_SENS1_DATA_18_SELECT_INPUT
// DAISY
#define SEL_EIM_D16_ALT3 0x0
#define SEL_EIM_A23_ALT2 0x1
// IOMUXC_IPU2_IPP_IND_SENS1_DATA_19_SELECT_INPUT
// DAISY
#define SEL_EIM_EB2_ALT3 0x0
#define SEL_EIM_A24_ALT2 0x1
// IOMUXC_IPU2_IPP_IND_SENS1_DATA_EN_SELECT_INPUT
// DAISY
#define SEL_EIM_D23_ALT4 0x0
#define SEL_EIM_DA10_ALT2 0x1
// IOMUXC_IPU2_IPP_IND_SENS1_HSYNC_SELECT_INPUT
// DAISY
#define SEL_EIM_EB3_ALT4 0x0
#define SEL_EIM_DA11_ALT2 0x1
// IOMUXC_IPU2_IPP_IND_SENS1_PIX_CLK_SELECT_INPUT
// DAISY
#define SEL_EIM_D17_ALT3 0x0
#define SEL_EIM_A16_ALT2 0x1
// IOMUXC_IPU2_IPP_IND_SENS1_VSYNC_SELECT_INPUT
// DAISY
#define SEL_EIM_D29_ALT6 0x0
#define SEL_EIM_DA12_ALT2 0x1
// IOMUXC_KPP_IPP_IND_COL_5_SELECT_INPUT
// DAISY
#define SEL_GPIO_0_ALT2 0x0
#define SEL_GPIO_19_ALT0 0x1
#define SEL_CSI0_DAT4_ALT3 0x2
#define SEL_SD2_CLK_ALT2 0x3
// IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT
// DAISY
#define SEL_GPIO_9_ALT2 0x0
#define SEL_CSI0_DAT6_ALT3 0x1
#define SEL_SD2_DAT3_ALT2 0x2
// IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT
// DAISY
#define SEL_SD2_DAT1_ALT4 0x0
#define SEL_GPIO_4_ALT2 0x1
#define SEL_CSI0_DAT8_ALT3 0x2
// IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT
// DAISY
#define SEL_GPIO_1_ALT2 0x0
#define SEL_CSI0_DAT5_ALT3 0x1
#define SEL_SD2_CMD_ALT2 0x2
// IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT
// DAISY
#define SEL_SD2_DAT2_ALT4 0x0
#define SEL_GPIO_2_ALT2 0x1
#define SEL_CSI0_DAT7_ALT3 0x2
// IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT
// DAISY
#define SEL_SD2_DAT0_ALT4 0x0
#define SEL_GPIO_5_ALT2 0x1
#define SEL_CSI0_DAT9_ALT3 0x2
// IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT
// DAISY
#define SEL_ENET_TXD1_ALT0 0x0
#define SEL_GPIO_3_ALT7 0x1
// IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT
// DAISY
#define SEL_ENET_MDC_ALT0 0x0
#define SEL_GPIO_2_ALT7 0x1
// IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT
// DAISY
#define SEL_ENET_RXD1_ALT0 0x0
#define SEL_GPIO_6_ALT7 0x1
// IOMUXC_SDMA_EVENTS_14_SELECT_INPUT
// DAISY
#define SEL_DISP0_DAT16_ALT4 0x0
#define SEL_GPIO_17_ALT3 0x1
// IOMUXC_SDMA_EVENTS_15_SELECT_INPUT
// DAISY
#define SEL_DISP0_DAT17_ALT4 0x0
#define SEL_GPIO_18_ALT3 0x1
// IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT
// DAISY
#define SEL_EIM_D21_ALT7 0x0
#define SEL_ENET_RX_ER_ALT3 0x1
#define SEL_KEY_COL3_ALT6 0x2
#define SEL_GPIO_16_ALT4 0x3
// IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT
// DAISY
#define SEL_RGMII_TXC_ALT2 0x0
#define SEL_ENET_CRS_DV_ALT3 0x1
// IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT
// DAISY
#define SEL_EIM_D19_ALT4 0x0
#define SEL_EIM_D20_ALT4 0x1
#define SEL_SD3_DAT0_ALT1 0x2
#define SEL_SD3_DAT1_ALT1 0x3
// IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT
// DAISY
#define SEL_CSI0_DAT10_ALT3 0x0
#define SEL_CSI0_DAT11_ALT3 0x1
#define SEL_SD3_DAT7_ALT1 0x2
#define SEL_SD3_DAT6_ALT1 0x3
// IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT
// DAISY
#define SEL_EIM_D28_ALT4 0x0
#define SEL_EIM_D29_ALT4 0x1
#define SEL_SD3_CMD_ALT1 0x2
#define SEL_SD3_CLK_ALT1 0x3
#define SEL_SD4_DAT5_ALT2 0x4
#define SEL_SD4_DAT6_ALT2 0x5
// IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT
// DAISY
#define SEL_EIM_D26_ALT4 0x0
#define SEL_EIM_D27_ALT4 0x1
#define SEL_GPIO_7_ALT4 0x2
#define SEL_GPIO_8_ALT4 0x3
#define SEL_SD3_DAT5_ALT1 0x4
#define SEL_SD3_DAT4_ALT1 0x5
#define SEL_SD4_DAT4_ALT2 0x6
#define SEL_SD4_DAT7_ALT2 0x7
// IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT
// DAISY
#define SEL_EIM_D23_ALT2 0x0
#define SEL_EIM_EB3_ALT2 0x1
#define SEL_EIM_D30_ALT4 0x2
#define SEL_EIM_D31_ALT4 0x3
#define SEL_SD3_DAT3_ALT1 0x4
#define SEL_SD3_RST_ALT1 0x5
// IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT
// DAISY
#define SEL_EIM_D24_ALT2 0x0
#define SEL_EIM_D25_ALT2 0x1
#define SEL_SD4_CMD_ALT2 0x2
#define SEL_SD4_CLK_ALT2 0x3
// IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT
// DAISY
#define SEL_CSI0_DAT16_ALT3 0x0
#define SEL_CSI0_DAT17_ALT3 0x1
// IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT
// DAISY
#define SEL_KEY_COL0_ALT4 0x0
#define SEL_KEY_ROW0_ALT4 0x1
#define SEL_CSI0_DAT12_ALT3 0x2
#define SEL_CSI0_DAT13_ALT3 0x3
// IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT
// DAISY
#define SEL_KEY_COL4_ALT4 0x0
#define SEL_KEY_ROW4_ALT4 0x1
#define SEL_CSI0_DAT18_ALT3 0x2
#define SEL_CSI0_DAT19_ALT3 0x3
// IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT
// DAISY
#define SEL_KEY_COL1_ALT4 0x0
#define SEL_KEY_ROW1_ALT4 0x1
#define SEL_CSI0_DAT14_ALT3 0x2
#define SEL_CSI0_DAT15_ALT3 0x3
// IOMUXC_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT
// DAISY
#define SEL_EIM_D21_ALT4 0x0
#define SEL_KEY_COL4_ALT2 0x1
// IOMUXC_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT
// DAISY
#define SEL_EIM_D30_ALT6 0x0
#define SEL_GPIO_3_ALT6 0x1
// IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT
// DAISY
#define SEL_DI0_PIN4_ALT3 0x0
#define SEL_GPIO_9_ALT6 0x1
#endif // _IOMUX_DEFINE_H_

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: iomux_register.h
#ifndef _IOMUX_REGISTER_H_
#define _IOMUX_REGISTER_H_
//
// IOMUXC_GPR*
//
#define IOMUXC_GPR0 0x020E0000
#define IOMUXC_GPR1 0x020E0004
#define IOMUXC_GPR2 0x020E0008
#define IOMUXC_GPR3 0x020E000C
#define IOMUXC_GPR4 0x020E0010
#define IOMUXC_GPR5 0x020E0014
#define IOMUXC_GPR6 0x020E0018
#define IOMUXC_GPR7 0x020E001C
#define IOMUXC_GPR8 0x020E0020
#define IOMUXC_GPR9 0x020E0024
#define IOMUXC_GPR10 0x020E0028
#define IOMUXC_GPR11 0x020E002C
#define IOMUXC_GPR12 0x020E0030
#define IOMUXC_GPR13 0x020E0034
//
// IOMUXC_OBSERVE_MUX_*
//
#define IOMUXC_OBSERVE_MUX_0 0x020E0038
#define IOMUXC_OBSERVE_MUX_1 0x020E003C
#define IOMUXC_OBSERVE_MUX_2 0x020E0040
#define IOMUXC_OBSERVE_MUX_3 0x020E0044
#define IOMUXC_OBSERVE_MUX_4 0x020E0048
//
// IOMUXC_SW_MUX_CTL_PAD_*
//
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DAT1 0x020E004C
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DAT2 0x020E0050
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DAT0 0x020E0054
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC 0x020E0058
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0 0x020E005C
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1 0x020E0060
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2 0x020E0064
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3 0x020E0068
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL 0x020E006C
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0 0x020E0070
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL 0x020E0074
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1 0x020E0078
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2 0x020E007C
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3 0x020E0080
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC 0x020E0084
#define IOMUXC_SW_MUX_CTL_PAD_EIM_A25 0x020E0088
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2 0x020E008C
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D16 0x020E0090
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D17 0x020E0094
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D18 0x020E0098
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D19 0x020E009C
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D20 0x020E00A0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D21 0x020E00A4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D22 0x020E00A8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D23 0x020E00AC
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3 0x020E00B0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D24 0x020E00B4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D25 0x020E00B8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D26 0x020E00BC
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D27 0x020E00C0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D28 0x020E00C4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D29 0x020E00C8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D30 0x020E00CC
#define IOMUXC_SW_MUX_CTL_PAD_EIM_D31 0x020E00D0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_A24 0x020E00D4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_A23 0x020E00D8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_A22 0x020E00DC
#define IOMUXC_SW_MUX_CTL_PAD_EIM_A21 0x020E00E0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_A20 0x020E00E4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_A19 0x020E00E8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_A18 0x020E00EC
#define IOMUXC_SW_MUX_CTL_PAD_EIM_A17 0x020E00F0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_A16 0x020E00F4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 0x020E00F8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 0x020E00FC
#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE 0x020E0100
#define IOMUXC_SW_MUX_CTL_PAD_EIM_RW 0x020E0104
#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA 0x020E0108
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 0x020E010C
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 0x020E0110
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA0 0x020E0114
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA1 0x020E0118
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA2 0x020E011C
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA3 0x020E0120
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA4 0x020E0124
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA5 0x020E0128
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA6 0x020E012C
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA7 0x020E0130
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA8 0x020E0134
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA9 0x020E0138
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA10 0x020E013C
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA11 0x020E0140
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA12 0x020E0144
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA13 0x020E0148
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA14 0x020E014C
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA15 0x020E0150
#define IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT 0x020E0154
#define IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK 0x020E0158
#define IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK 0x020E015C
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 0x020E0160
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN2 0x020E0164
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN3 0x020E0168
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN4 0x020E016C
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT0 0x020E0170
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT1 0x020E0174
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT2 0x020E0178
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT3 0x020E017C
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT4 0x020E0180
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT5 0x020E0184
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT6 0x020E0188
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT7 0x020E018C
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT8 0x020E0190
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT9 0x020E0194
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT10 0x020E0198
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT11 0x020E019C
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT12 0x020E01A0
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT13 0x020E01A4
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT14 0x020E01A8
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT15 0x020E01AC
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT16 0x020E01B0
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT17 0x020E01B4
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT18 0x020E01B8
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT19 0x020E01BC
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT20 0x020E01C0
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT21 0x020E01C4
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT22 0x020E01C8
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT23 0x020E01CC
#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO 0x020E01D0
#define IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK 0x020E01D4
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER 0x020E01D8
#define IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV 0x020E01DC
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RXD1 0x020E01E0
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RXD0 0x020E01E4
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN 0x020E01E8
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TXD1 0x020E01EC
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TXD0 0x020E01F0
#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDC 0x020E01F4
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x020E01F8
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x020E01FC
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x020E0200
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x020E0204
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x020E0208
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x020E020C
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x020E0210
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x020E0214
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x020E0218
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 0x020E021C
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_0 0x020E0220
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_1 0x020E0224
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_9 0x020E0228
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_3 0x020E022C
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_6 0x020E0230
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_2 0x020E0234
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_4 0x020E0238
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_5 0x020E023C
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_7 0x020E0240
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_8 0x020E0244
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_16 0x020E0248
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_17 0x020E024C
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_18 0x020E0250
#define IOMUXC_SW_MUX_CTL_PAD_GPIO_19 0x020E0254
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK 0x020E0258
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_MCLK 0x020E025C
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN 0x020E0260
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC 0x020E0264
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT4 0x020E0268
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT5 0x020E026C
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT6 0x020E0270
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT7 0x020E0274
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT8 0x020E0278
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT9 0x020E027C
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT10 0x020E0280
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT11 0x020E0284
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT12 0x020E0288
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT13 0x020E028C
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT14 0x020E0290
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT15 0x020E0294
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT16 0x020E0298
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT17 0x020E029C
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT18 0x020E02A0
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT19 0x020E02A4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DAT7 0x020E02A8
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DAT6 0x020E02AC
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DAT5 0x020E02B0
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DAT4 0x020E02B4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD 0x020E02B8
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK 0x020E02BC
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DAT0 0x020E02C0
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DAT1 0x020E02C4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DAT2 0x020E02C8
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DAT3 0x020E02CC
#define IOMUXC_SW_MUX_CTL_PAD_SD3_RST 0x020E02D0
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE 0x020E02D4
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE 0x020E02D8
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B 0x020E02DC
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0 0x020E02E0
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0 0x020E02E4
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1 0x020E02E8
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2 0x020E02EC
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3 0x020E02F0
#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x020E02F4
#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x020E02F8
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D0 0x020E02FC
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D1 0x020E0300
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D2 0x020E0304
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D3 0x020E0308
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D4 0x020E030C
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D5 0x020E0310
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D6 0x020E0314
#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D7 0x020E0318
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DAT0 0x020E031C
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DAT1 0x020E0320
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DAT2 0x020E0324
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DAT3 0x020E0328
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DAT4 0x020E032C
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DAT5 0x020E0330
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DAT6 0x020E0334
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DAT7 0x020E0338
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DAT1 0x020E033C
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DAT0 0x020E0340
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DAT3 0x020E0344
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x020E0348
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DAT2 0x020E034C
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x020E0350
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x020E0354
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x020E0358
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DAT3 0x020E035C
//
// IOMUXC_SW_PAD_CTL_PAD_*
// IOMUXC_SW_PAD_CTL_GRP_*
//
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DAT1 0x020E0360
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DAT2 0x020E0364
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DAT0 0x020E0368
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC 0x020E036C
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0 0x020E0370
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1 0x020E0374
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2 0x020E0378
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3 0x020E037C
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL 0x020E0380
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0 0x020E0384
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL 0x020E0388
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1 0x020E038C
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2 0x020E0390
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3 0x020E0394
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC 0x020E0398
#define IOMUXC_SW_PAD_CTL_PAD_EIM_A25 0x020E039C
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2 0x020E03A0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D16 0x020E03A4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D17 0x020E03A8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D18 0x020E03AC
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D19 0x020E03B0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D20 0x020E03B4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D21 0x020E03B8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D22 0x020E03BC
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D23 0x020E03C0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3 0x020E03C4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D24 0x020E03C8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D25 0x020E03CC
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D26 0x020E03D0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D27 0x020E03D4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D28 0x020E03D8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D29 0x020E03DC
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D30 0x020E03E0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_D31 0x020E03E4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_A24 0x020E03E8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_A23 0x020E03EC
#define IOMUXC_SW_PAD_CTL_PAD_EIM_A22 0x020E03F0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_A21 0x020E03F4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_A20 0x020E03F8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_A19 0x020E03FC
#define IOMUXC_SW_PAD_CTL_PAD_EIM_A18 0x020E0400
#define IOMUXC_SW_PAD_CTL_PAD_EIM_A17 0x020E0404
#define IOMUXC_SW_PAD_CTL_PAD_EIM_A16 0x020E0408
#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 0x020E040C
#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 0x020E0410
#define IOMUXC_SW_PAD_CTL_PAD_EIM_OE 0x020E0414
#define IOMUXC_SW_PAD_CTL_PAD_EIM_RW 0x020E0418
#define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA 0x020E041C
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 0x020E0420
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 0x020E0424
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA0 0x020E0428
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA1 0x020E042C
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA2 0x020E0430
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA3 0x020E0434
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA4 0x020E0438
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA5 0x020E043C
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA6 0x020E0440
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA7 0x020E0444
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA8 0x020E0448
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA9 0x020E044C
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA10 0x020E0450
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA11 0x020E0454
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA12 0x020E0458
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA13 0x020E045C
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA14 0x020E0460
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA15 0x020E0464
#define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT 0x020E0468
#define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK 0x020E046C
#define IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK 0x020E0470
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 0x020E0474
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN2 0x020E0478
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN3 0x020E047C
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN4 0x020E0480
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT0 0x020E0484
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT1 0x020E0488
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT2 0x020E048C
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT3 0x020E0490
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT4 0x020E0494
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT5 0x020E0498
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT6 0x020E049C
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT7 0x020E04A0
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT8 0x020E04A4
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT9 0x020E04A8
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT10 0x020E04AC
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT11 0x020E04B0
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT12 0x020E04B4
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT13 0x020E04B8
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT14 0x020E04BC
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT15 0x020E04C0
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT16 0x020E04C4
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT17 0x020E04C8
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT18 0x020E04CC
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT19 0x020E04D0
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT20 0x020E04D4
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT21 0x020E04D8
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT22 0x020E04DC
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT23 0x020E04E0
#define IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO 0x020E04E4
#define IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK 0x020E04E8
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER 0x020E04EC
#define IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV 0x020E04F0
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RXD1 0x020E04F4
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RXD0 0x020E04F8
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN 0x020E04FC
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TXD1 0x020E0500
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TXD0 0x020E0504
#define IOMUXC_SW_PAD_CTL_PAD_ENET_MDC 0x020E0508
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 0x020E050C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020E0510
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020E0514
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 0x020E0518
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 0x020E051C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x020E0520
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 0x020E0524
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x020E0528
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A0 0x020E052C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A1 0x020E0530
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A2 0x020E0534
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A3 0x020E0538
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A4 0x020E053C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A5 0x020E0540
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A6 0x020E0544
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A7 0x020E0548
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A8 0x020E054C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A9 0x020E0550
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A10 0x020E0554
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A11 0x020E0558
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A12 0x020E055C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A13 0x020E0560
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A14 0x020E0564
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_A15 0x020E0568
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020E056C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 0x020E0570
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 0x020E0574
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020E0578
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020E057C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020E0580
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020E0584
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 0x020E0588
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020E058C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020E0590
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 0x020E0594
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020E0598
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 0x020E059C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 0x020E05A0
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE 0x020E05A4
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 0x020E05A8
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020E05AC
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 0x020E05B0
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020E05B4
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 0x020E05B8
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020E05BC
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 0x020E05C0
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020E05C4
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x020E05C8
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x020E05CC
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x020E05D0
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x020E05D4
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x020E05D8
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x020E05DC
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x020E05E0
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x020E05E4
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 0x020E05E8
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 0x020E05EC
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_0 0x020E05F0
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_1 0x020E05F4
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_9 0x020E05F8
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_3 0x020E05FC
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_6 0x020E0600
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_2 0x020E0604
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_4 0x020E0608
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_5 0x020E060C
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_7 0x020E0610
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_8 0x020E0614
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_16 0x020E0618
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_17 0x020E061C
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_18 0x020E0620
#define IOMUXC_SW_PAD_CTL_PAD_GPIO_19 0x020E0624
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK 0x020E0628
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_MCLK 0x020E062C
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN 0x020E0630
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC 0x020E0634
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT4 0x020E0638
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT5 0x020E063C
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT6 0x020E0640
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT7 0x020E0644
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT8 0x020E0648
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT9 0x020E064C
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT10 0x020E0650
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT11 0x020E0654
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT12 0x020E0658
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT13 0x020E065C
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT14 0x020E0660
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT15 0x020E0664
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT16 0x020E0668
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT17 0x020E066C
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT18 0x020E0670
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT19 0x020E0674
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x020E0678
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x020E067C
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB 0x020E0680
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x020E0684
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x020E0688
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO 0x020E068C
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DAT7 0x020E0690
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DAT6 0x020E0694
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DAT5 0x020E0698
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DAT4 0x020E069C
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD 0x020E06A0
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK 0x020E06A4
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DAT0 0x020E06A8
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DAT1 0x020E06AC
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DAT2 0x020E06B0
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DAT3 0x020E06B4
#define IOMUXC_SW_PAD_CTL_PAD_SD3_RST 0x020E06B8
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE 0x020E06BC
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE 0x020E06C0
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B 0x020E06C4
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0 0x020E06C8
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0 0x020E06CC
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1 0x020E06D0
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2 0x020E06D4
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3 0x020E06D8
#define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD 0x020E06DC
#define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK 0x020E06E0
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D0 0x020E06E4
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D1 0x020E06E8
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D2 0x020E06EC
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D3 0x020E06F0
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D4 0x020E06F4
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D5 0x020E06F8
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D6 0x020E06FC
#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D7 0x020E0700
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DAT0 0x020E0704
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DAT1 0x020E0708
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DAT2 0x020E070C
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DAT3 0x020E0710
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DAT4 0x020E0714
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DAT5 0x020E0718
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DAT6 0x020E071C
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DAT7 0x020E0720
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DAT1 0x020E0724
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DAT0 0x020E0728
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DAT3 0x020E072C
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x020E0730
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DAT2 0x020E0734
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x020E0738
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 0x020E073C
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 0x020E0740
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DAT3 0x020E0744
#define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020E0748
#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020E074C
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020E0750
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 0x020E0754
#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020E0758
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 0x020E075C
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 0x020E0760
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 0x020E0764
#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020E0768
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 0x020E076C
#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020E0770
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020E0774
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 0x020E0778
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 0x020E077C
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 0x020E0780
#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020E0784
#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020E0788
#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020E078C
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII 0x020E0790
#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x020E0794
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020E0798
#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x020E079C
#define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020E07A0
#define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020E07A4
#define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020E07A8
#define IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM 0x020E07AC
//
// IOMUXC_*_SELECT_INPUT
//
#define IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT 0x020E07B0
#define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT 0x020E07B4
#define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT 0x020E07B8
#define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT 0x020E07BC
#define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT 0x020E07C0
#define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT 0x020E07C4
#define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT 0x020E07C8
#define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT 0x020E07CC
#define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT 0x020E07D0
#define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT 0x020E07D4
#define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT 0x020E07D8
#define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT 0x020E07DC
#define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT 0x020E07E0
#define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT 0x020E07E4
#define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT 0x020E07E8
#define IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT 0x020E07EC
#define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT 0x020E07F0
#define IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT 0x020E07F4
#define IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT 0x020E07F8
#define IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT 0x020E07FC
#define IOMUXC_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT 0x020E0800
#define IOMUXC_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT 0x020E0804
#define IOMUXC_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT 0x020E0808
#define IOMUXC_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT 0x020E080C
#define IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT 0x020E0810
#define IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT 0x020E0814
#define IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT 0x020E0818
#define IOMUXC_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT 0x020E081C
#define IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT 0x020E0820
#define IOMUXC_ECSPI4_IPP_IND_SS_B_0_SELECT_INPUT 0x020E0824
#define IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT 0x020E0828
#define IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT 0x020E082C
#define IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT 0x020E0830
#define IOMUXC_ECSPI5_IPP_IND_SS_B_0_SELECT_INPUT 0x020E0834
#define IOMUXC_ECSPI5_IPP_IND_SS_B_1_SELECT_INPUT 0x020E0838
#define IOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT 0x020E083C
#define IOMUXC_ENET_IPP_IND_MAC0_MDIO_SELECT_INPUT 0x020E0840
#define IOMUXC_ENET_IPP_IND_MAC0_RXCLK_SELECT_INPUT 0x020E0844
#define IOMUXC_ENET_IPP_IND_MAC0_RXDATA_0_SELECT_INPUT 0x020E0848
#define IOMUXC_ENET_IPP_IND_MAC0_RXDATA_1_SELECT_INPUT 0x020E084C
#define IOMUXC_ENET_IPP_IND_MAC0_RXDATA_2_SELECT_INPUT 0x020E0850
#define IOMUXC_ENET_IPP_IND_MAC0_RXDATA_3_SELECT_INPUT 0x020E0854
#define IOMUXC_ENET_IPP_IND_MAC0_RXEN_SELECT_INPUT 0x020E0858
#define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT 0x020E085C
#define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT 0x020E0860
#define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT 0x020E0864
#define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT 0x020E0868
#define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT 0x020E086C
#define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT 0x020E0870
#define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT 0x020E0874
#define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT 0x020E0878
#define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT 0x020E087C
#define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT 0x020E0880
#define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT 0x020E0884
#define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT 0x020E0888
#define IOMUXC_HDMI_TX_ICECIN_SELECT_INPUT 0x020E088C
#define IOMUXC_HDMI_TX_II2C_MSTH13TDDC_SCLIN_SELECT_INPUT 0x020E0890
#define IOMUXC_HDMI_TX_II2C_MSTH13TDDC_SDAIN_SELECT_INPUT 0x020E0894
#define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT 0x020E0898
#define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT 0x020E089C
#define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT 0x020E08A0
#define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT 0x020E08A4
#define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT 0x020E08A8
#define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT 0x020E08AC
#define IOMUXC_IPU2_IPP_IND_SENS1_DATA_10_SELECT_INPUT 0x020E08B0
#define IOMUXC_IPU2_IPP_IND_SENS1_DATA_11_SELECT_INPUT 0x020E08B4
#define IOMUXC_IPU2_IPP_IND_SENS1_DATA_12_SELECT_INPUT 0x020E08B8
#define IOMUXC_IPU2_IPP_IND_SENS1_DATA_13_SELECT_INPUT 0x020E08BC
#define IOMUXC_IPU2_IPP_IND_SENS1_DATA_14_SELECT_INPUT 0x020E08C0
#define IOMUXC_IPU2_IPP_IND_SENS1_DATA_15_SELECT_INPUT 0x020E08C4
#define IOMUXC_IPU2_IPP_IND_SENS1_DATA_16_SELECT_INPUT 0x020E08C8
#define IOMUXC_IPU2_IPP_IND_SENS1_DATA_17_SELECT_INPUT 0x020E08CC
#define IOMUXC_IPU2_IPP_IND_SENS1_DATA_18_SELECT_INPUT 0x020E08D0
#define IOMUXC_IPU2_IPP_IND_SENS1_DATA_19_SELECT_INPUT 0x020E08D4
#define IOMUXC_IPU2_IPP_IND_SENS1_DATA_EN_SELECT_INPUT 0x020E08D8
#define IOMUXC_IPU2_IPP_IND_SENS1_HSYNC_SELECT_INPUT 0x020E08DC
#define IOMUXC_IPU2_IPP_IND_SENS1_PIX_CLK_SELECT_INPUT 0x020E08E0
#define IOMUXC_IPU2_IPP_IND_SENS1_VSYNC_SELECT_INPUT 0x020E08E4
#define IOMUXC_KPP_IPP_IND_COL_5_SELECT_INPUT 0x020E08E8
#define IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT 0x020E08EC
#define IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT 0x020E08F0
#define IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT 0x020E08F4
#define IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT 0x020E08F8
#define IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT 0x020E08FC
#define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT 0x020E0900
#define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT 0x020E0904
#define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT 0x020E0908
#define IOMUXC_SDMA_EVENTS_14_SELECT_INPUT 0x020E090C
#define IOMUXC_SDMA_EVENTS_15_SELECT_INPUT 0x020E0910
#define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 0x020E0914
#define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT 0x020E0918
#define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT 0x020E091C
#define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT 0x020E0920
#define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT 0x020E0924
#define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT 0x020E0928
#define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT 0x020E092C
#define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT 0x020E0930
#define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT 0x020E0934
#define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT 0x020E0938
#define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT 0x020E093C
#define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT 0x020E0940
#define IOMUXC_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT 0x020E0944
#define IOMUXC_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT 0x020E0948
#define IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT 0x020E094C
#endif // _IOMUX_REGISTER_H_

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__IRQ_NUMBERS_H__)
#define __IRQ_NUMBERS_H__
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! @brief i.MX6 interrupt numbers.
//!
//! This enumeration lists the numbers for all of the interrupts available on the i.MX6 series.
//! Use these numbers when specifying an interrupt to the GIC.
//!
//! The first 16 interrupts are special in that they are reserved for software interrupts generated
//! by the SWI instruction.
enum _imx_interrupts
{
SW_INTERRUPT_0 = 0, //!< Software interrupt 0.
SW_INTERRUPT_1 = 1, //!< Software interrupt 1.
SW_INTERRUPT_2 = 2, //!< Software interrupt 2.
SW_INTERRUPT_3 = 3, //!< Software interrupt 3.
SW_INTERRUPT_4 = 4, //!< Software interrupt 4.
SW_INTERRUPT_5 = 5, //!< Software interrupt 5.
SW_INTERRUPT_6 = 6, //!< Software interrupt 6.
SW_INTERRUPT_7 = 7, //!< Software interrupt 7.
SW_INTERRUPT_8 = 8, //!< Software interrupt 8.
SW_INTERRUPT_9 = 9, //!< Software interrupt 9.
SW_INTERRUPT_10 = 10, //!< Software interrupt 10.
SW_INTERRUPT_11 = 11, //!< Software interrupt 11.
SW_INTERRUPT_12 = 12, //!< Software interrupt 12.
SW_INTERRUPT_13 = 13, //!< Software interrupt 13.
SW_INTERRUPT_14 = 14, //!< Software interrupt 14.
SW_INTERRUPT_15 = 15, //!< Software interrupt 15.
RSVD_INTERRUPT_16 = 16, //!< Reserved.
RSVD_INTERRUPT_17 = 17, //!< Reserved.
RSVD_INTERRUPT_18 = 18, //!< Reserved.
RSVD_INTERRUPT_19 = 19, //!< Reserved.
RSVD_INTERRUPT_20 = 20, //!< Reserved.
RSVD_INTERRUPT_21 = 21, //!< Reserved.
RSVD_INTERRUPT_22 = 22, //!< Reserved.
RSVD_INTERRUPT_23 = 23, //!< Reserved.
RSVD_INTERRUPT_24 = 24, //!< Reserved.
RSVD_INTERRUPT_25 = 25, //!< Reserved.
RSVD_INTERRUPT_26 = 26, //!< Reserved.
RSVD_INTERRUPT_27 = 27, //!< Reserved.
RSVD_INTERRUPT_28 = 28, //!< Reserved.
RSVD_INTERRUPT_29 = 29, //!< Reserved.
RSVD_INTERRUPT_30 = 30, //!< Reserved.
RSVD_INTERRUPT_31 = 31, //!< Reserved.
IMX_INT_IOMUXC_GPR = 32, //!< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot.
IMX_INT_CHEETAH_CSYSPWRUPREQ = 33, //!< @todo Listed as DAP in RM
IMX_INT_SDMA = 34, //!< Logical OR of all 48 SDMA interrupt requests/events from all channels.
IMX_INT_VPU_JPG = 35, //!< JPEG codec interrupt request.
IMX_INT_SNVS_LP_SET_PWR_OFF = 36, //!< PMIC power off request.
IMX_INT_IPU1_ERR = 37, //!< IPU1 error interrupt request.
IMX_INT_IPU1_FUNC = 38, //!< IPU1 sync interrupt request.
IMX_INT_IPU2_ERR = 39, //!< IPU2 error interrupt request.
IMX_INT_IPU2_FUNC = 40, //!< IPU2 sync interrupt request.
IMX_INT_GPU3D = 41, //!< GPU3D interrupt request.
IMX_INT_GPU2D = 42, //!< Idle interrupt from GPU2D (for S/W power gating).
IMX_INT_OPENVG_XAQ2 = 43, //!< GPU2D general interrupt request.
IMX_INT_VPU_IPI = 44, //!< VPU interrupt request.
IMX_INT_APBHDMA = 45, //!< Logical OR of 4 signals: dma_chan[0-3]_irq, GPMI operation channel description complete interrupt.
IMX_INT_EIM = 46, //!< EIM interrupt request.
IMX_INT_BCH = 47, //!< BCH operation complete interrupt.
IMX_INT_GPMI = 48, //!< GPMI operation timeout error interrupt.
IMX_INT_DTCP = 49, //!< DTCP interrupt request.
IMX_INT_VDOA = 50, //!< Logical OR of VDOA interrupt requests.
IMX_INT_SNVS = 51, //!< SNVS consolidated interrupt.
IMX_INT_SNVS_SEC = 52, //!< SNVS security interrupt.
IMX_INT_CSU = 53, //!< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted.
IMX_INT_USDHC1 = 54, //!< uSDHC1 (Enhanced SDHC) interrupt request.
IMX_INT_USDHC2 = 55, //!< uSDHC2 (Enhanced SDHC) interrupt request.
IMX_INT_USDHC3 = 56, //!< uSDHC3 (Enhanced SDHC) interrupt request.
IMX_INT_USDHC4 = 57, //!< uSDHC4 (Enhanced SDHC) interrupt request.
IMX_INT_UART1 = 58, //!< Logical OR of UART1 interrupt requests.
IMX_INT_UART2 = 59, //!< Logical OR of UART2 interrupt requests.
IMX_INT_UART3 = 60, //!< Logical OR of UART3 interrupt requests.
IMX_INT_UART4 = 61, //!< Logical OR of UART4 interrupt requests.
IMX_INT_UART5 = 62, //!< Logical OR of UART5 interrupt requests.
IMX_INT_ECSPI1 = 63, //!< eCSPI1 interrupt request.
IMX_INT_ECSPI2 = 64, //!< eCSPI2 interrupt request.
IMX_INT_ECSPI3 = 65, //!< eCSPI3 interrupt request.
IMX_INT_ECSPI4 = 66, //!< eCSPI4 interrupt request.
IMX_INT_ECSPI5 = 67, //!< eCSPI5 interrupt request.
IMX_INT_I2C1 = 68, //!< I2C1 interrupt request.
IMX_INT_I2C2 = 69, //!< I2C2 interrupt request.
IMX_INT_I2C3 = 70, //!< I2C3 interrupt request.
IMX_INT_SATA = 71, //!< SATA interrupt request.
IMX_INT_USBOH3_UH1 = 72, //!< USB Host 1 interrupt request.
IMX_INT_USBOH3_UH2 = 73, //!< USB Host 2 interrupt request.
IMX_INT_USBOH3_UH3 = 74, //!< USB Host 3 interrupt request.
IMX_INT_USBOH3_UOTG = 75, //!< USB OTG interrupt request.
IMX_INT_USB_UTMI0 = 76, //!< UTMI0 interrupt request.
IMX_INT_USB_UTMI1 = 77, //!< UTMI1 interrupt request.
IMX_INT_SSI1 = 78, //!< SSI1 interrupt request.
IMX_INT_SSI2 = 79, //!< SSI2 interrupt request.
IMX_INT_SSI3 = 80, //!< SSI3 interrupt request.
IMX_INT_TEMPERATURE = 81, //!< Temperature Sensor (temp. greater than threshold) interrupt request.
IMX_INT_ASRC = 82, //!< ASRC interrupt request.
IMX_INT_ESAI = 83, //!< ESAI interrupt request.
IMX_INT_SPDIF = 84, //!< Logical OR of SPDIF TX and SPDIF RX interrupts.
IMX_INT_MLB = 85, //!< MLB error interrupt request.
IMX_INT_PMU_ANA_BO = 86, //!< PMU analog regulator brown-out interrupt request.
IMX_INT_GPT = 87, //!< Logical OR of GPT rollover interrupt line, input capture 1 & 2 lines, output compare 1, 2 & 3 interrupt lines.
IMX_INT_EPIT1 = 88, //!< EPIT1 output compare interrupt.
IMX_INT_EPIT2 = 89, //!< EPIT2 output compare interrupt.
IMX_INT_GPIO1_INT7 = 90, //!< INT7 interrupt request.
IMX_INT_GPIO1_INT6 = 91, //!< INT6 interrupt request.
IMX_INT_GPIO1_INT5 = 92, //!< INT5 interrupt request.
IMX_INT_GPIO1_INT4 = 93, //!< INT4 interrupt request.
IMX_INT_GPIO1_INT3 = 94, //!< INT3 interrupt request.
IMX_INT_GPIO1_INT2 = 95, //!< INT2 interrupt request.
IMX_INT_GPIO1_INT1 = 96, //!< INT1 interrupt request.
IMX_INT_GPIO1_INT0 = 97, //!< INT0 interrupt request.
IMX_INT_GPIO1_INT15_0 = 98, //!< Combined interrupt indication for GPIO1 signals 0 - 15.
IMX_INT_GPIO1_INT31_16 = 99, //!< Combined interrupt indication for GPIO1 signals 16 - 31.
IMX_INT_GPIO2_INT15_0 = 100, //!< Combined interrupt indication for GPIO2 signals 0 - 15.
IMX_INT_GPIO2_INT31_16 = 101, //!< Combined interrupt indication for GPIO2 signals 16 - 31.
IMX_INT_GPIO3_INT15_0 = 102, //!< Combined interrupt indication for GPIO3 signals 0 - 15.
IMX_INT_GPIO3_INT31_16 = 103, //!< Combined interrupt indication for GPIO3 signals 16 - 31.
IMX_INT_GPIO4_INT15_0 = 104, //!< Combined interrupt indication for GPIO4 signals 0 - 15.
IMX_INT_GPIO4_INT31_16 = 105, //!< Combined interrupt indication for GPIO4 signals 16 - 31.
IMX_INT_GPIO5_INT15_0 = 106, //!< Combined interrupt indication for GPIO5 signals 0 - 15.
IMX_INT_GPIO5_INT31_16 = 107, //!< Combined interrupt indication for GPIO5 signals 16 - 31.
IMX_INT_GPIO6_INT15_0 = 108, //!< Combined interrupt indication for GPIO6 signals 0 - 15.
IMX_INT_GPIO6_INT31_16 = 109, //!< Combined interrupt indication for GPIO6 signals 16 - 31.
IMX_INT_GPIO7_INT15_0 = 110, //!< Combined interrupt indication for GPIO7 signals 0 - 15.
IMX_INT_GPIO7_INT31_16 = 111, //!< Combined interrupt indication for GPIO7 signals 16 - 31.
IMX_INT_WDOG1 = 112, //!< WDOG1 timer reset interrupt request.
IMX_INT_WDOG2 = 113, //!< WDOG2 timer reset interrupt request.
IMX_INT_KPP = 114, //!< Key Pad interrupt request.
IMX_INT_PWM1 = 115, //!< Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
IMX_INT_PWM2 = 116, //!< Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
IMX_INT_PWM3 = 117, //!< Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
IMX_INT_PWM4 = 118, //!< Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
IMX_INT_CCM_INT1 = 119, //!< CCM interrupt request 1.
IMX_INT_CCM_INT2 = 120, //!< CCM interrupt request 2.
IMX_INT_GPC_INT1 = 121, //!< GPC interrupt request 1.
IMX_INT_GPC_INT2 = 122, //!< GPC interrupt request 2.
IMX_INT_SRC = 123, //!< SRC interrupt request.
IMX_INT_CHEETAH_L2 = 124, //!< Logical OR of all L2 interrupt requests.
IMX_INT_CHEETAH_PARITY = 125, //!< Parity Check error interrupt request.
IMX_INT_CHEETAH_PERFORM = 126, //!< Logical OR of Performance Unit interrupts.
IMX_INT_CHEETAH_TRIGGER = 127, //!< Logical OR of CTI trigger outputs.
IMX_INT_SRC_CPU_WDOG = 128, //!< Combined CPU wdog interrupts (4x) out of SRC.
IMX_INT_INTERRUPT_129 = 129, //!< Reserved.
IMX_INT_INTERRUPT_130 = 130, //!< Reserved.
IMX_INT_INTERRUPT_131 = 131, //!< Reserved.
IMX_INT_CSI_INTR1 = 132, //!< MIPI CSI interrupt request 1.
IMX_INT_CSI_INTR2 = 133, //!< MIPI CSI interrupt request 2.
IMX_INT_DSI = 134, //!< MIPI DSI interrupt request.
IMX_INT_HSI = 135, //!< MIPI HSI interrupt request.
IMX_INT_SJC = 136, //!< SJC interrupt from General Purpose register.
IMX_INT_CAAM_INT0 = 137, //!< CAAM job ring 0 interrupt.
IMX_INT_CAAM_INT1 = 138, //!< CAAM job ring 1 interrupt.
IMX_INT_INTERRUPT_139 = 139, //!< Reserved.
IMX_INT_TZASC1 = 140, //!< ASC1 interrupt request.
IMX_INT_TZASC2 = 141, //!< ASC2 interrupt request.
IMX_INT_FLEXCAN1 = 142, //!< FLEXCAN1 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein.
IMX_INT_FLEXCAN2 = 143, //!< FLEXCAN2 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein.
IMX_INT_PERFMON1 = 144, //!< Reserved.
IMX_INT_PERFMON2 = 145, //!< Reserved.
IMX_INT_PERFMON3 = 146, //!< Reserved.
IMX_INT_HDMI_TX = 147, //!< HDMI master interrupt request.
IMX_INT_HDMI_TX_WAKEUP = 148, //!< HDMI CEC engine dedicated interrupt signal raised by a wake-up event.
IMX_INT_MLB_AHB0 = 149, //!< Channels [31:0] interrupt requests.
IMX_INT_ENET = 150, //!< MAC 0 IRQ, Logical OR of:
//! - MAC 0 Periodic Timer Overflow
//! - MAC 0 Time Stamp Available
//! - MAC 0 Payload Receive Error
//! - MAC 0 Transmit FIFO Underrun
//! - MAC 0 Collision Retry Limit
//! - MAC 0 Late Collision
//! - MAC 0 Ethernet Bus Error
//! - MAC 0 MII Data Transfer Done
//! - MAC 0 Receive Buffer Done
//! - MAC 0 Receive Frame Done
//! - MAC 0 Transmit Buffer Done
//! - MAC 0 Transmit Frame Done
//! - MAC 0 Graceful Stop
//! - MAC 0 Babbling Transmit Error
//! - MAC 0 Babbling Receive Error
//! - MAC 0 Wakeup Request [synchronous]
IMX_INT_ENET_1588 = 151, //!< MAC 0 1588 Timer interrupt [synchronous] request.
IMX_INT_PCIE_1 = 152, //!< PCIe interrupt request 1.
IMX_INT_PCIE_2 = 153, //!< PCIe interrupt request 2.
IMX_INT_PCIE_3 = 154, //!< PCIe interrupt request 3.
IMX_INT_PCIE_4 = 155, //!< PCIe interrupt request 4.
IMX_INT_DCIC1 = 156, //!< Logical OR of DCIC1 interrupt requests.
IMX_INT_DCIC2 = 157, //!< Logical OR of DCIC2 interrupt requests.
IMX_INT_MLB_AHB1 = 158, //!< Logical OR of channel[63:32] interrupt requests.
IMX_INT_PMU_DIG_BO = 159, //!< //!< PMU digital regulator brown-out interrupt request.
IMX_INTERRUPT_COUNT = 160 //!< Total number of interrupts.
};
#endif // __IRQ_NUMBERS_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PERFMON_IMX_H__
#define __PERFMON_IMX_H__
#include "soc_memory_map.h"
#include "irq_numbers.h"
/* Number of performance monitors used in the i.MX6 */
#define PERFMON_INST 3
typedef enum {
PERFMON_ID1,
PERFMON_ID2,
PERFMON_ID3,
} perfmon_id_e;
typedef struct {
uint32_t base; /* module base address */
uint32_t irq_id; /* ID of its interrupt */
} perfmon_param;
/* used to list the instances of performance monitors */
static const perfmon_param perfmon_list[PERFMON_INST] = {
{PERFMON1_BASE_ADDR, IMX_INT_PERFMON1},
{PERFMON2_BASE_ADDR, IMX_INT_PERFMON2},
{PERFMON3_BASE_ADDR, IMX_INT_PERFMON3},
};
#endif /* __PERFMON_IMX_H__ */

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
#ifndef _REGS_H
#define _REGS_H 1
//
// define base address of the register block only if it is not already
// defined, which allows the compiler to override at build time for
// users who've mapped their registers to locations other than the
// physical location
//
#ifndef REGS_BASE
#define REGS_BASE 0x00000000
#endif
//
// common register types
//
#ifndef __LANGUAGE_ASM__
typedef unsigned char reg8_t;
typedef unsigned short reg16_t;
typedef unsigned int reg32_t;
#endif
//
// Typecast macro for C or asm. In C, the cast is applied, while in asm it is excluded. This is
// used to simplify macro definitions in the module register headers.
//
#ifndef __REG_VALUE_TYPE
#ifndef __LANGUAGE_ASM__
#define __REG_VALUE_TYPE(v, t) ((t)(v))
#else
#define __REG_VALUE_TYPE(v, t) (v)
#endif
#endif
//
// macros for single instance registers
//
#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field)
#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field)
#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field)
#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v))
#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v))
#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v))
#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym
#define BF_RD(reg, field) HW_##reg.B.field
#define BF_WR(reg, field, v) BW_##reg##_##field(v)
#define BF_CS1(reg, f1, v1) \
(HW_##reg##_CLR(BM_##reg##_##f1), \
HW_##reg##_SET(BF_##reg##_##f1(v1)))
#define BF_CS2(reg, f1, v1, f2, v2) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2)))
#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3)))
#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4)))
#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5)))
#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6)))
#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7)))
#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7 | \
BM_##reg##_##f8), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7) | \
BF_##reg##_##f8(v8)))
//
// macros for multiple instance registers
//
#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field)
#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field)
#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field)
#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v))
#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v))
#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v))
#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym
#define BF_RDn(reg, n, field) HW_##reg(n).B.field
#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v)
#define BF_CS1n(reg, n, f1, v1) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
#define BF_CS2n(reg, n, f1, v1, f2, v2) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2))))
#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3))))
#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4))))
#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5))))
#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6))))
#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7))))
#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7 | \
BM_##reg##_##f8)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7) | \
BF_##reg##_##f8(v8))))
//
// macros for single instance MULTI-BLOCK registers
//
#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field)
#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field)
#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field)
#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v))
#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v))
#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v))
#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym
#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field
#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v)
#define BFn_CS1(reg, blk, f1, v1) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
#define BFn_CS2(reg, blk, f1, v1, f2, v2) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2)))
#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3)))
#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4)))
#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5)))
#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6)))
#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7)))
#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7 | \
BM_##reg##_##f8), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7) | \
BF_##reg##_##f8(v8)))
//
// macros for MULTI-BLOCK multiple instance registers
//
#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field)
#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field)
#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field)
#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym
#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field
#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v)
#define BFn_CS1n(reg, blk, n, f1, v1) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2))))
#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3))))
#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4))))
#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5))))
#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6))))
#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7))))
#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7 | \
BM_##reg##_##f8)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7) | \
BF_##reg##_##f8(v8))))
#endif // _REGS_H
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_ARMGLOBALTIMER_REGISTERS_H__
#define __HW_ARMGLOBALTIMER_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ ARMGLOBALTIMER
*
* ARM Cortex-A9 Global Timer
*
* Registers defined in this header file:
* - HW_ARMGLOBALTIMER_COUNTERn - Global Timer Counter Registers
* - HW_ARMGLOBALTIMER_CONTROL - Global Timer Control Register
* - HW_ARMGLOBALTIMER_IRQSTATUS - Global Timer Interrupt Status Register
* - HW_ARMGLOBALTIMER_COMPARATORn - Global Timer Comparator Value Registers
* - HW_ARMGLOBALTIMER_AUTOINCREMENT - Global Timer Auto-increment Register
*
* - hw_armglobaltimer_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_ARMGLOBALTIMER_BASE
#define HW_ARMGLOBALTIMER_INSTANCE_COUNT (1) //!< Number of instances of the ARMGLOBALTIMER module.
#define REGS_ARMGLOBALTIMER_BASE (0x00a00000) //!< Base address for ARMGLOBALTIMER.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_ARMGLOBALTIMER_COUNTERn - Global Timer Counter Registers
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_ARMGLOBALTIMER_COUNTERn - Global Timer Counter Registers (RW)
*
* Reset value: 0x00000000
*
* There are two timer counter registers. They are the lower 32-bit timer counter at offset 0x00 and
* the upper 32-bit timer counter at offset 0x04.
*/
typedef union _hw_armglobaltimer_countern
{
reg32_t U;
struct _hw_armglobaltimer_countern_bitfields
{
unsigned VALUE : 32; //!< [31:0] 32-bits of the counter value.
} B;
} hw_armglobaltimer_countern_t;
#endif
/*!
* @name Constants and macros for entire ARMGLOBALTIMER_COUNTERn register
*/
//@{
//! @brief Number of instances of the ARMGLOBALTIMER_COUNTERn register.
#define HW_ARMGLOBALTIMER_COUNTERn_COUNT (2)
#define HW_ARMGLOBALTIMER_COUNTERn_ADDR(n) (REGS_ARMGLOBALTIMER_BASE + 0x200 + (0x4 * (n)))
#ifndef __LANGUAGE_ASM__
#define HW_ARMGLOBALTIMER_COUNTERn(n) (*(volatile hw_armglobaltimer_countern_t *) HW_ARMGLOBALTIMER_COUNTERn_ADDR(n))
#define HW_ARMGLOBALTIMER_COUNTERn_RD(n) (HW_ARMGLOBALTIMER_COUNTERn(n).U)
#define HW_ARMGLOBALTIMER_COUNTERn_WR(n, v) (HW_ARMGLOBALTIMER_COUNTERn(n).U = (v))
#define HW_ARMGLOBALTIMER_COUNTERn_SET(n, v) (HW_ARMGLOBALTIMER_COUNTERn_WR(n, HW_ARMGLOBALTIMER_COUNTERn_RD(n) | (v)))
#define HW_ARMGLOBALTIMER_COUNTERn_CLR(n, v) (HW_ARMGLOBALTIMER_COUNTERn_WR(n, HW_ARMGLOBALTIMER_COUNTERn_RD(n) & ~(v)))
#define HW_ARMGLOBALTIMER_COUNTERn_TOG(n, v) (HW_ARMGLOBALTIMER_COUNTERn_WR(n, HW_ARMGLOBALTIMER_COUNTERn_RD(n) ^ (v)))
#endif
//@}
/*
* constants & macros for individual ARMGLOBALTIMER_COUNTERn bitfields
*/
/*! @name Register ARMGLOBALTIMER_COUNTERn, field VALUE[31:0] (RW)
*
* 32-bits of the counter value.
*/
//@{
#define BP_ARMGLOBALTIMER_COUNTERn_VALUE (0) //!< Bit position for ARMGLOBALTIMER_COUNTERn_VALUE.
#define BM_ARMGLOBALTIMER_COUNTERn_VALUE (0xffffffff) //!< Bit mask for ARMGLOBALTIMER_COUNTERn_VALUE.
//! @brief Get value of ARMGLOBALTIMER_COUNTERn_VALUE from a register value.
#define BG_ARMGLOBALTIMER_COUNTERn_VALUE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ARMGLOBALTIMER_COUNTERn_VALUE) >> BP_ARMGLOBALTIMER_COUNTERn_VALUE)
//! @brief Format value for bitfield ARMGLOBALTIMER_COUNTERn_VALUE.
#define BF_ARMGLOBALTIMER_COUNTERn_VALUE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ARMGLOBALTIMER_COUNTERn_VALUE) & BM_ARMGLOBALTIMER_COUNTERn_VALUE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the VALUE field to a new value.
#define BW_ARMGLOBALTIMER_COUNTERn_VALUE(n, v) (HW_ARMGLOBALTIMER_COUNTERn_WR(n, (HW_ARMGLOBALTIMER_COUNTERn_RD(n) & ~BM_ARMGLOBALTIMER_COUNTERn_VALUE) | BF_ARMGLOBALTIMER_COUNTERn_VALUE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_ARMGLOBALTIMER_CONTROL - Global Timer Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_ARMGLOBALTIMER_CONTROL - Global Timer Control Register (RW)
*
* Reset value: 0x00000000
*
* Configuration and control of the Global Timer.
*/
typedef union _hw_armglobaltimer_control
{
reg32_t U;
struct _hw_armglobaltimer_control_bitfields
{
unsigned TIMER_ENABLE : 1; //!< [0] Timer enable.
unsigned COMP_ENABLE : 1; //!< [1] This bit is banked per Cortex-A9 processor.
unsigned IRQ_ENABLE : 1; //!< [2] This bit is banked per Cortex-A9 processor.
unsigned AUTO_INCREMENT : 1; //!< [3] This bit is banked per Cortex-A9 processor.
unsigned RESERVED0 : 4; //!< [7:4] Reserved
unsigned PRESCALER : 8; //!< [15:8] The prescaler modifies the clock period for the decrementing event for the Counter Register.
unsigned RESERVED1 : 16; //!< [31:16] Reserved.
} B;
} hw_armglobaltimer_control_t;
#endif
/*!
* @name Constants and macros for entire ARMGLOBALTIMER_CONTROL register
*/
//@{
#define HW_ARMGLOBALTIMER_CONTROL_ADDR (REGS_ARMGLOBALTIMER_BASE + 0x208)
#ifndef __LANGUAGE_ASM__
#define HW_ARMGLOBALTIMER_CONTROL (*(volatile hw_armglobaltimer_control_t *) HW_ARMGLOBALTIMER_CONTROL_ADDR)
#define HW_ARMGLOBALTIMER_CONTROL_RD() (HW_ARMGLOBALTIMER_CONTROL.U)
#define HW_ARMGLOBALTIMER_CONTROL_WR(v) (HW_ARMGLOBALTIMER_CONTROL.U = (v))
#define HW_ARMGLOBALTIMER_CONTROL_SET(v) (HW_ARMGLOBALTIMER_CONTROL_WR(HW_ARMGLOBALTIMER_CONTROL_RD() | (v)))
#define HW_ARMGLOBALTIMER_CONTROL_CLR(v) (HW_ARMGLOBALTIMER_CONTROL_WR(HW_ARMGLOBALTIMER_CONTROL_RD() & ~(v)))
#define HW_ARMGLOBALTIMER_CONTROL_TOG(v) (HW_ARMGLOBALTIMER_CONTROL_WR(HW_ARMGLOBALTIMER_CONTROL_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual ARMGLOBALTIMER_CONTROL bitfields
*/
/*! @name Register ARMGLOBALTIMER_CONTROL, field TIMER_ENABLE[0] (RW)
*
* Timer enable.
*
* Values:
* - DISABLED = 0 - Timer is disabled and the counter does not increment. All registers can still be read and written.
* - ENABLED = 1 - Timer is enabled and the counter increments normally.
*/
//@{
#define BP_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE (0) //!< Bit position for ARMGLOBALTIMER_CONTROL_TIMER_ENABLE.
#define BM_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE (0x00000001) //!< Bit mask for ARMGLOBALTIMER_CONTROL_TIMER_ENABLE.
//! @brief Get value of ARMGLOBALTIMER_CONTROL_TIMER_ENABLE from a register value.
#define BG_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE) >> BP_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE)
//! @brief Format value for bitfield ARMGLOBALTIMER_CONTROL_TIMER_ENABLE.
#define BF_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE) & BM_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TIMER_ENABLE field to a new value.
#define BW_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE(v) (HW_ARMGLOBALTIMER_CONTROL_WR((HW_ARMGLOBALTIMER_CONTROL_RD() & ~BM_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE) | BF_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE(v)))
#endif
//! @brief Macro to simplify usage of value macros.
#define BF_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE_V(v) BF_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE(BV_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE__##v)
#define BV_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE__DISABLED (0x0) //!< Timer is disabled and the counter does not increment. All registers can still be read and written.
#define BV_ARMGLOBALTIMER_CONTROL_TIMER_ENABLE__ENABLED (0x1) //!< Timer is enabled and the counter increments normally.
//@}
/*! @name Register ARMGLOBALTIMER_CONTROL, field COMP_ENABLE[1] (RW)
*
* This bit is banked per Cortex-A9 processor. If set, it enables the comparison between the 64-bit
* Timer Counter and the related 64-bit Comparator Register. When the Auto-increment and Comp enable
* bits are set, an IRQ is generated every auto-increment register value.
*
* Values:
* - DISABLED = 0 - Comparison is disabled.
* - ENABLED = 1 - Comparison is enabled.
*/
//@{
#define BP_ARMGLOBALTIMER_CONTROL_COMP_ENABLE (1) //!< Bit position for ARMGLOBALTIMER_CONTROL_COMP_ENABLE.
#define BM_ARMGLOBALTIMER_CONTROL_COMP_ENABLE (0x00000002) //!< Bit mask for ARMGLOBALTIMER_CONTROL_COMP_ENABLE.
//! @brief Get value of ARMGLOBALTIMER_CONTROL_COMP_ENABLE from a register value.
#define BG_ARMGLOBALTIMER_CONTROL_COMP_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ARMGLOBALTIMER_CONTROL_COMP_ENABLE) >> BP_ARMGLOBALTIMER_CONTROL_COMP_ENABLE)
//! @brief Format value for bitfield ARMGLOBALTIMER_CONTROL_COMP_ENABLE.
#define BF_ARMGLOBALTIMER_CONTROL_COMP_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ARMGLOBALTIMER_CONTROL_COMP_ENABLE) & BM_ARMGLOBALTIMER_CONTROL_COMP_ENABLE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the COMP_ENABLE field to a new value.
#define BW_ARMGLOBALTIMER_CONTROL_COMP_ENABLE(v) (HW_ARMGLOBALTIMER_CONTROL_WR((HW_ARMGLOBALTIMER_CONTROL_RD() & ~BM_ARMGLOBALTIMER_CONTROL_COMP_ENABLE) | BF_ARMGLOBALTIMER_CONTROL_COMP_ENABLE(v)))
#endif
//! @brief Macro to simplify usage of value macros.
#define BF_ARMGLOBALTIMER_CONTROL_COMP_ENABLE_V(v) BF_ARMGLOBALTIMER_CONTROL_COMP_ENABLE(BV_ARMGLOBALTIMER_CONTROL_COMP_ENABLE__##v)
#define BV_ARMGLOBALTIMER_CONTROL_COMP_ENABLE__DISABLED (0x0) //!< Comparison is disabled.
#define BV_ARMGLOBALTIMER_CONTROL_COMP_ENABLE__ENABLED (0x1) //!< Comparison is enabled.
//@}
/*! @name Register ARMGLOBALTIMER_CONTROL, field IRQ_ENABLE[2] (RW)
*
* This bit is banked per Cortex-A9 processor. If set, the interrupt ID 27 is set as pending in the
* Interrupt Distributor when the event flag is set in the Timer Status Register.
*
* Values:
* - DISABLED = 0 - Interrupts are disabled.
* - ENABLED = 1 - Interrupts are enabled.
*/
//@{
#define BP_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE (2) //!< Bit position for ARMGLOBALTIMER_CONTROL_IRQ_ENABLE.
#define BM_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE (0x00000004) //!< Bit mask for ARMGLOBALTIMER_CONTROL_IRQ_ENABLE.
//! @brief Get value of ARMGLOBALTIMER_CONTROL_IRQ_ENABLE from a register value.
#define BG_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE) >> BP_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE)
//! @brief Format value for bitfield ARMGLOBALTIMER_CONTROL_IRQ_ENABLE.
#define BF_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE) & BM_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IRQ_ENABLE field to a new value.
#define BW_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE(v) (HW_ARMGLOBALTIMER_CONTROL_WR((HW_ARMGLOBALTIMER_CONTROL_RD() & ~BM_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE) | BF_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE(v)))
#endif
//! @brief Macro to simplify usage of value macros.
#define BF_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE_V(v) BF_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE(BV_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE__##v)
#define BV_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE__DISABLED (0x0) //!< Interrupts are disabled.
#define BV_ARMGLOBALTIMER_CONTROL_IRQ_ENABLE__ENABLED (0x1) //!< Interrupts are enabled.
//@}
/*! @name Register ARMGLOBALTIMER_CONTROL, field AUTO_INCREMENT[3] (RW)
*
* This bit is banked per Cortex-A9 processor.
*
* Values:
* - SINGLE_SHOT_MODE = 0 - When the counter reaches the comparator value, sets the event flag. It is the responsibility of
* software to update the comparator value to get more events.
* - AUTO_INCREMENT_MODE = 1 - Each time the counter reaches the comparator value, the comparator register is incremented with the
* auto-increment register, so that more events can be set periodically without any software
* updates.
*/
//@{
#define BP_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT (3) //!< Bit position for ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT.
#define BM_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT (0x00000008) //!< Bit mask for ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT.
//! @brief Get value of ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT from a register value.
#define BG_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT) >> BP_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT)
//! @brief Format value for bitfield ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT.
#define BF_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT) & BM_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT)
#ifndef __LANGUAGE_ASM__
//! @brief Set the AUTO_INCREMENT field to a new value.
#define BW_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT(v) (HW_ARMGLOBALTIMER_CONTROL_WR((HW_ARMGLOBALTIMER_CONTROL_RD() & ~BM_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT) | BF_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT(v)))
#endif
//! @brief Macro to simplify usage of value macros.
#define BF_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT_V(v) BF_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT(BV_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT__##v)
#define BV_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT__SINGLE_SHOT_MODE (0x0) //!< When the counter reaches the comparator value, sets the event flag. It is the responsibility of software to update the comparator value to get more events.
#define BV_ARMGLOBALTIMER_CONTROL_AUTO_INCREMENT__AUTO_INCREMENT_MODE (0x1) //!< Each time the counter reaches the comparator value, the comparator register is incremented with the auto-increment register, so that more events can be set periodically without any software updates.
//@}
/*! @name Register ARMGLOBALTIMER_CONTROL, field PRESCALER[15:8] (RW)
*
* The prescaler modifies the clock period for the decrementing event for the Counter Register.
*/
//@{
#define BP_ARMGLOBALTIMER_CONTROL_PRESCALER (8) //!< Bit position for ARMGLOBALTIMER_CONTROL_PRESCALER.
#define BM_ARMGLOBALTIMER_CONTROL_PRESCALER (0x0000ff00) //!< Bit mask for ARMGLOBALTIMER_CONTROL_PRESCALER.
//! @brief Get value of ARMGLOBALTIMER_CONTROL_PRESCALER from a register value.
#define BG_ARMGLOBALTIMER_CONTROL_PRESCALER(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ARMGLOBALTIMER_CONTROL_PRESCALER) >> BP_ARMGLOBALTIMER_CONTROL_PRESCALER)
//! @brief Format value for bitfield ARMGLOBALTIMER_CONTROL_PRESCALER.
#define BF_ARMGLOBALTIMER_CONTROL_PRESCALER(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ARMGLOBALTIMER_CONTROL_PRESCALER) & BM_ARMGLOBALTIMER_CONTROL_PRESCALER)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PRESCALER field to a new value.
#define BW_ARMGLOBALTIMER_CONTROL_PRESCALER(v) (HW_ARMGLOBALTIMER_CONTROL_WR((HW_ARMGLOBALTIMER_CONTROL_RD() & ~BM_ARMGLOBALTIMER_CONTROL_PRESCALER) | BF_ARMGLOBALTIMER_CONTROL_PRESCALER(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_ARMGLOBALTIMER_IRQSTATUS - Global Timer Interrupt Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_ARMGLOBALTIMER_IRQSTATUS - Global Timer Interrupt Status Register (RW)
*
* Reset value: 0x00000000
*
* This is a banked register for all Cortex-A9 processors present.
*/
typedef union _hw_armglobaltimer_irqstatus
{
reg32_t U;
struct _hw_armglobaltimer_irqstatus_bitfields
{
unsigned EVENT_FLAG : 1; //!< [0] The event flag is a sticky bit that is automatically set when the Counter Register reaches the Comparator Register value.
unsigned RESERVED0 : 31; //!< [31:1] Reserved.
} B;
} hw_armglobaltimer_irqstatus_t;
#endif
/*!
* @name Constants and macros for entire ARMGLOBALTIMER_IRQSTATUS register
*/
//@{
#define HW_ARMGLOBALTIMER_IRQSTATUS_ADDR (REGS_ARMGLOBALTIMER_BASE + 0x20c)
#ifndef __LANGUAGE_ASM__
#define HW_ARMGLOBALTIMER_IRQSTATUS (*(volatile hw_armglobaltimer_irqstatus_t *) HW_ARMGLOBALTIMER_IRQSTATUS_ADDR)
#define HW_ARMGLOBALTIMER_IRQSTATUS_RD() (HW_ARMGLOBALTIMER_IRQSTATUS.U)
#define HW_ARMGLOBALTIMER_IRQSTATUS_WR(v) (HW_ARMGLOBALTIMER_IRQSTATUS.U = (v))
#define HW_ARMGLOBALTIMER_IRQSTATUS_SET(v) (HW_ARMGLOBALTIMER_IRQSTATUS_WR(HW_ARMGLOBALTIMER_IRQSTATUS_RD() | (v)))
#define HW_ARMGLOBALTIMER_IRQSTATUS_CLR(v) (HW_ARMGLOBALTIMER_IRQSTATUS_WR(HW_ARMGLOBALTIMER_IRQSTATUS_RD() & ~(v)))
#define HW_ARMGLOBALTIMER_IRQSTATUS_TOG(v) (HW_ARMGLOBALTIMER_IRQSTATUS_WR(HW_ARMGLOBALTIMER_IRQSTATUS_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual ARMGLOBALTIMER_IRQSTATUS bitfields
*/
/*! @name Register ARMGLOBALTIMER_IRQSTATUS, field EVENT_FLAG[0] (W1C)
*
* The event flag is a sticky bit that is automatically set when the Counter Register reaches the
* Comparator Register value. If the timer interrupt is enabled, Interrupt ID 27 is set as pending
* in the Interrupt Distributor after the event flag is set. The event flag is cleared when written
* to 1.
*/
//@{
#define BP_ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG (0) //!< Bit position for ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG.
#define BM_ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG (0x00000001) //!< Bit mask for ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG.
//! @brief Get value of ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG from a register value.
#define BG_ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG) >> BP_ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG)
//! @brief Format value for bitfield ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG.
#define BF_ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG) & BM_ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG)
#ifndef __LANGUAGE_ASM__
//! @brief Set the EVENT_FLAG field to a new value.
#define BW_ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG(v) (HW_ARMGLOBALTIMER_IRQSTATUS_WR((HW_ARMGLOBALTIMER_IRQSTATUS_RD() & ~BM_ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG) | BF_ARMGLOBALTIMER_IRQSTATUS_EVENT_FLAG(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_ARMGLOBALTIMER_COMPARATORn - Global Timer Comparator Value Registers
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_ARMGLOBALTIMER_COMPARATORn - Global Timer Comparator Value Registers (RW)
*
* Reset value: 0x00000000
*
* There are two timer counter registers. They are the lower 32-bit timer counter at offset 0x00 and
* the upper 32-bit timer counter at offset 0x04.
*/
typedef union _hw_armglobaltimer_comparatorn
{
reg32_t U;
struct _hw_armglobaltimer_comparatorn_bitfields
{
unsigned VALUE : 32; //!< [31:0] 32-bits of the comparator value.
} B;
} hw_armglobaltimer_comparatorn_t;
#endif
/*!
* @name Constants and macros for entire ARMGLOBALTIMER_COMPARATORn register
*/
//@{
//! @brief Number of instances of the ARMGLOBALTIMER_COMPARATORn register.
#define HW_ARMGLOBALTIMER_COMPARATORn_COUNT (2)
#define HW_ARMGLOBALTIMER_COMPARATORn_ADDR(n) (REGS_ARMGLOBALTIMER_BASE + 0x210 + (0x4 * (n)))
#ifndef __LANGUAGE_ASM__
#define HW_ARMGLOBALTIMER_COMPARATORn(n) (*(volatile hw_armglobaltimer_comparatorn_t *) HW_ARMGLOBALTIMER_COMPARATORn_ADDR(n))
#define HW_ARMGLOBALTIMER_COMPARATORn_RD(n) (HW_ARMGLOBALTIMER_COMPARATORn(n).U)
#define HW_ARMGLOBALTIMER_COMPARATORn_WR(n, v) (HW_ARMGLOBALTIMER_COMPARATORn(n).U = (v))
#define HW_ARMGLOBALTIMER_COMPARATORn_SET(n, v) (HW_ARMGLOBALTIMER_COMPARATORn_WR(n, HW_ARMGLOBALTIMER_COMPARATORn_RD(n) | (v)))
#define HW_ARMGLOBALTIMER_COMPARATORn_CLR(n, v) (HW_ARMGLOBALTIMER_COMPARATORn_WR(n, HW_ARMGLOBALTIMER_COMPARATORn_RD(n) & ~(v)))
#define HW_ARMGLOBALTIMER_COMPARATORn_TOG(n, v) (HW_ARMGLOBALTIMER_COMPARATORn_WR(n, HW_ARMGLOBALTIMER_COMPARATORn_RD(n) ^ (v)))
#endif
//@}
/*
* constants & macros for individual ARMGLOBALTIMER_COMPARATORn bitfields
*/
/*! @name Register ARMGLOBALTIMER_COMPARATORn, field VALUE[31:0] (RW)
*
* 32-bits of the comparator value.
*/
//@{
#define BP_ARMGLOBALTIMER_COMPARATORn_VALUE (0) //!< Bit position for ARMGLOBALTIMER_COMPARATORn_VALUE.
#define BM_ARMGLOBALTIMER_COMPARATORn_VALUE (0xffffffff) //!< Bit mask for ARMGLOBALTIMER_COMPARATORn_VALUE.
//! @brief Get value of ARMGLOBALTIMER_COMPARATORn_VALUE from a register value.
#define BG_ARMGLOBALTIMER_COMPARATORn_VALUE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ARMGLOBALTIMER_COMPARATORn_VALUE) >> BP_ARMGLOBALTIMER_COMPARATORn_VALUE)
//! @brief Format value for bitfield ARMGLOBALTIMER_COMPARATORn_VALUE.
#define BF_ARMGLOBALTIMER_COMPARATORn_VALUE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ARMGLOBALTIMER_COMPARATORn_VALUE) & BM_ARMGLOBALTIMER_COMPARATORn_VALUE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the VALUE field to a new value.
#define BW_ARMGLOBALTIMER_COMPARATORn_VALUE(n, v) (HW_ARMGLOBALTIMER_COMPARATORn_WR(n, (HW_ARMGLOBALTIMER_COMPARATORn_RD(n) & ~BM_ARMGLOBALTIMER_COMPARATORn_VALUE) | BF_ARMGLOBALTIMER_COMPARATORn_VALUE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_ARMGLOBALTIMER_AUTOINCREMENT - Global Timer Auto-increment Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_ARMGLOBALTIMER_AUTOINCREMENT - Global Timer Auto-increment Register (RW)
*
* Reset value: 0x00000000
*
* This 32-bit register gives the increment value of the Comparator Register when the Auto-increment
* bit is set in the Timer Control Register. Each Cortex-A9 processor present has its own Auto-
* increment Register. If the comp enable and auto-increment bits are set when the global counter
* reaches the Comparator Register value, the comparator is incremented by the auto-increment value,
* so that a new event can be set periodically. The global timer is not affected and goes on
* incrementing.
*/
typedef union _hw_armglobaltimer_autoincrement
{
reg32_t U;
struct _hw_armglobaltimer_autoincrement_bitfields
{
unsigned VALUE : 32; //!< [31:0] 32-bit auto-increment value.
} B;
} hw_armglobaltimer_autoincrement_t;
#endif
/*!
* @name Constants and macros for entire ARMGLOBALTIMER_AUTOINCREMENT register
*/
//@{
#define HW_ARMGLOBALTIMER_AUTOINCREMENT_ADDR (REGS_ARMGLOBALTIMER_BASE + 0x218)
#ifndef __LANGUAGE_ASM__
#define HW_ARMGLOBALTIMER_AUTOINCREMENT (*(volatile hw_armglobaltimer_autoincrement_t *) HW_ARMGLOBALTIMER_AUTOINCREMENT_ADDR)
#define HW_ARMGLOBALTIMER_AUTOINCREMENT_RD() (HW_ARMGLOBALTIMER_AUTOINCREMENT.U)
#define HW_ARMGLOBALTIMER_AUTOINCREMENT_WR(v) (HW_ARMGLOBALTIMER_AUTOINCREMENT.U = (v))
#define HW_ARMGLOBALTIMER_AUTOINCREMENT_SET(v) (HW_ARMGLOBALTIMER_AUTOINCREMENT_WR(HW_ARMGLOBALTIMER_AUTOINCREMENT_RD() | (v)))
#define HW_ARMGLOBALTIMER_AUTOINCREMENT_CLR(v) (HW_ARMGLOBALTIMER_AUTOINCREMENT_WR(HW_ARMGLOBALTIMER_AUTOINCREMENT_RD() & ~(v)))
#define HW_ARMGLOBALTIMER_AUTOINCREMENT_TOG(v) (HW_ARMGLOBALTIMER_AUTOINCREMENT_WR(HW_ARMGLOBALTIMER_AUTOINCREMENT_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual ARMGLOBALTIMER_AUTOINCREMENT bitfields
*/
/*! @name Register ARMGLOBALTIMER_AUTOINCREMENT, field VALUE[31:0] (RW)
*
* 32-bit auto-increment value.
*/
//@{
#define BP_ARMGLOBALTIMER_AUTOINCREMENT_VALUE (0) //!< Bit position for ARMGLOBALTIMER_AUTOINCREMENT_VALUE.
#define BM_ARMGLOBALTIMER_AUTOINCREMENT_VALUE (0xffffffff) //!< Bit mask for ARMGLOBALTIMER_AUTOINCREMENT_VALUE.
//! @brief Get value of ARMGLOBALTIMER_AUTOINCREMENT_VALUE from a register value.
#define BG_ARMGLOBALTIMER_AUTOINCREMENT_VALUE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ARMGLOBALTIMER_AUTOINCREMENT_VALUE) >> BP_ARMGLOBALTIMER_AUTOINCREMENT_VALUE)
//! @brief Format value for bitfield ARMGLOBALTIMER_AUTOINCREMENT_VALUE.
#define BF_ARMGLOBALTIMER_AUTOINCREMENT_VALUE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ARMGLOBALTIMER_AUTOINCREMENT_VALUE) & BM_ARMGLOBALTIMER_AUTOINCREMENT_VALUE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the VALUE field to a new value.
#define BW_ARMGLOBALTIMER_AUTOINCREMENT_VALUE(v) (HW_ARMGLOBALTIMER_AUTOINCREMENT_WR((HW_ARMGLOBALTIMER_AUTOINCREMENT_RD() & ~BM_ARMGLOBALTIMER_AUTOINCREMENT_VALUE) | BF_ARMGLOBALTIMER_AUTOINCREMENT_VALUE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_armglobaltimer_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All ARMGLOBALTIMER module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_armglobaltimer
{
reg32_t _reserved0[128];
volatile hw_armglobaltimer_countern_t COUNTERn[2]; //!< Global Timer Counter Registers
volatile hw_armglobaltimer_control_t CONTROL; //!< Global Timer Control Register
volatile hw_armglobaltimer_irqstatus_t IRQSTATUS; //!< Global Timer Interrupt Status Register
volatile hw_armglobaltimer_comparatorn_t COMPARATORn[2]; //!< Global Timer Comparator Value Registers
volatile hw_armglobaltimer_autoincrement_t AUTOINCREMENT; //!< Global Timer Auto-increment Register
} hw_armglobaltimer_t;
#pragma pack()
//! @brief Macro to access all ARMGLOBALTIMER registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_ARMGLOBALTIMER</code>.
#define HW_ARMGLOBALTIMER (*(hw_armglobaltimer_t *) REGS_ARMGLOBALTIMER_BASE)
#endif
#endif // __HW_ARMGLOBALTIMER_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_CSI2IPU_REGISTERS_H__
#define __HW_CSI2IPU_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ CSI2IPU
*
* CSI2IPU
*
* Registers defined in this header file:
* - HW_CSI2IPU_SW_RST - CSI 2 IPU Gasket Software Reset
*
* - hw_csi2ipu_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_CSI2IPU_BASE
#define HW_CSI2IPU_INSTANCE_COUNT (1) //!< Number of instances of the CSI2IPU module.
#define REGS_CSI2IPU_BASE (0x021dc000) //!< Base address for CSI2IPU.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_CSI2IPU_SW_RST - CSI 2 IPU Gasket Software Reset
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_CSI2IPU_SW_RST - CSI 2 IPU Gasket Software Reset (RW)
*
* Reset value: 0x00000000
*
* This register describes the IPU interface signals.
*/
typedef union _hw_csi2ipu_sw_rst
{
reg32_t U;
struct _hw_csi2ipu_sw_rst_bitfields
{
unsigned SW_RST : 1; //!< [0] Software Reset
unsigned CLK_SEL : 1; //!< [1] Clock mode selection
unsigned YUV422_8BIT_FM : 1; //!< [2] YUV422 8-bit mode selection
unsigned RGB444_FM : 1; //!< [3] rgb444 mode selection
unsigned RESERVED0 : 28; //!< [31:4] Reserved.
} B;
} hw_csi2ipu_sw_rst_t;
#endif
/*!
* @name Constants and macros for entire CSI2IPU_SW_RST register
*/
//@{
#define HW_CSI2IPU_SW_RST_ADDR (REGS_CSI2IPU_BASE + 0xf00)
#ifndef __LANGUAGE_ASM__
#define HW_CSI2IPU_SW_RST (*(volatile hw_csi2ipu_sw_rst_t *) HW_CSI2IPU_SW_RST_ADDR)
#define HW_CSI2IPU_SW_RST_RD() (HW_CSI2IPU_SW_RST.U)
#define HW_CSI2IPU_SW_RST_WR(v) (HW_CSI2IPU_SW_RST.U = (v))
#define HW_CSI2IPU_SW_RST_SET(v) (HW_CSI2IPU_SW_RST_WR(HW_CSI2IPU_SW_RST_RD() | (v)))
#define HW_CSI2IPU_SW_RST_CLR(v) (HW_CSI2IPU_SW_RST_WR(HW_CSI2IPU_SW_RST_RD() & ~(v)))
#define HW_CSI2IPU_SW_RST_TOG(v) (HW_CSI2IPU_SW_RST_WR(HW_CSI2IPU_SW_RST_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual CSI2IPU_SW_RST bitfields
*/
/*! @name Register CSI2IPU_SW_RST, field SW_RST[0] (RW)
*
* Software Reset
*
* Values:
* - 0 - Software Reset Disable
* - 1 - Software Reset Enable
*/
//@{
#define BP_CSI2IPU_SW_RST_SW_RST (0) //!< Bit position for CSI2IPU_SW_RST_SW_RST.
#define BM_CSI2IPU_SW_RST_SW_RST (0x00000001) //!< Bit mask for CSI2IPU_SW_RST_SW_RST.
//! @brief Get value of CSI2IPU_SW_RST_SW_RST from a register value.
#define BG_CSI2IPU_SW_RST_SW_RST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CSI2IPU_SW_RST_SW_RST) >> BP_CSI2IPU_SW_RST_SW_RST)
//! @brief Format value for bitfield CSI2IPU_SW_RST_SW_RST.
#define BF_CSI2IPU_SW_RST_SW_RST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CSI2IPU_SW_RST_SW_RST) & BM_CSI2IPU_SW_RST_SW_RST)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SW_RST field to a new value.
#define BW_CSI2IPU_SW_RST_SW_RST(v) (HW_CSI2IPU_SW_RST_WR((HW_CSI2IPU_SW_RST_RD() & ~BM_CSI2IPU_SW_RST_SW_RST) | BF_CSI2IPU_SW_RST_SW_RST(v)))
#endif
//@}
/*! @name Register CSI2IPU_SW_RST, field CLK_SEL[1] (RW)
*
* Clock mode selection
*
* Values:
* - 0 - Gated Mode
* - 1 - Non-Gated Mode
*/
//@{
#define BP_CSI2IPU_SW_RST_CLK_SEL (1) //!< Bit position for CSI2IPU_SW_RST_CLK_SEL.
#define BM_CSI2IPU_SW_RST_CLK_SEL (0x00000002) //!< Bit mask for CSI2IPU_SW_RST_CLK_SEL.
//! @brief Get value of CSI2IPU_SW_RST_CLK_SEL from a register value.
#define BG_CSI2IPU_SW_RST_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CSI2IPU_SW_RST_CLK_SEL) >> BP_CSI2IPU_SW_RST_CLK_SEL)
//! @brief Format value for bitfield CSI2IPU_SW_RST_CLK_SEL.
#define BF_CSI2IPU_SW_RST_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CSI2IPU_SW_RST_CLK_SEL) & BM_CSI2IPU_SW_RST_CLK_SEL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CLK_SEL field to a new value.
#define BW_CSI2IPU_SW_RST_CLK_SEL(v) (HW_CSI2IPU_SW_RST_WR((HW_CSI2IPU_SW_RST_RD() & ~BM_CSI2IPU_SW_RST_CLK_SEL) | BF_CSI2IPU_SW_RST_CLK_SEL(v)))
#endif
//@}
/*! @name Register CSI2IPU_SW_RST, field YUV422_8BIT_FM[2] (RW)
*
* YUV422 8-bit mode selection
*
* Values:
* - 0 - YUYV
* - 1 - UYVY
*/
//@{
#define BP_CSI2IPU_SW_RST_YUV422_8BIT_FM (2) //!< Bit position for CSI2IPU_SW_RST_YUV422_8BIT_FM.
#define BM_CSI2IPU_SW_RST_YUV422_8BIT_FM (0x00000004) //!< Bit mask for CSI2IPU_SW_RST_YUV422_8BIT_FM.
//! @brief Get value of CSI2IPU_SW_RST_YUV422_8BIT_FM from a register value.
#define BG_CSI2IPU_SW_RST_YUV422_8BIT_FM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CSI2IPU_SW_RST_YUV422_8BIT_FM) >> BP_CSI2IPU_SW_RST_YUV422_8BIT_FM)
//! @brief Format value for bitfield CSI2IPU_SW_RST_YUV422_8BIT_FM.
#define BF_CSI2IPU_SW_RST_YUV422_8BIT_FM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CSI2IPU_SW_RST_YUV422_8BIT_FM) & BM_CSI2IPU_SW_RST_YUV422_8BIT_FM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the YUV422_8BIT_FM field to a new value.
#define BW_CSI2IPU_SW_RST_YUV422_8BIT_FM(v) (HW_CSI2IPU_SW_RST_WR((HW_CSI2IPU_SW_RST_RD() & ~BM_CSI2IPU_SW_RST_YUV422_8BIT_FM) | BF_CSI2IPU_SW_RST_YUV422_8BIT_FM(v)))
#endif
//@}
/*! @name Register CSI2IPU_SW_RST, field RGB444_FM[3] (RW)
*
* rgb444 mode selection
*
* Values:
* - 0 - {4’h0,r4b4g4}
* - 1 - {r4,1’b0,g4,2’b00,b4,1’b0}
*/
//@{
#define BP_CSI2IPU_SW_RST_RGB444_FM (3) //!< Bit position for CSI2IPU_SW_RST_RGB444_FM.
#define BM_CSI2IPU_SW_RST_RGB444_FM (0x00000008) //!< Bit mask for CSI2IPU_SW_RST_RGB444_FM.
//! @brief Get value of CSI2IPU_SW_RST_RGB444_FM from a register value.
#define BG_CSI2IPU_SW_RST_RGB444_FM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CSI2IPU_SW_RST_RGB444_FM) >> BP_CSI2IPU_SW_RST_RGB444_FM)
//! @brief Format value for bitfield CSI2IPU_SW_RST_RGB444_FM.
#define BF_CSI2IPU_SW_RST_RGB444_FM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CSI2IPU_SW_RST_RGB444_FM) & BM_CSI2IPU_SW_RST_RGB444_FM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the RGB444_FM field to a new value.
#define BW_CSI2IPU_SW_RST_RGB444_FM(v) (HW_CSI2IPU_SW_RST_WR((HW_CSI2IPU_SW_RST_RD() & ~BM_CSI2IPU_SW_RST_RGB444_FM) | BF_CSI2IPU_SW_RST_RGB444_FM(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_csi2ipu_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All CSI2IPU module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_csi2ipu
{
reg32_t _reserved0[960];
volatile hw_csi2ipu_sw_rst_t SW_RST; //!< CSI 2 IPU Gasket Software Reset
} hw_csi2ipu_t;
#pragma pack()
//! @brief Macro to access all CSI2IPU registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_CSI2IPU</code>.
#define HW_CSI2IPU (*(hw_csi2ipu_t *) REGS_CSI2IPU_BASE)
#endif
#endif // __HW_CSI2IPU_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_DCIC_REGISTERS_H__
#define __HW_DCIC_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ DCIC
*
* DCIC
*
* Registers defined in this header file:
* - HW_DCIC_DCICC - DCIC Control Register
* - HW_DCIC_DCICIC - DCIC Interrupt Control Register
* - HW_DCIC_DCICS - DCIC Status Register
* - HW_DCIC_DCICRC - DCIC ROI Config Register m
* - HW_DCIC_DCICRS - DCIC ROI Size Register m
* - HW_DCIC_DCICRRS - DCIC ROI Reference Signature Register m
* - HW_DCIC_DCICRCS - DCIC ROI Calculated Signature m
*
* - hw_dcic_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_DCIC_BASE
#define HW_DCIC_INSTANCE_COUNT (2) //!< Number of instances of the DCIC module.
#define HW_DCIC1 (1) //!< Instance number for DCIC1.
#define HW_DCIC2 (2) //!< Instance number for DCIC2.
#define REGS_DCIC1_BASE (0x020e4000) //!< Base address for DCIC instance number 1.
#define REGS_DCIC2_BASE (0x020e8000) //!< Base address for DCIC instance number 2.
//! @brief Get the base address of DCIC by instance number.
//! @param x DCIC instance number, from 1 through 2.
#define REGS_DCIC_BASE(x) ( (x) == HW_DCIC1 ? REGS_DCIC1_BASE : (x) == HW_DCIC2 ? REGS_DCIC2_BASE : 0x00d00000)
//! @brief Get the instance number given a base address.
//! @param b Base address for an instance of DCIC.
#define REGS_DCIC_INSTANCE(b) ( (b) == REGS_DCIC1_BASE ? HW_DCIC1 : (b) == REGS_DCIC2_BASE ? HW_DCIC2 : 0)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DCIC_DCICC - DCIC Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DCIC_DCICC - DCIC Control Register (RW)
*
* Reset value: 0x00000070
*/
typedef union _hw_dcic_dcicc
{
reg32_t U;
struct _hw_dcic_dcicc_bitfields
{
unsigned IC_EN : 1; //!< [0] Integrity Check enable.
unsigned RESERVED0 : 3; //!< [3:1] Reserved
unsigned DE_POL : 1; //!< [4] DATA_EN_IN signal polarity.
unsigned HSYNC_POL : 1; //!< [5] HSYNC_IN signal polarity.
unsigned VSYNC_POL : 1; //!< [6] VSYNC_IN signal polarity.
unsigned CLK_POL : 1; //!< [7] DISP_CLK signal polarity.
unsigned RESERVED1 : 24; //!< [31:8] Reserved
} B;
} hw_dcic_dcicc_t;
#endif
/*!
* @name Constants and macros for entire DCIC_DCICC register
*/
//@{
#define HW_DCIC_DCICC_ADDR(x) (REGS_DCIC_BASE(x) + 0x0)
#ifndef __LANGUAGE_ASM__
#define HW_DCIC_DCICC(x) (*(volatile hw_dcic_dcicc_t *) HW_DCIC_DCICC_ADDR(x))
#define HW_DCIC_DCICC_RD(x) (HW_DCIC_DCICC(x).U)
#define HW_DCIC_DCICC_WR(x, v) (HW_DCIC_DCICC(x).U = (v))
#define HW_DCIC_DCICC_SET(x, v) (HW_DCIC_DCICC_WR(x, HW_DCIC_DCICC_RD(x) | (v)))
#define HW_DCIC_DCICC_CLR(x, v) (HW_DCIC_DCICC_WR(x, HW_DCIC_DCICC_RD(x) & ~(v)))
#define HW_DCIC_DCICC_TOG(x, v) (HW_DCIC_DCICC_WR(x, HW_DCIC_DCICC_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual DCIC_DCICC bitfields
*/
/*! @name Register DCIC_DCICC, field IC_EN[0] (RW)
*
* Integrity Check enable. Main enable switch.
*
* Values:
* - 0 - Disabled
* - 1 - Enabled
*/
//@{
#define BP_DCIC_DCICC_IC_EN (0) //!< Bit position for DCIC_DCICC_IC_EN.
#define BM_DCIC_DCICC_IC_EN (0x00000001) //!< Bit mask for DCIC_DCICC_IC_EN.
//! @brief Get value of DCIC_DCICC_IC_EN from a register value.
#define BG_DCIC_DCICC_IC_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICC_IC_EN) >> BP_DCIC_DCICC_IC_EN)
//! @brief Format value for bitfield DCIC_DCICC_IC_EN.
#define BF_DCIC_DCICC_IC_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICC_IC_EN) & BM_DCIC_DCICC_IC_EN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IC_EN field to a new value.
#define BW_DCIC_DCICC_IC_EN(x, v) (HW_DCIC_DCICC_WR(x, (HW_DCIC_DCICC_RD(x) & ~BM_DCIC_DCICC_IC_EN) | BF_DCIC_DCICC_IC_EN(v)))
#endif
//@}
/*! @name Register DCIC_DCICC, field DE_POL[4] (RW)
*
* DATA_EN_IN signal polarity.
*
* Values:
* - 0 - Active High.
* - 1 - Active Low (default).
*/
//@{
#define BP_DCIC_DCICC_DE_POL (4) //!< Bit position for DCIC_DCICC_DE_POL.
#define BM_DCIC_DCICC_DE_POL (0x00000010) //!< Bit mask for DCIC_DCICC_DE_POL.
//! @brief Get value of DCIC_DCICC_DE_POL from a register value.
#define BG_DCIC_DCICC_DE_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICC_DE_POL) >> BP_DCIC_DCICC_DE_POL)
//! @brief Format value for bitfield DCIC_DCICC_DE_POL.
#define BF_DCIC_DCICC_DE_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICC_DE_POL) & BM_DCIC_DCICC_DE_POL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DE_POL field to a new value.
#define BW_DCIC_DCICC_DE_POL(x, v) (HW_DCIC_DCICC_WR(x, (HW_DCIC_DCICC_RD(x) & ~BM_DCIC_DCICC_DE_POL) | BF_DCIC_DCICC_DE_POL(v)))
#endif
//@}
/*! @name Register DCIC_DCICC, field HSYNC_POL[5] (RW)
*
* HSYNC_IN signal polarity.
*
* Values:
* - 0 - Active High.
* - 1 - Active Low (default).
*/
//@{
#define BP_DCIC_DCICC_HSYNC_POL (5) //!< Bit position for DCIC_DCICC_HSYNC_POL.
#define BM_DCIC_DCICC_HSYNC_POL (0x00000020) //!< Bit mask for DCIC_DCICC_HSYNC_POL.
//! @brief Get value of DCIC_DCICC_HSYNC_POL from a register value.
#define BG_DCIC_DCICC_HSYNC_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICC_HSYNC_POL) >> BP_DCIC_DCICC_HSYNC_POL)
//! @brief Format value for bitfield DCIC_DCICC_HSYNC_POL.
#define BF_DCIC_DCICC_HSYNC_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICC_HSYNC_POL) & BM_DCIC_DCICC_HSYNC_POL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the HSYNC_POL field to a new value.
#define BW_DCIC_DCICC_HSYNC_POL(x, v) (HW_DCIC_DCICC_WR(x, (HW_DCIC_DCICC_RD(x) & ~BM_DCIC_DCICC_HSYNC_POL) | BF_DCIC_DCICC_HSYNC_POL(v)))
#endif
//@}
/*! @name Register DCIC_DCICC, field VSYNC_POL[6] (RW)
*
* VSYNC_IN signal polarity.
*
* Values:
* - 0 - Active High.
* - 1 - Active Low (default).
*/
//@{
#define BP_DCIC_DCICC_VSYNC_POL (6) //!< Bit position for DCIC_DCICC_VSYNC_POL.
#define BM_DCIC_DCICC_VSYNC_POL (0x00000040) //!< Bit mask for DCIC_DCICC_VSYNC_POL.
//! @brief Get value of DCIC_DCICC_VSYNC_POL from a register value.
#define BG_DCIC_DCICC_VSYNC_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICC_VSYNC_POL) >> BP_DCIC_DCICC_VSYNC_POL)
//! @brief Format value for bitfield DCIC_DCICC_VSYNC_POL.
#define BF_DCIC_DCICC_VSYNC_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICC_VSYNC_POL) & BM_DCIC_DCICC_VSYNC_POL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the VSYNC_POL field to a new value.
#define BW_DCIC_DCICC_VSYNC_POL(x, v) (HW_DCIC_DCICC_WR(x, (HW_DCIC_DCICC_RD(x) & ~BM_DCIC_DCICC_VSYNC_POL) | BF_DCIC_DCICC_VSYNC_POL(v)))
#endif
//@}
/*! @name Register DCIC_DCICC, field CLK_POL[7] (RW)
*
* DISP_CLK signal polarity.
*
* Values:
* - 0 - Not inverted (default).
* - 1 - Inverted.
*/
//@{
#define BP_DCIC_DCICC_CLK_POL (7) //!< Bit position for DCIC_DCICC_CLK_POL.
#define BM_DCIC_DCICC_CLK_POL (0x00000080) //!< Bit mask for DCIC_DCICC_CLK_POL.
//! @brief Get value of DCIC_DCICC_CLK_POL from a register value.
#define BG_DCIC_DCICC_CLK_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICC_CLK_POL) >> BP_DCIC_DCICC_CLK_POL)
//! @brief Format value for bitfield DCIC_DCICC_CLK_POL.
#define BF_DCIC_DCICC_CLK_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICC_CLK_POL) & BM_DCIC_DCICC_CLK_POL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CLK_POL field to a new value.
#define BW_DCIC_DCICC_CLK_POL(x, v) (HW_DCIC_DCICC_WR(x, (HW_DCIC_DCICC_RD(x) & ~BM_DCIC_DCICC_CLK_POL) | BF_DCIC_DCICC_CLK_POL(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DCIC_DCICIC - DCIC Interrupt Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DCIC_DCICIC - DCIC Interrupt Control Register (RW)
*
* Reset value: 0x00000003
*/
typedef union _hw_dcic_dcicic
{
reg32_t U;
struct _hw_dcic_dcicic_bitfields
{
unsigned EI_MASK : 1; //!< [0] Error Interrupt mask.
unsigned FI_MASK : 1; //!< [1] Functional Interrupt mask.
unsigned RESERVED0 : 1; //!< [2] Reserved
unsigned FREEZE_MASK : 1; //!< [3] Disable change of interrupt masks.
unsigned RESERVED1 : 12; //!< [15:4] Reserved
unsigned EXT_SIG_EN : 1; //!< [16] External controller mismatch indication signal.
unsigned RESERVED2 : 15; //!< [31:17] Reserved
} B;
} hw_dcic_dcicic_t;
#endif
/*!
* @name Constants and macros for entire DCIC_DCICIC register
*/
//@{
#define HW_DCIC_DCICIC_ADDR(x) (REGS_DCIC_BASE(x) + 0x4)
#ifndef __LANGUAGE_ASM__
#define HW_DCIC_DCICIC(x) (*(volatile hw_dcic_dcicic_t *) HW_DCIC_DCICIC_ADDR(x))
#define HW_DCIC_DCICIC_RD(x) (HW_DCIC_DCICIC(x).U)
#define HW_DCIC_DCICIC_WR(x, v) (HW_DCIC_DCICIC(x).U = (v))
#define HW_DCIC_DCICIC_SET(x, v) (HW_DCIC_DCICIC_WR(x, HW_DCIC_DCICIC_RD(x) | (v)))
#define HW_DCIC_DCICIC_CLR(x, v) (HW_DCIC_DCICIC_WR(x, HW_DCIC_DCICIC_RD(x) & ~(v)))
#define HW_DCIC_DCICIC_TOG(x, v) (HW_DCIC_DCICIC_WR(x, HW_DCIC_DCICIC_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual DCIC_DCICIC bitfields
*/
/*! @name Register DCIC_DCICIC, field EI_MASK[0] (RW)
*
* Error Interrupt mask. Can be changed only while FREEZE_MASK = 0.
*
* Values:
* - 0 - Mask disabled - Interrupt assertion enabled
* - 1 - Mask enabled - Interrupt assertion disabled (default)
*/
//@{
#define BP_DCIC_DCICIC_EI_MASK (0) //!< Bit position for DCIC_DCICIC_EI_MASK.
#define BM_DCIC_DCICIC_EI_MASK (0x00000001) //!< Bit mask for DCIC_DCICIC_EI_MASK.
//! @brief Get value of DCIC_DCICIC_EI_MASK from a register value.
#define BG_DCIC_DCICIC_EI_MASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICIC_EI_MASK) >> BP_DCIC_DCICIC_EI_MASK)
//! @brief Format value for bitfield DCIC_DCICIC_EI_MASK.
#define BF_DCIC_DCICIC_EI_MASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICIC_EI_MASK) & BM_DCIC_DCICIC_EI_MASK)
#ifndef __LANGUAGE_ASM__
//! @brief Set the EI_MASK field to a new value.
#define BW_DCIC_DCICIC_EI_MASK(x, v) (HW_DCIC_DCICIC_WR(x, (HW_DCIC_DCICIC_RD(x) & ~BM_DCIC_DCICIC_EI_MASK) | BF_DCIC_DCICIC_EI_MASK(v)))
#endif
//@}
/*! @name Register DCIC_DCICIC, field FI_MASK[1] (RW)
*
* Functional Interrupt mask. Can be changed only while FREEZE_MASK = 0.
*
* Values:
* - 0 - Mask disabled - Interrupt assertion enabled
* - 1 - Mask enabled - Interrupt assertion disabled (default)
*/
//@{
#define BP_DCIC_DCICIC_FI_MASK (1) //!< Bit position for DCIC_DCICIC_FI_MASK.
#define BM_DCIC_DCICIC_FI_MASK (0x00000002) //!< Bit mask for DCIC_DCICIC_FI_MASK.
//! @brief Get value of DCIC_DCICIC_FI_MASK from a register value.
#define BG_DCIC_DCICIC_FI_MASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICIC_FI_MASK) >> BP_DCIC_DCICIC_FI_MASK)
//! @brief Format value for bitfield DCIC_DCICIC_FI_MASK.
#define BF_DCIC_DCICIC_FI_MASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICIC_FI_MASK) & BM_DCIC_DCICIC_FI_MASK)
#ifndef __LANGUAGE_ASM__
//! @brief Set the FI_MASK field to a new value.
#define BW_DCIC_DCICIC_FI_MASK(x, v) (HW_DCIC_DCICIC_WR(x, (HW_DCIC_DCICIC_RD(x) & ~BM_DCIC_DCICIC_FI_MASK) | BF_DCIC_DCICIC_FI_MASK(v)))
#endif
//@}
/*! @name Register DCIC_DCICIC, field FREEZE_MASK[3] (RW)
*
* Disable change of interrupt masks. "Sticky" bit which can be set once and cleared by reset only.
*
* Values:
* - 0 - Masks change allowed (default)
* - 1 - Masks are frozen
*/
//@{
#define BP_DCIC_DCICIC_FREEZE_MASK (3) //!< Bit position for DCIC_DCICIC_FREEZE_MASK.
#define BM_DCIC_DCICIC_FREEZE_MASK (0x00000008) //!< Bit mask for DCIC_DCICIC_FREEZE_MASK.
//! @brief Get value of DCIC_DCICIC_FREEZE_MASK from a register value.
#define BG_DCIC_DCICIC_FREEZE_MASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICIC_FREEZE_MASK) >> BP_DCIC_DCICIC_FREEZE_MASK)
//! @brief Format value for bitfield DCIC_DCICIC_FREEZE_MASK.
#define BF_DCIC_DCICIC_FREEZE_MASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICIC_FREEZE_MASK) & BM_DCIC_DCICIC_FREEZE_MASK)
#ifndef __LANGUAGE_ASM__
//! @brief Set the FREEZE_MASK field to a new value.
#define BW_DCIC_DCICIC_FREEZE_MASK(x, v) (HW_DCIC_DCICIC_WR(x, (HW_DCIC_DCICIC_RD(x) & ~BM_DCIC_DCICIC_FREEZE_MASK) | BF_DCIC_DCICIC_FREEZE_MASK(v)))
#endif
//@}
/*! @name Register DCIC_DCICIC, field EXT_SIG_EN[16] (RW)
*
* External controller mismatch indication signal.
*
* Values:
* - 0 - Disabled (default)
* - 1 - Enabled
*/
//@{
#define BP_DCIC_DCICIC_EXT_SIG_EN (16) //!< Bit position for DCIC_DCICIC_EXT_SIG_EN.
#define BM_DCIC_DCICIC_EXT_SIG_EN (0x00010000) //!< Bit mask for DCIC_DCICIC_EXT_SIG_EN.
//! @brief Get value of DCIC_DCICIC_EXT_SIG_EN from a register value.
#define BG_DCIC_DCICIC_EXT_SIG_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICIC_EXT_SIG_EN) >> BP_DCIC_DCICIC_EXT_SIG_EN)
//! @brief Format value for bitfield DCIC_DCICIC_EXT_SIG_EN.
#define BF_DCIC_DCICIC_EXT_SIG_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICIC_EXT_SIG_EN) & BM_DCIC_DCICIC_EXT_SIG_EN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the EXT_SIG_EN field to a new value.
#define BW_DCIC_DCICIC_EXT_SIG_EN(x, v) (HW_DCIC_DCICIC_WR(x, (HW_DCIC_DCICIC_RD(x) & ~BM_DCIC_DCICIC_EXT_SIG_EN) | BF_DCIC_DCICIC_EXT_SIG_EN(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DCIC_DCICS - DCIC Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DCIC_DCICS - DCIC Status Register (W1C)
*
* Reset value: 0x00000000
*/
typedef union _hw_dcic_dcics
{
reg32_t U;
struct _hw_dcic_dcics_bitfields
{
unsigned ROI_MATCH_STAT : 16; //!< [15:0] Each set bit of this field indicates there was a mismatch at appropriate ROIs signature during the last frame.
unsigned EI_STAT : 1; //!< [16] Error Interrupt status.
unsigned FI_STAT : 1; //!< [17] Functional Interrupt status.
unsigned RESERVED0 : 14; //!< [31:18] Reserved
} B;
} hw_dcic_dcics_t;
#endif
/*!
* @name Constants and macros for entire DCIC_DCICS register
*/
//@{
#define HW_DCIC_DCICS_ADDR(x) (REGS_DCIC_BASE(x) + 0x8)
#ifndef __LANGUAGE_ASM__
#define HW_DCIC_DCICS(x) (*(volatile hw_dcic_dcics_t *) HW_DCIC_DCICS_ADDR(x))
#define HW_DCIC_DCICS_RD(x) (HW_DCIC_DCICS(x).U)
#define HW_DCIC_DCICS_WR(x, v) (HW_DCIC_DCICS(x).U = (v))
#define HW_DCIC_DCICS_SET(x, v) (HW_DCIC_DCICS_WR(x, HW_DCIC_DCICS_RD(x) | (v)))
#define HW_DCIC_DCICS_CLR(x, v) (HW_DCIC_DCICS_WR(x, HW_DCIC_DCICS_RD(x) & ~(v)))
#define HW_DCIC_DCICS_TOG(x, v) (HW_DCIC_DCICS_WR(x, HW_DCIC_DCICS_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual DCIC_DCICS bitfields
*/
/*! @name Register DCIC_DCICS, field ROI_MATCH_STAT[15:0] (W1C)
*
* Each set bit of this field indicates there was a mismatch at appropriate ROIs signature during
* the last frame. Valid only for active ROIs. Write "1" to clear.
*
* Values:
* - 0 - ROI calculated CRC matches expected signature
* - 1 - Mismatch at ROI calculated CRC
*/
//@{
#define BP_DCIC_DCICS_ROI_MATCH_STAT (0) //!< Bit position for DCIC_DCICS_ROI_MATCH_STAT.
#define BM_DCIC_DCICS_ROI_MATCH_STAT (0x0000ffff) //!< Bit mask for DCIC_DCICS_ROI_MATCH_STAT.
//! @brief Get value of DCIC_DCICS_ROI_MATCH_STAT from a register value.
#define BG_DCIC_DCICS_ROI_MATCH_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICS_ROI_MATCH_STAT) >> BP_DCIC_DCICS_ROI_MATCH_STAT)
//! @brief Format value for bitfield DCIC_DCICS_ROI_MATCH_STAT.
#define BF_DCIC_DCICS_ROI_MATCH_STAT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICS_ROI_MATCH_STAT) & BM_DCIC_DCICS_ROI_MATCH_STAT)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ROI_MATCH_STAT field to a new value.
#define BW_DCIC_DCICS_ROI_MATCH_STAT(x, v) (HW_DCIC_DCICS_WR(x, (HW_DCIC_DCICS_RD(x) & ~BM_DCIC_DCICS_ROI_MATCH_STAT) | BF_DCIC_DCICS_ROI_MATCH_STAT(v)))
#endif
//@}
/*! @name Register DCIC_DCICS, field EI_STAT[16] (RO)
*
* Error Interrupt status. Result of "OR" operation on ROI_MATCH_STAT[15:0] bits. Cleared when these
* bits are clear.
*
* Values:
* - 0 - No pending Interrupt
* - 1 - Pending Interrupt
*/
//@{
#define BP_DCIC_DCICS_EI_STAT (16) //!< Bit position for DCIC_DCICS_EI_STAT.
#define BM_DCIC_DCICS_EI_STAT (0x00010000) //!< Bit mask for DCIC_DCICS_EI_STAT.
//! @brief Get value of DCIC_DCICS_EI_STAT from a register value.
#define BG_DCIC_DCICS_EI_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICS_EI_STAT) >> BP_DCIC_DCICS_EI_STAT)
//@}
/*! @name Register DCIC_DCICS, field FI_STAT[17] (W1C)
*
* Functional Interrupt status. Write "1" to clear.
*
* Values:
* - 0 - No pending Interrupt
* - 1 - Pending Interrupt
*/
//@{
#define BP_DCIC_DCICS_FI_STAT (17) //!< Bit position for DCIC_DCICS_FI_STAT.
#define BM_DCIC_DCICS_FI_STAT (0x00020000) //!< Bit mask for DCIC_DCICS_FI_STAT.
//! @brief Get value of DCIC_DCICS_FI_STAT from a register value.
#define BG_DCIC_DCICS_FI_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICS_FI_STAT) >> BP_DCIC_DCICS_FI_STAT)
//! @brief Format value for bitfield DCIC_DCICS_FI_STAT.
#define BF_DCIC_DCICS_FI_STAT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICS_FI_STAT) & BM_DCIC_DCICS_FI_STAT)
#ifndef __LANGUAGE_ASM__
//! @brief Set the FI_STAT field to a new value.
#define BW_DCIC_DCICS_FI_STAT(x, v) (HW_DCIC_DCICS_WR(x, (HW_DCIC_DCICS_RD(x) & ~BM_DCIC_DCICS_FI_STAT) | BF_DCIC_DCICS_FI_STAT(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DCIC_DCICRC - DCIC ROI Config Register m
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DCIC_DCICRC - DCIC ROI Config Register m (RW)
*
* Reset value: 0x00000000
*/
typedef union _hw_dcic_dcicrc
{
reg32_t U;
struct _hw_dcic_dcicrc_bitfields
{
unsigned START_OFFSET_X : 13; //!< [12:0] Column number of ROIs upper-left corner (X coordinate)
unsigned RESERVED0 : 3; //!< [15:13] Reserved
unsigned START_OFFSET_Y : 12; //!< [27:16] Row number of ROIs upper-left corner (Y coordinate)
unsigned RESERVED1 : 2; //!< [29:28] Reserved
unsigned ROI_FREEZE : 1; //!< [30] When set, the only parameter of ROI #m that can be changed is reference signature.
unsigned ROI_EN : 1; //!< [31] ROI #m tracking enable
} B;
} hw_dcic_dcicrc_t;
#endif
/*!
* @name Constants and macros for entire DCIC_DCICRC register
*/
//@{
#define HW_DCIC_DCICRC_ADDR(x) (REGS_DCIC_BASE(x) + 0x10)
#ifndef __LANGUAGE_ASM__
#define HW_DCIC_DCICRC(x) (*(volatile hw_dcic_dcicrc_t *) HW_DCIC_DCICRC_ADDR(x))
#define HW_DCIC_DCICRC_RD(x) (HW_DCIC_DCICRC(x).U)
#define HW_DCIC_DCICRC_WR(x, v) (HW_DCIC_DCICRC(x).U = (v))
#define HW_DCIC_DCICRC_SET(x, v) (HW_DCIC_DCICRC_WR(x, HW_DCIC_DCICRC_RD(x) | (v)))
#define HW_DCIC_DCICRC_CLR(x, v) (HW_DCIC_DCICRC_WR(x, HW_DCIC_DCICRC_RD(x) & ~(v)))
#define HW_DCIC_DCICRC_TOG(x, v) (HW_DCIC_DCICRC_WR(x, HW_DCIC_DCICRC_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual DCIC_DCICRC bitfields
*/
/*! @name Register DCIC_DCICRC, field START_OFFSET_X[12:0] (RW)
*
* Column number of ROIs upper-left corner (X coordinate) Range: 0 to 2^ 13 -1
*/
//@{
#define BP_DCIC_DCICRC_START_OFFSET_X (0) //!< Bit position for DCIC_DCICRC_START_OFFSET_X.
#define BM_DCIC_DCICRC_START_OFFSET_X (0x00001fff) //!< Bit mask for DCIC_DCICRC_START_OFFSET_X.
//! @brief Get value of DCIC_DCICRC_START_OFFSET_X from a register value.
#define BG_DCIC_DCICRC_START_OFFSET_X(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRC_START_OFFSET_X) >> BP_DCIC_DCICRC_START_OFFSET_X)
//! @brief Format value for bitfield DCIC_DCICRC_START_OFFSET_X.
#define BF_DCIC_DCICRC_START_OFFSET_X(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRC_START_OFFSET_X) & BM_DCIC_DCICRC_START_OFFSET_X)
#ifndef __LANGUAGE_ASM__
//! @brief Set the START_OFFSET_X field to a new value.
#define BW_DCIC_DCICRC_START_OFFSET_X(x, v) (HW_DCIC_DCICRC_WR(x, (HW_DCIC_DCICRC_RD(x) & ~BM_DCIC_DCICRC_START_OFFSET_X) | BF_DCIC_DCICRC_START_OFFSET_X(v)))
#endif
//@}
/*! @name Register DCIC_DCICRC, field START_OFFSET_Y[27:16] (RW)
*
* Row number of ROIs upper-left corner (Y coordinate) Range: 0 to 2^ 12 -1
*/
//@{
#define BP_DCIC_DCICRC_START_OFFSET_Y (16) //!< Bit position for DCIC_DCICRC_START_OFFSET_Y.
#define BM_DCIC_DCICRC_START_OFFSET_Y (0x0fff0000) //!< Bit mask for DCIC_DCICRC_START_OFFSET_Y.
//! @brief Get value of DCIC_DCICRC_START_OFFSET_Y from a register value.
#define BG_DCIC_DCICRC_START_OFFSET_Y(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRC_START_OFFSET_Y) >> BP_DCIC_DCICRC_START_OFFSET_Y)
//! @brief Format value for bitfield DCIC_DCICRC_START_OFFSET_Y.
#define BF_DCIC_DCICRC_START_OFFSET_Y(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRC_START_OFFSET_Y) & BM_DCIC_DCICRC_START_OFFSET_Y)
#ifndef __LANGUAGE_ASM__
//! @brief Set the START_OFFSET_Y field to a new value.
#define BW_DCIC_DCICRC_START_OFFSET_Y(x, v) (HW_DCIC_DCICRC_WR(x, (HW_DCIC_DCICRC_RD(x) & ~BM_DCIC_DCICRC_START_OFFSET_Y) | BF_DCIC_DCICRC_START_OFFSET_Y(v)))
#endif
//@}
/*! @name Register DCIC_DCICRC, field ROI_FREEZE[30] (RW)
*
* When set, the only parameter of ROI #m that can be changed is reference signature. "Sticky" bit -
* can be set once and cleared by reset only.
*
* Values:
* - 0 - ROI configuration can be changed
* - 1 - ROI configuration is frozen
*/
//@{
#define BP_DCIC_DCICRC_ROI_FREEZE (30) //!< Bit position for DCIC_DCICRC_ROI_FREEZE.
#define BM_DCIC_DCICRC_ROI_FREEZE (0x40000000) //!< Bit mask for DCIC_DCICRC_ROI_FREEZE.
//! @brief Get value of DCIC_DCICRC_ROI_FREEZE from a register value.
#define BG_DCIC_DCICRC_ROI_FREEZE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRC_ROI_FREEZE) >> BP_DCIC_DCICRC_ROI_FREEZE)
//! @brief Format value for bitfield DCIC_DCICRC_ROI_FREEZE.
#define BF_DCIC_DCICRC_ROI_FREEZE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRC_ROI_FREEZE) & BM_DCIC_DCICRC_ROI_FREEZE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ROI_FREEZE field to a new value.
#define BW_DCIC_DCICRC_ROI_FREEZE(x, v) (HW_DCIC_DCICRC_WR(x, (HW_DCIC_DCICRC_RD(x) & ~BM_DCIC_DCICRC_ROI_FREEZE) | BF_DCIC_DCICRC_ROI_FREEZE(v)))
#endif
//@}
/*! @name Register DCIC_DCICRC, field ROI_EN[31] (RW)
*
* ROI #m tracking enable
*
* Values:
* - 0 - Disabled
* - 1 - Enabled
*/
//@{
#define BP_DCIC_DCICRC_ROI_EN (31) //!< Bit position for DCIC_DCICRC_ROI_EN.
#define BM_DCIC_DCICRC_ROI_EN (0x80000000) //!< Bit mask for DCIC_DCICRC_ROI_EN.
//! @brief Get value of DCIC_DCICRC_ROI_EN from a register value.
#define BG_DCIC_DCICRC_ROI_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRC_ROI_EN) >> BP_DCIC_DCICRC_ROI_EN)
//! @brief Format value for bitfield DCIC_DCICRC_ROI_EN.
#define BF_DCIC_DCICRC_ROI_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRC_ROI_EN) & BM_DCIC_DCICRC_ROI_EN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ROI_EN field to a new value.
#define BW_DCIC_DCICRC_ROI_EN(x, v) (HW_DCIC_DCICRC_WR(x, (HW_DCIC_DCICRC_RD(x) & ~BM_DCIC_DCICRC_ROI_EN) | BF_DCIC_DCICRC_ROI_EN(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DCIC_DCICRS - DCIC ROI Size Register m
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DCIC_DCICRS - DCIC ROI Size Register m (RW)
*
* Reset value: 0x00000000
*/
typedef union _hw_dcic_dcicrs
{
reg32_t U;
struct _hw_dcic_dcicrs_bitfields
{
unsigned END_OFFSET_X : 13; //!< [12:0] Column number of ROIs lower-right corner (X coordinate)
unsigned RESERVED0 : 3; //!< [15:13] Reserved
unsigned END_OFFSET_Y : 12; //!< [27:16] Row number of ROIs lower-right corner (Y coordinate)
unsigned RESERVED1 : 4; //!< [31:28] Reserved
} B;
} hw_dcic_dcicrs_t;
#endif
/*!
* @name Constants and macros for entire DCIC_DCICRS register
*/
//@{
#define HW_DCIC_DCICRS_ADDR(x) (REGS_DCIC_BASE(x) + 0x14)
#ifndef __LANGUAGE_ASM__
#define HW_DCIC_DCICRS(x) (*(volatile hw_dcic_dcicrs_t *) HW_DCIC_DCICRS_ADDR(x))
#define HW_DCIC_DCICRS_RD(x) (HW_DCIC_DCICRS(x).U)
#define HW_DCIC_DCICRS_WR(x, v) (HW_DCIC_DCICRS(x).U = (v))
#define HW_DCIC_DCICRS_SET(x, v) (HW_DCIC_DCICRS_WR(x, HW_DCIC_DCICRS_RD(x) | (v)))
#define HW_DCIC_DCICRS_CLR(x, v) (HW_DCIC_DCICRS_WR(x, HW_DCIC_DCICRS_RD(x) & ~(v)))
#define HW_DCIC_DCICRS_TOG(x, v) (HW_DCIC_DCICRS_WR(x, HW_DCIC_DCICRS_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual DCIC_DCICRS bitfields
*/
/*! @name Register DCIC_DCICRS, field END_OFFSET_X[12:0] (RW)
*
* Column number of ROIs lower-right corner (X coordinate) Range: 1 to 2^ 13 -1
*/
//@{
#define BP_DCIC_DCICRS_END_OFFSET_X (0) //!< Bit position for DCIC_DCICRS_END_OFFSET_X.
#define BM_DCIC_DCICRS_END_OFFSET_X (0x00001fff) //!< Bit mask for DCIC_DCICRS_END_OFFSET_X.
//! @brief Get value of DCIC_DCICRS_END_OFFSET_X from a register value.
#define BG_DCIC_DCICRS_END_OFFSET_X(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRS_END_OFFSET_X) >> BP_DCIC_DCICRS_END_OFFSET_X)
//! @brief Format value for bitfield DCIC_DCICRS_END_OFFSET_X.
#define BF_DCIC_DCICRS_END_OFFSET_X(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRS_END_OFFSET_X) & BM_DCIC_DCICRS_END_OFFSET_X)
#ifndef __LANGUAGE_ASM__
//! @brief Set the END_OFFSET_X field to a new value.
#define BW_DCIC_DCICRS_END_OFFSET_X(x, v) (HW_DCIC_DCICRS_WR(x, (HW_DCIC_DCICRS_RD(x) & ~BM_DCIC_DCICRS_END_OFFSET_X) | BF_DCIC_DCICRS_END_OFFSET_X(v)))
#endif
//@}
/*! @name Register DCIC_DCICRS, field END_OFFSET_Y[27:16] (RW)
*
* Row number of ROIs lower-right corner (Y coordinate) Range: 1 to 2^ 12 -1
*/
//@{
#define BP_DCIC_DCICRS_END_OFFSET_Y (16) //!< Bit position for DCIC_DCICRS_END_OFFSET_Y.
#define BM_DCIC_DCICRS_END_OFFSET_Y (0x0fff0000) //!< Bit mask for DCIC_DCICRS_END_OFFSET_Y.
//! @brief Get value of DCIC_DCICRS_END_OFFSET_Y from a register value.
#define BG_DCIC_DCICRS_END_OFFSET_Y(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRS_END_OFFSET_Y) >> BP_DCIC_DCICRS_END_OFFSET_Y)
//! @brief Format value for bitfield DCIC_DCICRS_END_OFFSET_Y.
#define BF_DCIC_DCICRS_END_OFFSET_Y(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRS_END_OFFSET_Y) & BM_DCIC_DCICRS_END_OFFSET_Y)
#ifndef __LANGUAGE_ASM__
//! @brief Set the END_OFFSET_Y field to a new value.
#define BW_DCIC_DCICRS_END_OFFSET_Y(x, v) (HW_DCIC_DCICRS_WR(x, (HW_DCIC_DCICRS_RD(x) & ~BM_DCIC_DCICRS_END_OFFSET_Y) | BF_DCIC_DCICRS_END_OFFSET_Y(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DCIC_DCICRRS - DCIC ROI Reference Signature Register m
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DCIC_DCICRRS - DCIC ROI Reference Signature Register m (RW)
*
* Reset value: 0x00000000
*/
typedef union _hw_dcic_dcicrrs
{
reg32_t U;
struct _hw_dcic_dcicrrs_bitfields
{
unsigned REFERENCE_SIGNATURE : 32; //!< [31:0] 32-bit expected signature (CRC calculation result) for ROI #m
} B;
} hw_dcic_dcicrrs_t;
#endif
/*!
* @name Constants and macros for entire DCIC_DCICRRS register
*/
//@{
#define HW_DCIC_DCICRRS_ADDR(x) (REGS_DCIC_BASE(x) + 0x18)
#ifndef __LANGUAGE_ASM__
#define HW_DCIC_DCICRRS(x) (*(volatile hw_dcic_dcicrrs_t *) HW_DCIC_DCICRRS_ADDR(x))
#define HW_DCIC_DCICRRS_RD(x) (HW_DCIC_DCICRRS(x).U)
#define HW_DCIC_DCICRRS_WR(x, v) (HW_DCIC_DCICRRS(x).U = (v))
#define HW_DCIC_DCICRRS_SET(x, v) (HW_DCIC_DCICRRS_WR(x, HW_DCIC_DCICRRS_RD(x) | (v)))
#define HW_DCIC_DCICRRS_CLR(x, v) (HW_DCIC_DCICRRS_WR(x, HW_DCIC_DCICRRS_RD(x) & ~(v)))
#define HW_DCIC_DCICRRS_TOG(x, v) (HW_DCIC_DCICRRS_WR(x, HW_DCIC_DCICRRS_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual DCIC_DCICRRS bitfields
*/
/*! @name Register DCIC_DCICRRS, field REFERENCE_SIGNATURE[31:0] (RW)
*
* 32-bit expected signature (CRC calculation result) for ROI #m
*/
//@{
#define BP_DCIC_DCICRRS_REFERENCE_SIGNATURE (0) //!< Bit position for DCIC_DCICRRS_REFERENCE_SIGNATURE.
#define BM_DCIC_DCICRRS_REFERENCE_SIGNATURE (0xffffffff) //!< Bit mask for DCIC_DCICRRS_REFERENCE_SIGNATURE.
//! @brief Get value of DCIC_DCICRRS_REFERENCE_SIGNATURE from a register value.
#define BG_DCIC_DCICRRS_REFERENCE_SIGNATURE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRRS_REFERENCE_SIGNATURE) >> BP_DCIC_DCICRRS_REFERENCE_SIGNATURE)
//! @brief Format value for bitfield DCIC_DCICRRS_REFERENCE_SIGNATURE.
#define BF_DCIC_DCICRRS_REFERENCE_SIGNATURE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRRS_REFERENCE_SIGNATURE) & BM_DCIC_DCICRRS_REFERENCE_SIGNATURE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the REFERENCE_SIGNATURE field to a new value.
#define BW_DCIC_DCICRRS_REFERENCE_SIGNATURE(x, v) (HW_DCIC_DCICRRS_WR(x, (HW_DCIC_DCICRRS_RD(x) & ~BM_DCIC_DCICRRS_REFERENCE_SIGNATURE) | BF_DCIC_DCICRRS_REFERENCE_SIGNATURE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DCIC_DCICRCS - DCIC ROI Calculated Signature m
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DCIC_DCICRCS - DCIC ROI Calculated Signature m (RO)
*
* Reset value: 0x00000000
*/
typedef union _hw_dcic_dcicrcs
{
reg32_t U;
struct _hw_dcic_dcicrcs_bitfields
{
unsigned CALCULATED_SIGNATURE : 32; //!< [31:0] 32-bit actual signature (CRC calculation result) for ROI #m during the last frame.
} B;
} hw_dcic_dcicrcs_t;
#endif
/*!
* @name Constants and macros for entire DCIC_DCICRCS register
*/
//@{
#define HW_DCIC_DCICRCS_ADDR(x) (REGS_DCIC_BASE(x) + 0x1c)
#ifndef __LANGUAGE_ASM__
#define HW_DCIC_DCICRCS(x) (*(volatile hw_dcic_dcicrcs_t *) HW_DCIC_DCICRCS_ADDR(x))
#define HW_DCIC_DCICRCS_RD(x) (HW_DCIC_DCICRCS(x).U)
#endif
//@}
/*
* constants & macros for individual DCIC_DCICRCS bitfields
*/
/*! @name Register DCIC_DCICRCS, field CALCULATED_SIGNATURE[31:0] (RO)
*
* 32-bit actual signature (CRC calculation result) for ROI #m during the last frame. Updated
* automatically at the beginning of a next frame.
*/
//@{
#define BP_DCIC_DCICRCS_CALCULATED_SIGNATURE (0) //!< Bit position for DCIC_DCICRCS_CALCULATED_SIGNATURE.
#define BM_DCIC_DCICRCS_CALCULATED_SIGNATURE (0xffffffff) //!< Bit mask for DCIC_DCICRCS_CALCULATED_SIGNATURE.
//! @brief Get value of DCIC_DCICRCS_CALCULATED_SIGNATURE from a register value.
#define BG_DCIC_DCICRCS_CALCULATED_SIGNATURE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRCS_CALCULATED_SIGNATURE) >> BP_DCIC_DCICRCS_CALCULATED_SIGNATURE)
//@}
//-------------------------------------------------------------------------------------------
// hw_dcic_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All DCIC module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_dcic
{
volatile hw_dcic_dcicc_t DCICC; //!< DCIC Control Register
volatile hw_dcic_dcicic_t DCICIC; //!< DCIC Interrupt Control Register
volatile hw_dcic_dcics_t DCICS; //!< DCIC Status Register
reg32_t _reserved0;
volatile hw_dcic_dcicrc_t DCICRC; //!< DCIC ROI Config Register m
volatile hw_dcic_dcicrs_t DCICRS; //!< DCIC ROI Size Register m
volatile hw_dcic_dcicrrs_t DCICRRS; //!< DCIC ROI Reference Signature Register m
volatile hw_dcic_dcicrcs_t DCICRCS; //!< DCIC ROI Calculated Signature m
} hw_dcic_t;
#pragma pack()
//! @brief Macro to access all DCIC registers.
//! @param x DCIC instance number.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_DCIC(0)</code>.
#define HW_DCIC(x) (*(hw_dcic_t *) REGS_DCIC_BASE(x))
#endif
#endif // __HW_DCIC_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_EPIT_REGISTERS_H__
#define __HW_EPIT_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ EPIT
*
* EPIT
*
* Registers defined in this header file:
* - HW_EPIT_CR - Control register
* - HW_EPIT_SR - Status register
* - HW_EPIT_LR - Load register
* - HW_EPIT_CMPR - Compare register
* - HW_EPIT_CNR - Counter register
*
* - hw_epit_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_EPIT_BASE
#define HW_EPIT_INSTANCE_COUNT (2) //!< Number of instances of the EPIT module.
#define HW_EPIT1 (1) //!< Instance number for EPIT1.
#define HW_EPIT2 (2) //!< Instance number for EPIT2.
#define REGS_EPIT1_BASE (0x020d0000) //!< Base address for EPIT instance number 1.
#define REGS_EPIT2_BASE (0x020d4000) //!< Base address for EPIT instance number 2.
//! @brief Get the base address of EPIT by instance number.
//! @param x EPIT instance number, from 1 through 2.
#define REGS_EPIT_BASE(x) ( (x) == HW_EPIT1 ? REGS_EPIT1_BASE : (x) == HW_EPIT2 ? REGS_EPIT2_BASE : 0x00d00000)
//! @brief Get the instance number given a base address.
//! @param b Base address for an instance of EPIT.
#define REGS_EPIT_INSTANCE(b) ( (b) == REGS_EPIT1_BASE ? HW_EPIT1 : (b) == REGS_EPIT2_BASE ? HW_EPIT2 : 0)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_EPIT_CR - Control register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_EPIT_CR - Control register (RW)
*
* Reset value: 0x00000000
*
* The EPIT control register (EPIT_CR) is used to configure the operating settings of the EPIT. It
* contains the clock division prescaler value and also the interrupt enable bit. Additionally, it
* contains other control bits which are described below. Peripheral Bus Write access to EPIT
* Control Register (EPIT_CR) results in one cycle of the wait state, while other valid peripheral
* bus accesses are with 0 wait state.
*/
typedef union _hw_epit_cr
{
reg32_t U;
struct _hw_epit_cr_bitfields
{
unsigned EN : 1; //!< [0] This bit enables the EPIT.
unsigned ENMOD : 1; //!< [1] EPIT enable mode.
unsigned OCIEN : 1; //!< [2] Output compare interrupt enable.
unsigned RLD : 1; //!< [3] Counter reload control.
unsigned PRESCALAR : 12; //!< [15:4] Counter clock prescaler value.
unsigned SWR : 1; //!< [16] Software reset.
unsigned IOVW : 1; //!< [17] EPIT counter overwrite enable.
unsigned DBGEN : 1; //!< [18] This bit is used to keep the EPIT functional in debug mode.
unsigned WAITEN : 1; //!< [19] This read/write control bit enables the operation of the EPIT during wait mode.
unsigned RESERVED0 : 1; //!< [20] Reserved.
unsigned STOPEN : 1; //!< [21] EPIT stop mode enable.
unsigned OM : 2; //!< [23:22] EPIT output mode.This bit field determines the mode of EPIT output on the output pin.
unsigned CLKSRC : 2; //!< [25:24] Select clock source
unsigned RESERVED1 : 6; //!< [31:26] Reserved.
} B;
} hw_epit_cr_t;
#endif
/*!
* @name Constants and macros for entire EPIT_CR register
*/
//@{
#define HW_EPIT_CR_ADDR(x) (REGS_EPIT_BASE(x) + 0x0)
#ifndef __LANGUAGE_ASM__
#define HW_EPIT_CR(x) (*(volatile hw_epit_cr_t *) HW_EPIT_CR_ADDR(x))
#define HW_EPIT_CR_RD(x) (HW_EPIT_CR(x).U)
#define HW_EPIT_CR_WR(x, v) (HW_EPIT_CR(x).U = (v))
#define HW_EPIT_CR_SET(x, v) (HW_EPIT_CR_WR(x, HW_EPIT_CR_RD(x) | (v)))
#define HW_EPIT_CR_CLR(x, v) (HW_EPIT_CR_WR(x, HW_EPIT_CR_RD(x) & ~(v)))
#define HW_EPIT_CR_TOG(x, v) (HW_EPIT_CR_WR(x, HW_EPIT_CR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual EPIT_CR bitfields
*/
/*! @name Register EPIT_CR, field EN[0] (RW)
*
* This bit enables the EPIT. EPIT counter and prescaler value when EPIT is enabled (EN = 1), is
* dependent upon ENMOD and RLD bit as described for ENMOD bit. It is recommended that all registers
* be properly programmed before setting this bit. This bit is reset by a hardware reset. A software
* reset does not affect this bit.
*
* Values:
* - 0 - EPIT is disabled
* - 1 - EPIT is enabled
*/
//@{
#define BP_EPIT_CR_EN (0) //!< Bit position for EPIT_CR_EN.
#define BM_EPIT_CR_EN (0x00000001) //!< Bit mask for EPIT_CR_EN.
//! @brief Get value of EPIT_CR_EN from a register value.
#define BG_EPIT_CR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_EN) >> BP_EPIT_CR_EN)
//! @brief Format value for bitfield EPIT_CR_EN.
#define BF_EPIT_CR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_EN) & BM_EPIT_CR_EN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the EN field to a new value.
#define BW_EPIT_CR_EN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_EN) | BF_EPIT_CR_EN(v)))
#endif
//@}
/*! @name Register EPIT_CR, field ENMOD[1] (RW)
*
* EPIT enable mode. When EPIT is disabled (EN=0), both main counter and prescaler counter freeze
* their count at current count values. ENMOD bit is a r/w bit that determines the counter value
* when the EPIT is enabled again by setting EN bit. If ENMOD bit is set, then main counter is
* loaded with the load value (If RLD=1)/ 0xFFFF_FFFF (If RLD=0) and prescaler counter is reset,
* when EPIT is enabled (EN=1). If ENMOD is programmed to 0 then both main counter and prescaler
* counter restart counting from their frozen values when EPIT is enabled (EN=1). If EPIT is
* programmed to be disabled in a low-power mode (STOP/WAIT/DEBUG), then both the main counter and
* the prescaler counter freeze at their current count values when EPIT enters low-power mode. When
* EPIT exits the low-power mode, both main counter and prescaler counter start counting from their
* frozen values irrespective of the ENMOD bit. This bit is reset by a hardware reset. A software
* reset does not affect this bit.
*
* Values:
* - 0 - Counter starts counting from the value it had when it was disabled.
* - 1 - Counter starts count from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0)
*/
//@{
#define BP_EPIT_CR_ENMOD (1) //!< Bit position for EPIT_CR_ENMOD.
#define BM_EPIT_CR_ENMOD (0x00000002) //!< Bit mask for EPIT_CR_ENMOD.
//! @brief Get value of EPIT_CR_ENMOD from a register value.
#define BG_EPIT_CR_ENMOD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_ENMOD) >> BP_EPIT_CR_ENMOD)
//! @brief Format value for bitfield EPIT_CR_ENMOD.
#define BF_EPIT_CR_ENMOD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_ENMOD) & BM_EPIT_CR_ENMOD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ENMOD field to a new value.
#define BW_EPIT_CR_ENMOD(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_ENMOD) | BF_EPIT_CR_ENMOD(v)))
#endif
//@}
/*! @name Register EPIT_CR, field OCIEN[2] (RW)
*
* Output compare interrupt enable. This bit enables the generation of interrupt on occurrence of
* compare event.
*
* Values:
* - 0 - Compare interrupt disabled
* - 1 - Compare interrupt enabled
*/
//@{
#define BP_EPIT_CR_OCIEN (2) //!< Bit position for EPIT_CR_OCIEN.
#define BM_EPIT_CR_OCIEN (0x00000004) //!< Bit mask for EPIT_CR_OCIEN.
//! @brief Get value of EPIT_CR_OCIEN from a register value.
#define BG_EPIT_CR_OCIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_OCIEN) >> BP_EPIT_CR_OCIEN)
//! @brief Format value for bitfield EPIT_CR_OCIEN.
#define BF_EPIT_CR_OCIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_OCIEN) & BM_EPIT_CR_OCIEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the OCIEN field to a new value.
#define BW_EPIT_CR_OCIEN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_OCIEN) | BF_EPIT_CR_OCIEN(v)))
#endif
//@}
/*! @name Register EPIT_CR, field RLD[3] (RW)
*
* Counter reload control. This bit is cleared by hardware reset. It decides the counter
* functionality, whether to run in free-running mode or set-and-forget mode.
*
* Values:
* - 0 - When the counter reaches zero it rolls over to 0xFFFF_FFFF (free-running mode)
* - 1 - When the counter reaches zero it reloads from the modulus register (set-and-forget mode)
*/
//@{
#define BP_EPIT_CR_RLD (3) //!< Bit position for EPIT_CR_RLD.
#define BM_EPIT_CR_RLD (0x00000008) //!< Bit mask for EPIT_CR_RLD.
//! @brief Get value of EPIT_CR_RLD from a register value.
#define BG_EPIT_CR_RLD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_RLD) >> BP_EPIT_CR_RLD)
//! @brief Format value for bitfield EPIT_CR_RLD.
#define BF_EPIT_CR_RLD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_RLD) & BM_EPIT_CR_RLD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the RLD field to a new value.
#define BW_EPIT_CR_RLD(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_RLD) | BF_EPIT_CR_RLD(v)))
#endif
//@}
/*! @name Register EPIT_CR, field PRESCALAR[15:4] (RW)
*
* Counter clock prescaler value. This bit field determines the prescaler value by which the clock
* is divided before it goes to the counter
*
* Values:
* - 0x000 - Divide by 1
* - 0x001 - Divide by 2...
* - 0xFFF - Divide by 4096
*/
//@{
#define BP_EPIT_CR_PRESCALAR (4) //!< Bit position for EPIT_CR_PRESCALAR.
#define BM_EPIT_CR_PRESCALAR (0x0000fff0) //!< Bit mask for EPIT_CR_PRESCALAR.
//! @brief Get value of EPIT_CR_PRESCALAR from a register value.
#define BG_EPIT_CR_PRESCALAR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_PRESCALAR) >> BP_EPIT_CR_PRESCALAR)
//! @brief Format value for bitfield EPIT_CR_PRESCALAR.
#define BF_EPIT_CR_PRESCALAR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_PRESCALAR) & BM_EPIT_CR_PRESCALAR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PRESCALAR field to a new value.
#define BW_EPIT_CR_PRESCALAR(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_PRESCALAR) | BF_EPIT_CR_PRESCALAR(v)))
#endif
//@}
/*! @name Register EPIT_CR, field SWR[16] (RW)
*
* Software reset. The EPIT is reset when this bit is set to 1. It is a self clearing bit. This bit
* is set when the block is in reset state and is cleared when the reset procedure is over. Setting
* this bit resets all the registers to their reset values, except for the EN, ENMOD, STOPEN, WAITEN
* and DBGEN bits in this control register
*
* Values:
* - 0 - EPIT is out of reset
* - 1 - EPIT is undergoing reset
*/
//@{
#define BP_EPIT_CR_SWR (16) //!< Bit position for EPIT_CR_SWR.
#define BM_EPIT_CR_SWR (0x00010000) //!< Bit mask for EPIT_CR_SWR.
//! @brief Get value of EPIT_CR_SWR from a register value.
#define BG_EPIT_CR_SWR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_SWR) >> BP_EPIT_CR_SWR)
//! @brief Format value for bitfield EPIT_CR_SWR.
#define BF_EPIT_CR_SWR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_SWR) & BM_EPIT_CR_SWR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SWR field to a new value.
#define BW_EPIT_CR_SWR(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_SWR) | BF_EPIT_CR_SWR(v)))
#endif
//@}
/*! @name Register EPIT_CR, field IOVW[17] (RW)
*
* EPIT counter overwrite enable. This bit controls the counter data when the modulus register is
* written. When this bit is set, all writes to the load register overwrites the counter contents
* and the counter starts subsequently counting down from the programmed value.
*
* Values:
* - 0 - Write to load register does not result in counter value being overwritten.
* - 1 - Write to load register results in immediate overwriting of counter value.
*/
//@{
#define BP_EPIT_CR_IOVW (17) //!< Bit position for EPIT_CR_IOVW.
#define BM_EPIT_CR_IOVW (0x00020000) //!< Bit mask for EPIT_CR_IOVW.
//! @brief Get value of EPIT_CR_IOVW from a register value.
#define BG_EPIT_CR_IOVW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_IOVW) >> BP_EPIT_CR_IOVW)
//! @brief Format value for bitfield EPIT_CR_IOVW.
#define BF_EPIT_CR_IOVW(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_IOVW) & BM_EPIT_CR_IOVW)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IOVW field to a new value.
#define BW_EPIT_CR_IOVW(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_IOVW) | BF_EPIT_CR_IOVW(v)))
#endif
//@}
/*! @name Register EPIT_CR, field DBGEN[18] (RW)
*
* This bit is used to keep the EPIT functional in debug mode. When this bit is cleared, the input
* clock is gated off in debug mode.This bit is reset by hardware reset. A software reset does not
* affect this bit.
*
* Values:
* - 0 - Inactive in debug mode
* - 1 - Active in debug mode
*/
//@{
#define BP_EPIT_CR_DBGEN (18) //!< Bit position for EPIT_CR_DBGEN.
#define BM_EPIT_CR_DBGEN (0x00040000) //!< Bit mask for EPIT_CR_DBGEN.
//! @brief Get value of EPIT_CR_DBGEN from a register value.
#define BG_EPIT_CR_DBGEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_DBGEN) >> BP_EPIT_CR_DBGEN)
//! @brief Format value for bitfield EPIT_CR_DBGEN.
#define BF_EPIT_CR_DBGEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_DBGEN) & BM_EPIT_CR_DBGEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DBGEN field to a new value.
#define BW_EPIT_CR_DBGEN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_DBGEN) | BF_EPIT_CR_DBGEN(v)))
#endif
//@}
/*! @name Register EPIT_CR, field WAITEN[19] (RW)
*
* This read/write control bit enables the operation of the EPIT during wait mode. This bit is reset
* by a hardware reset. A software reset does not affect this bit.
*
* Values:
* - 0 - EPIT is disabled in wait mode
* - 1 - EPIT is enabled in wait mode
*/
//@{
#define BP_EPIT_CR_WAITEN (19) //!< Bit position for EPIT_CR_WAITEN.
#define BM_EPIT_CR_WAITEN (0x00080000) //!< Bit mask for EPIT_CR_WAITEN.
//! @brief Get value of EPIT_CR_WAITEN from a register value.
#define BG_EPIT_CR_WAITEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_WAITEN) >> BP_EPIT_CR_WAITEN)
//! @brief Format value for bitfield EPIT_CR_WAITEN.
#define BF_EPIT_CR_WAITEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_WAITEN) & BM_EPIT_CR_WAITEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WAITEN field to a new value.
#define BW_EPIT_CR_WAITEN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_WAITEN) | BF_EPIT_CR_WAITEN(v)))
#endif
//@}
/*! @name Register EPIT_CR, field STOPEN[21] (RW)
*
* EPIT stop mode enable. This read/write control bit enables the operation of the EPIT during stop
* mode. This bit is reset by a hardware reset and unaffected by software reset.
*
* Values:
* - 0 - EPIT is disabled in stop mode
* - 1 - EPIT is enabled in stop mode
*/
//@{
#define BP_EPIT_CR_STOPEN (21) //!< Bit position for EPIT_CR_STOPEN.
#define BM_EPIT_CR_STOPEN (0x00200000) //!< Bit mask for EPIT_CR_STOPEN.
//! @brief Get value of EPIT_CR_STOPEN from a register value.
#define BG_EPIT_CR_STOPEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_STOPEN) >> BP_EPIT_CR_STOPEN)
//! @brief Format value for bitfield EPIT_CR_STOPEN.
#define BF_EPIT_CR_STOPEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_STOPEN) & BM_EPIT_CR_STOPEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the STOPEN field to a new value.
#define BW_EPIT_CR_STOPEN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_STOPEN) | BF_EPIT_CR_STOPEN(v)))
#endif
//@}
/*! @name Register EPIT_CR, field OM[23:22] (RW)
*
* EPIT output mode.This bit field determines the mode of EPIT output on the output pin.
*
* Values:
* - 00 - EPIT output is disconnected from pad
* - 01 - Toggle output pin
* - 10 - Clear output pin
* - 11 - Set output pin
*/
//@{
#define BP_EPIT_CR_OM (22) //!< Bit position for EPIT_CR_OM.
#define BM_EPIT_CR_OM (0x00c00000) //!< Bit mask for EPIT_CR_OM.
//! @brief Get value of EPIT_CR_OM from a register value.
#define BG_EPIT_CR_OM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_OM) >> BP_EPIT_CR_OM)
//! @brief Format value for bitfield EPIT_CR_OM.
#define BF_EPIT_CR_OM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_OM) & BM_EPIT_CR_OM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the OM field to a new value.
#define BW_EPIT_CR_OM(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_OM) | BF_EPIT_CR_OM(v)))
#endif
//@}
/*! @name Register EPIT_CR, field CLKSRC[25:24] (RW)
*
* Select clock source These bits determine which clock input is to be selected for running the
* counter. This field value should only be changed when the EPIT is disabled by clearing the EN bit
* in this register. For other programming requirements while changing clock source, refer to .
*
* Values:
* - 00 - Clock is off
* - 01 - Peripheral clock
* - 10 - High-frequency reference clock
* - 11 - Low-frequency reference clock
*/
//@{
#define BP_EPIT_CR_CLKSRC (24) //!< Bit position for EPIT_CR_CLKSRC.
#define BM_EPIT_CR_CLKSRC (0x03000000) //!< Bit mask for EPIT_CR_CLKSRC.
//! @brief Get value of EPIT_CR_CLKSRC from a register value.
#define BG_EPIT_CR_CLKSRC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_CLKSRC) >> BP_EPIT_CR_CLKSRC)
//! @brief Format value for bitfield EPIT_CR_CLKSRC.
#define BF_EPIT_CR_CLKSRC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_CLKSRC) & BM_EPIT_CR_CLKSRC)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CLKSRC field to a new value.
#define BW_EPIT_CR_CLKSRC(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_CLKSRC) | BF_EPIT_CR_CLKSRC(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_EPIT_SR - Status register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_EPIT_SR - Status register (RW)
*
* Reset value: 0x00000000
*
* The EPIT status register (EPIT_SR) has a single status bit for the output compare event. The bit
* is a write 1 to clear bit.
*/
typedef union _hw_epit_sr
{
reg32_t U;
struct _hw_epit_sr_bitfields
{
unsigned OCIF : 1; //!< [0] Output compare interrupt flag.
unsigned RESERVED0 : 31; //!< [31:1] Reserved.
} B;
} hw_epit_sr_t;
#endif
/*!
* @name Constants and macros for entire EPIT_SR register
*/
//@{
#define HW_EPIT_SR_ADDR(x) (REGS_EPIT_BASE(x) + 0x4)
#ifndef __LANGUAGE_ASM__
#define HW_EPIT_SR(x) (*(volatile hw_epit_sr_t *) HW_EPIT_SR_ADDR(x))
#define HW_EPIT_SR_RD(x) (HW_EPIT_SR(x).U)
#define HW_EPIT_SR_WR(x, v) (HW_EPIT_SR(x).U = (v))
#define HW_EPIT_SR_SET(x, v) (HW_EPIT_SR_WR(x, HW_EPIT_SR_RD(x) | (v)))
#define HW_EPIT_SR_CLR(x, v) (HW_EPIT_SR_WR(x, HW_EPIT_SR_RD(x) & ~(v)))
#define HW_EPIT_SR_TOG(x, v) (HW_EPIT_SR_WR(x, HW_EPIT_SR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual EPIT_SR bitfields
*/
/*! @name Register EPIT_SR, field OCIF[0] (W1C)
*
* Output compare interrupt flag. This bit is the interrupt flag that is set when the content of
* counter equals the content of the compare register (EPIT_CMPR). The bit is a write 1 to clear
* bit.
*
* Values:
* - 0 - Compare event has not occurred
* - 1 - Compare event occurred
*/
//@{
#define BP_EPIT_SR_OCIF (0) //!< Bit position for EPIT_SR_OCIF.
#define BM_EPIT_SR_OCIF (0x00000001) //!< Bit mask for EPIT_SR_OCIF.
//! @brief Get value of EPIT_SR_OCIF from a register value.
#define BG_EPIT_SR_OCIF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_SR_OCIF) >> BP_EPIT_SR_OCIF)
//! @brief Format value for bitfield EPIT_SR_OCIF.
#define BF_EPIT_SR_OCIF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_SR_OCIF) & BM_EPIT_SR_OCIF)
#ifndef __LANGUAGE_ASM__
//! @brief Set the OCIF field to a new value.
#define BW_EPIT_SR_OCIF(x, v) (HW_EPIT_SR_WR(x, (HW_EPIT_SR_RD(x) & ~BM_EPIT_SR_OCIF) | BF_EPIT_SR_OCIF(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_EPIT_LR - Load register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_EPIT_LR - Load register (RW)
*
* Reset value: 0xffffffff
*
* The EPIT load register (EPIT_LR) contains the value that is to be loaded into the counter when
* EPIT counter reaches zero if the RLD bit in EPIT_CR is set. If the IOVW bit in the EPIT_CR is set
* then a write to this register overwrites the value of the EPIT counter register in addition to
* updating this registers value. This overwrite feature is active even if the RLD bit is not set.
*/
typedef union _hw_epit_lr
{
reg32_t U;
struct _hw_epit_lr_bitfields
{
unsigned LOAD : 32; //!< [31:0] Load value.
} B;
} hw_epit_lr_t;
#endif
/*!
* @name Constants and macros for entire EPIT_LR register
*/
//@{
#define HW_EPIT_LR_ADDR(x) (REGS_EPIT_BASE(x) + 0x8)
#ifndef __LANGUAGE_ASM__
#define HW_EPIT_LR(x) (*(volatile hw_epit_lr_t *) HW_EPIT_LR_ADDR(x))
#define HW_EPIT_LR_RD(x) (HW_EPIT_LR(x).U)
#define HW_EPIT_LR_WR(x, v) (HW_EPIT_LR(x).U = (v))
#define HW_EPIT_LR_SET(x, v) (HW_EPIT_LR_WR(x, HW_EPIT_LR_RD(x) | (v)))
#define HW_EPIT_LR_CLR(x, v) (HW_EPIT_LR_WR(x, HW_EPIT_LR_RD(x) & ~(v)))
#define HW_EPIT_LR_TOG(x, v) (HW_EPIT_LR_WR(x, HW_EPIT_LR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual EPIT_LR bitfields
*/
/*! @name Register EPIT_LR, field LOAD[31:0] (RW)
*
* Load value. Value that is loaded into the counter at the start of each count cycle.
*/
//@{
#define BP_EPIT_LR_LOAD (0) //!< Bit position for EPIT_LR_LOAD.
#define BM_EPIT_LR_LOAD (0xffffffff) //!< Bit mask for EPIT_LR_LOAD.
//! @brief Get value of EPIT_LR_LOAD from a register value.
#define BG_EPIT_LR_LOAD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_LR_LOAD) >> BP_EPIT_LR_LOAD)
//! @brief Format value for bitfield EPIT_LR_LOAD.
#define BF_EPIT_LR_LOAD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_LR_LOAD) & BM_EPIT_LR_LOAD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LOAD field to a new value.
#define BW_EPIT_LR_LOAD(x, v) (HW_EPIT_LR_WR(x, (HW_EPIT_LR_RD(x) & ~BM_EPIT_LR_LOAD) | BF_EPIT_LR_LOAD(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_EPIT_CMPR - Compare register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_EPIT_CMPR - Compare register (RW)
*
* Reset value: 0x00000000
*
* The EPIT compare register (EPIT_CMPR) holds the value that determines when a compare event is
* generated.
*/
typedef union _hw_epit_cmpr
{
reg32_t U;
struct _hw_epit_cmpr_bitfields
{
unsigned COMPARE : 32; //!< [31:0] Compare Value.
} B;
} hw_epit_cmpr_t;
#endif
/*!
* @name Constants and macros for entire EPIT_CMPR register
*/
//@{
#define HW_EPIT_CMPR_ADDR(x) (REGS_EPIT_BASE(x) + 0xc)
#ifndef __LANGUAGE_ASM__
#define HW_EPIT_CMPR(x) (*(volatile hw_epit_cmpr_t *) HW_EPIT_CMPR_ADDR(x))
#define HW_EPIT_CMPR_RD(x) (HW_EPIT_CMPR(x).U)
#define HW_EPIT_CMPR_WR(x, v) (HW_EPIT_CMPR(x).U = (v))
#define HW_EPIT_CMPR_SET(x, v) (HW_EPIT_CMPR_WR(x, HW_EPIT_CMPR_RD(x) | (v)))
#define HW_EPIT_CMPR_CLR(x, v) (HW_EPIT_CMPR_WR(x, HW_EPIT_CMPR_RD(x) & ~(v)))
#define HW_EPIT_CMPR_TOG(x, v) (HW_EPIT_CMPR_WR(x, HW_EPIT_CMPR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual EPIT_CMPR bitfields
*/
/*! @name Register EPIT_CMPR, field COMPARE[31:0] (RW)
*
* Compare Value. When the counter value equals this bit field value a compare event is generated.
*/
//@{
#define BP_EPIT_CMPR_COMPARE (0) //!< Bit position for EPIT_CMPR_COMPARE.
#define BM_EPIT_CMPR_COMPARE (0xffffffff) //!< Bit mask for EPIT_CMPR_COMPARE.
//! @brief Get value of EPIT_CMPR_COMPARE from a register value.
#define BG_EPIT_CMPR_COMPARE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CMPR_COMPARE) >> BP_EPIT_CMPR_COMPARE)
//! @brief Format value for bitfield EPIT_CMPR_COMPARE.
#define BF_EPIT_CMPR_COMPARE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CMPR_COMPARE) & BM_EPIT_CMPR_COMPARE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the COMPARE field to a new value.
#define BW_EPIT_CMPR_COMPARE(x, v) (HW_EPIT_CMPR_WR(x, (HW_EPIT_CMPR_RD(x) & ~BM_EPIT_CMPR_COMPARE) | BF_EPIT_CMPR_COMPARE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_EPIT_CNR - Counter register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_EPIT_CNR - Counter register (RO)
*
* Reset value: 0xffffffff
*
* The EPIT counter register (EPIT_CNR) contains the current count value and can be read at any time
* without disturbing the counter. This is a read-only register and any attempt to write into it
* generates a transfer error. But if the IOVW bit in EPIT_CR is set, the value of this register can
* be overwritten with a write to EPIT_LR. This change is reflected when this register is
* subsequently read.
*/
typedef union _hw_epit_cnr
{
reg32_t U;
struct _hw_epit_cnr_bitfields
{
unsigned COUNT : 32; //!< [31:0] Counter value.
} B;
} hw_epit_cnr_t;
#endif
/*!
* @name Constants and macros for entire EPIT_CNR register
*/
//@{
#define HW_EPIT_CNR_ADDR(x) (REGS_EPIT_BASE(x) + 0x10)
#ifndef __LANGUAGE_ASM__
#define HW_EPIT_CNR(x) (*(volatile hw_epit_cnr_t *) HW_EPIT_CNR_ADDR(x))
#define HW_EPIT_CNR_RD(x) (HW_EPIT_CNR(x).U)
#endif
//@}
/*
* constants & macros for individual EPIT_CNR bitfields
*/
/*! @name Register EPIT_CNR, field COUNT[31:0] (RO)
*
* Counter value. This contains the current value of the counter.
*/
//@{
#define BP_EPIT_CNR_COUNT (0) //!< Bit position for EPIT_CNR_COUNT.
#define BM_EPIT_CNR_COUNT (0xffffffff) //!< Bit mask for EPIT_CNR_COUNT.
//! @brief Get value of EPIT_CNR_COUNT from a register value.
#define BG_EPIT_CNR_COUNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CNR_COUNT) >> BP_EPIT_CNR_COUNT)
//@}
//-------------------------------------------------------------------------------------------
// hw_epit_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All EPIT module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_epit
{
volatile hw_epit_cr_t CR; //!< Control register
volatile hw_epit_sr_t SR; //!< Status register
volatile hw_epit_lr_t LR; //!< Load register
volatile hw_epit_cmpr_t CMPR; //!< Compare register
volatile hw_epit_cnr_t CNR; //!< Counter register
} hw_epit_t;
#pragma pack()
//! @brief Macro to access all EPIT registers.
//! @param x EPIT instance number.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_EPIT(0)</code>.
#define HW_EPIT(x) (*(hw_epit_t *) REGS_EPIT_BASE(x))
#endif
#endif // __HW_EPIT_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_GPC_REGISTERS_H__
#define __HW_GPC_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ GPC
*
* GPC
*
* Registers defined in this header file:
* - HW_GPC_CNTR - GPC Interface control register
* - HW_GPC_PGR - GPC Power Gating Register
* - HW_GPC_IMR1 - IRQ masking register 1
* - HW_GPC_IMR2 - IRQ masking register 2
* - HW_GPC_IMR3 - IRQ masking register 3
* - HW_GPC_IMR4 - IRQ masking register 4
* - HW_GPC_ISR1 - IRQ status resister 1
* - HW_GPC_ISR2 - IRQ status resister 2
* - HW_GPC_ISR3 - IRQ status resister 3
* - HW_GPC_ISR4 - IRQ status resister 4
*
* - hw_gpc_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_GPC_BASE
#define HW_GPC_INSTANCE_COUNT (1) //!< Number of instances of the GPC module.
#define REGS_GPC_BASE (0x020dc000) //!< Base address for GPC.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPC_CNTR - GPC Interface control register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_CNTR - GPC Interface control register (RW)
*
* Reset value: 0x00100000
*/
typedef union _hw_gpc_cntr
{
reg32_t U;
struct _hw_gpc_cntr_bitfields
{
unsigned GPU_VPU_PDN_REQ : 1; //!< [0] GPU /VPU Power Down request.
unsigned GPU_VPU_PUP_REQ : 1; //!< [1] GPU /VPU Power Up request.
unsigned RESERVED2 : 14; //!< [15:2] Reserved.
unsigned DVFS0CR : 1; //!< [16] DVFS0 (ARM) Change request (bit is read-only)
unsigned RESERVED3 : 4; //!< [20:17] Reserved.
unsigned GPCIRQM : 1; //!< [21] GPC interrupt/event masking
unsigned RESERVED4 : 10; //!< [31:22] Reserved.
} B;
} hw_gpc_cntr_t;
#endif
/*!
* @name Constants and macros for entire GPC_CNTR register
*/
//@{
#define HW_GPC_CNTR_ADDR (REGS_GPC_BASE + 0x0)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_CNTR (*(volatile hw_gpc_cntr_t *) HW_GPC_CNTR_ADDR)
#define HW_GPC_CNTR_RD() (HW_GPC_CNTR.U)
#define HW_GPC_CNTR_WR(v) (HW_GPC_CNTR.U = (v))
#define HW_GPC_CNTR_SET(v) (HW_GPC_CNTR_WR(HW_GPC_CNTR_RD() | (v)))
#define HW_GPC_CNTR_CLR(v) (HW_GPC_CNTR_WR(HW_GPC_CNTR_RD() & ~(v)))
#define HW_GPC_CNTR_TOG(v) (HW_GPC_CNTR_WR(HW_GPC_CNTR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual GPC_CNTR bitfields
*/
/*! @name Register GPC_CNTR, field GPU_VPU_PDN_REQ[0] (RW)
*
* GPU /VPU Power Down request. Self-cleared bit. * Note: Power switch for GPU /VPU power domain is
* controlled by ANALOG configuration, not GPU /VPU PGC signals
*
* Values:
* - 0 - no request
* - 1 - Request Power Down sequence to start for GPU /VPU
*/
//@{
#define BP_GPC_CNTR_GPU_VPU_PDN_REQ (0) //!< Bit position for GPC_CNTR_GPU_VPU_PDN_REQ.
#define BM_GPC_CNTR_GPU_VPU_PDN_REQ (0x00000001) //!< Bit mask for GPC_CNTR_GPU_VPU_PDN_REQ.
//! @brief Get value of GPC_CNTR_GPU_VPU_PDN_REQ from a register value.
#define BG_GPC_CNTR_GPU_VPU_PDN_REQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_CNTR_GPU_VPU_PDN_REQ) >> BP_GPC_CNTR_GPU_VPU_PDN_REQ)
//! @brief Format value for bitfield GPC_CNTR_GPU_VPU_PDN_REQ.
#define BF_GPC_CNTR_GPU_VPU_PDN_REQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_CNTR_GPU_VPU_PDN_REQ) & BM_GPC_CNTR_GPU_VPU_PDN_REQ)
#ifndef __LANGUAGE_ASM__
//! @brief Set the GPU_VPU_PDN_REQ field to a new value.
#define BW_GPC_CNTR_GPU_VPU_PDN_REQ(v) (HW_GPC_CNTR_WR((HW_GPC_CNTR_RD() & ~BM_GPC_CNTR_GPU_VPU_PDN_REQ) | BF_GPC_CNTR_GPU_VPU_PDN_REQ(v)))
#endif
//@}
/*! @name Register GPC_CNTR, field GPU_VPU_PUP_REQ[1] (RW)
*
* GPU /VPU Power Up request. Self-cleared bit. * Note: Power switch for GPU /VPU power domain is
* controlled by ANALOG configuration, not GPU /VPU PGC signals
*
* Values:
* - 0 - no request
* - 1 - Request Power Up sequence to start for GPU /VPU
*/
//@{
#define BP_GPC_CNTR_GPU_VPU_PUP_REQ (1) //!< Bit position for GPC_CNTR_GPU_VPU_PUP_REQ.
#define BM_GPC_CNTR_GPU_VPU_PUP_REQ (0x00000002) //!< Bit mask for GPC_CNTR_GPU_VPU_PUP_REQ.
//! @brief Get value of GPC_CNTR_GPU_VPU_PUP_REQ from a register value.
#define BG_GPC_CNTR_GPU_VPU_PUP_REQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_CNTR_GPU_VPU_PUP_REQ) >> BP_GPC_CNTR_GPU_VPU_PUP_REQ)
//! @brief Format value for bitfield GPC_CNTR_GPU_VPU_PUP_REQ.
#define BF_GPC_CNTR_GPU_VPU_PUP_REQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_CNTR_GPU_VPU_PUP_REQ) & BM_GPC_CNTR_GPU_VPU_PUP_REQ)
#ifndef __LANGUAGE_ASM__
//! @brief Set the GPU_VPU_PUP_REQ field to a new value.
#define BW_GPC_CNTR_GPU_VPU_PUP_REQ(v) (HW_GPC_CNTR_WR((HW_GPC_CNTR_RD() & ~BM_GPC_CNTR_GPU_VPU_PUP_REQ) | BF_GPC_CNTR_GPU_VPU_PUP_REQ(v)))
#endif
//@}
/*! @name Register GPC_CNTR, field DVFS0CR[16] (RO)
*
* DVFS0 (ARM) Change request (bit is read-only)
*
* Values:
* - 0 - DVFS0 has no request
* - 1 - DVFS0 is requesting for frequency/voltage update
*/
//@{
#define BP_GPC_CNTR_DVFS0CR (16) //!< Bit position for GPC_CNTR_DVFS0CR.
#define BM_GPC_CNTR_DVFS0CR (0x00010000) //!< Bit mask for GPC_CNTR_DVFS0CR.
//! @brief Get value of GPC_CNTR_DVFS0CR from a register value.
#define BG_GPC_CNTR_DVFS0CR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_CNTR_DVFS0CR) >> BP_GPC_CNTR_DVFS0CR)
//@}
/*! @name Register GPC_CNTR, field GPCIRQM[21] (RW)
*
* GPC interrupt/event masking
*
* Values:
* - 0 - not masked
* - 1 - interrupt/event is masked
*/
//@{
#define BP_GPC_CNTR_GPCIRQM (21) //!< Bit position for GPC_CNTR_GPCIRQM.
#define BM_GPC_CNTR_GPCIRQM (0x00200000) //!< Bit mask for GPC_CNTR_GPCIRQM.
//! @brief Get value of GPC_CNTR_GPCIRQM from a register value.
#define BG_GPC_CNTR_GPCIRQM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_CNTR_GPCIRQM) >> BP_GPC_CNTR_GPCIRQM)
//! @brief Format value for bitfield GPC_CNTR_GPCIRQM.
#define BF_GPC_CNTR_GPCIRQM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_CNTR_GPCIRQM) & BM_GPC_CNTR_GPCIRQM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the GPCIRQM field to a new value.
#define BW_GPC_CNTR_GPCIRQM(v) (HW_GPC_CNTR_WR((HW_GPC_CNTR_RD() & ~BM_GPC_CNTR_GPCIRQM) | BF_GPC_CNTR_GPCIRQM(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPC_PGR - GPC Power Gating Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_PGR - GPC Power Gating Register (RW)
*
* Reset value: 0x00000000
*/
typedef union _hw_gpc_pgr
{
reg32_t U;
struct _hw_gpc_pgr_bitfields
{
unsigned RESERVED0 : 29; //!< [28:0] Reserved
unsigned DRCIC : 2; //!< [30:29] Debug ref cir in mux control
unsigned RESERVED1 : 1; //!< [31] Reserved
} B;
} hw_gpc_pgr_t;
#endif
/*!
* @name Constants and macros for entire GPC_PGR register
*/
//@{
#define HW_GPC_PGR_ADDR (REGS_GPC_BASE + 0x4)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_PGR (*(volatile hw_gpc_pgr_t *) HW_GPC_PGR_ADDR)
#define HW_GPC_PGR_RD() (HW_GPC_PGR.U)
#define HW_GPC_PGR_WR(v) (HW_GPC_PGR.U = (v))
#define HW_GPC_PGR_SET(v) (HW_GPC_PGR_WR(HW_GPC_PGR_RD() | (v)))
#define HW_GPC_PGR_CLR(v) (HW_GPC_PGR_WR(HW_GPC_PGR_RD() & ~(v)))
#define HW_GPC_PGR_TOG(v) (HW_GPC_PGR_WR(HW_GPC_PGR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual GPC_PGR bitfields
*/
/*! @name Register GPC_PGR, field DRCIC[30:29] (RW)
*
* Debug ref cir in mux control
*
* Values:
* - 00 - ccm_cosr_1_clk_in
* - 01 - ccm_cosr_2_clk_in
* - 10 - restricted
* - 11 - restricted
*/
//@{
#define BP_GPC_PGR_DRCIC (29) //!< Bit position for GPC_PGR_DRCIC.
#define BM_GPC_PGR_DRCIC (0x60000000) //!< Bit mask for GPC_PGR_DRCIC.
//! @brief Get value of GPC_PGR_DRCIC from a register value.
#define BG_GPC_PGR_DRCIC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_PGR_DRCIC) >> BP_GPC_PGR_DRCIC)
//! @brief Format value for bitfield GPC_PGR_DRCIC.
#define BF_GPC_PGR_DRCIC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_PGR_DRCIC) & BM_GPC_PGR_DRCIC)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DRCIC field to a new value.
#define BW_GPC_PGR_DRCIC(v) (HW_GPC_PGR_WR((HW_GPC_PGR_RD() & ~BM_GPC_PGR_DRCIC) | BF_GPC_PGR_DRCIC(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPC_IMR1 - IRQ masking register 1
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_IMR1 - IRQ masking register 1 (RW)
*
* Reset value: 0x00000000
*
* IMR1 Register - masking of irq[63:32].
*/
typedef union _hw_gpc_imr1
{
reg32_t U;
struct _hw_gpc_imr1_bitfields
{
unsigned IMR1 : 32; //!< [31:0] IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked
} B;
} hw_gpc_imr1_t;
#endif
/*!
* @name Constants and macros for entire GPC_IMR1 register
*/
//@{
#define HW_GPC_IMR1_ADDR (REGS_GPC_BASE + 0x8)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_IMR1 (*(volatile hw_gpc_imr1_t *) HW_GPC_IMR1_ADDR)
#define HW_GPC_IMR1_RD() (HW_GPC_IMR1.U)
#define HW_GPC_IMR1_WR(v) (HW_GPC_IMR1.U = (v))
#define HW_GPC_IMR1_SET(v) (HW_GPC_IMR1_WR(HW_GPC_IMR1_RD() | (v)))
#define HW_GPC_IMR1_CLR(v) (HW_GPC_IMR1_WR(HW_GPC_IMR1_RD() & ~(v)))
#define HW_GPC_IMR1_TOG(v) (HW_GPC_IMR1_WR(HW_GPC_IMR1_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual GPC_IMR1 bitfields
*/
/*! @name Register GPC_IMR1, field IMR1[31:0] (RW)
*
* IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked
*/
//@{
#define BP_GPC_IMR1_IMR1 (0) //!< Bit position for GPC_IMR1_IMR1.
#define BM_GPC_IMR1_IMR1 (0xffffffff) //!< Bit mask for GPC_IMR1_IMR1.
//! @brief Get value of GPC_IMR1_IMR1 from a register value.
#define BG_GPC_IMR1_IMR1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_IMR1_IMR1) >> BP_GPC_IMR1_IMR1)
//! @brief Format value for bitfield GPC_IMR1_IMR1.
#define BF_GPC_IMR1_IMR1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_IMR1_IMR1) & BM_GPC_IMR1_IMR1)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IMR1 field to a new value.
#define BW_GPC_IMR1_IMR1(v) (HW_GPC_IMR1_WR((HW_GPC_IMR1_RD() & ~BM_GPC_IMR1_IMR1) | BF_GPC_IMR1_IMR1(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPC_IMR2 - IRQ masking register 2
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_IMR2 - IRQ masking register 2 (RW)
*
* Reset value: 0x00000000
*
* IMR2 Register - masking of irq[95:64].
*/
typedef union _hw_gpc_imr2
{
reg32_t U;
struct _hw_gpc_imr2_bitfields
{
unsigned IMR2 : 32; //!< [31:0] IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked
} B;
} hw_gpc_imr2_t;
#endif
/*!
* @name Constants and macros for entire GPC_IMR2 register
*/
//@{
#define HW_GPC_IMR2_ADDR (REGS_GPC_BASE + 0xc)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_IMR2 (*(volatile hw_gpc_imr2_t *) HW_GPC_IMR2_ADDR)
#define HW_GPC_IMR2_RD() (HW_GPC_IMR2.U)
#define HW_GPC_IMR2_WR(v) (HW_GPC_IMR2.U = (v))
#define HW_GPC_IMR2_SET(v) (HW_GPC_IMR2_WR(HW_GPC_IMR2_RD() | (v)))
#define HW_GPC_IMR2_CLR(v) (HW_GPC_IMR2_WR(HW_GPC_IMR2_RD() & ~(v)))
#define HW_GPC_IMR2_TOG(v) (HW_GPC_IMR2_WR(HW_GPC_IMR2_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual GPC_IMR2 bitfields
*/
/*! @name Register GPC_IMR2, field IMR2[31:0] (RW)
*
* IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked
*/
//@{
#define BP_GPC_IMR2_IMR2 (0) //!< Bit position for GPC_IMR2_IMR2.
#define BM_GPC_IMR2_IMR2 (0xffffffff) //!< Bit mask for GPC_IMR2_IMR2.
//! @brief Get value of GPC_IMR2_IMR2 from a register value.
#define BG_GPC_IMR2_IMR2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_IMR2_IMR2) >> BP_GPC_IMR2_IMR2)
//! @brief Format value for bitfield GPC_IMR2_IMR2.
#define BF_GPC_IMR2_IMR2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_IMR2_IMR2) & BM_GPC_IMR2_IMR2)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IMR2 field to a new value.
#define BW_GPC_IMR2_IMR2(v) (HW_GPC_IMR2_WR((HW_GPC_IMR2_RD() & ~BM_GPC_IMR2_IMR2) | BF_GPC_IMR2_IMR2(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPC_IMR3 - IRQ masking register 3
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_IMR3 - IRQ masking register 3 (RW)
*
* Reset value: 0x00000000
*
* IMR3 Register - masking of irq[127:96].
*/
typedef union _hw_gpc_imr3
{
reg32_t U;
struct _hw_gpc_imr3_bitfields
{
unsigned IMR3 : 32; //!< [31:0] IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked
} B;
} hw_gpc_imr3_t;
#endif
/*!
* @name Constants and macros for entire GPC_IMR3 register
*/
//@{
#define HW_GPC_IMR3_ADDR (REGS_GPC_BASE + 0x10)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_IMR3 (*(volatile hw_gpc_imr3_t *) HW_GPC_IMR3_ADDR)
#define HW_GPC_IMR3_RD() (HW_GPC_IMR3.U)
#define HW_GPC_IMR3_WR(v) (HW_GPC_IMR3.U = (v))
#define HW_GPC_IMR3_SET(v) (HW_GPC_IMR3_WR(HW_GPC_IMR3_RD() | (v)))
#define HW_GPC_IMR3_CLR(v) (HW_GPC_IMR3_WR(HW_GPC_IMR3_RD() & ~(v)))
#define HW_GPC_IMR3_TOG(v) (HW_GPC_IMR3_WR(HW_GPC_IMR3_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual GPC_IMR3 bitfields
*/
/*! @name Register GPC_IMR3, field IMR3[31:0] (RW)
*
* IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked
*/
//@{
#define BP_GPC_IMR3_IMR3 (0) //!< Bit position for GPC_IMR3_IMR3.
#define BM_GPC_IMR3_IMR3 (0xffffffff) //!< Bit mask for GPC_IMR3_IMR3.
//! @brief Get value of GPC_IMR3_IMR3 from a register value.
#define BG_GPC_IMR3_IMR3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_IMR3_IMR3) >> BP_GPC_IMR3_IMR3)
//! @brief Format value for bitfield GPC_IMR3_IMR3.
#define BF_GPC_IMR3_IMR3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_IMR3_IMR3) & BM_GPC_IMR3_IMR3)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IMR3 field to a new value.
#define BW_GPC_IMR3_IMR3(v) (HW_GPC_IMR3_WR((HW_GPC_IMR3_RD() & ~BM_GPC_IMR3_IMR3) | BF_GPC_IMR3_IMR3(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPC_IMR4 - IRQ masking register 4
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_IMR4 - IRQ masking register 4 (RW)
*
* Reset value: 0x00000000
*
* IMR4 Register - masking of irq[159:128].
*/
typedef union _hw_gpc_imr4
{
reg32_t U;
struct _hw_gpc_imr4_bitfields
{
unsigned IMR4 : 32; //!< [31:0] IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked
} B;
} hw_gpc_imr4_t;
#endif
/*!
* @name Constants and macros for entire GPC_IMR4 register
*/
//@{
#define HW_GPC_IMR4_ADDR (REGS_GPC_BASE + 0x14)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_IMR4 (*(volatile hw_gpc_imr4_t *) HW_GPC_IMR4_ADDR)
#define HW_GPC_IMR4_RD() (HW_GPC_IMR4.U)
#define HW_GPC_IMR4_WR(v) (HW_GPC_IMR4.U = (v))
#define HW_GPC_IMR4_SET(v) (HW_GPC_IMR4_WR(HW_GPC_IMR4_RD() | (v)))
#define HW_GPC_IMR4_CLR(v) (HW_GPC_IMR4_WR(HW_GPC_IMR4_RD() & ~(v)))
#define HW_GPC_IMR4_TOG(v) (HW_GPC_IMR4_WR(HW_GPC_IMR4_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual GPC_IMR4 bitfields
*/
/*! @name Register GPC_IMR4, field IMR4[31:0] (RW)
*
* IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked
*/
//@{
#define BP_GPC_IMR4_IMR4 (0) //!< Bit position for GPC_IMR4_IMR4.
#define BM_GPC_IMR4_IMR4 (0xffffffff) //!< Bit mask for GPC_IMR4_IMR4.
//! @brief Get value of GPC_IMR4_IMR4 from a register value.
#define BG_GPC_IMR4_IMR4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_IMR4_IMR4) >> BP_GPC_IMR4_IMR4)
//! @brief Format value for bitfield GPC_IMR4_IMR4.
#define BF_GPC_IMR4_IMR4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_IMR4_IMR4) & BM_GPC_IMR4_IMR4)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IMR4 field to a new value.
#define BW_GPC_IMR4_IMR4(v) (HW_GPC_IMR4_WR((HW_GPC_IMR4_RD() & ~BM_GPC_IMR4_IMR4) | BF_GPC_IMR4_IMR4(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPC_ISR1 - IRQ status resister 1
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_ISR1 - IRQ status resister 1 (RO)
*
* Reset value: 0x00000000
*
* ISR1 Register - status of irq [63:32].
*/
typedef union _hw_gpc_isr1
{
reg32_t U;
struct _hw_gpc_isr1_bitfields
{
unsigned ISR1 : 32; //!< [31:0] IRQ[63:32] status, read only
} B;
} hw_gpc_isr1_t;
#endif
/*!
* @name Constants and macros for entire GPC_ISR1 register
*/
//@{
#define HW_GPC_ISR1_ADDR (REGS_GPC_BASE + 0x18)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_ISR1 (*(volatile hw_gpc_isr1_t *) HW_GPC_ISR1_ADDR)
#define HW_GPC_ISR1_RD() (HW_GPC_ISR1.U)
#endif
//@}
/*
* constants & macros for individual GPC_ISR1 bitfields
*/
/*! @name Register GPC_ISR1, field ISR1[31:0] (RO)
*
* IRQ[63:32] status, read only
*/
//@{
#define BP_GPC_ISR1_ISR1 (0) //!< Bit position for GPC_ISR1_ISR1.
#define BM_GPC_ISR1_ISR1 (0xffffffff) //!< Bit mask for GPC_ISR1_ISR1.
//! @brief Get value of GPC_ISR1_ISR1 from a register value.
#define BG_GPC_ISR1_ISR1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_ISR1_ISR1) >> BP_GPC_ISR1_ISR1)
//@}
//-------------------------------------------------------------------------------------------
// HW_GPC_ISR2 - IRQ status resister 2
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_ISR2 - IRQ status resister 2 (RO)
*
* Reset value: 0x00000000
*
* ISR2 Register - status of irq [95:64].
*/
typedef union _hw_gpc_isr2
{
reg32_t U;
struct _hw_gpc_isr2_bitfields
{
unsigned ISR2 : 32; //!< [31:0] IRQ[95:64] status, read only
} B;
} hw_gpc_isr2_t;
#endif
/*!
* @name Constants and macros for entire GPC_ISR2 register
*/
//@{
#define HW_GPC_ISR2_ADDR (REGS_GPC_BASE + 0x1c)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_ISR2 (*(volatile hw_gpc_isr2_t *) HW_GPC_ISR2_ADDR)
#define HW_GPC_ISR2_RD() (HW_GPC_ISR2.U)
#endif
//@}
/*
* constants & macros for individual GPC_ISR2 bitfields
*/
/*! @name Register GPC_ISR2, field ISR2[31:0] (RO)
*
* IRQ[95:64] status, read only
*/
//@{
#define BP_GPC_ISR2_ISR2 (0) //!< Bit position for GPC_ISR2_ISR2.
#define BM_GPC_ISR2_ISR2 (0xffffffff) //!< Bit mask for GPC_ISR2_ISR2.
//! @brief Get value of GPC_ISR2_ISR2 from a register value.
#define BG_GPC_ISR2_ISR2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_ISR2_ISR2) >> BP_GPC_ISR2_ISR2)
//@}
//-------------------------------------------------------------------------------------------
// HW_GPC_ISR3 - IRQ status resister 3
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_ISR3 - IRQ status resister 3 (RO)
*
* Reset value: 0x00000000
*
* ISR3 Register - status of irq [127:96].
*/
typedef union _hw_gpc_isr3
{
reg32_t U;
struct _hw_gpc_isr3_bitfields
{
unsigned ISR3 : 32; //!< [31:0] IRQ[127:96] status, read only
} B;
} hw_gpc_isr3_t;
#endif
/*!
* @name Constants and macros for entire GPC_ISR3 register
*/
//@{
#define HW_GPC_ISR3_ADDR (REGS_GPC_BASE + 0x20)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_ISR3 (*(volatile hw_gpc_isr3_t *) HW_GPC_ISR3_ADDR)
#define HW_GPC_ISR3_RD() (HW_GPC_ISR3.U)
#endif
//@}
/*
* constants & macros for individual GPC_ISR3 bitfields
*/
/*! @name Register GPC_ISR3, field ISR3[31:0] (RO)
*
* IRQ[127:96] status, read only
*/
//@{
#define BP_GPC_ISR3_ISR3 (0) //!< Bit position for GPC_ISR3_ISR3.
#define BM_GPC_ISR3_ISR3 (0xffffffff) //!< Bit mask for GPC_ISR3_ISR3.
//! @brief Get value of GPC_ISR3_ISR3 from a register value.
#define BG_GPC_ISR3_ISR3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_ISR3_ISR3) >> BP_GPC_ISR3_ISR3)
//@}
//-------------------------------------------------------------------------------------------
// HW_GPC_ISR4 - IRQ status resister 4
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_ISR4 - IRQ status resister 4 (RO)
*
* Reset value: 0x00000000
*
* ISR4 Register - status of irq [159:128].
*/
typedef union _hw_gpc_isr4
{
reg32_t U;
struct _hw_gpc_isr4_bitfields
{
unsigned ISR4 : 32; //!< [31:0] IRQ[159:128] status, read only
} B;
} hw_gpc_isr4_t;
#endif
/*!
* @name Constants and macros for entire GPC_ISR4 register
*/
//@{
#define HW_GPC_ISR4_ADDR (REGS_GPC_BASE + 0x24)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_ISR4 (*(volatile hw_gpc_isr4_t *) HW_GPC_ISR4_ADDR)
#define HW_GPC_ISR4_RD() (HW_GPC_ISR4.U)
#endif
//@}
/*
* constants & macros for individual GPC_ISR4 bitfields
*/
/*! @name Register GPC_ISR4, field ISR4[31:0] (RO)
*
* IRQ[159:128] status, read only
*/
//@{
#define BP_GPC_ISR4_ISR4 (0) //!< Bit position for GPC_ISR4_ISR4.
#define BM_GPC_ISR4_ISR4 (0xffffffff) //!< Bit mask for GPC_ISR4_ISR4.
//! @brief Get value of GPC_ISR4_ISR4 from a register value.
#define BG_GPC_ISR4_ISR4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_ISR4_ISR4) >> BP_GPC_ISR4_ISR4)
//@}
//-------------------------------------------------------------------------------------------
// hw_gpc_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All GPC module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_gpc
{
volatile hw_gpc_cntr_t CNTR; //!< GPC Interface control register
volatile hw_gpc_pgr_t PGR; //!< GPC Power Gating Register
volatile hw_gpc_imr1_t IMR1; //!< IRQ masking register 1
volatile hw_gpc_imr2_t IMR2; //!< IRQ masking register 2
volatile hw_gpc_imr3_t IMR3; //!< IRQ masking register 3
volatile hw_gpc_imr4_t IMR4; //!< IRQ masking register 4
volatile hw_gpc_isr1_t ISR1; //!< IRQ status resister 1
volatile hw_gpc_isr2_t ISR2; //!< IRQ status resister 2
volatile hw_gpc_isr3_t ISR3; //!< IRQ status resister 3
volatile hw_gpc_isr4_t ISR4; //!< IRQ status resister 4
} hw_gpc_t;
#pragma pack()
//! @brief Macro to access all GPC registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_GPC</code>.
#define HW_GPC (*(hw_gpc_t *) REGS_GPC_BASE)
#endif
#endif // __HW_GPC_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_I2C_REGISTERS_H__
#define __HW_I2C_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ I2C
*
* I2C
*
* Registers defined in this header file:
* - HW_I2C_IADR - I2C Address Register
* - HW_I2C_IFDR - I2C Frequency Divider Register
* - HW_I2C_I2CR - I2C Control Register
* - HW_I2C_I2SR - I2C Status Register
* - HW_I2C_I2DR - I2C Data I/O Register
*
* - hw_i2c_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_I2C_BASE
#define HW_I2C_INSTANCE_COUNT (3) //!< Number of instances of the I2C module.
#define HW_I2C1 (1) //!< Instance number for I2C1.
#define HW_I2C2 (2) //!< Instance number for I2C2.
#define HW_I2C3 (3) //!< Instance number for I2C3.
#define REGS_I2C1_BASE (0x021a0000) //!< Base address for I2C instance number 1.
#define REGS_I2C2_BASE (0x021a4000) //!< Base address for I2C instance number 2.
#define REGS_I2C3_BASE (0x021a8000) //!< Base address for I2C instance number 3.
//! @brief Get the base address of I2C by instance number.
//! @param x I2C instance number, from 1 through 3.
#define REGS_I2C_BASE(x) ( (x) == HW_I2C1 ? REGS_I2C1_BASE : (x) == HW_I2C2 ? REGS_I2C2_BASE : (x) == HW_I2C3 ? REGS_I2C3_BASE : 0x00d00000)
//! @brief Get the instance number given a base address.
//! @param b Base address for an instance of I2C.
#define REGS_I2C_INSTANCE(b) ( (b) == REGS_I2C1_BASE ? HW_I2C1 : (b) == REGS_I2C2_BASE ? HW_I2C2 : (b) == REGS_I2C3_BASE ? HW_I2C3 : 0)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_I2C_IADR - I2C Address Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_I2C_IADR - I2C Address Register (RW)
*
* Reset value: 0x0000
*/
typedef union _hw_i2c_iadr
{
reg16_t U;
struct _hw_i2c_iadr_bitfields
{
unsigned short RESERVED0 : 1; //!< [0] Reserved
unsigned short ADR : 7; //!< [7:1] Slave address.
unsigned short RESERVED1 : 8; //!< [15:8] Reserved
} B;
} hw_i2c_iadr_t;
#endif
/*!
* @name Constants and macros for entire I2C_IADR register
*/
//@{
#define HW_I2C_IADR_ADDR(x) (REGS_I2C_BASE(x) + 0x0)
#ifndef __LANGUAGE_ASM__
#define HW_I2C_IADR(x) (*(volatile hw_i2c_iadr_t *) HW_I2C_IADR_ADDR(x))
#define HW_I2C_IADR_RD(x) (HW_I2C_IADR(x).U)
#define HW_I2C_IADR_WR(x, v) (HW_I2C_IADR(x).U = (v))
#define HW_I2C_IADR_SET(x, v) (HW_I2C_IADR_WR(x, HW_I2C_IADR_RD(x) | (v)))
#define HW_I2C_IADR_CLR(x, v) (HW_I2C_IADR_WR(x, HW_I2C_IADR_RD(x) & ~(v)))
#define HW_I2C_IADR_TOG(x, v) (HW_I2C_IADR_WR(x, HW_I2C_IADR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual I2C_IADR bitfields
*/
/*! @name Register I2C_IADR, field ADR[7:1] (RW)
*
* Slave address. Contains the specific slave address to be used by the I2C. Slave mode is the
* default I2C mode for an address match on the bus. The I2C_IADR holds the address the I2C responds
* to when addressed as a slave. The slave address is not the address sent on the bus during the
* address transfer. The register is not reset by a software reset.
*/
//@{
#define BP_I2C_IADR_ADR (1) //!< Bit position for I2C_IADR_ADR.
#define BM_I2C_IADR_ADR (0x000000fe) //!< Bit mask for I2C_IADR_ADR.
//! @brief Get value of I2C_IADR_ADR from a register value.
#define BG_I2C_IADR_ADR(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_IADR_ADR) >> BP_I2C_IADR_ADR)
//! @brief Format value for bitfield I2C_IADR_ADR.
#define BF_I2C_IADR_ADR(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_IADR_ADR) & BM_I2C_IADR_ADR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ADR field to a new value.
#define BW_I2C_IADR_ADR(x, v) (HW_I2C_IADR_WR(x, (HW_I2C_IADR_RD(x) & ~BM_I2C_IADR_ADR) | BF_I2C_IADR_ADR(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_I2C_IFDR - I2C Frequency Divider Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_I2C_IFDR - I2C Frequency Divider Register (RW)
*
* Reset value: 0x0000
*
* The I2C_IFDR provides a programmable prescaler to configure the clock for bit-rate selection. The
* register does not get reset by software reset. The following table describes the Divider values
* for register field "IC". Table below describes the register values for field "IC". I2C_IFDR
* Register Field Values IC Divider IC Divider IC Divider IC Divider 0x00 30 0x10 288 0x20 22 0x30
* 160 0x01 32 0x11 320 0x21 24 0x31 192 0x02 36 0x12 384 0x22 26 0x32 224 0x03 42 0x13 480 0x23 28
* 0x33 256 0x04 48 0x14 576 0x24 32 0x34 320 0x05 52 0x15 640 0x25 36 0x35 384 0x06 60 0x16 768
* 0x26 40 0x36 448 0x07 72 0x17 960 0x27 44 0x37 512 0x08 80 0x18 1152 0x28 48 0x38 640 0x09 88
* 0x19 1280 0x29 56 0x39 768 0x0A 104 0x1A 1536 0x2A 64 0x3A 896 0x0B 128 0x1B 1920 0x2B 72 0x3B
* 1024 0x0C 144 0x1C 2304 0x2C 80 0x3C 1280 0x0D 160 0x1D 2560 0x2D 96 0x3D 1536 0x0E 192 0x1E 3072
* 0x2E 112 0x3E 1792 0x0F 240 0x1F 3840 0x2F 128 0x3F 2048
*/
typedef union _hw_i2c_ifdr
{
reg16_t U;
struct _hw_i2c_ifdr_bitfields
{
unsigned short IC : 6; //!< [5:0] I2C clock rate.
unsigned short RESERVED0 : 10; //!< [15:6] Reserved
} B;
} hw_i2c_ifdr_t;
#endif
/*!
* @name Constants and macros for entire I2C_IFDR register
*/
//@{
#define HW_I2C_IFDR_ADDR(x) (REGS_I2C_BASE(x) + 0x4)
#ifndef __LANGUAGE_ASM__
#define HW_I2C_IFDR(x) (*(volatile hw_i2c_ifdr_t *) HW_I2C_IFDR_ADDR(x))
#define HW_I2C_IFDR_RD(x) (HW_I2C_IFDR(x).U)
#define HW_I2C_IFDR_WR(x, v) (HW_I2C_IFDR(x).U = (v))
#define HW_I2C_IFDR_SET(x, v) (HW_I2C_IFDR_WR(x, HW_I2C_IFDR_RD(x) | (v)))
#define HW_I2C_IFDR_CLR(x, v) (HW_I2C_IFDR_WR(x, HW_I2C_IFDR_RD(x) & ~(v)))
#define HW_I2C_IFDR_TOG(x, v) (HW_I2C_IFDR_WR(x, HW_I2C_IFDR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual I2C_IFDR bitfields
*/
/*! @name Register I2C_IFDR, field IC[5:0] (RW)
*
* I2C clock rate. Pre-scales the clock for bit-rate selection. Due to potentially slow I2Cn_SCL and
* I2Cn_SDA rise and fall times, bus signals are sampled at the prescaler frequency. The serial bit
* clock frequency may be lower than IPG_CLK_ROOT divided by the divider shown in the I2C Data I/O
* Register. The IC value should not be changed during the data transfer, however, it can be changed
* before REPEAT START or START programming sequence in I2C. The I2C protocol supports bit rates up
* to 400 kbps. The IC bits need to be programmed in accordance with this constraint.
*/
//@{
#define BP_I2C_IFDR_IC (0) //!< Bit position for I2C_IFDR_IC.
#define BM_I2C_IFDR_IC (0x0000003f) //!< Bit mask for I2C_IFDR_IC.
//! @brief Get value of I2C_IFDR_IC from a register value.
#define BG_I2C_IFDR_IC(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_IFDR_IC) >> BP_I2C_IFDR_IC)
//! @brief Format value for bitfield I2C_IFDR_IC.
#define BF_I2C_IFDR_IC(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_IFDR_IC) & BM_I2C_IFDR_IC)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IC field to a new value.
#define BW_I2C_IFDR_IC(x, v) (HW_I2C_IFDR_WR(x, (HW_I2C_IFDR_RD(x) & ~BM_I2C_IFDR_IC) | BF_I2C_IFDR_IC(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_I2C_I2CR - I2C Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_I2C_I2CR - I2C Control Register (RW)
*
* Reset value: 0x0000
*
* The I2C_I2CR is used to enable the I2C and the I2C interrupt. It also contains bits that govern
* operation as a slave or a master.
*/
typedef union _hw_i2c_i2cr
{
reg16_t U;
struct _hw_i2c_i2cr_bitfields
{
unsigned short RESERVED0 : 2; //!< [1:0] Reserved
unsigned short RSTA : 1; //!< [2] Repeat start.
unsigned short TXAK : 1; //!< [3] Transmit acknowledge enable.
unsigned short MTX : 1; //!< [4] Transmit/receive mode select bit.
unsigned short MSTA : 1; //!< [5] Master/slave mode select bit.
unsigned short IIEN : 1; //!< [6] I2C interrupt enable.
unsigned short IEN : 1; //!< [7] I2C enable.
unsigned short RESERVED1 : 8; //!< [15:8] Reserved
} B;
} hw_i2c_i2cr_t;
#endif
/*!
* @name Constants and macros for entire I2C_I2CR register
*/
//@{
#define HW_I2C_I2CR_ADDR(x) (REGS_I2C_BASE(x) + 0x8)
#ifndef __LANGUAGE_ASM__
#define HW_I2C_I2CR(x) (*(volatile hw_i2c_i2cr_t *) HW_I2C_I2CR_ADDR(x))
#define HW_I2C_I2CR_RD(x) (HW_I2C_I2CR(x).U)
#define HW_I2C_I2CR_WR(x, v) (HW_I2C_I2CR(x).U = (v))
#define HW_I2C_I2CR_SET(x, v) (HW_I2C_I2CR_WR(x, HW_I2C_I2CR_RD(x) | (v)))
#define HW_I2C_I2CR_CLR(x, v) (HW_I2C_I2CR_WR(x, HW_I2C_I2CR_RD(x) & ~(v)))
#define HW_I2C_I2CR_TOG(x, v) (HW_I2C_I2CR_WR(x, HW_I2C_I2CR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual I2C_I2CR bitfields
*/
/*! @name Register I2C_I2CR, field RSTA[2] (WORZ)
*
* Repeat start. Always reads as 0. Attempting a repeat start without bus mastership causes loss of
* arbitration.
*
* Values:
* - 0 - No repeat start
* - 1 - Generates a repeated START condition
*/
//@{
#define BP_I2C_I2CR_RSTA (2) //!< Bit position for I2C_I2CR_RSTA.
#define BM_I2C_I2CR_RSTA (0x00000004) //!< Bit mask for I2C_I2CR_RSTA.
//! @brief Get value of I2C_I2CR_RSTA from a register value.
#define BG_I2C_I2CR_RSTA(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_RSTA) >> BP_I2C_I2CR_RSTA)
//! @brief Format value for bitfield I2C_I2CR_RSTA.
#define BF_I2C_I2CR_RSTA(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_RSTA) & BM_I2C_I2CR_RSTA)
//@}
/*! @name Register I2C_I2CR, field TXAK[3] (RW)
*
* Transmit acknowledge enable. Specifies the value driven onto I2Cn_SDA during acknowledge cycles
* for both master and slave receivers. Writing TXAK applies only when the I2C bus is a receiver.
*
* Values:
* - 0 - An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.
* - 1 - No acknowledge signal response is sent (that is, the acknowledge bit = 1).
*/
//@{
#define BP_I2C_I2CR_TXAK (3) //!< Bit position for I2C_I2CR_TXAK.
#define BM_I2C_I2CR_TXAK (0x00000008) //!< Bit mask for I2C_I2CR_TXAK.
//! @brief Get value of I2C_I2CR_TXAK from a register value.
#define BG_I2C_I2CR_TXAK(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_TXAK) >> BP_I2C_I2CR_TXAK)
//! @brief Format value for bitfield I2C_I2CR_TXAK.
#define BF_I2C_I2CR_TXAK(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_TXAK) & BM_I2C_I2CR_TXAK)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TXAK field to a new value.
#define BW_I2C_I2CR_TXAK(x, v) (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_TXAK) | BF_I2C_I2CR_TXAK(v)))
#endif
//@}
/*! @name Register I2C_I2CR, field MTX[4] (RW)
*
* Transmit/receive mode select bit. Selects the direction of master and slave transfers.
*
* Values:
* - 0 - Receive. When a slave is addressed, the software should set MTX according to the slave read/write
* bit in the I2C status register (I2C_I2SR[SRW]).
* - 1 - Transmit. In master mode, MTX should be set according to the type of transfer required. Therefore,
* for address cycles, MTX is always 1.
*/
//@{
#define BP_I2C_I2CR_MTX (4) //!< Bit position for I2C_I2CR_MTX.
#define BM_I2C_I2CR_MTX (0x00000010) //!< Bit mask for I2C_I2CR_MTX.
//! @brief Get value of I2C_I2CR_MTX from a register value.
#define BG_I2C_I2CR_MTX(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_MTX) >> BP_I2C_I2CR_MTX)
//! @brief Format value for bitfield I2C_I2CR_MTX.
#define BF_I2C_I2CR_MTX(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_MTX) & BM_I2C_I2CR_MTX)
#ifndef __LANGUAGE_ASM__
//! @brief Set the MTX field to a new value.
#define BW_I2C_I2CR_MTX(x, v) (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_MTX) | BF_I2C_I2CR_MTX(v)))
#endif
//@}
/*! @name Register I2C_I2CR, field MSTA[5] (RW)
*
* Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without generating
* a STOP signal. Module clock should be on for writing to the MSTA bit. The MSTA bit is cleared by
* software to generate a STOP condition; it can also be cleared by hardware when the I2C loses the
* bus arbitration.
*
* Values:
* - 0 - Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode.
* - 1 - Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects master mode.
*/
//@{
#define BP_I2C_I2CR_MSTA (5) //!< Bit position for I2C_I2CR_MSTA.
#define BM_I2C_I2CR_MSTA (0x00000020) //!< Bit mask for I2C_I2CR_MSTA.
//! @brief Get value of I2C_I2CR_MSTA from a register value.
#define BG_I2C_I2CR_MSTA(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_MSTA) >> BP_I2C_I2CR_MSTA)
//! @brief Format value for bitfield I2C_I2CR_MSTA.
#define BF_I2C_I2CR_MSTA(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_MSTA) & BM_I2C_I2CR_MSTA)
#ifndef __LANGUAGE_ASM__
//! @brief Set the MSTA field to a new value.
#define BW_I2C_I2CR_MSTA(x, v) (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_MSTA) | BF_I2C_I2CR_MSTA(v)))
#endif
//@}
/*! @name Register I2C_I2CR, field IIEN[6] (RW)
*
* I2C interrupt enable. If data is written during the START condition, that is, just after setting
* the I2C_I2CR[MSTA] and I2C_I2CR[MTX] bits, then the ICF bit is cleared at the falling edge of
* SCLK after START. If data is written after the START condition and falling edge of SCLK, then ICF
* bit is cleared as soon as data is written.
*
* Values:
* - 0 - I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an interrupt
* condition occurs.
* - 1 - I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set.
*/
//@{
#define BP_I2C_I2CR_IIEN (6) //!< Bit position for I2C_I2CR_IIEN.
#define BM_I2C_I2CR_IIEN (0x00000040) //!< Bit mask for I2C_I2CR_IIEN.
//! @brief Get value of I2C_I2CR_IIEN from a register value.
#define BG_I2C_I2CR_IIEN(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_IIEN) >> BP_I2C_I2CR_IIEN)
//! @brief Format value for bitfield I2C_I2CR_IIEN.
#define BF_I2C_I2CR_IIEN(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_IIEN) & BM_I2C_I2CR_IIEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IIEN field to a new value.
#define BW_I2C_I2CR_IIEN(x, v) (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_IIEN) | BF_I2C_I2CR_IIEN(v)))
#endif
//@}
/*! @name Register I2C_I2CR, field IEN[7] (RW)
*
* I2C enable. Also controls the software reset of the entire I2C. Resetting the bit generates an
* internal reset to the block. If the block is enabled in the middle of a byte transfer, slave mode
* ignores the current bus transfer and starts operating when the next start condition is detected.
* Master mode is not aware that the bus is busy so initiating a start cycle may corrupt the current
* bus cycle, ultimately causing either the current master or the I2C to lose arbitration. After
* which, bus operation returns to normal.
*
* Values:
* - 0 - The block is disabled, but registers can still be accessed.
* - 1 - The I2C is enabled. This bit must be set before any other I2C_I2CR bits have any effect.
*/
//@{
#define BP_I2C_I2CR_IEN (7) //!< Bit position for I2C_I2CR_IEN.
#define BM_I2C_I2CR_IEN (0x00000080) //!< Bit mask for I2C_I2CR_IEN.
//! @brief Get value of I2C_I2CR_IEN from a register value.
#define BG_I2C_I2CR_IEN(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_IEN) >> BP_I2C_I2CR_IEN)
//! @brief Format value for bitfield I2C_I2CR_IEN.
#define BF_I2C_I2CR_IEN(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_IEN) & BM_I2C_I2CR_IEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IEN field to a new value.
#define BW_I2C_I2CR_IEN(x, v) (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_IEN) | BF_I2C_I2CR_IEN(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_I2C_I2SR - I2C Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_I2C_I2SR - I2C Status Register (RW)
*
* Reset value: 0x0081
*
* The I2C_I2SR contains bits that indicate transaction direction and status.
*/
typedef union _hw_i2c_i2sr
{
reg16_t U;
struct _hw_i2c_i2sr_bitfields
{
unsigned short RXAK : 1; //!< [0] Received acknowledge.
unsigned short IIF : 1; //!< [1] I2C interrupt.
unsigned short SRW : 1; //!< [2] Slave read/write.
unsigned short RESERVED0 : 1; //!< [3] Reserved
unsigned short IAL : 1; //!< [4] Arbitration lost.
unsigned short IBB : 1; //!< [5] I2C bus busy bit.
unsigned short IAAS : 1; //!< [6] I2C addressed as a slave bit.
unsigned short ICF : 1; //!< [7] Data transferring bit.
unsigned short RESERVED1 : 8; //!< [15:8] Reserved
} B;
} hw_i2c_i2sr_t;
#endif
/*!
* @name Constants and macros for entire I2C_I2SR register
*/
//@{
#define HW_I2C_I2SR_ADDR(x) (REGS_I2C_BASE(x) + 0xc)
#ifndef __LANGUAGE_ASM__
#define HW_I2C_I2SR(x) (*(volatile hw_i2c_i2sr_t *) HW_I2C_I2SR_ADDR(x))
#define HW_I2C_I2SR_RD(x) (HW_I2C_I2SR(x).U)
#define HW_I2C_I2SR_WR(x, v) (HW_I2C_I2SR(x).U = (v))
#define HW_I2C_I2SR_SET(x, v) (HW_I2C_I2SR_WR(x, HW_I2C_I2SR_RD(x) | (v)))
#define HW_I2C_I2SR_CLR(x, v) (HW_I2C_I2SR_WR(x, HW_I2C_I2SR_RD(x) & ~(v)))
#define HW_I2C_I2SR_TOG(x, v) (HW_I2C_I2SR_WR(x, HW_I2C_I2SR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual I2C_I2SR bitfields
*/
/*! @name Register I2C_I2SR, field RXAK[0] (RO)
*
* Received acknowledge. This is the value received of the I2Cn_SDA input for the acknowledge bit
* during a bus cycle.
*
* Values:
* - 0 - An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus.
* - 1 - A "No acknowledge" signal was detected at the ninth clock.
*/
//@{
#define BP_I2C_I2SR_RXAK (0) //!< Bit position for I2C_I2SR_RXAK.
#define BM_I2C_I2SR_RXAK (0x00000001) //!< Bit mask for I2C_I2SR_RXAK.
//! @brief Get value of I2C_I2SR_RXAK from a register value.
#define BG_I2C_I2SR_RXAK(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_RXAK) >> BP_I2C_I2SR_RXAK)
//@}
/*! @name Register I2C_I2SR, field IIF[1] (RW)
*
* I2C interrupt. Must be cleared by the software by writing a "0" to it in the interrupt routine.
* The software cannot set the bit.
*
* Values:
* - 0 - No I2C interrupt pending.
* - 1 - An interrupt is pending. This causes a processor interrupt request (if the interrupt enable is
* asserted [IIEN = 1]). The interrupt is set when one of the following occurs: One byte
* transfer is completed (the interrupt is set at the falling edge of the ninth clock). An
* address is received that matches its own specific address in slave-receive mode. Arbitration
* is lost.
*/
//@{
#define BP_I2C_I2SR_IIF (1) //!< Bit position for I2C_I2SR_IIF.
#define BM_I2C_I2SR_IIF (0x00000002) //!< Bit mask for I2C_I2SR_IIF.
//! @brief Get value of I2C_I2SR_IIF from a register value.
#define BG_I2C_I2SR_IIF(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_IIF) >> BP_I2C_I2SR_IIF)
//! @brief Format value for bitfield I2C_I2SR_IIF.
#define BF_I2C_I2SR_IIF(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2SR_IIF) & BM_I2C_I2SR_IIF)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IIF field to a new value.
#define BW_I2C_I2SR_IIF(x, v) (HW_I2C_I2SR_WR(x, (HW_I2C_I2SR_RD(x) & ~BM_I2C_I2SR_IIF) | BF_I2C_I2SR_IIF(v)))
#endif
//@}
/*! @name Register I2C_I2SR, field SRW[2] (RO)
*
* Slave read/write. When the I2C is addressed as a slave, IAAS is set, and the slave read/write bit
* (SRW) indicates the value of the R/W command bit of the calling address sent from the master. SRW
* is valid only when a complete transfer has occurred, no other transfers have been initiated, and
* the I2C is a slave and has an address match.
*
* Values:
* - 0 - Slave receive, master writing to slave
* - 1 - Slave transmit, master reading from slave
*/
//@{
#define BP_I2C_I2SR_SRW (2) //!< Bit position for I2C_I2SR_SRW.
#define BM_I2C_I2SR_SRW (0x00000004) //!< Bit mask for I2C_I2SR_SRW.
//! @brief Get value of I2C_I2SR_SRW from a register value.
#define BG_I2C_I2SR_SRW(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_SRW) >> BP_I2C_I2SR_SRW)
//@}
/*! @name Register I2C_I2SR, field IAL[4] (RW)
*
* Arbitration lost. Set by hardware in the following circumstances (IAL must be cleared by software
* by writing a "0" to it at the start of the interrupt service routine): I2Cn_SDA input sampled low
* when the master drives high during an address or data-transmit cycle. I2Cn_SDA input sampled low
* when the master drives high during the acknowledge bit of a data-receive cycle. For the above two
* cases, the bit is set at the falling edge of 9th I2Cn_SCL clock during the ACK cycle. A start
* cycle is attempted when the bus is busy. A repeated start cycle is requested in slave mode. A
* stop condition is detected when the master did not request it. Software cannot set the bit.
*
* Values:
* - 0 - No arbitration lost.
* - 1 - Arbitration is lost.
*/
//@{
#define BP_I2C_I2SR_IAL (4) //!< Bit position for I2C_I2SR_IAL.
#define BM_I2C_I2SR_IAL (0x00000010) //!< Bit mask for I2C_I2SR_IAL.
//! @brief Get value of I2C_I2SR_IAL from a register value.
#define BG_I2C_I2SR_IAL(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_IAL) >> BP_I2C_I2SR_IAL)
//! @brief Format value for bitfield I2C_I2SR_IAL.
#define BF_I2C_I2SR_IAL(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2SR_IAL) & BM_I2C_I2SR_IAL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IAL field to a new value.
#define BW_I2C_I2SR_IAL(x, v) (HW_I2C_I2SR_WR(x, (HW_I2C_I2SR_RD(x) & ~BM_I2C_I2SR_IAL) | BF_I2C_I2SR_IAL(v)))
#endif
//@}
/*! @name Register I2C_I2SR, field IBB[5] (RO)
*
* I2C bus busy bit. Indicates the status of the bus. When I2C is enabled (I2C_I2CR[IEN] = 1), it
* continuously polls the bus data (SDAK) and clock (SCLK) signals to determine a START or STOP
* condition.
*
* Values:
* - 0 - Bus is idle. If a STOP signal is detected, IBB is cleared.
* - 1 - Bus is busy. When START is detected, IBB is set.
*/
//@{
#define BP_I2C_I2SR_IBB (5) //!< Bit position for I2C_I2SR_IBB.
#define BM_I2C_I2SR_IBB (0x00000020) //!< Bit mask for I2C_I2SR_IBB.
//! @brief Get value of I2C_I2SR_IBB from a register value.
#define BG_I2C_I2SR_IBB(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_IBB) >> BP_I2C_I2SR_IBB)
//@}
/*! @name Register I2C_I2SR, field IAAS[6] (RO)
*
* I2C addressed as a slave bit. The ARM platform is interrupted if the interrupt enable
* (I2C_I2CR[IIEN]) is set. The ARM platform must check the slave read/write bit (SRW) and set its
* TX/RX mode accordingly. Writing to I2C_I2CR clears this bit.
*
* Values:
* - 0 - Not addressed
* - 1 - Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address.
*/
//@{
#define BP_I2C_I2SR_IAAS (6) //!< Bit position for I2C_I2SR_IAAS.
#define BM_I2C_I2SR_IAAS (0x00000040) //!< Bit mask for I2C_I2SR_IAAS.
//! @brief Get value of I2C_I2SR_IAAS from a register value.
#define BG_I2C_I2SR_IAAS(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_IAAS) >> BP_I2C_I2SR_IAAS)
//@}
/*! @name Register I2C_I2SR, field ICF[7] (RO)
*
* Data transferring bit. While one byte of data is transferred, ICF is cleared.
*
* Values:
* - 0 - Transfer is in progress.
* - 1 - Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte
* transfer.
*/
//@{
#define BP_I2C_I2SR_ICF (7) //!< Bit position for I2C_I2SR_ICF.
#define BM_I2C_I2SR_ICF (0x00000080) //!< Bit mask for I2C_I2SR_ICF.
//! @brief Get value of I2C_I2SR_ICF from a register value.
#define BG_I2C_I2SR_ICF(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_ICF) >> BP_I2C_I2SR_ICF)
//@}
//-------------------------------------------------------------------------------------------
// HW_I2C_I2DR - I2C Data I/O Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_I2C_I2DR - I2C Data I/O Register (RW)
*
* Reset value: 0x0000
*
* In master-receive mode, reading the data register allows a read to occur and initiates the next
* byte to be received. In slave mode, the same function is available after it is addressed.
*/
typedef union _hw_i2c_i2dr
{
reg16_t U;
struct _hw_i2c_i2dr_bitfields
{
unsigned short DATA : 8; //!< [7:0] Data Byte.
unsigned short RESERVED0 : 8; //!< [15:8] Reserved
} B;
} hw_i2c_i2dr_t;
#endif
/*!
* @name Constants and macros for entire I2C_I2DR register
*/
//@{
#define HW_I2C_I2DR_ADDR(x) (REGS_I2C_BASE(x) + 0x10)
#ifndef __LANGUAGE_ASM__
#define HW_I2C_I2DR(x) (*(volatile hw_i2c_i2dr_t *) HW_I2C_I2DR_ADDR(x))
#define HW_I2C_I2DR_RD(x) (HW_I2C_I2DR(x).U)
#define HW_I2C_I2DR_WR(x, v) (HW_I2C_I2DR(x).U = (v))
#define HW_I2C_I2DR_SET(x, v) (HW_I2C_I2DR_WR(x, HW_I2C_I2DR_RD(x) | (v)))
#define HW_I2C_I2DR_CLR(x, v) (HW_I2C_I2DR_WR(x, HW_I2C_I2DR_RD(x) & ~(v)))
#define HW_I2C_I2DR_TOG(x, v) (HW_I2C_I2DR_WR(x, HW_I2C_I2DR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual I2C_I2DR bitfields
*/
/*! @name Register I2C_I2DR, field DATA[7:0] (RW)
*
* Data Byte. Holds the last data byte received or the next data byte to be transferred. Software
* writes the next data byte to be transmitted or reads the data byte received. The core-written
* value in I2C_I2DR cannot be read back by the core. Only data written by the I2C bus side can be
* read.
*/
//@{
#define BP_I2C_I2DR_DATA (0) //!< Bit position for I2C_I2DR_DATA.
#define BM_I2C_I2DR_DATA (0x000000ff) //!< Bit mask for I2C_I2DR_DATA.
//! @brief Get value of I2C_I2DR_DATA from a register value.
#define BG_I2C_I2DR_DATA(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2DR_DATA) >> BP_I2C_I2DR_DATA)
//! @brief Format value for bitfield I2C_I2DR_DATA.
#define BF_I2C_I2DR_DATA(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2DR_DATA) & BM_I2C_I2DR_DATA)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DATA field to a new value.
#define BW_I2C_I2DR_DATA(x, v) (HW_I2C_I2DR_WR(x, (HW_I2C_I2DR_RD(x) & ~BM_I2C_I2DR_DATA) | BF_I2C_I2DR_DATA(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_i2c_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All I2C module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_i2c
{
volatile hw_i2c_iadr_t IADR; //!< I2C Address Register
reg16_t _reserved0;
volatile hw_i2c_ifdr_t IFDR; //!< I2C Frequency Divider Register
reg16_t _reserved1;
volatile hw_i2c_i2cr_t I2CR; //!< I2C Control Register
reg16_t _reserved2;
volatile hw_i2c_i2sr_t I2SR; //!< I2C Status Register
reg16_t _reserved3;
volatile hw_i2c_i2dr_t I2DR; //!< I2C Data I/O Register
} hw_i2c_t;
#pragma pack()
//! @brief Macro to access all I2C registers.
//! @param x I2C instance number.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_I2C(0)</code>.
#define HW_I2C(x) (*(hw_i2c_t *) REGS_I2C_BASE(x))
#endif
#endif // __HW_I2C_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_KPP_REGISTERS_H__
#define __HW_KPP_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ KPP
*
* KPP Registers
*
* Registers defined in this header file:
* - HW_KPP_KPCR - Keypad Control Register
* - HW_KPP_KPSR - Keypad Status Register
* - HW_KPP_KDDR - Keypad Data Direction Register
* - HW_KPP_KPDR - Keypad Data Register
*
* - hw_kpp_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_KPP_BASE
#define HW_KPP_INSTANCE_COUNT (1) //!< Number of instances of the KPP module.
#define REGS_KPP_BASE (0x020b8000) //!< Base address for KPP.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_KPP_KPCR - Keypad Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_KPP_KPCR - Keypad Control Register (RW)
*
* Reset value: 0x0000
*
* The Keypad Control Register determines which of the eight possible column strobes are to be open
* drain when configured as outputs, and which of the eight row sense lines are considered in
* generating an interrupt to the core. It is up to the programmer to ensure that pins being used
* for functions other than the keypad are properly disabled. The KPP_KPCR register is byte- or
* half-word-addressable.
*/
typedef union _hw_kpp_kpcr
{
reg16_t U;
struct _hw_kpp_kpcr_bitfields
{
unsigned short KRE : 8; //!< [7:0] Keypad Row Enable.
unsigned short KCO : 8; //!< [15:8] Keypad Column Strobe Open-Drain Enable.
} B;
} hw_kpp_kpcr_t;
#endif
/*!
* @name Constants and macros for entire KPP_KPCR register
*/
//@{
#define HW_KPP_KPCR_ADDR (REGS_KPP_BASE + 0x0)
#ifndef __LANGUAGE_ASM__
#define HW_KPP_KPCR (*(volatile hw_kpp_kpcr_t *) HW_KPP_KPCR_ADDR)
#define HW_KPP_KPCR_RD() (HW_KPP_KPCR.U)
#define HW_KPP_KPCR_WR(v) (HW_KPP_KPCR.U = (v))
#define HW_KPP_KPCR_SET(v) (HW_KPP_KPCR_WR(HW_KPP_KPCR_RD() | (v)))
#define HW_KPP_KPCR_CLR(v) (HW_KPP_KPCR_WR(HW_KPP_KPCR_RD() & ~(v)))
#define HW_KPP_KPCR_TOG(v) (HW_KPP_KPCR_WR(HW_KPP_KPCR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual KPP_KPCR bitfields
*/
/*! @name Register KPP_KPCR, field KRE[7:0] (RW)
*
* Keypad Row Enable. Setting a row enable control bit in this register enables the corresponding
* row line to participate in interrupt generation. Likewise, clearing a bit disables that row from
* being used to generate an interrupt. This register is cleared by a reset, disabling all rows. The
* row-enable logic is independent of the programmed direction of the pin. Writing a "0" to the data
* register of the pins configured as outputs will cause a keypad interrupt to be generated if the
* row enable associated with that bit is set.
*
* Values:
* - 0 - Row is not included in the keypad key press detect.
* - 1 - Row is included in the keypad key press detect.
*/
//@{
#define BP_KPP_KPCR_KRE (0) //!< Bit position for KPP_KPCR_KRE.
#define BM_KPP_KPCR_KRE (0x000000ff) //!< Bit mask for KPP_KPCR_KRE.
//! @brief Get value of KPP_KPCR_KRE from a register value.
#define BG_KPP_KPCR_KRE(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_KPP_KPCR_KRE) >> BP_KPP_KPCR_KRE)
//! @brief Format value for bitfield KPP_KPCR_KRE.
#define BF_KPP_KPCR_KRE(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_KPP_KPCR_KRE) & BM_KPP_KPCR_KRE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the KRE field to a new value.
#define BW_KPP_KPCR_KRE(v) (HW_KPP_KPCR_WR((HW_KPP_KPCR_RD() & ~BM_KPP_KPCR_KRE) | BF_KPP_KPCR_KRE(v)))
#endif
//@}
/*! @name Register KPP_KPCR, field KCO[15:8] (RW)
*
* Keypad Column Strobe Open-Drain Enable. Setting a column open-drain enable bit (KCO7-KCO0)
* disables the pull-up driver on that pin. Clearing the bit allows the pin to drive to the high
* state. This bit has no effect when the pin is configured as an input. Configuration of external
* port control logic (for example, IOMUX) should be done properly so that the KPP controls an open-
* drain enable of the pin.
*
* Values:
* - TOTEM_POLE = 0 - Column strobe output is totem pole drive.
* - OPEN_DRAIN = 1 - Column strobe output is open drain.
*/
//@{
#define BP_KPP_KPCR_KCO (8) //!< Bit position for KPP_KPCR_KCO.
#define BM_KPP_KPCR_KCO (0x0000ff00) //!< Bit mask for KPP_KPCR_KCO.
//! @brief Get value of KPP_KPCR_KCO from a register value.
#define BG_KPP_KPCR_KCO(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_KPP_KPCR_KCO) >> BP_KPP_KPCR_KCO)
//! @brief Format value for bitfield KPP_KPCR_KCO.
#define BF_KPP_KPCR_KCO(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_KPP_KPCR_KCO) & BM_KPP_KPCR_KCO)
#ifndef __LANGUAGE_ASM__
//! @brief Set the KCO field to a new value.
#define BW_KPP_KPCR_KCO(v) (HW_KPP_KPCR_WR((HW_KPP_KPCR_RD() & ~BM_KPP_KPCR_KCO) | BF_KPP_KPCR_KCO(v)))
#endif
//! @brief Macro to simplify usage of value macros.
#define BF_KPP_KPCR_KCO_V(v) BF_KPP_KPCR_KCO(BV_KPP_KPCR_KCO__##v)
#define BV_KPP_KPCR_KCO__TOTEM_POLE (0x0) //!< Column strobe output is totem pole drive.
#define BV_KPP_KPCR_KCO__OPEN_DRAIN (0x1) //!< Column strobe output is open drain.
//@}
//-------------------------------------------------------------------------------------------
// HW_KPP_KPSR - Keypad Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_KPP_KPSR - Keypad Status Register (RW)
*
* Reset value: 0x0400
*
* The Keypad Status Register reflects the state of the key press detect circuit. The KPP_KPSR
* register is byte- or half-word-addressable.
*/
typedef union _hw_kpp_kpsr
{
reg16_t U;
struct _hw_kpp_kpsr_bitfields
{
unsigned short KPKD : 1; //!< [0] Keypad Key Depress.
unsigned short KPKR : 1; //!< [1] Keypad Key Release.
unsigned short KDSC : 1; //!< [2] Key Depress Synchronizer Clear.
unsigned short KRSS : 1; //!< [3] Key Release Synchronizer Set.
unsigned short RESERVED0 : 4; //!< [7:4] Reserved, should be cleared
unsigned short KDIE : 1; //!< [8] Keypad Key Depress Interrupt Enable.
unsigned short KRIE : 1; //!< [9] Keypad Release Interrupt Enable.
unsigned short RESERVED1 : 6; //!< [15:10] Reserved
} B;
} hw_kpp_kpsr_t;
#endif
/*!
* @name Constants and macros for entire KPP_KPSR register
*/
//@{
#define HW_KPP_KPSR_ADDR (REGS_KPP_BASE + 0x2)
#ifndef __LANGUAGE_ASM__
#define HW_KPP_KPSR (*(volatile hw_kpp_kpsr_t *) HW_KPP_KPSR_ADDR)
#define HW_KPP_KPSR_RD() (HW_KPP_KPSR.U)
#define HW_KPP_KPSR_WR(v) (HW_KPP_KPSR.U = (v))
#define HW_KPP_KPSR_SET(v) (HW_KPP_KPSR_WR(HW_KPP_KPSR_RD() | (v)))
#define HW_KPP_KPSR_CLR(v) (HW_KPP_KPSR_WR(HW_KPP_KPSR_RD() & ~(v)))
#define HW_KPP_KPSR_TOG(v) (HW_KPP_KPSR_WR(HW_KPP_KPSR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual KPP_KPSR bitfields
*/
/*! @name Register KPP_KPSR, field KPKD[0] (W1C)
*
* Keypad Key Depress. The keypad key depress (KPKD) status bit is set when one or more enabled rows
* are detected low after synchronization. The KPKD status bit remains set until cleared by the
* software. The KPKD bit may be used to generate a maskable key depress interrupt. If desired, the
* software may clear the key press synchronizer chain to allow a repeated interrupt to be generated
* while a key remains pressed. In this case, a new interrupt will be generated after the
* synchronizer delay (4 cycles of the low frequency reference clock elapses if a key remains
* pressed. This functionality can be used to detect a long key press. This allows detection of
* additional key presses of the same key or other keys. Due to the logic function of the release
* and depress synchronizer chains, it is possible to see the re-assertion of a status flag (KPKD or
* KPKR) if it is cleared by the software prior to the system exiting the state it represents.
*
* Values:
* - 0 - No key presses detected
* - 1 - A key has been depressed
*/
//@{
#define BP_KPP_KPSR_KPKD (0) //!< Bit position for KPP_KPSR_KPKD.
#define BM_KPP_KPSR_KPKD (0x00000001) //!< Bit mask for KPP_KPSR_KPKD.
//! @brief Get value of KPP_KPSR_KPKD from a register value.
#define BG_KPP_KPSR_KPKD(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_KPP_KPSR_KPKD) >> BP_KPP_KPSR_KPKD)
//! @brief Format value for bitfield KPP_KPSR_KPKD.
#define BF_KPP_KPSR_KPKD(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_KPP_KPSR_KPKD) & BM_KPP_KPSR_KPKD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the KPKD field to a new value.
#define BW_KPP_KPSR_KPKD(v) (HW_KPP_KPSR_WR((HW_KPP_KPSR_RD() & ~BM_KPP_KPSR_KPKD) | BF_KPP_KPSR_KPKD(v)))
#endif
//@}
/*! @name Register KPP_KPSR, field KPKR[1] (W1C)
*
* Keypad Key Release. The keypad key release (KPKR) status bit is set when all enabled rows are
* detected high after synchronization (the KPKR status bit will be set when cleared by a reset).
* The KPKR bit may be used to generate a maskable key release interrupt. The key release
* synchronizer may be set high by software after scanning the keypad to ensure a known state. Due
* to the logic function of the release and depress synchronizer chains, it is possible to see the
* re-assertion of a status flag (KPKD or KPKR) if it is cleared by software prior to the system
* exiting the state it represents. Reset value of register is "0" as long as reset is asserted.
* However when reset is de-asserted, the value of the register depends upon the external row pins
* and can become "1".
*
* Values:
* - 0 - No key release detected
* - 1 - All keys have been released
*/
//@{
#define BP_KPP_KPSR_KPKR (1) //!< Bit position for KPP_KPSR_KPKR.
#define BM_KPP_KPSR_KPKR (0x00000002) //!< Bit mask for KPP_KPSR_KPKR.
//! @brief Get value of KPP_KPSR_KPKR from a register value.
#define BG_KPP_KPSR_KPKR(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_KPP_KPSR_KPKR) >> BP_KPP_KPSR_KPKR)
//! @brief Format value for bitfield KPP_KPSR_KPKR.
#define BF_KPP_KPSR_KPKR(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_KPP_KPSR_KPKR) & BM_KPP_KPSR_KPKR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the KPKR field to a new value.
#define BW_KPP_KPSR_KPKR(v) (HW_KPP_KPSR_WR((HW_KPP_KPSR_RD() & ~BM_KPP_KPSR_KPKR) | BF_KPP_KPSR_KPKR(v)))
#endif
//@}
/*! @name Register KPP_KPSR, field KDSC[2] (WORZ)
*
* Key Depress Synchronizer Clear. Self-clear bit. The Key depress synchronizer is cleared by
* writing a logic "1" into this bit. Reads return a value of "0".
*
* Values:
* - 0 - No effect
* - 1 - Set bits that clear the keypad depress synchronizer chain
*/
//@{
#define BP_KPP_KPSR_KDSC (2) //!< Bit position for KPP_KPSR_KDSC.
#define BM_KPP_KPSR_KDSC (0x00000004) //!< Bit mask for KPP_KPSR_KDSC.
//! @brief Get value of KPP_KPSR_KDSC from a register value.
#define BG_KPP_KPSR_KDSC(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_KPP_KPSR_KDSC) >> BP_KPP_KPSR_KDSC)
//! @brief Format value for bitfield KPP_KPSR_KDSC.
#define BF_KPP_KPSR_KDSC(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_KPP_KPSR_KDSC) & BM_KPP_KPSR_KDSC)
//@}
/*! @name Register KPP_KPSR, field KRSS[3] (WORZ)
*
* Key Release Synchronizer Set. Self-clear bit. The Key release synchronizer is set by writing a
* logic one into this bit. Reads return a value of "0".
*
* Values:
* - 0 - No effect
* - 1 - Set bits which sets keypad release synchronizer chain
*/
//@{
#define BP_KPP_KPSR_KRSS (3) //!< Bit position for KPP_KPSR_KRSS.
#define BM_KPP_KPSR_KRSS (0x00000008) //!< Bit mask for KPP_KPSR_KRSS.
//! @brief Get value of KPP_KPSR_KRSS from a register value.
#define BG_KPP_KPSR_KRSS(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_KPP_KPSR_KRSS) >> BP_KPP_KPSR_KRSS)
//! @brief Format value for bitfield KPP_KPSR_KRSS.
#define BF_KPP_KPSR_KRSS(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_KPP_KPSR_KRSS) & BM_KPP_KPSR_KRSS)
//@}
/*! @name Register KPP_KPSR, field KDIE[8] (RW)
*
* Keypad Key Depress Interrupt Enable. Software should ensure that the interrupt for a Key Release
* event is masked until it has entered the key pressed state, and vice-versa, unless this activity
* is desired (as might be the case when a repeated interrupt is to be generated). The synchronizer
* chains are capable of being initialized to detect repeated key presses or releases. If they are
* not initialized when the corresponding event flag is cleared, false interrupts may be generated
* for depress (or release) events shorter than the length of the corresponding chain.
*
* Values:
* - 0 - No interrupt request is generated when KPKD is set.
* - 1 - An interrupt request is generated when KPKD is set.
*/
//@{
#define BP_KPP_KPSR_KDIE (8) //!< Bit position for KPP_KPSR_KDIE.
#define BM_KPP_KPSR_KDIE (0x00000100) //!< Bit mask for KPP_KPSR_KDIE.
//! @brief Get value of KPP_KPSR_KDIE from a register value.
#define BG_KPP_KPSR_KDIE(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_KPP_KPSR_KDIE) >> BP_KPP_KPSR_KDIE)
//! @brief Format value for bitfield KPP_KPSR_KDIE.
#define BF_KPP_KPSR_KDIE(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_KPP_KPSR_KDIE) & BM_KPP_KPSR_KDIE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the KDIE field to a new value.
#define BW_KPP_KPSR_KDIE(v) (HW_KPP_KPSR_WR((HW_KPP_KPSR_RD() & ~BM_KPP_KPSR_KDIE) | BF_KPP_KPSR_KDIE(v)))
#endif
//@}
/*! @name Register KPP_KPSR, field KRIE[9] (RW)
*
* Keypad Release Interrupt Enable. The software should ensure that the interrupt for a Key Release
* event is masked until it has entered the key pressed state, and vice versa, unless this activity
* is desired (as might be the case when a repeated interrupt is to be generated). The synchronizer
* chains are capable of being initialized to detect repeated key presses or releases. If they are
* not initialized when the corresponding event flag is cleared, false interrupts may be generated
* for depress (or release) events shorter than the length of the corresponding chain.
*
* Values:
* - 0 - No interrupt request is generated when KPKR is set.
* - 1 - An interrupt request is generated when KPKR is set.
*/
//@{
#define BP_KPP_KPSR_KRIE (9) //!< Bit position for KPP_KPSR_KRIE.
#define BM_KPP_KPSR_KRIE (0x00000200) //!< Bit mask for KPP_KPSR_KRIE.
//! @brief Get value of KPP_KPSR_KRIE from a register value.
#define BG_KPP_KPSR_KRIE(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_KPP_KPSR_KRIE) >> BP_KPP_KPSR_KRIE)
//! @brief Format value for bitfield KPP_KPSR_KRIE.
#define BF_KPP_KPSR_KRIE(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_KPP_KPSR_KRIE) & BM_KPP_KPSR_KRIE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the KRIE field to a new value.
#define BW_KPP_KPSR_KRIE(v) (HW_KPP_KPSR_WR((HW_KPP_KPSR_RD() & ~BM_KPP_KPSR_KRIE) | BF_KPP_KPSR_KRIE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_KPP_KDDR - Keypad Data Direction Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_KPP_KDDR - Keypad Data Direction Register (RW)
*
* Reset value: 0x0000
*
* The bits in the KPP_KDDR control the direction of the keypad port pins. The upper eight bits in
* the register affect the pins designated as column strobes, while the lower eight bits affect the
* row sense pins. Setting any bit in this register configures the corresponding pin as an output.
* Clearing any bit in this register configures the corresponding port pin as an input. For the
* Keypad Row DDR, an internal pull-up is enabled if the corresponding bit is clear. This register
* is cleared by a reset, configuring all pins as inputs. The KPP_KDDR register is byte- or half-
* word addressable. When a pin is used as row pin for keypad purposes, all corresponding pull-ups
* should be enabled at the upper level (for example, IOMUX) when the bit in KRDD is cleared.
*/
typedef union _hw_kpp_kddr
{
reg16_t U;
struct _hw_kpp_kddr_bitfields
{
unsigned short KRDD : 8; //!< [7:0] Keypad Row Data Direction.
unsigned short KCDD : 8; //!< [15:8] Keypad Column Data Direction Register.
} B;
} hw_kpp_kddr_t;
#endif
/*!
* @name Constants and macros for entire KPP_KDDR register
*/
//@{
#define HW_KPP_KDDR_ADDR (REGS_KPP_BASE + 0x4)
#ifndef __LANGUAGE_ASM__
#define HW_KPP_KDDR (*(volatile hw_kpp_kddr_t *) HW_KPP_KDDR_ADDR)
#define HW_KPP_KDDR_RD() (HW_KPP_KDDR.U)
#define HW_KPP_KDDR_WR(v) (HW_KPP_KDDR.U = (v))
#define HW_KPP_KDDR_SET(v) (HW_KPP_KDDR_WR(HW_KPP_KDDR_RD() | (v)))
#define HW_KPP_KDDR_CLR(v) (HW_KPP_KDDR_WR(HW_KPP_KDDR_RD() & ~(v)))
#define HW_KPP_KDDR_TOG(v) (HW_KPP_KDDR_WR(HW_KPP_KDDR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual KPP_KDDR bitfields
*/
/*! @name Register KPP_KDDR, field KRDD[7:0] (RW)
*
* Keypad Row Data Direction. Setting a bit configures the corresponding ROW n pin as an output
* (where n = 7 through 0).
*
* Values:
* - INPUT = 0 - ROWn pin configured as an input.
* - OUTPUT = 1 - ROWn pin configured as an output.
*/
//@{
#define BP_KPP_KDDR_KRDD (0) //!< Bit position for KPP_KDDR_KRDD.
#define BM_KPP_KDDR_KRDD (0x000000ff) //!< Bit mask for KPP_KDDR_KRDD.
//! @brief Get value of KPP_KDDR_KRDD from a register value.
#define BG_KPP_KDDR_KRDD(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_KPP_KDDR_KRDD) >> BP_KPP_KDDR_KRDD)
//! @brief Format value for bitfield KPP_KDDR_KRDD.
#define BF_KPP_KDDR_KRDD(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_KPP_KDDR_KRDD) & BM_KPP_KDDR_KRDD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the KRDD field to a new value.
#define BW_KPP_KDDR_KRDD(v) (HW_KPP_KDDR_WR((HW_KPP_KDDR_RD() & ~BM_KPP_KDDR_KRDD) | BF_KPP_KDDR_KRDD(v)))
#endif
//! @brief Macro to simplify usage of value macros.
#define BF_KPP_KDDR_KRDD_V(v) BF_KPP_KDDR_KRDD(BV_KPP_KDDR_KRDD__##v)
#define BV_KPP_KDDR_KRDD__INPUT (0x0) //!< ROWn pin configured as an input.
#define BV_KPP_KDDR_KRDD__OUTPUT (0x1) //!< ROWn pin configured as an output.
//@}
/*! @name Register KPP_KDDR, field KCDD[15:8] (RW)
*
* Keypad Column Data Direction Register. Setting a bit configures the corresponding COL n pin as an
* output (where n = 7 through 0).
*
* Values:
* - INPUT = 0 - COLn pin is configured as an input.
* - OUTPUT = 1 - COLn pin is configured as an output.
*/
//@{
#define BP_KPP_KDDR_KCDD (8) //!< Bit position for KPP_KDDR_KCDD.
#define BM_KPP_KDDR_KCDD (0x0000ff00) //!< Bit mask for KPP_KDDR_KCDD.
//! @brief Get value of KPP_KDDR_KCDD from a register value.
#define BG_KPP_KDDR_KCDD(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_KPP_KDDR_KCDD) >> BP_KPP_KDDR_KCDD)
//! @brief Format value for bitfield KPP_KDDR_KCDD.
#define BF_KPP_KDDR_KCDD(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_KPP_KDDR_KCDD) & BM_KPP_KDDR_KCDD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the KCDD field to a new value.
#define BW_KPP_KDDR_KCDD(v) (HW_KPP_KDDR_WR((HW_KPP_KDDR_RD() & ~BM_KPP_KDDR_KCDD) | BF_KPP_KDDR_KCDD(v)))
#endif
//! @brief Macro to simplify usage of value macros.
#define BF_KPP_KDDR_KCDD_V(v) BF_KPP_KDDR_KCDD(BV_KPP_KDDR_KCDD__##v)
#define BV_KPP_KDDR_KCDD__INPUT (0x0) //!< COLn pin is configured as an input.
#define BV_KPP_KDDR_KCDD__OUTPUT (0x1) //!< COLn pin is configured as an output.
//@}
//-------------------------------------------------------------------------------------------
// HW_KPP_KPDR - Keypad Data Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_KPP_KPDR - Keypad Data Register (RW)
*
* Reset value: 0x0000
*
* This 16-bit register is used to access the column and row data. Data written to this register is
* stored in an internal latch, and for each pin configured as an output, the stored data is driven
* onto the pin. A read of this register returns the value on the pin for those bits configured as
* inputs. Otherwise, the value read is the value stored in the register. The KPP_KPDR register is
* byte- or half-word addressable. This register is not initialized by a reset. Valid data should be
* written to this register before any bits are configured as outputs.
*/
typedef union _hw_kpp_kpdr
{
reg16_t U;
struct _hw_kpp_kpdr_bitfields
{
unsigned short KRD : 8; //!< [7:0] Keypad Row Data.
unsigned short KCD : 8; //!< [15:8] Keypad Column Data.
} B;
} hw_kpp_kpdr_t;
#endif
/*!
* @name Constants and macros for entire KPP_KPDR register
*/
//@{
#define HW_KPP_KPDR_ADDR (REGS_KPP_BASE + 0x6)
#ifndef __LANGUAGE_ASM__
#define HW_KPP_KPDR (*(volatile hw_kpp_kpdr_t *) HW_KPP_KPDR_ADDR)
#define HW_KPP_KPDR_RD() (HW_KPP_KPDR.U)
#define HW_KPP_KPDR_WR(v) (HW_KPP_KPDR.U = (v))
#define HW_KPP_KPDR_SET(v) (HW_KPP_KPDR_WR(HW_KPP_KPDR_RD() | (v)))
#define HW_KPP_KPDR_CLR(v) (HW_KPP_KPDR_WR(HW_KPP_KPDR_RD() & ~(v)))
#define HW_KPP_KPDR_TOG(v) (HW_KPP_KPDR_WR(HW_KPP_KPDR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual KPP_KPDR bitfields
*/
/*! @name Register KPP_KPDR, field KRD[7:0] (RW)
*
* Keypad Row Data. A read of these bits returns the value on the pin for those bits configured as
* inputs. Otherwise, the value read is the value stored in the register. 0 Read/Write "0" from/to
* row ports 1 Read/Write "1" from/to row ports
*/
//@{
#define BP_KPP_KPDR_KRD (0) //!< Bit position for KPP_KPDR_KRD.
#define BM_KPP_KPDR_KRD (0x000000ff) //!< Bit mask for KPP_KPDR_KRD.
//! @brief Get value of KPP_KPDR_KRD from a register value.
#define BG_KPP_KPDR_KRD(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_KPP_KPDR_KRD) >> BP_KPP_KPDR_KRD)
//! @brief Format value for bitfield KPP_KPDR_KRD.
#define BF_KPP_KPDR_KRD(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_KPP_KPDR_KRD) & BM_KPP_KPDR_KRD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the KRD field to a new value.
#define BW_KPP_KPDR_KRD(v) (HW_KPP_KPDR_WR((HW_KPP_KPDR_RD() & ~BM_KPP_KPDR_KRD) | BF_KPP_KPDR_KRD(v)))
#endif
//@}
/*! @name Register KPP_KPDR, field KCD[15:8] (RW)
*
* Keypad Column Data. A read of these bits returns the value on the pin for those bits configured
* as inputs. Otherwise, the value read is the value stored in the register. 0 Read/Write "0"
* from/to column ports 1 Read/Write "1" from/to column ports
*/
//@{
#define BP_KPP_KPDR_KCD (8) //!< Bit position for KPP_KPDR_KCD.
#define BM_KPP_KPDR_KCD (0x0000ff00) //!< Bit mask for KPP_KPDR_KCD.
//! @brief Get value of KPP_KPDR_KCD from a register value.
#define BG_KPP_KPDR_KCD(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_KPP_KPDR_KCD) >> BP_KPP_KPDR_KCD)
//! @brief Format value for bitfield KPP_KPDR_KCD.
#define BF_KPP_KPDR_KCD(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_KPP_KPDR_KCD) & BM_KPP_KPDR_KCD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the KCD field to a new value.
#define BW_KPP_KPDR_KCD(v) (HW_KPP_KPDR_WR((HW_KPP_KPDR_RD() & ~BM_KPP_KPDR_KCD) | BF_KPP_KPDR_KCD(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_kpp_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All KPP module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_kpp
{
volatile hw_kpp_kpcr_t KPCR; //!< Keypad Control Register
volatile hw_kpp_kpsr_t KPSR; //!< Keypad Status Register
volatile hw_kpp_kddr_t KDDR; //!< Keypad Data Direction Register
volatile hw_kpp_kpdr_t KPDR; //!< Keypad Data Register
} hw_kpp_t;
#pragma pack()
//! @brief Macro to access all KPP registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_KPP</code>.
#define HW_KPP (*(hw_kpp_t *) REGS_KPP_BASE)
#endif
#endif // __HW_KPP_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_LDB_REGISTERS_H__
#define __HW_LDB_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ LDB
*
* LDB
*
* Registers defined in this header file:
* - HW_LDB_CTRL - LDB Control Register
*
* - hw_ldb_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_LDB_BASE
#define HW_LDB_INSTANCE_COUNT (1) //!< Number of instances of the LDB module.
#define REGS_LDB_BASE (0x020e0008) //!< Base address for LDB.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_LDB_CTRL - LDB Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_LDB_CTRL - LDB Control Register (RW)
*
* Reset value: 0x00000000
*
* The register is implemented in the IOMUX Controller block (IOMUXC), as the register IOMUXC_GPR2.
*/
typedef union _hw_ldb_ctrl
{
reg32_t U;
struct _hw_ldb_ctrl_bitfields
{
unsigned CH0_MODE : 2; //!< [1:0] LVDS channel 0 operation mode
unsigned CH1_MODE : 2; //!< [3:2] LVDS channel 1 operation mode
unsigned SPLIT_MODE_EN : 1; //!< [4] Enable split mode.
unsigned DATA_WIDTH_CH0 : 1; //!< [5] Data width for LVDS channel 0.
unsigned BIT_MAPPING_CH0 : 1; //!< [6] Data mapping for LVDS channel 0.
unsigned DATA_WIDTH_CH1 : 1; //!< [7] Data width for LVDS channel 1.
unsigned BIT_MAPPING_CH1 : 1; //!< [8] Data mapping for LVDS channel 1.
unsigned DI0_VS_POLARITY : 1; //!< [9] Vsync polarity for IPU's DI0 interface.
unsigned DI1_VS_POLARITY : 1; //!< [10] Vsync polarity for IPU's DI1 interface.
unsigned RESERVED0 : 5; //!< [15:11] Reserved.
unsigned LVDS_CLK_SHIFT : 3; //!< [18:16] Shifts the LVDS output clock in relation to the data.
unsigned RESERVED1 : 1; //!< [19] Reserved
unsigned COUNTER_RESET_VAL : 2; //!< [21:20] Reset value for the LDB counter which determines when the shift registers are loaded with data.
unsigned RESERVED2 : 10; //!< [31:22] Reserved
} B;
} hw_ldb_ctrl_t;
#endif
/*!
* @name Constants and macros for entire LDB_CTRL register
*/
//@{
#define HW_LDB_CTRL_ADDR (REGS_LDB_BASE + 0x0)
#ifndef __LANGUAGE_ASM__
#define HW_LDB_CTRL (*(volatile hw_ldb_ctrl_t *) HW_LDB_CTRL_ADDR)
#define HW_LDB_CTRL_RD() (HW_LDB_CTRL.U)
#define HW_LDB_CTRL_WR(v) (HW_LDB_CTRL.U = (v))
#define HW_LDB_CTRL_SET(v) (HW_LDB_CTRL_WR(HW_LDB_CTRL_RD() | (v)))
#define HW_LDB_CTRL_CLR(v) (HW_LDB_CTRL_WR(HW_LDB_CTRL_RD() & ~(v)))
#define HW_LDB_CTRL_TOG(v) (HW_LDB_CTRL_WR(HW_LDB_CTRL_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual LDB_CTRL bitfields
*/
/*! @name Register LDB_CTRL, field CH0_MODE[1:0] (RW)
*
* LVDS channel 0 operation mode
*
* Values:
* - 00 - Channel disabled.
* - 01 - Channel enabled, routed to DI0
* - 10 - Channel disabled.
* - 11 - Channel enabled, routed to DI1.
*/
//@{
#define BP_LDB_CTRL_CH0_MODE (0) //!< Bit position for LDB_CTRL_CH0_MODE.
#define BM_LDB_CTRL_CH0_MODE (0x00000003) //!< Bit mask for LDB_CTRL_CH0_MODE.
//! @brief Get value of LDB_CTRL_CH0_MODE from a register value.
#define BG_LDB_CTRL_CH0_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_LDB_CTRL_CH0_MODE) >> BP_LDB_CTRL_CH0_MODE)
//! @brief Format value for bitfield LDB_CTRL_CH0_MODE.
#define BF_LDB_CTRL_CH0_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_LDB_CTRL_CH0_MODE) & BM_LDB_CTRL_CH0_MODE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CH0_MODE field to a new value.
#define BW_LDB_CTRL_CH0_MODE(v) (HW_LDB_CTRL_WR((HW_LDB_CTRL_RD() & ~BM_LDB_CTRL_CH0_MODE) | BF_LDB_CTRL_CH0_MODE(v)))
#endif
//@}
/*! @name Register LDB_CTRL, field CH1_MODE[3:2] (RW)
*
* LVDS channel 1 operation mode
*
* Values:
* - 00 - Channel disabled.
* - 01 - Channel enabled, routed to DI0
* - 10 - Channel disabled.
* - 11 - Channel enabled, routed to DI1.
*/
//@{
#define BP_LDB_CTRL_CH1_MODE (2) //!< Bit position for LDB_CTRL_CH1_MODE.
#define BM_LDB_CTRL_CH1_MODE (0x0000000c) //!< Bit mask for LDB_CTRL_CH1_MODE.
//! @brief Get value of LDB_CTRL_CH1_MODE from a register value.
#define BG_LDB_CTRL_CH1_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_LDB_CTRL_CH1_MODE) >> BP_LDB_CTRL_CH1_MODE)
//! @brief Format value for bitfield LDB_CTRL_CH1_MODE.
#define BF_LDB_CTRL_CH1_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_LDB_CTRL_CH1_MODE) & BM_LDB_CTRL_CH1_MODE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CH1_MODE field to a new value.
#define BW_LDB_CTRL_CH1_MODE(v) (HW_LDB_CTRL_WR((HW_LDB_CTRL_RD() & ~BM_LDB_CTRL_CH1_MODE) | BF_LDB_CTRL_CH1_MODE(v)))
#endif
//@}
/*! @name Register LDB_CTRL, field SPLIT_MODE_EN[4] (RW)
*
* Enable split mode. In this mode both channels should be enabled and working with the same DI
* (ch0_mode and ch1_mode should both be either '01' or '11')
*
* Values:
* - 0 - Split mode is disabled.
* - 1 - Split mode is enabled.
*/
//@{
#define BP_LDB_CTRL_SPLIT_MODE_EN (4) //!< Bit position for LDB_CTRL_SPLIT_MODE_EN.
#define BM_LDB_CTRL_SPLIT_MODE_EN (0x00000010) //!< Bit mask for LDB_CTRL_SPLIT_MODE_EN.
//! @brief Get value of LDB_CTRL_SPLIT_MODE_EN from a register value.
#define BG_LDB_CTRL_SPLIT_MODE_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_LDB_CTRL_SPLIT_MODE_EN) >> BP_LDB_CTRL_SPLIT_MODE_EN)
//! @brief Format value for bitfield LDB_CTRL_SPLIT_MODE_EN.
#define BF_LDB_CTRL_SPLIT_MODE_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_LDB_CTRL_SPLIT_MODE_EN) & BM_LDB_CTRL_SPLIT_MODE_EN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SPLIT_MODE_EN field to a new value.
#define BW_LDB_CTRL_SPLIT_MODE_EN(v) (HW_LDB_CTRL_WR((HW_LDB_CTRL_RD() & ~BM_LDB_CTRL_SPLIT_MODE_EN) | BF_LDB_CTRL_SPLIT_MODE_EN(v)))
#endif
//@}
/*! @name Register LDB_CTRL, field DATA_WIDTH_CH0[5] (RW)
*
* Data width for LVDS channel 0. This bit must be set when using JEIDA standard (bit_mapping_ch0 is
* set)
*
* Values:
* - 0 - Data width is 18 bits wide (lvds0_tx3 is not used)
* - 1 - Data width is 24 bits wide.
*/
//@{
#define BP_LDB_CTRL_DATA_WIDTH_CH0 (5) //!< Bit position for LDB_CTRL_DATA_WIDTH_CH0.
#define BM_LDB_CTRL_DATA_WIDTH_CH0 (0x00000020) //!< Bit mask for LDB_CTRL_DATA_WIDTH_CH0.
//! @brief Get value of LDB_CTRL_DATA_WIDTH_CH0 from a register value.
#define BG_LDB_CTRL_DATA_WIDTH_CH0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_LDB_CTRL_DATA_WIDTH_CH0) >> BP_LDB_CTRL_DATA_WIDTH_CH0)
//! @brief Format value for bitfield LDB_CTRL_DATA_WIDTH_CH0.
#define BF_LDB_CTRL_DATA_WIDTH_CH0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_LDB_CTRL_DATA_WIDTH_CH0) & BM_LDB_CTRL_DATA_WIDTH_CH0)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DATA_WIDTH_CH0 field to a new value.
#define BW_LDB_CTRL_DATA_WIDTH_CH0(v) (HW_LDB_CTRL_WR((HW_LDB_CTRL_RD() & ~BM_LDB_CTRL_DATA_WIDTH_CH0) | BF_LDB_CTRL_DATA_WIDTH_CH0(v)))
#endif
//@}
/*! @name Register LDB_CTRL, field BIT_MAPPING_CH0[6] (RW)
*
* Data mapping for LVDS channel 0.
*
* Values:
* - 0 - Use SPWG standard.
* - 1 - Use JEIDA standard.
*/
//@{
#define BP_LDB_CTRL_BIT_MAPPING_CH0 (6) //!< Bit position for LDB_CTRL_BIT_MAPPING_CH0.
#define BM_LDB_CTRL_BIT_MAPPING_CH0 (0x00000040) //!< Bit mask for LDB_CTRL_BIT_MAPPING_CH0.
//! @brief Get value of LDB_CTRL_BIT_MAPPING_CH0 from a register value.
#define BG_LDB_CTRL_BIT_MAPPING_CH0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_LDB_CTRL_BIT_MAPPING_CH0) >> BP_LDB_CTRL_BIT_MAPPING_CH0)
//! @brief Format value for bitfield LDB_CTRL_BIT_MAPPING_CH0.
#define BF_LDB_CTRL_BIT_MAPPING_CH0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_LDB_CTRL_BIT_MAPPING_CH0) & BM_LDB_CTRL_BIT_MAPPING_CH0)
#ifndef __LANGUAGE_ASM__
//! @brief Set the BIT_MAPPING_CH0 field to a new value.
#define BW_LDB_CTRL_BIT_MAPPING_CH0(v) (HW_LDB_CTRL_WR((HW_LDB_CTRL_RD() & ~BM_LDB_CTRL_BIT_MAPPING_CH0) | BF_LDB_CTRL_BIT_MAPPING_CH0(v)))
#endif
//@}
/*! @name Register LDB_CTRL, field DATA_WIDTH_CH1[7] (RW)
*
* Data width for LVDS channel 1. This bit must be set when using JEIDA standard (bit_mapping_ch1 is
* set)
*
* Values:
* - 0 - Data width is 18 bits wide (lvds1_tx3 is not used)
* - 1 - Data width is 24 bits wide.
*/
//@{
#define BP_LDB_CTRL_DATA_WIDTH_CH1 (7) //!< Bit position for LDB_CTRL_DATA_WIDTH_CH1.
#define BM_LDB_CTRL_DATA_WIDTH_CH1 (0x00000080) //!< Bit mask for LDB_CTRL_DATA_WIDTH_CH1.
//! @brief Get value of LDB_CTRL_DATA_WIDTH_CH1 from a register value.
#define BG_LDB_CTRL_DATA_WIDTH_CH1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_LDB_CTRL_DATA_WIDTH_CH1) >> BP_LDB_CTRL_DATA_WIDTH_CH1)
//! @brief Format value for bitfield LDB_CTRL_DATA_WIDTH_CH1.
#define BF_LDB_CTRL_DATA_WIDTH_CH1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_LDB_CTRL_DATA_WIDTH_CH1) & BM_LDB_CTRL_DATA_WIDTH_CH1)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DATA_WIDTH_CH1 field to a new value.
#define BW_LDB_CTRL_DATA_WIDTH_CH1(v) (HW_LDB_CTRL_WR((HW_LDB_CTRL_RD() & ~BM_LDB_CTRL_DATA_WIDTH_CH1) | BF_LDB_CTRL_DATA_WIDTH_CH1(v)))
#endif
//@}
/*! @name Register LDB_CTRL, field BIT_MAPPING_CH1[8] (RW)
*
* Data mapping for LVDS channel 1.
*
* Values:
* - 0 - Use SPWG standard.
* - 1 - Use JEIDA standard.
*/
//@{
#define BP_LDB_CTRL_BIT_MAPPING_CH1 (8) //!< Bit position for LDB_CTRL_BIT_MAPPING_CH1.
#define BM_LDB_CTRL_BIT_MAPPING_CH1 (0x00000100) //!< Bit mask for LDB_CTRL_BIT_MAPPING_CH1.
//! @brief Get value of LDB_CTRL_BIT_MAPPING_CH1 from a register value.
#define BG_LDB_CTRL_BIT_MAPPING_CH1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_LDB_CTRL_BIT_MAPPING_CH1) >> BP_LDB_CTRL_BIT_MAPPING_CH1)
//! @brief Format value for bitfield LDB_CTRL_BIT_MAPPING_CH1.
#define BF_LDB_CTRL_BIT_MAPPING_CH1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_LDB_CTRL_BIT_MAPPING_CH1) & BM_LDB_CTRL_BIT_MAPPING_CH1)
#ifndef __LANGUAGE_ASM__
//! @brief Set the BIT_MAPPING_CH1 field to a new value.
#define BW_LDB_CTRL_BIT_MAPPING_CH1(v) (HW_LDB_CTRL_WR((HW_LDB_CTRL_RD() & ~BM_LDB_CTRL_BIT_MAPPING_CH1) | BF_LDB_CTRL_BIT_MAPPING_CH1(v)))
#endif
//@}
/*! @name Register LDB_CTRL, field DI0_VS_POLARITY[9] (RW)
*
* Vsync polarity for IPU's DI0 interface.
*
* Values:
* - 0 - ipu_di0_vsync is active high.
* - 1 - ipu_di0_vsync is active low.
*/
//@{
#define BP_LDB_CTRL_DI0_VS_POLARITY (9) //!< Bit position for LDB_CTRL_DI0_VS_POLARITY.
#define BM_LDB_CTRL_DI0_VS_POLARITY (0x00000200) //!< Bit mask for LDB_CTRL_DI0_VS_POLARITY.
//! @brief Get value of LDB_CTRL_DI0_VS_POLARITY from a register value.
#define BG_LDB_CTRL_DI0_VS_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_LDB_CTRL_DI0_VS_POLARITY) >> BP_LDB_CTRL_DI0_VS_POLARITY)
//! @brief Format value for bitfield LDB_CTRL_DI0_VS_POLARITY.
#define BF_LDB_CTRL_DI0_VS_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_LDB_CTRL_DI0_VS_POLARITY) & BM_LDB_CTRL_DI0_VS_POLARITY)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DI0_VS_POLARITY field to a new value.
#define BW_LDB_CTRL_DI0_VS_POLARITY(v) (HW_LDB_CTRL_WR((HW_LDB_CTRL_RD() & ~BM_LDB_CTRL_DI0_VS_POLARITY) | BF_LDB_CTRL_DI0_VS_POLARITY(v)))
#endif
//@}
/*! @name Register LDB_CTRL, field DI1_VS_POLARITY[10] (RW)
*
* Vsync polarity for IPU's DI1 interface.
*
* Values:
* - 0 - ipu_di1_vsync is active high.
* - 1 - ipu_di1_vsync is active low.
*/
//@{
#define BP_LDB_CTRL_DI1_VS_POLARITY (10) //!< Bit position for LDB_CTRL_DI1_VS_POLARITY.
#define BM_LDB_CTRL_DI1_VS_POLARITY (0x00000400) //!< Bit mask for LDB_CTRL_DI1_VS_POLARITY.
//! @brief Get value of LDB_CTRL_DI1_VS_POLARITY from a register value.
#define BG_LDB_CTRL_DI1_VS_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_LDB_CTRL_DI1_VS_POLARITY) >> BP_LDB_CTRL_DI1_VS_POLARITY)
//! @brief Format value for bitfield LDB_CTRL_DI1_VS_POLARITY.
#define BF_LDB_CTRL_DI1_VS_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_LDB_CTRL_DI1_VS_POLARITY) & BM_LDB_CTRL_DI1_VS_POLARITY)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DI1_VS_POLARITY field to a new value.
#define BW_LDB_CTRL_DI1_VS_POLARITY(v) (HW_LDB_CTRL_WR((HW_LDB_CTRL_RD() & ~BM_LDB_CTRL_DI1_VS_POLARITY) | BF_LDB_CTRL_DI1_VS_POLARITY(v)))
#endif
//@}
/*! @name Register LDB_CTRL, field LVDS_CLK_SHIFT[18:16] (RW)
*
* Shifts the LVDS output clock in relation to the data. Used for debug purposes only. In normal
* functional operation must be '000'
*
* Values:
* - 000 - Output clock is '1100011' (normal operation)
* - 001 - Output clock is '1110001'
* - 010 - Output clock is '1111000'
* - 011 - Output clock is '1000111'
* - 100 - Output clock is '0001111'
* - 101 - Output clock is '0011111'
* - 110 - Output clock is '0111100'
* - 111 - Output clock is '1100011'
*/
//@{
#define BP_LDB_CTRL_LVDS_CLK_SHIFT (16) //!< Bit position for LDB_CTRL_LVDS_CLK_SHIFT.
#define BM_LDB_CTRL_LVDS_CLK_SHIFT (0x00070000) //!< Bit mask for LDB_CTRL_LVDS_CLK_SHIFT.
//! @brief Get value of LDB_CTRL_LVDS_CLK_SHIFT from a register value.
#define BG_LDB_CTRL_LVDS_CLK_SHIFT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_LDB_CTRL_LVDS_CLK_SHIFT) >> BP_LDB_CTRL_LVDS_CLK_SHIFT)
//! @brief Format value for bitfield LDB_CTRL_LVDS_CLK_SHIFT.
#define BF_LDB_CTRL_LVDS_CLK_SHIFT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_LDB_CTRL_LVDS_CLK_SHIFT) & BM_LDB_CTRL_LVDS_CLK_SHIFT)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LVDS_CLK_SHIFT field to a new value.
#define BW_LDB_CTRL_LVDS_CLK_SHIFT(v) (HW_LDB_CTRL_WR((HW_LDB_CTRL_RD() & ~BM_LDB_CTRL_LVDS_CLK_SHIFT) | BF_LDB_CTRL_LVDS_CLK_SHIFT(v)))
#endif
//@}
/*! @name Register LDB_CTRL, field COUNTER_RESET_VAL[21:20] (RW)
*
* Reset value for the LDB counter which determines when the shift registers are loaded with data.
* Used for debug purposes only. In normal functional operation must be '00'
*
* Values:
* - 00 - Reset value is 5
* - 01 - Reset value is 3
* - 10 - Reset value is 4
* - 11 - Reset value is 6
*/
//@{
#define BP_LDB_CTRL_COUNTER_RESET_VAL (20) //!< Bit position for LDB_CTRL_COUNTER_RESET_VAL.
#define BM_LDB_CTRL_COUNTER_RESET_VAL (0x00300000) //!< Bit mask for LDB_CTRL_COUNTER_RESET_VAL.
//! @brief Get value of LDB_CTRL_COUNTER_RESET_VAL from a register value.
#define BG_LDB_CTRL_COUNTER_RESET_VAL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_LDB_CTRL_COUNTER_RESET_VAL) >> BP_LDB_CTRL_COUNTER_RESET_VAL)
//! @brief Format value for bitfield LDB_CTRL_COUNTER_RESET_VAL.
#define BF_LDB_CTRL_COUNTER_RESET_VAL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_LDB_CTRL_COUNTER_RESET_VAL) & BM_LDB_CTRL_COUNTER_RESET_VAL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the COUNTER_RESET_VAL field to a new value.
#define BW_LDB_CTRL_COUNTER_RESET_VAL(v) (HW_LDB_CTRL_WR((HW_LDB_CTRL_RD() & ~BM_LDB_CTRL_COUNTER_RESET_VAL) | BF_LDB_CTRL_COUNTER_RESET_VAL(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_ldb_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All LDB module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_ldb
{
volatile hw_ldb_ctrl_t CTRL; //!< LDB Control Register
} hw_ldb_t;
#pragma pack()
//! @brief Macro to access all LDB registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_LDB</code>.
#define HW_LDB (*(hw_ldb_t *) REGS_LDB_BASE)
#endif
#endif // __HW_LDB_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_PGC_REGISTERS_H__
#define __HW_PGC_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ PGC
*
* PGC
*
* Registers defined in this header file:
* - HW_PGC_GPU_CTRL - PGC Control Register
* - HW_PGC_GPU_PUPSCR - Power Up Sequence Control Register
* - HW_PGC_GPU_PDNSCR - Pull Down Sequence Control Register
* - HW_PGC_GPU_SR - Power Gating Controller Status Register
* - HW_PGC_CPU_CTRL - PGC Control Register
* - HW_PGC_CPU_PUPSCR - Power Up Sequence Control Register
* - HW_PGC_CPU_PDNSCR - Pull Down Sequence Control Register
* - HW_PGC_CPU_SR - Power Gating Controller Status Register
*
* - hw_pgc_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_PGC_BASE
#define HW_PGC_INSTANCE_COUNT (1) //!< Number of instances of the PGC module.
#define REGS_PGC_BASE (0x020dc000) //!< Base address for PGC.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PGC_GPU_CTRL - PGC Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PGC_GPU_CTRL - PGC Control Register (RW)
*
* Reset value: 0x00000000
*
* The PGCR enables the response to a power-down request.
*/
typedef union _hw_pgc_gpu_ctrl
{
reg32_t U;
struct _hw_pgc_gpu_ctrl_bitfields
{
unsigned PCR : 1; //!< [0] Power Control
unsigned RESERVED0 : 31; //!< [31:1] Reserved.
} B;
} hw_pgc_gpu_ctrl_t;
#endif
/*!
* @name Constants and macros for entire PGC_GPU_CTRL register
*/
//@{
#define HW_PGC_GPU_CTRL_ADDR (REGS_PGC_BASE + 0x260)
#ifndef __LANGUAGE_ASM__
#define HW_PGC_GPU_CTRL (*(volatile hw_pgc_gpu_ctrl_t *) HW_PGC_GPU_CTRL_ADDR)
#define HW_PGC_GPU_CTRL_RD() (HW_PGC_GPU_CTRL.U)
#define HW_PGC_GPU_CTRL_WR(v) (HW_PGC_GPU_CTRL.U = (v))
#define HW_PGC_GPU_CTRL_SET(v) (HW_PGC_GPU_CTRL_WR(HW_PGC_GPU_CTRL_RD() | (v)))
#define HW_PGC_GPU_CTRL_CLR(v) (HW_PGC_GPU_CTRL_WR(HW_PGC_GPU_CTRL_RD() & ~(v)))
#define HW_PGC_GPU_CTRL_TOG(v) (HW_PGC_GPU_CTRL_WR(HW_PGC_GPU_CTRL_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual PGC_GPU_CTRL bitfields
*/
/*! @name Register PGC_GPU_CTRL, field PCR[0] (RW)
*
* Power Control PCR must not change from power-down request (pdn_req) assertion until the target
* subsystem is completely powered up.
*
* Values:
* - 0 - Do not switch off power even if pdn_req is asserted.
* - 1 - Switch off power when pdn_req is asserted.
*/
//@{
#define BP_PGC_GPU_CTRL_PCR (0) //!< Bit position for PGC_GPU_CTRL_PCR.
#define BM_PGC_GPU_CTRL_PCR (0x00000001) //!< Bit mask for PGC_GPU_CTRL_PCR.
//! @brief Get value of PGC_GPU_CTRL_PCR from a register value.
#define BG_PGC_GPU_CTRL_PCR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PGC_GPU_CTRL_PCR) >> BP_PGC_GPU_CTRL_PCR)
//! @brief Format value for bitfield PGC_GPU_CTRL_PCR.
#define BF_PGC_GPU_CTRL_PCR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PGC_GPU_CTRL_PCR) & BM_PGC_GPU_CTRL_PCR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PCR field to a new value.
#define BW_PGC_GPU_CTRL_PCR(v) (HW_PGC_GPU_CTRL_WR((HW_PGC_GPU_CTRL_RD() & ~BM_PGC_GPU_CTRL_PCR) | BF_PGC_GPU_CTRL_PCR(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PGC_GPU_PUPSCR - Power Up Sequence Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PGC_GPU_PUPSCR - Power Up Sequence Control Register (RW)
*
* Reset value: 0x00000f01
*
* The PUPSCR contains the power-up timing parameters. See .
*/
typedef union _hw_pgc_gpu_pupscr
{
reg32_t U;
struct _hw_pgc_gpu_pupscr_bitfields
{
unsigned SW : 6; //!< [5:0] After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b.
unsigned RESERVED0 : 2; //!< [7:6] Reserved.
unsigned SW2ISO : 6; //!< [13:8] After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation.
unsigned RESERVED1 : 18; //!< [31:14] Reserved.
} B;
} hw_pgc_gpu_pupscr_t;
#endif
/*!
* @name Constants and macros for entire PGC_GPU_PUPSCR register
*/
//@{
#define HW_PGC_GPU_PUPSCR_ADDR (REGS_PGC_BASE + 0x264)
#ifndef __LANGUAGE_ASM__
#define HW_PGC_GPU_PUPSCR (*(volatile hw_pgc_gpu_pupscr_t *) HW_PGC_GPU_PUPSCR_ADDR)
#define HW_PGC_GPU_PUPSCR_RD() (HW_PGC_GPU_PUPSCR.U)
#define HW_PGC_GPU_PUPSCR_WR(v) (HW_PGC_GPU_PUPSCR.U = (v))
#define HW_PGC_GPU_PUPSCR_SET(v) (HW_PGC_GPU_PUPSCR_WR(HW_PGC_GPU_PUPSCR_RD() | (v)))
#define HW_PGC_GPU_PUPSCR_CLR(v) (HW_PGC_GPU_PUPSCR_WR(HW_PGC_GPU_PUPSCR_RD() & ~(v)))
#define HW_PGC_GPU_PUPSCR_TOG(v) (HW_PGC_GPU_PUPSCR_WR(HW_PGC_GPU_PUPSCR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual PGC_GPU_PUPSCR bitfields
*/
/*! @name Register PGC_GPU_PUPSCR, field SW[5:0] (RW)
*
* After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value
* of SW before asserting switch_b. SW must not be programmed to zero. The PGC clock is generated
* from the IPG_CLK_ROOT. for frequency configuration of the IPG_CLK_ROOT. See .
*/
//@{
#define BP_PGC_GPU_PUPSCR_SW (0) //!< Bit position for PGC_GPU_PUPSCR_SW.
#define BM_PGC_GPU_PUPSCR_SW (0x0000003f) //!< Bit mask for PGC_GPU_PUPSCR_SW.
//! @brief Get value of PGC_GPU_PUPSCR_SW from a register value.
#define BG_PGC_GPU_PUPSCR_SW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PGC_GPU_PUPSCR_SW) >> BP_PGC_GPU_PUPSCR_SW)
//! @brief Format value for bitfield PGC_GPU_PUPSCR_SW.
#define BF_PGC_GPU_PUPSCR_SW(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PGC_GPU_PUPSCR_SW) & BM_PGC_GPU_PUPSCR_SW)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SW field to a new value.
#define BW_PGC_GPU_PUPSCR_SW(v) (HW_PGC_GPU_PUPSCR_WR((HW_PGC_GPU_PUPSCR_RD() & ~BM_PGC_GPU_PUPSCR_SW) | BF_PGC_GPU_PUPSCR_SW(v)))
#endif
//@}
/*! @name Register PGC_GPU_PUPSCR, field SW2ISO[13:8] (RW)
*
* After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before
* negating isolation. SW2ISO must not be programmed to zero.
*/
//@{
#define BP_PGC_GPU_PUPSCR_SW2ISO (8) //!< Bit position for PGC_GPU_PUPSCR_SW2ISO.
#define BM_PGC_GPU_PUPSCR_SW2ISO (0x00003f00) //!< Bit mask for PGC_GPU_PUPSCR_SW2ISO.
//! @brief Get value of PGC_GPU_PUPSCR_SW2ISO from a register value.
#define BG_PGC_GPU_PUPSCR_SW2ISO(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PGC_GPU_PUPSCR_SW2ISO) >> BP_PGC_GPU_PUPSCR_SW2ISO)
//! @brief Format value for bitfield PGC_GPU_PUPSCR_SW2ISO.
#define BF_PGC_GPU_PUPSCR_SW2ISO(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PGC_GPU_PUPSCR_SW2ISO) & BM_PGC_GPU_PUPSCR_SW2ISO)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SW2ISO field to a new value.
#define BW_PGC_GPU_PUPSCR_SW2ISO(v) (HW_PGC_GPU_PUPSCR_WR((HW_PGC_GPU_PUPSCR_RD() & ~BM_PGC_GPU_PUPSCR_SW2ISO) | BF_PGC_GPU_PUPSCR_SW2ISO(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PGC_GPU_PDNSCR - Pull Down Sequence Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PGC_GPU_PDNSCR - Pull Down Sequence Control Register (RW)
*
* Reset value: 0x00000101
*
* The PDNSCR contains the power-down timing parameters. See .
*/
typedef union _hw_pgc_gpu_pdnscr
{
reg32_t U;
struct _hw_pgc_gpu_pdnscr_bitfields
{
unsigned ISO : 6; //!< [5:0] After a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation.
unsigned RESERVED0 : 2; //!< [7:6] Reserved.
unsigned ISO2SW : 6; //!< [13:8] After asserting isolation, the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b.
unsigned RESERVED1 : 18; //!< [31:14] Reserved.
} B;
} hw_pgc_gpu_pdnscr_t;
#endif
/*!
* @name Constants and macros for entire PGC_GPU_PDNSCR register
*/
//@{
#define HW_PGC_GPU_PDNSCR_ADDR (REGS_PGC_BASE + 0x268)
#ifndef __LANGUAGE_ASM__
#define HW_PGC_GPU_PDNSCR (*(volatile hw_pgc_gpu_pdnscr_t *) HW_PGC_GPU_PDNSCR_ADDR)
#define HW_PGC_GPU_PDNSCR_RD() (HW_PGC_GPU_PDNSCR.U)
#define HW_PGC_GPU_PDNSCR_WR(v) (HW_PGC_GPU_PDNSCR.U = (v))
#define HW_PGC_GPU_PDNSCR_SET(v) (HW_PGC_GPU_PDNSCR_WR(HW_PGC_GPU_PDNSCR_RD() | (v)))
#define HW_PGC_GPU_PDNSCR_CLR(v) (HW_PGC_GPU_PDNSCR_WR(HW_PGC_GPU_PDNSCR_RD() & ~(v)))
#define HW_PGC_GPU_PDNSCR_TOG(v) (HW_PGC_GPU_PDNSCR_WR(HW_PGC_GPU_PDNSCR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual PGC_GPU_PDNSCR bitfields
*/
/*! @name Register PGC_GPU_PDNSCR, field ISO[5:0] (RW)
*
* After a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the
* value of ISO before asserting isolation. ISO must not be programmed to zero.
*/
//@{
#define BP_PGC_GPU_PDNSCR_ISO (0) //!< Bit position for PGC_GPU_PDNSCR_ISO.
#define BM_PGC_GPU_PDNSCR_ISO (0x0000003f) //!< Bit mask for PGC_GPU_PDNSCR_ISO.
//! @brief Get value of PGC_GPU_PDNSCR_ISO from a register value.
#define BG_PGC_GPU_PDNSCR_ISO(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PGC_GPU_PDNSCR_ISO) >> BP_PGC_GPU_PDNSCR_ISO)
//! @brief Format value for bitfield PGC_GPU_PDNSCR_ISO.
#define BF_PGC_GPU_PDNSCR_ISO(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PGC_GPU_PDNSCR_ISO) & BM_PGC_GPU_PDNSCR_ISO)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ISO field to a new value.
#define BW_PGC_GPU_PDNSCR_ISO(v) (HW_PGC_GPU_PDNSCR_WR((HW_PGC_GPU_PDNSCR_RD() & ~BM_PGC_GPU_PDNSCR_ISO) | BF_PGC_GPU_PDNSCR_ISO(v)))
#endif
//@}
/*! @name Register PGC_GPU_PDNSCR, field ISO2SW[13:8] (RW)
*
* After asserting isolation, the PGC waits a number of clocks equal to the value of ISO2SW before
* negating switch_b. ISO2SW must not be programmed to zero.
*/
//@{
#define BP_PGC_GPU_PDNSCR_ISO2SW (8) //!< Bit position for PGC_GPU_PDNSCR_ISO2SW.
#define BM_PGC_GPU_PDNSCR_ISO2SW (0x00003f00) //!< Bit mask for PGC_GPU_PDNSCR_ISO2SW.
//! @brief Get value of PGC_GPU_PDNSCR_ISO2SW from a register value.
#define BG_PGC_GPU_PDNSCR_ISO2SW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PGC_GPU_PDNSCR_ISO2SW) >> BP_PGC_GPU_PDNSCR_ISO2SW)
//! @brief Format value for bitfield PGC_GPU_PDNSCR_ISO2SW.
#define BF_PGC_GPU_PDNSCR_ISO2SW(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PGC_GPU_PDNSCR_ISO2SW) & BM_PGC_GPU_PDNSCR_ISO2SW)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ISO2SW field to a new value.
#define BW_PGC_GPU_PDNSCR_ISO2SW(v) (HW_PGC_GPU_PDNSCR_WR((HW_PGC_GPU_PDNSCR_RD() & ~BM_PGC_GPU_PDNSCR_ISO2SW) | BF_PGC_GPU_PDNSCR_ISO2SW(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PGC_GPU_SR - Power Gating Controller Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PGC_GPU_SR - Power Gating Controller Status Register (RW)
*
* Reset value: 0x00000000
*
* The PDNSCR contains the power-down timing parameters. See .
*/
typedef union _hw_pgc_gpu_sr
{
reg32_t U;
struct _hw_pgc_gpu_sr_bitfields
{
unsigned PSR : 1; //!< [0] Power status.
unsigned RESERVED0 : 31; //!< [31:1] Reserved.
} B;
} hw_pgc_gpu_sr_t;
#endif
/*!
* @name Constants and macros for entire PGC_GPU_SR register
*/
//@{
#define HW_PGC_GPU_SR_ADDR (REGS_PGC_BASE + 0x26c)
#ifndef __LANGUAGE_ASM__
#define HW_PGC_GPU_SR (*(volatile hw_pgc_gpu_sr_t *) HW_PGC_GPU_SR_ADDR)
#define HW_PGC_GPU_SR_RD() (HW_PGC_GPU_SR.U)
#define HW_PGC_GPU_SR_WR(v) (HW_PGC_GPU_SR.U = (v))
#define HW_PGC_GPU_SR_SET(v) (HW_PGC_GPU_SR_WR(HW_PGC_GPU_SR_RD() | (v)))
#define HW_PGC_GPU_SR_CLR(v) (HW_PGC_GPU_SR_WR(HW_PGC_GPU_SR_RD() & ~(v)))
#define HW_PGC_GPU_SR_TOG(v) (HW_PGC_GPU_SR_WR(HW_PGC_GPU_SR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual PGC_GPU_SR bitfields
*/
/*! @name Register PGC_GPU_SR, field PSR[0] (RW)
*
* Power status. When in functional (or software-controlled debug) mode, PGC hardware sets PSR as
* soon as any of the power control output changes its state to one. Write one to clear this bit.
* Software should clear this bit after power up; otherwise, PSR continues to reflect the power
* status of the initial power down.
*
* Values:
* - 0 - The target subsystem was not powered down for the previous power-down request.
* - 1 - The target subsystem was powered down for the previous power-down request.
*/
//@{
#define BP_PGC_GPU_SR_PSR (0) //!< Bit position for PGC_GPU_SR_PSR.
#define BM_PGC_GPU_SR_PSR (0x00000001) //!< Bit mask for PGC_GPU_SR_PSR.
//! @brief Get value of PGC_GPU_SR_PSR from a register value.
#define BG_PGC_GPU_SR_PSR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PGC_GPU_SR_PSR) >> BP_PGC_GPU_SR_PSR)
//! @brief Format value for bitfield PGC_GPU_SR_PSR.
#define BF_PGC_GPU_SR_PSR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PGC_GPU_SR_PSR) & BM_PGC_GPU_SR_PSR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PSR field to a new value.
#define BW_PGC_GPU_SR_PSR(v) (HW_PGC_GPU_SR_WR((HW_PGC_GPU_SR_RD() & ~BM_PGC_GPU_SR_PSR) | BF_PGC_GPU_SR_PSR(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PGC_CPU_CTRL - PGC Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PGC_CPU_CTRL - PGC Control Register (RW)
*
* Reset value: 0x00000000
*
* The PGCR enables the response to a power-down request.
*/
typedef union _hw_pgc_cpu_ctrl
{
reg32_t U;
struct _hw_pgc_cpu_ctrl_bitfields
{
unsigned PCR : 1; //!< [0] Power Control
unsigned RESERVED0 : 31; //!< [31:1] Reserved.
} B;
} hw_pgc_cpu_ctrl_t;
#endif
/*!
* @name Constants and macros for entire PGC_CPU_CTRL register
*/
//@{
#define HW_PGC_CPU_CTRL_ADDR (REGS_PGC_BASE + 0x2a0)
#ifndef __LANGUAGE_ASM__
#define HW_PGC_CPU_CTRL (*(volatile hw_pgc_cpu_ctrl_t *) HW_PGC_CPU_CTRL_ADDR)
#define HW_PGC_CPU_CTRL_RD() (HW_PGC_CPU_CTRL.U)
#define HW_PGC_CPU_CTRL_WR(v) (HW_PGC_CPU_CTRL.U = (v))
#define HW_PGC_CPU_CTRL_SET(v) (HW_PGC_CPU_CTRL_WR(HW_PGC_CPU_CTRL_RD() | (v)))
#define HW_PGC_CPU_CTRL_CLR(v) (HW_PGC_CPU_CTRL_WR(HW_PGC_CPU_CTRL_RD() & ~(v)))
#define HW_PGC_CPU_CTRL_TOG(v) (HW_PGC_CPU_CTRL_WR(HW_PGC_CPU_CTRL_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual PGC_CPU_CTRL bitfields
*/
/*! @name Register PGC_CPU_CTRL, field PCR[0] (RW)
*
* Power Control PCR must not change from power-down request (pdn_req) assertion until the target
* subsystem is completely powered up.
*
* Values:
* - 0 - Do not switch off power even if pdn_req is asserted.
* - 1 - Switch off power when pdn_req is asserted.
*/
//@{
#define BP_PGC_CPU_CTRL_PCR (0) //!< Bit position for PGC_CPU_CTRL_PCR.
#define BM_PGC_CPU_CTRL_PCR (0x00000001) //!< Bit mask for PGC_CPU_CTRL_PCR.
//! @brief Get value of PGC_CPU_CTRL_PCR from a register value.
#define BG_PGC_CPU_CTRL_PCR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PGC_CPU_CTRL_PCR) >> BP_PGC_CPU_CTRL_PCR)
//! @brief Format value for bitfield PGC_CPU_CTRL_PCR.
#define BF_PGC_CPU_CTRL_PCR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PGC_CPU_CTRL_PCR) & BM_PGC_CPU_CTRL_PCR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PCR field to a new value.
#define BW_PGC_CPU_CTRL_PCR(v) (HW_PGC_CPU_CTRL_WR((HW_PGC_CPU_CTRL_RD() & ~BM_PGC_CPU_CTRL_PCR) | BF_PGC_CPU_CTRL_PCR(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PGC_CPU_PUPSCR - Power Up Sequence Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PGC_CPU_PUPSCR - Power Up Sequence Control Register (RW)
*
* Reset value: 0x00000f01
*
* The PUPSCR contains the power-up timing parameters. See .
*/
typedef union _hw_pgc_cpu_pupscr
{
reg32_t U;
struct _hw_pgc_cpu_pupscr_bitfields
{
unsigned SW : 6; //!< [5:0] After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b.
unsigned RESERVED0 : 2; //!< [7:6] Reserved.
unsigned SW2ISO : 6; //!< [13:8] After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation.
unsigned RESERVED1 : 18; //!< [31:14] Reserved.
} B;
} hw_pgc_cpu_pupscr_t;
#endif
/*!
* @name Constants and macros for entire PGC_CPU_PUPSCR register
*/
//@{
#define HW_PGC_CPU_PUPSCR_ADDR (REGS_PGC_BASE + 0x2a4)
#ifndef __LANGUAGE_ASM__
#define HW_PGC_CPU_PUPSCR (*(volatile hw_pgc_cpu_pupscr_t *) HW_PGC_CPU_PUPSCR_ADDR)
#define HW_PGC_CPU_PUPSCR_RD() (HW_PGC_CPU_PUPSCR.U)
#define HW_PGC_CPU_PUPSCR_WR(v) (HW_PGC_CPU_PUPSCR.U = (v))
#define HW_PGC_CPU_PUPSCR_SET(v) (HW_PGC_CPU_PUPSCR_WR(HW_PGC_CPU_PUPSCR_RD() | (v)))
#define HW_PGC_CPU_PUPSCR_CLR(v) (HW_PGC_CPU_PUPSCR_WR(HW_PGC_CPU_PUPSCR_RD() & ~(v)))
#define HW_PGC_CPU_PUPSCR_TOG(v) (HW_PGC_CPU_PUPSCR_WR(HW_PGC_CPU_PUPSCR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual PGC_CPU_PUPSCR bitfields
*/
/*! @name Register PGC_CPU_PUPSCR, field SW[5:0] (RW)
*
* After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value
* of SW before asserting switch_b. SW must not be programmed to zero. The PGC clock is generated
* from the IPG_CLK_ROOT. for frequency configuration of the IPG_CLK_ROOT. See .
*/
//@{
#define BP_PGC_CPU_PUPSCR_SW (0) //!< Bit position for PGC_CPU_PUPSCR_SW.
#define BM_PGC_CPU_PUPSCR_SW (0x0000003f) //!< Bit mask for PGC_CPU_PUPSCR_SW.
//! @brief Get value of PGC_CPU_PUPSCR_SW from a register value.
#define BG_PGC_CPU_PUPSCR_SW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PGC_CPU_PUPSCR_SW) >> BP_PGC_CPU_PUPSCR_SW)
//! @brief Format value for bitfield PGC_CPU_PUPSCR_SW.
#define BF_PGC_CPU_PUPSCR_SW(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PGC_CPU_PUPSCR_SW) & BM_PGC_CPU_PUPSCR_SW)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SW field to a new value.
#define BW_PGC_CPU_PUPSCR_SW(v) (HW_PGC_CPU_PUPSCR_WR((HW_PGC_CPU_PUPSCR_RD() & ~BM_PGC_CPU_PUPSCR_SW) | BF_PGC_CPU_PUPSCR_SW(v)))
#endif
//@}
/*! @name Register PGC_CPU_PUPSCR, field SW2ISO[13:8] (RW)
*
* After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before
* negating isolation. SW2ISO must not be programmed to zero.
*/
//@{
#define BP_PGC_CPU_PUPSCR_SW2ISO (8) //!< Bit position for PGC_CPU_PUPSCR_SW2ISO.
#define BM_PGC_CPU_PUPSCR_SW2ISO (0x00003f00) //!< Bit mask for PGC_CPU_PUPSCR_SW2ISO.
//! @brief Get value of PGC_CPU_PUPSCR_SW2ISO from a register value.
#define BG_PGC_CPU_PUPSCR_SW2ISO(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PGC_CPU_PUPSCR_SW2ISO) >> BP_PGC_CPU_PUPSCR_SW2ISO)
//! @brief Format value for bitfield PGC_CPU_PUPSCR_SW2ISO.
#define BF_PGC_CPU_PUPSCR_SW2ISO(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PGC_CPU_PUPSCR_SW2ISO) & BM_PGC_CPU_PUPSCR_SW2ISO)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SW2ISO field to a new value.
#define BW_PGC_CPU_PUPSCR_SW2ISO(v) (HW_PGC_CPU_PUPSCR_WR((HW_PGC_CPU_PUPSCR_RD() & ~BM_PGC_CPU_PUPSCR_SW2ISO) | BF_PGC_CPU_PUPSCR_SW2ISO(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PGC_CPU_PDNSCR - Pull Down Sequence Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PGC_CPU_PDNSCR - Pull Down Sequence Control Register (RW)
*
* Reset value: 0x00000101
*
* The PDNSCR contains the power-down timing parameters. See .
*/
typedef union _hw_pgc_cpu_pdnscr
{
reg32_t U;
struct _hw_pgc_cpu_pdnscr_bitfields
{
unsigned ISO : 6; //!< [5:0] After a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation.
unsigned RESERVED0 : 2; //!< [7:6] Reserved.
unsigned ISO2SW : 6; //!< [13:8] After asserting isolation, the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b.
unsigned RESERVED1 : 18; //!< [31:14] Reserved.
} B;
} hw_pgc_cpu_pdnscr_t;
#endif
/*!
* @name Constants and macros for entire PGC_CPU_PDNSCR register
*/
//@{
#define HW_PGC_CPU_PDNSCR_ADDR (REGS_PGC_BASE + 0x2a8)
#ifndef __LANGUAGE_ASM__
#define HW_PGC_CPU_PDNSCR (*(volatile hw_pgc_cpu_pdnscr_t *) HW_PGC_CPU_PDNSCR_ADDR)
#define HW_PGC_CPU_PDNSCR_RD() (HW_PGC_CPU_PDNSCR.U)
#define HW_PGC_CPU_PDNSCR_WR(v) (HW_PGC_CPU_PDNSCR.U = (v))
#define HW_PGC_CPU_PDNSCR_SET(v) (HW_PGC_CPU_PDNSCR_WR(HW_PGC_CPU_PDNSCR_RD() | (v)))
#define HW_PGC_CPU_PDNSCR_CLR(v) (HW_PGC_CPU_PDNSCR_WR(HW_PGC_CPU_PDNSCR_RD() & ~(v)))
#define HW_PGC_CPU_PDNSCR_TOG(v) (HW_PGC_CPU_PDNSCR_WR(HW_PGC_CPU_PDNSCR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual PGC_CPU_PDNSCR bitfields
*/
/*! @name Register PGC_CPU_PDNSCR, field ISO[5:0] (RW)
*
* After a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the
* value of ISO before asserting isolation. ISO must not be programmed to zero.
*/
//@{
#define BP_PGC_CPU_PDNSCR_ISO (0) //!< Bit position for PGC_CPU_PDNSCR_ISO.
#define BM_PGC_CPU_PDNSCR_ISO (0x0000003f) //!< Bit mask for PGC_CPU_PDNSCR_ISO.
//! @brief Get value of PGC_CPU_PDNSCR_ISO from a register value.
#define BG_PGC_CPU_PDNSCR_ISO(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PGC_CPU_PDNSCR_ISO) >> BP_PGC_CPU_PDNSCR_ISO)
//! @brief Format value for bitfield PGC_CPU_PDNSCR_ISO.
#define BF_PGC_CPU_PDNSCR_ISO(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PGC_CPU_PDNSCR_ISO) & BM_PGC_CPU_PDNSCR_ISO)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ISO field to a new value.
#define BW_PGC_CPU_PDNSCR_ISO(v) (HW_PGC_CPU_PDNSCR_WR((HW_PGC_CPU_PDNSCR_RD() & ~BM_PGC_CPU_PDNSCR_ISO) | BF_PGC_CPU_PDNSCR_ISO(v)))
#endif
//@}
/*! @name Register PGC_CPU_PDNSCR, field ISO2SW[13:8] (RW)
*
* After asserting isolation, the PGC waits a number of clocks equal to the value of ISO2SW before
* negating switch_b. ISO2SW must not be programmed to zero.
*/
//@{
#define BP_PGC_CPU_PDNSCR_ISO2SW (8) //!< Bit position for PGC_CPU_PDNSCR_ISO2SW.
#define BM_PGC_CPU_PDNSCR_ISO2SW (0x00003f00) //!< Bit mask for PGC_CPU_PDNSCR_ISO2SW.
//! @brief Get value of PGC_CPU_PDNSCR_ISO2SW from a register value.
#define BG_PGC_CPU_PDNSCR_ISO2SW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PGC_CPU_PDNSCR_ISO2SW) >> BP_PGC_CPU_PDNSCR_ISO2SW)
//! @brief Format value for bitfield PGC_CPU_PDNSCR_ISO2SW.
#define BF_PGC_CPU_PDNSCR_ISO2SW(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PGC_CPU_PDNSCR_ISO2SW) & BM_PGC_CPU_PDNSCR_ISO2SW)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ISO2SW field to a new value.
#define BW_PGC_CPU_PDNSCR_ISO2SW(v) (HW_PGC_CPU_PDNSCR_WR((HW_PGC_CPU_PDNSCR_RD() & ~BM_PGC_CPU_PDNSCR_ISO2SW) | BF_PGC_CPU_PDNSCR_ISO2SW(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PGC_CPU_SR - Power Gating Controller Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PGC_CPU_SR - Power Gating Controller Status Register (RW)
*
* Reset value: 0x00000000
*
* The PDNSCR contains the power-down timing parameters. See .
*/
typedef union _hw_pgc_cpu_sr
{
reg32_t U;
struct _hw_pgc_cpu_sr_bitfields
{
unsigned PSR : 1; //!< [0] Power status.
unsigned RESERVED0 : 31; //!< [31:1] Reserved.
} B;
} hw_pgc_cpu_sr_t;
#endif
/*!
* @name Constants and macros for entire PGC_CPU_SR register
*/
//@{
#define HW_PGC_CPU_SR_ADDR (REGS_PGC_BASE + 0x2ac)
#ifndef __LANGUAGE_ASM__
#define HW_PGC_CPU_SR (*(volatile hw_pgc_cpu_sr_t *) HW_PGC_CPU_SR_ADDR)
#define HW_PGC_CPU_SR_RD() (HW_PGC_CPU_SR.U)
#define HW_PGC_CPU_SR_WR(v) (HW_PGC_CPU_SR.U = (v))
#define HW_PGC_CPU_SR_SET(v) (HW_PGC_CPU_SR_WR(HW_PGC_CPU_SR_RD() | (v)))
#define HW_PGC_CPU_SR_CLR(v) (HW_PGC_CPU_SR_WR(HW_PGC_CPU_SR_RD() & ~(v)))
#define HW_PGC_CPU_SR_TOG(v) (HW_PGC_CPU_SR_WR(HW_PGC_CPU_SR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual PGC_CPU_SR bitfields
*/
/*! @name Register PGC_CPU_SR, field PSR[0] (RW)
*
* Power status. When in functional (or software-controlled debug) mode, PGC hardware sets PSR as
* soon as any of the power control output changes its state to one. Write one to clear this bit.
* Software should clear this bit after power up; otherwise, PSR continues to reflect the power
* status of the initial power down.
*
* Values:
* - 0 - The target subsystem was not powered down for the previous power-down request.
* - 1 - The target subsystem was powered down for the previous power-down request.
*/
//@{
#define BP_PGC_CPU_SR_PSR (0) //!< Bit position for PGC_CPU_SR_PSR.
#define BM_PGC_CPU_SR_PSR (0x00000001) //!< Bit mask for PGC_CPU_SR_PSR.
//! @brief Get value of PGC_CPU_SR_PSR from a register value.
#define BG_PGC_CPU_SR_PSR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PGC_CPU_SR_PSR) >> BP_PGC_CPU_SR_PSR)
//! @brief Format value for bitfield PGC_CPU_SR_PSR.
#define BF_PGC_CPU_SR_PSR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PGC_CPU_SR_PSR) & BM_PGC_CPU_SR_PSR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PSR field to a new value.
#define BW_PGC_CPU_SR_PSR(v) (HW_PGC_CPU_SR_WR((HW_PGC_CPU_SR_RD() & ~BM_PGC_CPU_SR_PSR) | BF_PGC_CPU_SR_PSR(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_pgc_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All PGC module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_pgc
{
reg32_t _reserved0[152];
volatile hw_pgc_gpu_ctrl_t GPU_CTRL; //!< PGC Control Register
volatile hw_pgc_gpu_pupscr_t GPU_PUPSCR; //!< Power Up Sequence Control Register
volatile hw_pgc_gpu_pdnscr_t GPU_PDNSCR; //!< Pull Down Sequence Control Register
volatile hw_pgc_gpu_sr_t GPU_SR; //!< Power Gating Controller Status Register
reg32_t _reserved1[12];
volatile hw_pgc_cpu_ctrl_t CPU_CTRL; //!< PGC Control Register
volatile hw_pgc_cpu_pupscr_t CPU_PUPSCR; //!< Power Up Sequence Control Register
volatile hw_pgc_cpu_pdnscr_t CPU_PDNSCR; //!< Pull Down Sequence Control Register
volatile hw_pgc_cpu_sr_t CPU_SR; //!< Power Gating Controller Status Register
} hw_pgc_t;
#pragma pack()
//! @brief Macro to access all PGC registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_PGC</code>.
#define HW_PGC (*(hw_pgc_t *) REGS_PGC_BASE)
#endif
#endif // __HW_PGC_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_PWM_REGISTERS_H__
#define __HW_PWM_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ PWM
*
* PWM
*
* Registers defined in this header file:
* - HW_PWM_PWMCR - PWM Control Register
* - HW_PWM_PWMSR - PWM Status Register
* - HW_PWM_PWMIR - PWM Interrupt Register
* - HW_PWM_PWMSAR - PWM Sample Register
* - HW_PWM_PWMPR - PWM Period Register
* - HW_PWM_PWMCNR - PWM Counter Register
*
* - hw_pwm_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_PWM_BASE
#define HW_PWM_INSTANCE_COUNT (4) //!< Number of instances of the PWM module.
#define HW_PWM1 (1) //!< Instance number for PWM1.
#define HW_PWM2 (2) //!< Instance number for PWM2.
#define HW_PWM3 (3) //!< Instance number for PWM3.
#define HW_PWM4 (4) //!< Instance number for PWM4.
#define REGS_PWM1_BASE (0x02080000) //!< Base address for PWM instance number 1.
#define REGS_PWM2_BASE (0x02084000) //!< Base address for PWM instance number 2.
#define REGS_PWM3_BASE (0x02088000) //!< Base address for PWM instance number 3.
#define REGS_PWM4_BASE (0x0208c000) //!< Base address for PWM instance number 4.
//! @brief Get the base address of PWM by instance number.
//! @param x PWM instance number, from 1 through 4.
#define REGS_PWM_BASE(x) ( (x) == HW_PWM1 ? REGS_PWM1_BASE : (x) == HW_PWM2 ? REGS_PWM2_BASE : (x) == HW_PWM3 ? REGS_PWM3_BASE : (x) == HW_PWM4 ? REGS_PWM4_BASE : 0x00d00000)
//! @brief Get the instance number given a base address.
//! @param b Base address for an instance of PWM.
#define REGS_PWM_INSTANCE(b) ( (b) == REGS_PWM1_BASE ? HW_PWM1 : (b) == REGS_PWM2_BASE ? HW_PWM2 : (b) == REGS_PWM3_BASE ? HW_PWM3 : (b) == REGS_PWM4_BASE ? HW_PWM4 : 0)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PWM_PWMCR - PWM Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PWM_PWMCR - PWM Control Register (RW)
*
* Reset value: 0x00000000
*
* The PWM control register (PWM_PWMCR) is used to configure the operating settings of the PWM. It
* contains the prescaler for the clock division.
*/
typedef union _hw_pwm_pwmcr
{
reg32_t U;
struct _hw_pwm_pwmcr_bitfields
{
unsigned EN : 1; //!< [0] PWM Enable.
unsigned REPEAT : 2; //!< [2:1] Sample Repeat.
unsigned SWR : 1; //!< [3] Software Reset.
unsigned PRESCALER : 12; //!< [15:4] Counter Clock Prescaler Value.
unsigned CLKSRC : 2; //!< [17:16] Select Clock Source.
unsigned POUTC : 2; //!< [19:18] PWM Output Configuration.
unsigned HCTR : 1; //!< [20] Half-word Data Swap Control.
unsigned BCTR : 1; //!< [21] Byte Data Swap Control.
unsigned DBGEN : 1; //!< [22] Debug Mode Enable.
unsigned WAITEN : 1; //!< [23] Wait Mode Enable.
unsigned DOZEN : 1; //!< [24] Doze Mode Enable.
unsigned STOPEN : 1; //!< [25] Stop Mode Enable.
unsigned FWM : 2; //!< [27:26] FIFO Water Mark.
unsigned RESERVED0 : 4; //!< [31:28] Reserved.
} B;
} hw_pwm_pwmcr_t;
#endif
/*!
* @name Constants and macros for entire PWM_PWMCR register
*/
//@{
#define HW_PWM_PWMCR_ADDR(x) (REGS_PWM_BASE(x) + 0x0)
#ifndef __LANGUAGE_ASM__
#define HW_PWM_PWMCR(x) (*(volatile hw_pwm_pwmcr_t *) HW_PWM_PWMCR_ADDR(x))
#define HW_PWM_PWMCR_RD(x) (HW_PWM_PWMCR(x).U)
#define HW_PWM_PWMCR_WR(x, v) (HW_PWM_PWMCR(x).U = (v))
#define HW_PWM_PWMCR_SET(x, v) (HW_PWM_PWMCR_WR(x, HW_PWM_PWMCR_RD(x) | (v)))
#define HW_PWM_PWMCR_CLR(x, v) (HW_PWM_PWMCR_WR(x, HW_PWM_PWMCR_RD(x) & ~(v)))
#define HW_PWM_PWMCR_TOG(x, v) (HW_PWM_PWMCR_WR(x, HW_PWM_PWMCR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual PWM_PWMCR bitfields
*/
/*! @name Register PWM_PWMCR, field EN[0] (RW)
*
* PWM Enable. This bit enables the PWM. If this bit is not enabled, the clock prescaler and the
* counter is reset. When the PWM is enabled, it begins a new period, the output pin is set to start
* a new period while the prescaler and counter are released and counting begins. To make the PWM
* work with softreset and disable/enable, users can do software reset by seting the SWR bit, wait
* software reset done, configure the registers, and then enable the PWM by setting this bit to "1"
* Users can also disable/enable the PWM if PWM would like to be stopped and resumed with same
* registers configurations .
*
* Values:
* - 0 - PWM disabled
* - 1 - PWM enabled
*/
//@{
#define BP_PWM_PWMCR_EN (0) //!< Bit position for PWM_PWMCR_EN.
#define BM_PWM_PWMCR_EN (0x00000001) //!< Bit mask for PWM_PWMCR_EN.
//! @brief Get value of PWM_PWMCR_EN from a register value.
#define BG_PWM_PWMCR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCR_EN) >> BP_PWM_PWMCR_EN)
//! @brief Format value for bitfield PWM_PWMCR_EN.
#define BF_PWM_PWMCR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMCR_EN) & BM_PWM_PWMCR_EN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the EN field to a new value.
#define BW_PWM_PWMCR_EN(x, v) (HW_PWM_PWMCR_WR(x, (HW_PWM_PWMCR_RD(x) & ~BM_PWM_PWMCR_EN) | BF_PWM_PWMCR_EN(v)))
#endif
//@}
/*! @name Register PWM_PWMCR, field REPEAT[2:1] (RW)
*
* Sample Repeat. This bit field determines the number of times each sample from the FIFO is to be
* used.
*
* Values:
* - 00 - Use each sample once
* - 01 - Use each sample twice
* - 10 - Use each sample four times
* - 11 - Use each sample eight times
*/
//@{
#define BP_PWM_PWMCR_REPEAT (1) //!< Bit position for PWM_PWMCR_REPEAT.
#define BM_PWM_PWMCR_REPEAT (0x00000006) //!< Bit mask for PWM_PWMCR_REPEAT.
//! @brief Get value of PWM_PWMCR_REPEAT from a register value.
#define BG_PWM_PWMCR_REPEAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCR_REPEAT) >> BP_PWM_PWMCR_REPEAT)
//! @brief Format value for bitfield PWM_PWMCR_REPEAT.
#define BF_PWM_PWMCR_REPEAT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMCR_REPEAT) & BM_PWM_PWMCR_REPEAT)
#ifndef __LANGUAGE_ASM__
//! @brief Set the REPEAT field to a new value.
#define BW_PWM_PWMCR_REPEAT(x, v) (HW_PWM_PWMCR_WR(x, (HW_PWM_PWMCR_RD(x) & ~BM_PWM_PWMCR_REPEAT) | BF_PWM_PWMCR_REPEAT(v)))
#endif
//@}
/*! @name Register PWM_PWMCR, field SWR[3] (RW)
*
* Software Reset. PWM is reset when this bit is set to 1. It is a self clearing bit. A write 1 to
* this bit is a single wait state write cycle. When the block is in reset state this bit is set and
* is cleared when the reset procedure is over. Setting this bit resets all the registers to their
* reset values except for the STOPEN, DOZEN, WAITEN, and DBGEN bits in this control register .
*
* Values:
* - 0 - PWM is out of reset
* - 1 - PWM is undergoing reset
*/
//@{
#define BP_PWM_PWMCR_SWR (3) //!< Bit position for PWM_PWMCR_SWR.
#define BM_PWM_PWMCR_SWR (0x00000008) //!< Bit mask for PWM_PWMCR_SWR.
//! @brief Get value of PWM_PWMCR_SWR from a register value.
#define BG_PWM_PWMCR_SWR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCR_SWR) >> BP_PWM_PWMCR_SWR)
//! @brief Format value for bitfield PWM_PWMCR_SWR.
#define BF_PWM_PWMCR_SWR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMCR_SWR) & BM_PWM_PWMCR_SWR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SWR field to a new value.
#define BW_PWM_PWMCR_SWR(x, v) (HW_PWM_PWMCR_WR(x, (HW_PWM_PWMCR_RD(x) & ~BM_PWM_PWMCR_SWR) | BF_PWM_PWMCR_SWR(v)))
#endif
//@}
/*! @name Register PWM_PWMCR, field PRESCALER[15:4] (RW)
*
* Counter Clock Prescaler Value. This bit field determines the value by which the clock will be
* divided before it goes to the counter.
*
* Values:
* - 0x000 - Divide by 1
* - 0x001 - Divide by 2
* - 0xfff - Divide by 4096
*/
//@{
#define BP_PWM_PWMCR_PRESCALER (4) //!< Bit position for PWM_PWMCR_PRESCALER.
#define BM_PWM_PWMCR_PRESCALER (0x0000fff0) //!< Bit mask for PWM_PWMCR_PRESCALER.
//! @brief Get value of PWM_PWMCR_PRESCALER from a register value.
#define BG_PWM_PWMCR_PRESCALER(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCR_PRESCALER) >> BP_PWM_PWMCR_PRESCALER)
//! @brief Format value for bitfield PWM_PWMCR_PRESCALER.
#define BF_PWM_PWMCR_PRESCALER(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMCR_PRESCALER) & BM_PWM_PWMCR_PRESCALER)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PRESCALER field to a new value.
#define BW_PWM_PWMCR_PRESCALER(x, v) (HW_PWM_PWMCR_WR(x, (HW_PWM_PWMCR_RD(x) & ~BM_PWM_PWMCR_PRESCALER) | BF_PWM_PWMCR_PRESCALER(v)))
#endif
//@}
/*! @name Register PWM_PWMCR, field CLKSRC[17:16] (RW)
*
* Select Clock Source. These bits determine which clock input will be selected for running the
* counter. After reset the system functional clock is selected. The input clock can also be turned
* off if these bits are set to 00. This field value should only be changed when the PWM is disabled
*
* Values:
* - 00 - Clock is off
* - 01 - ipg_clk
* - 10 - ipg_clk_highfreq
* - 11 - ipg_clk_32k
*/
//@{
#define BP_PWM_PWMCR_CLKSRC (16) //!< Bit position for PWM_PWMCR_CLKSRC.
#define BM_PWM_PWMCR_CLKSRC (0x00030000) //!< Bit mask for PWM_PWMCR_CLKSRC.
//! @brief Get value of PWM_PWMCR_CLKSRC from a register value.
#define BG_PWM_PWMCR_CLKSRC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCR_CLKSRC) >> BP_PWM_PWMCR_CLKSRC)
//! @brief Format value for bitfield PWM_PWMCR_CLKSRC.
#define BF_PWM_PWMCR_CLKSRC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMCR_CLKSRC) & BM_PWM_PWMCR_CLKSRC)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CLKSRC field to a new value.
#define BW_PWM_PWMCR_CLKSRC(x, v) (HW_PWM_PWMCR_WR(x, (HW_PWM_PWMCR_RD(x) & ~BM_PWM_PWMCR_CLKSRC) | BF_PWM_PWMCR_CLKSRC(v)))
#endif
//@}
/*! @name Register PWM_PWMCR, field POUTC[19:18] (RW)
*
* PWM Output Configuration. This bit field determines the mode of PWM output on the output pin.
*
* Values:
* - 00 - Output pin is set at rollover and cleared at comparison
* - 01 - Output pin is cleared at rollover and set at comparison
* - 10 - PWM output is disconnected
* - 11 - PWM output is disconnected
*/
//@{
#define BP_PWM_PWMCR_POUTC (18) //!< Bit position for PWM_PWMCR_POUTC.
#define BM_PWM_PWMCR_POUTC (0x000c0000) //!< Bit mask for PWM_PWMCR_POUTC.
//! @brief Get value of PWM_PWMCR_POUTC from a register value.
#define BG_PWM_PWMCR_POUTC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCR_POUTC) >> BP_PWM_PWMCR_POUTC)
//! @brief Format value for bitfield PWM_PWMCR_POUTC.
#define BF_PWM_PWMCR_POUTC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMCR_POUTC) & BM_PWM_PWMCR_POUTC)
#ifndef __LANGUAGE_ASM__
//! @brief Set the POUTC field to a new value.
#define BW_PWM_PWMCR_POUTC(x, v) (HW_PWM_PWMCR_WR(x, (HW_PWM_PWMCR_RD(x) & ~BM_PWM_PWMCR_POUTC) | BF_PWM_PWMCR_POUTC(v)))
#endif
//@}
/*! @name Register PWM_PWMCR, field HCTR[20] (RW)
*
* Half-word Data Swap Control. This bit determines which half word data from the 32-bit IP Bus
* interface is written into the lower 16 bits of the sample register.
*
* Values:
* - 0 - Half word swapping does not take place
* - 1 - Half words from write data bus are swapped
*/
//@{
#define BP_PWM_PWMCR_HCTR (20) //!< Bit position for PWM_PWMCR_HCTR.
#define BM_PWM_PWMCR_HCTR (0x00100000) //!< Bit mask for PWM_PWMCR_HCTR.
//! @brief Get value of PWM_PWMCR_HCTR from a register value.
#define BG_PWM_PWMCR_HCTR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCR_HCTR) >> BP_PWM_PWMCR_HCTR)
//! @brief Format value for bitfield PWM_PWMCR_HCTR.
#define BF_PWM_PWMCR_HCTR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMCR_HCTR) & BM_PWM_PWMCR_HCTR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the HCTR field to a new value.
#define BW_PWM_PWMCR_HCTR(x, v) (HW_PWM_PWMCR_WR(x, (HW_PWM_PWMCR_RD(x) & ~BM_PWM_PWMCR_HCTR) | BF_PWM_PWMCR_HCTR(v)))
#endif
//@}
/*! @name Register PWM_PWMCR, field BCTR[21] (RW)
*
* Byte Data Swap Control. This bit determines the byte ordering of the 16-bit data when it goes
* into the FIFO from the sample register.
*
* Values:
* - 0 - byte ordering remains the same
* - 1 - byte ordering is reversed
*/
//@{
#define BP_PWM_PWMCR_BCTR (21) //!< Bit position for PWM_PWMCR_BCTR.
#define BM_PWM_PWMCR_BCTR (0x00200000) //!< Bit mask for PWM_PWMCR_BCTR.
//! @brief Get value of PWM_PWMCR_BCTR from a register value.
#define BG_PWM_PWMCR_BCTR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCR_BCTR) >> BP_PWM_PWMCR_BCTR)
//! @brief Format value for bitfield PWM_PWMCR_BCTR.
#define BF_PWM_PWMCR_BCTR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMCR_BCTR) & BM_PWM_PWMCR_BCTR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the BCTR field to a new value.
#define BW_PWM_PWMCR_BCTR(x, v) (HW_PWM_PWMCR_WR(x, (HW_PWM_PWMCR_RD(x) & ~BM_PWM_PWMCR_BCTR) | BF_PWM_PWMCR_BCTR(v)))
#endif
//@}
/*! @name Register PWM_PWMCR, field DBGEN[22] (RW)
*
* Debug Mode Enable. This bit keeps the PWM functional in debug mode. When this bit is cleared, the
* input clock is gated off in debug mode. This bit is not affected by software reset. It is cleared
* by hardware reset.
*
* Values:
* - 0 - Inactive in debug mode
* - 1 - Active in debug mode
*/
//@{
#define BP_PWM_PWMCR_DBGEN (22) //!< Bit position for PWM_PWMCR_DBGEN.
#define BM_PWM_PWMCR_DBGEN (0x00400000) //!< Bit mask for PWM_PWMCR_DBGEN.
//! @brief Get value of PWM_PWMCR_DBGEN from a register value.
#define BG_PWM_PWMCR_DBGEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCR_DBGEN) >> BP_PWM_PWMCR_DBGEN)
//! @brief Format value for bitfield PWM_PWMCR_DBGEN.
#define BF_PWM_PWMCR_DBGEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMCR_DBGEN) & BM_PWM_PWMCR_DBGEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DBGEN field to a new value.
#define BW_PWM_PWMCR_DBGEN(x, v) (HW_PWM_PWMCR_WR(x, (HW_PWM_PWMCR_RD(x) & ~BM_PWM_PWMCR_DBGEN) | BF_PWM_PWMCR_DBGEN(v)))
#endif
//@}
/*! @name Register PWM_PWMCR, field WAITEN[23] (RW)
*
* Wait Mode Enable. This bit keeps the PWM functional in wait mode. When this bit is cleared, the
* input clock is gated off in wait mode. This bit is not affected by software reset. It is cleared
* by hardware reset.
*
* Values:
* - 0 - Inactive in wait mode
* - 1 - Active in wait mode
*/
//@{
#define BP_PWM_PWMCR_WAITEN (23) //!< Bit position for PWM_PWMCR_WAITEN.
#define BM_PWM_PWMCR_WAITEN (0x00800000) //!< Bit mask for PWM_PWMCR_WAITEN.
//! @brief Get value of PWM_PWMCR_WAITEN from a register value.
#define BG_PWM_PWMCR_WAITEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCR_WAITEN) >> BP_PWM_PWMCR_WAITEN)
//! @brief Format value for bitfield PWM_PWMCR_WAITEN.
#define BF_PWM_PWMCR_WAITEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMCR_WAITEN) & BM_PWM_PWMCR_WAITEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WAITEN field to a new value.
#define BW_PWM_PWMCR_WAITEN(x, v) (HW_PWM_PWMCR_WR(x, (HW_PWM_PWMCR_RD(x) & ~BM_PWM_PWMCR_WAITEN) | BF_PWM_PWMCR_WAITEN(v)))
#endif
//@}
/*! @name Register PWM_PWMCR, field DOZEN[24] (RW)
*
* Doze Mode Enable. This bit keeps the PWM functional in doze mode. When this bit is cleared, the
* input clock is gated off in doze mode. This bit is not affected by software reset. It is cleared
* by hardware reset.
*
* Values:
* - 0 - Inactive in doze mode
* - 1 - Active in doze mode
*/
//@{
#define BP_PWM_PWMCR_DOZEN (24) //!< Bit position for PWM_PWMCR_DOZEN.
#define BM_PWM_PWMCR_DOZEN (0x01000000) //!< Bit mask for PWM_PWMCR_DOZEN.
//! @brief Get value of PWM_PWMCR_DOZEN from a register value.
#define BG_PWM_PWMCR_DOZEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCR_DOZEN) >> BP_PWM_PWMCR_DOZEN)
//! @brief Format value for bitfield PWM_PWMCR_DOZEN.
#define BF_PWM_PWMCR_DOZEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMCR_DOZEN) & BM_PWM_PWMCR_DOZEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DOZEN field to a new value.
#define BW_PWM_PWMCR_DOZEN(x, v) (HW_PWM_PWMCR_WR(x, (HW_PWM_PWMCR_RD(x) & ~BM_PWM_PWMCR_DOZEN) | BF_PWM_PWMCR_DOZEN(v)))
#endif
//@}
/*! @name Register PWM_PWMCR, field STOPEN[25] (RW)
*
* Stop Mode Enable. This bit keeps the PWM functional while in stop mode. When this bit is cleared,
* the input clock is gated off in stop mode. This bit is not affected by software reset. It is
* cleared by hardware reset.
*
* Values:
* - 0 - Inactive in stop mode
* - 1 - Active in stop mode
*/
//@{
#define BP_PWM_PWMCR_STOPEN (25) //!< Bit position for PWM_PWMCR_STOPEN.
#define BM_PWM_PWMCR_STOPEN (0x02000000) //!< Bit mask for PWM_PWMCR_STOPEN.
//! @brief Get value of PWM_PWMCR_STOPEN from a register value.
#define BG_PWM_PWMCR_STOPEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCR_STOPEN) >> BP_PWM_PWMCR_STOPEN)
//! @brief Format value for bitfield PWM_PWMCR_STOPEN.
#define BF_PWM_PWMCR_STOPEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMCR_STOPEN) & BM_PWM_PWMCR_STOPEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the STOPEN field to a new value.
#define BW_PWM_PWMCR_STOPEN(x, v) (HW_PWM_PWMCR_WR(x, (HW_PWM_PWMCR_RD(x) & ~BM_PWM_PWMCR_STOPEN) | BF_PWM_PWMCR_STOPEN(v)))
#endif
//@}
/*! @name Register PWM_PWMCR, field FWM[27:26] (RW)
*
* FIFO Water Mark. These bits are used to set the data level at which the FIFO empty flag will be
* set and the corresponding interrupt generated
*
* Values:
* - 00 - FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO
* - 01 - FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO
* - 10 - FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO
* - 11 - FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO
*/
//@{
#define BP_PWM_PWMCR_FWM (26) //!< Bit position for PWM_PWMCR_FWM.
#define BM_PWM_PWMCR_FWM (0x0c000000) //!< Bit mask for PWM_PWMCR_FWM.
//! @brief Get value of PWM_PWMCR_FWM from a register value.
#define BG_PWM_PWMCR_FWM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCR_FWM) >> BP_PWM_PWMCR_FWM)
//! @brief Format value for bitfield PWM_PWMCR_FWM.
#define BF_PWM_PWMCR_FWM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMCR_FWM) & BM_PWM_PWMCR_FWM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the FWM field to a new value.
#define BW_PWM_PWMCR_FWM(x, v) (HW_PWM_PWMCR_WR(x, (HW_PWM_PWMCR_RD(x) & ~BM_PWM_PWMCR_FWM) | BF_PWM_PWMCR_FWM(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PWM_PWMSR - PWM Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PWM_PWMSR - PWM Status Register (W1C)
*
* Reset value: 0x00000008
*
* The PWM status register (PWM_PWMSR) contains seven bits which display the state of the FIFO and
* the occurrence of rollover and compare events. The FIFOAV bit is read-only but the other four
* bits can be cleared by writing 1 to them. The FE, ROV, and CMP bits are associated with FIFO-
* Empty, Roll-over, and Compare interrupts, respectively.
*/
typedef union _hw_pwm_pwmsr
{
reg32_t U;
struct _hw_pwm_pwmsr_bitfields
{
unsigned FIFOAV : 3; //!< [2:0] FIFO Available.
unsigned FE : 1; //!< [3] FIFO Empty Status Bit.
unsigned ROV : 1; //!< [4] Roll-over Status.
unsigned CMP : 1; //!< [5] Compare Status.
unsigned FWE : 1; //!< [6] FIFO Write Error Status.
unsigned RESERVED0 : 25; //!< [31:7] Reserved.
} B;
} hw_pwm_pwmsr_t;
#endif
/*!
* @name Constants and macros for entire PWM_PWMSR register
*/
//@{
#define HW_PWM_PWMSR_ADDR(x) (REGS_PWM_BASE(x) + 0x4)
#ifndef __LANGUAGE_ASM__
#define HW_PWM_PWMSR(x) (*(volatile hw_pwm_pwmsr_t *) HW_PWM_PWMSR_ADDR(x))
#define HW_PWM_PWMSR_RD(x) (HW_PWM_PWMSR(x).U)
#define HW_PWM_PWMSR_WR(x, v) (HW_PWM_PWMSR(x).U = (v))
#define HW_PWM_PWMSR_SET(x, v) (HW_PWM_PWMSR_WR(x, HW_PWM_PWMSR_RD(x) | (v)))
#define HW_PWM_PWMSR_CLR(x, v) (HW_PWM_PWMSR_WR(x, HW_PWM_PWMSR_RD(x) & ~(v)))
#define HW_PWM_PWMSR_TOG(x, v) (HW_PWM_PWMSR_WR(x, HW_PWM_PWMSR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual PWM_PWMSR bitfields
*/
/*! @name Register PWM_PWMSR, field FIFOAV[2:0] (RO)
*
* FIFO Available. These read-only bits indicate the data level remaining in the FIFO. An attempted
* write to these bits will not affect their value and no transfer error is generated.
*
* Values:
* - 000 - No data available
* - 001 - 1 word of data in FIFO
* - 010 - 2 words of data in FIFO
* - 011 - 3 words of data in FIFO
* - 100 - 4 words of data in FIFO
* - 101 - unused
* - 110 - unused
* - 111 - unused
*/
//@{
#define BP_PWM_PWMSR_FIFOAV (0) //!< Bit position for PWM_PWMSR_FIFOAV.
#define BM_PWM_PWMSR_FIFOAV (0x00000007) //!< Bit mask for PWM_PWMSR_FIFOAV.
//! @brief Get value of PWM_PWMSR_FIFOAV from a register value.
#define BG_PWM_PWMSR_FIFOAV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMSR_FIFOAV) >> BP_PWM_PWMSR_FIFOAV)
//@}
/*! @name Register PWM_PWMSR, field FE[3] (W1C)
*
* FIFO Empty Status Bit. This bit indicates the FIFO data level in comparison to the water level
* set by FWM field in the control register.
*
* Values:
* - 0 - Data level is above water mark
* - 1 - When the data level falls below the mark set by FWM field
*/
//@{
#define BP_PWM_PWMSR_FE (3) //!< Bit position for PWM_PWMSR_FE.
#define BM_PWM_PWMSR_FE (0x00000008) //!< Bit mask for PWM_PWMSR_FE.
//! @brief Get value of PWM_PWMSR_FE from a register value.
#define BG_PWM_PWMSR_FE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMSR_FE) >> BP_PWM_PWMSR_FE)
//! @brief Format value for bitfield PWM_PWMSR_FE.
#define BF_PWM_PWMSR_FE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMSR_FE) & BM_PWM_PWMSR_FE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the FE field to a new value.
#define BW_PWM_PWMSR_FE(x, v) (HW_PWM_PWMSR_WR(x, (HW_PWM_PWMSR_RD(x) & ~BM_PWM_PWMSR_FE) | BF_PWM_PWMSR_FE(v)))
#endif
//@}
/*! @name Register PWM_PWMSR, field ROV[4] (W1C)
*
* Roll-over Status. This bit shows that a roll-over event has occurred.
*
* Values:
* - 0 - Roll-over event not occurred
* - 1 - Roll-over event occurred
*/
//@{
#define BP_PWM_PWMSR_ROV (4) //!< Bit position for PWM_PWMSR_ROV.
#define BM_PWM_PWMSR_ROV (0x00000010) //!< Bit mask for PWM_PWMSR_ROV.
//! @brief Get value of PWM_PWMSR_ROV from a register value.
#define BG_PWM_PWMSR_ROV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMSR_ROV) >> BP_PWM_PWMSR_ROV)
//! @brief Format value for bitfield PWM_PWMSR_ROV.
#define BF_PWM_PWMSR_ROV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMSR_ROV) & BM_PWM_PWMSR_ROV)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ROV field to a new value.
#define BW_PWM_PWMSR_ROV(x, v) (HW_PWM_PWMSR_WR(x, (HW_PWM_PWMSR_RD(x) & ~BM_PWM_PWMSR_ROV) | BF_PWM_PWMSR_ROV(v)))
#endif
//@}
/*! @name Register PWM_PWMSR, field CMP[5] (W1C)
*
* Compare Status. This bit shows that a compare event has occurred.
*
* Values:
* - 0 - Compare event not occurred
* - 1 - Compare event occurred
*/
//@{
#define BP_PWM_PWMSR_CMP (5) //!< Bit position for PWM_PWMSR_CMP.
#define BM_PWM_PWMSR_CMP (0x00000020) //!< Bit mask for PWM_PWMSR_CMP.
//! @brief Get value of PWM_PWMSR_CMP from a register value.
#define BG_PWM_PWMSR_CMP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMSR_CMP) >> BP_PWM_PWMSR_CMP)
//! @brief Format value for bitfield PWM_PWMSR_CMP.
#define BF_PWM_PWMSR_CMP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMSR_CMP) & BM_PWM_PWMSR_CMP)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CMP field to a new value.
#define BW_PWM_PWMSR_CMP(x, v) (HW_PWM_PWMSR_WR(x, (HW_PWM_PWMSR_RD(x) & ~BM_PWM_PWMSR_CMP) | BF_PWM_PWMSR_CMP(v)))
#endif
//@}
/*! @name Register PWM_PWMSR, field FWE[6] (W1C)
*
* FIFO Write Error Status. This bit shows that an attempt has been made to write FIFO when it is
* full.
*
* Values:
* - 0 - FIFO write error not occurred
* - 1 - FIFO write error occurred
*/
//@{
#define BP_PWM_PWMSR_FWE (6) //!< Bit position for PWM_PWMSR_FWE.
#define BM_PWM_PWMSR_FWE (0x00000040) //!< Bit mask for PWM_PWMSR_FWE.
//! @brief Get value of PWM_PWMSR_FWE from a register value.
#define BG_PWM_PWMSR_FWE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMSR_FWE) >> BP_PWM_PWMSR_FWE)
//! @brief Format value for bitfield PWM_PWMSR_FWE.
#define BF_PWM_PWMSR_FWE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMSR_FWE) & BM_PWM_PWMSR_FWE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the FWE field to a new value.
#define BW_PWM_PWMSR_FWE(x, v) (HW_PWM_PWMSR_WR(x, (HW_PWM_PWMSR_RD(x) & ~BM_PWM_PWMSR_FWE) | BF_PWM_PWMSR_FWE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PWM_PWMIR - PWM Interrupt Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PWM_PWMIR - PWM Interrupt Register (RW)
*
* Reset value: 0x00000000
*
* The PWM Interrupt register (PWM_PWMIR) contains three bits which control the generation of the
* compare, rollover and FIFO empty interrupts.
*/
typedef union _hw_pwm_pwmir
{
reg32_t U;
struct _hw_pwm_pwmir_bitfields
{
unsigned FIE : 1; //!< [0] FIFO Empty Interrupt Enable.
unsigned RIE : 1; //!< [1] Roll-over Interrupt Enable.
unsigned CIE : 1; //!< [2] Compare Interrupt Enable.
unsigned RESERVED0 : 29; //!< [31:3] Reserved.
} B;
} hw_pwm_pwmir_t;
#endif
/*!
* @name Constants and macros for entire PWM_PWMIR register
*/
//@{
#define HW_PWM_PWMIR_ADDR(x) (REGS_PWM_BASE(x) + 0x8)
#ifndef __LANGUAGE_ASM__
#define HW_PWM_PWMIR(x) (*(volatile hw_pwm_pwmir_t *) HW_PWM_PWMIR_ADDR(x))
#define HW_PWM_PWMIR_RD(x) (HW_PWM_PWMIR(x).U)
#define HW_PWM_PWMIR_WR(x, v) (HW_PWM_PWMIR(x).U = (v))
#define HW_PWM_PWMIR_SET(x, v) (HW_PWM_PWMIR_WR(x, HW_PWM_PWMIR_RD(x) | (v)))
#define HW_PWM_PWMIR_CLR(x, v) (HW_PWM_PWMIR_WR(x, HW_PWM_PWMIR_RD(x) & ~(v)))
#define HW_PWM_PWMIR_TOG(x, v) (HW_PWM_PWMIR_WR(x, HW_PWM_PWMIR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual PWM_PWMIR bitfields
*/
/*! @name Register PWM_PWMIR, field FIE[0] (RW)
*
* FIFO Empty Interrupt Enable. This bit controls the generation of the FIFO Empty interrupt.
*
* Values:
* - 0 - FIFO Empty interrupt disabled
* - 1 - FIFO Empty interrupt enabled
*/
//@{
#define BP_PWM_PWMIR_FIE (0) //!< Bit position for PWM_PWMIR_FIE.
#define BM_PWM_PWMIR_FIE (0x00000001) //!< Bit mask for PWM_PWMIR_FIE.
//! @brief Get value of PWM_PWMIR_FIE from a register value.
#define BG_PWM_PWMIR_FIE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMIR_FIE) >> BP_PWM_PWMIR_FIE)
//! @brief Format value for bitfield PWM_PWMIR_FIE.
#define BF_PWM_PWMIR_FIE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMIR_FIE) & BM_PWM_PWMIR_FIE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the FIE field to a new value.
#define BW_PWM_PWMIR_FIE(x, v) (HW_PWM_PWMIR_WR(x, (HW_PWM_PWMIR_RD(x) & ~BM_PWM_PWMIR_FIE) | BF_PWM_PWMIR_FIE(v)))
#endif
//@}
/*! @name Register PWM_PWMIR, field RIE[1] (RW)
*
* Roll-over Interrupt Enable. This bit controls the generation of the Rollover interrupt.
*
* Values:
* - 0 - Roll-over interrupt not enabled
* - 1 - Roll-over Interrupt enabled
*/
//@{
#define BP_PWM_PWMIR_RIE (1) //!< Bit position for PWM_PWMIR_RIE.
#define BM_PWM_PWMIR_RIE (0x00000002) //!< Bit mask for PWM_PWMIR_RIE.
//! @brief Get value of PWM_PWMIR_RIE from a register value.
#define BG_PWM_PWMIR_RIE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMIR_RIE) >> BP_PWM_PWMIR_RIE)
//! @brief Format value for bitfield PWM_PWMIR_RIE.
#define BF_PWM_PWMIR_RIE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMIR_RIE) & BM_PWM_PWMIR_RIE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the RIE field to a new value.
#define BW_PWM_PWMIR_RIE(x, v) (HW_PWM_PWMIR_WR(x, (HW_PWM_PWMIR_RD(x) & ~BM_PWM_PWMIR_RIE) | BF_PWM_PWMIR_RIE(v)))
#endif
//@}
/*! @name Register PWM_PWMIR, field CIE[2] (RW)
*
* Compare Interrupt Enable. This bit controls the generation of the Compare interrupt.
*
* Values:
* - 0 - Compare Interrupt not enabled
* - 1 - Compare Interrupt enabled
*/
//@{
#define BP_PWM_PWMIR_CIE (2) //!< Bit position for PWM_PWMIR_CIE.
#define BM_PWM_PWMIR_CIE (0x00000004) //!< Bit mask for PWM_PWMIR_CIE.
//! @brief Get value of PWM_PWMIR_CIE from a register value.
#define BG_PWM_PWMIR_CIE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMIR_CIE) >> BP_PWM_PWMIR_CIE)
//! @brief Format value for bitfield PWM_PWMIR_CIE.
#define BF_PWM_PWMIR_CIE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMIR_CIE) & BM_PWM_PWMIR_CIE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CIE field to a new value.
#define BW_PWM_PWMIR_CIE(x, v) (HW_PWM_PWMIR_WR(x, (HW_PWM_PWMIR_RD(x) & ~BM_PWM_PWMIR_CIE) | BF_PWM_PWMIR_CIE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PWM_PWMSAR - PWM Sample Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PWM_PWMSAR - PWM Sample Register (RW)
*
* Reset value: 0x00000000
*
* The PWM sample register (PWM_PWMSAR) is the input to the FIFO. 16-bit words are loaded into the
* FIFO. The FIFO can be written at any time, but can be read only when the PWM is enabled. The PWM
* will run at the last set duty-cycle setting if all the values of the FIFO has been utilized,
* until the FIFO is reloaded or the PWM is disabled. When a new value is written, the duty cycle
* changes after the current period is over. A value of zero in the sample register will result in
* the PWMO output signal always being low/high (POUTC = 00 it will be low and POUTC = 01 it will be
* high), and no output waveform will be produced. If the value in this register is higher than the
* PERIOD + 1, the output will never be set/reset depending on POUTC value.
*/
typedef union _hw_pwm_pwmsar
{
reg32_t U;
struct _hw_pwm_pwmsar_bitfields
{
unsigned SAMPLE : 16; //!< [15:0] Sample Value.
unsigned RESERVED0 : 16; //!< [31:16] These are reserved bits and writing a value will not affect the functionality of PWM and are always read as zero.
} B;
} hw_pwm_pwmsar_t;
#endif
/*!
* @name Constants and macros for entire PWM_PWMSAR register
*/
//@{
#define HW_PWM_PWMSAR_ADDR(x) (REGS_PWM_BASE(x) + 0xc)
#ifndef __LANGUAGE_ASM__
#define HW_PWM_PWMSAR(x) (*(volatile hw_pwm_pwmsar_t *) HW_PWM_PWMSAR_ADDR(x))
#define HW_PWM_PWMSAR_RD(x) (HW_PWM_PWMSAR(x).U)
#define HW_PWM_PWMSAR_WR(x, v) (HW_PWM_PWMSAR(x).U = (v))
#define HW_PWM_PWMSAR_SET(x, v) (HW_PWM_PWMSAR_WR(x, HW_PWM_PWMSAR_RD(x) | (v)))
#define HW_PWM_PWMSAR_CLR(x, v) (HW_PWM_PWMSAR_WR(x, HW_PWM_PWMSAR_RD(x) & ~(v)))
#define HW_PWM_PWMSAR_TOG(x, v) (HW_PWM_PWMSAR_WR(x, HW_PWM_PWMSAR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual PWM_PWMSAR bitfields
*/
/*! @name Register PWM_PWMSAR, field SAMPLE[15:0] (RW)
*
* Sample Value. This is the input to the 4x16 FIFO. The value in this register denotes the value of
* the sample being currently used.
*/
//@{
#define BP_PWM_PWMSAR_SAMPLE (0) //!< Bit position for PWM_PWMSAR_SAMPLE.
#define BM_PWM_PWMSAR_SAMPLE (0x0000ffff) //!< Bit mask for PWM_PWMSAR_SAMPLE.
//! @brief Get value of PWM_PWMSAR_SAMPLE from a register value.
#define BG_PWM_PWMSAR_SAMPLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMSAR_SAMPLE) >> BP_PWM_PWMSAR_SAMPLE)
//! @brief Format value for bitfield PWM_PWMSAR_SAMPLE.
#define BF_PWM_PWMSAR_SAMPLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMSAR_SAMPLE) & BM_PWM_PWMSAR_SAMPLE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SAMPLE field to a new value.
#define BW_PWM_PWMSAR_SAMPLE(x, v) (HW_PWM_PWMSAR_WR(x, (HW_PWM_PWMSAR_RD(x) & ~BM_PWM_PWMSAR_SAMPLE) | BF_PWM_PWMSAR_SAMPLE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PWM_PWMPR - PWM Period Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PWM_PWMPR - PWM Period Register (RW)
*
* Reset value: 0x0000fffe
*
* The PWM period register (PWM_PWMPR) determines the period of the PWM output signal. After the
* counter value matches PERIOD + 1, the counter is reset to start another period. PWMO (Hz) =
* PCLK(Hz) / (period +2) A value of zero in the PWM_PWMPR will result in a period of two clock
* cycles for the output signal. Writing 0xFFFF to this register will achieve the same result as
* writing 0xFFFE. A change in the period value due to a write in PWM_PWMPR results in the counter
* being reset to zero and the start of a new count period. Settings PWM_PWMPR to 0xFFFF when
* PWMx_PWMCR REPEAT bits are set to non-zero values is not allowed.
*/
typedef union _hw_pwm_pwmpr
{
reg32_t U;
struct _hw_pwm_pwmpr_bitfields
{
unsigned PERIOD : 16; //!< [15:0] Period Value.
unsigned RESERVED0 : 16; //!< [31:16] These are reserved bits and writing a value will not affect the functionality of PWM and are always read as zero.
} B;
} hw_pwm_pwmpr_t;
#endif
/*!
* @name Constants and macros for entire PWM_PWMPR register
*/
//@{
#define HW_PWM_PWMPR_ADDR(x) (REGS_PWM_BASE(x) + 0x10)
#ifndef __LANGUAGE_ASM__
#define HW_PWM_PWMPR(x) (*(volatile hw_pwm_pwmpr_t *) HW_PWM_PWMPR_ADDR(x))
#define HW_PWM_PWMPR_RD(x) (HW_PWM_PWMPR(x).U)
#define HW_PWM_PWMPR_WR(x, v) (HW_PWM_PWMPR(x).U = (v))
#define HW_PWM_PWMPR_SET(x, v) (HW_PWM_PWMPR_WR(x, HW_PWM_PWMPR_RD(x) | (v)))
#define HW_PWM_PWMPR_CLR(x, v) (HW_PWM_PWMPR_WR(x, HW_PWM_PWMPR_RD(x) & ~(v)))
#define HW_PWM_PWMPR_TOG(x, v) (HW_PWM_PWMPR_WR(x, HW_PWM_PWMPR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual PWM_PWMPR bitfields
*/
/*! @name Register PWM_PWMPR, field PERIOD[15:0] (RW)
*
* Period Value. These bits determine the Period of the count cycle. The counter counts up to
* [Period Value] +1 and is then reset to 0x0000.
*/
//@{
#define BP_PWM_PWMPR_PERIOD (0) //!< Bit position for PWM_PWMPR_PERIOD.
#define BM_PWM_PWMPR_PERIOD (0x0000ffff) //!< Bit mask for PWM_PWMPR_PERIOD.
//! @brief Get value of PWM_PWMPR_PERIOD from a register value.
#define BG_PWM_PWMPR_PERIOD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMPR_PERIOD) >> BP_PWM_PWMPR_PERIOD)
//! @brief Format value for bitfield PWM_PWMPR_PERIOD.
#define BF_PWM_PWMPR_PERIOD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_PWM_PWMPR_PERIOD) & BM_PWM_PWMPR_PERIOD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PERIOD field to a new value.
#define BW_PWM_PWMPR_PERIOD(x, v) (HW_PWM_PWMPR_WR(x, (HW_PWM_PWMPR_RD(x) & ~BM_PWM_PWMPR_PERIOD) | BF_PWM_PWMPR_PERIOD(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PWM_PWMCNR - PWM Counter Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PWM_PWMCNR - PWM Counter Register (RO)
*
* Reset value: 0x00000000
*
* The read-only pulse-width modulator counter register (PWM_PWMCNR) contains the current count
* value and can be read at any time without disturbing the counter.
*/
typedef union _hw_pwm_pwmcnr
{
reg32_t U;
struct _hw_pwm_pwmcnr_bitfields
{
unsigned COUNT : 16; //!< [15:0] Counter Value.
unsigned RESERVED0 : 16; //!< [31:16] These are reserved bits and writing a value will not affect the functionality of PWM and are always read as zero.
} B;
} hw_pwm_pwmcnr_t;
#endif
/*!
* @name Constants and macros for entire PWM_PWMCNR register
*/
//@{
#define HW_PWM_PWMCNR_ADDR(x) (REGS_PWM_BASE(x) + 0x14)
#ifndef __LANGUAGE_ASM__
#define HW_PWM_PWMCNR(x) (*(volatile hw_pwm_pwmcnr_t *) HW_PWM_PWMCNR_ADDR(x))
#define HW_PWM_PWMCNR_RD(x) (HW_PWM_PWMCNR(x).U)
#endif
//@}
/*
* constants & macros for individual PWM_PWMCNR bitfields
*/
/*! @name Register PWM_PWMCNR, field COUNT[15:0] (RO)
*
* Counter Value. These bits are the counter register value and denotes the current count state the
* counter register is in.
*/
//@{
#define BP_PWM_PWMCNR_COUNT (0) //!< Bit position for PWM_PWMCNR_COUNT.
#define BM_PWM_PWMCNR_COUNT (0x0000ffff) //!< Bit mask for PWM_PWMCNR_COUNT.
//! @brief Get value of PWM_PWMCNR_COUNT from a register value.
#define BG_PWM_PWMCNR_COUNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_PWM_PWMCNR_COUNT) >> BP_PWM_PWMCNR_COUNT)
//@}
//-------------------------------------------------------------------------------------------
// hw_pwm_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All PWM module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_pwm
{
volatile hw_pwm_pwmcr_t PWMCR; //!< PWM Control Register
volatile hw_pwm_pwmsr_t PWMSR; //!< PWM Status Register
volatile hw_pwm_pwmir_t PWMIR; //!< PWM Interrupt Register
volatile hw_pwm_pwmsar_t PWMSAR; //!< PWM Sample Register
volatile hw_pwm_pwmpr_t PWMPR; //!< PWM Period Register
volatile hw_pwm_pwmcnr_t PWMCNR; //!< PWM Counter Register
} hw_pwm_t;
#pragma pack()
//! @brief Macro to access all PWM registers.
//! @param x PWM instance number.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_PWM(0)</code>.
#define HW_PWM(x) (*(hw_pwm_t *) REGS_PWM_BASE(x))
#endif
#endif // __HW_PWM_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_ROMC_REGISTERS_H__
#define __HW_ROMC_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ ROMC
*
* ROMC
*
* Registers defined in this header file:
* - HW_ROMC_ROMPATCHnD - ROMC Data Registers
* - HW_ROMC_ROMPATCHCNTL - ROMC Control Register
* - HW_ROMC_ROMPATCHENH - ROMC Enable Register High
* - HW_ROMC_ROMPATCHENL - ROMC Enable Register Low
* - HW_ROMC_ROMPATCHnA - ROMC Address Registers
* - HW_ROMC_ROMPATCHSR - ROMC Status Register
*
* - hw_romc_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_ROMC_BASE
#define HW_ROMC_INSTANCE_COUNT (1) //!< Number of instances of the ROMC module.
#define REGS_ROMC_BASE (0x021ac000) //!< Base address for ROMC.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_ROMC_ROMPATCHnD - ROMC Data Registers
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_ROMC_ROMPATCHnD - ROMC Data Registers (RW)
*
* Reset value: 0x00000000
*
* The ROMC data registers (ROMC_ROMPATCHD7 through ROMC_ROMPATCHD0) store the data to use for the 8
* 1-word data fix events. Each register is associated with an address comparator (7 through 0).
* When a data fixing event occurs, the value in the data register corresponding to the comparator
* that has the address match is put on the romc_hrdata[31:0] bus until romc_hready is asserted by
* the ROM controller to terminate the access. A MUX external to the ROMC will select this data over
* that of romc_hrdata[31:0] in returning read data to the ARM core. The selection is done with the
* control bus rompatch_romc_hrdata_ovr[1:0] with both bits asserted by the ROMC. If more than one
* address comparators match, the highest-numbered one takes precedence, and the value in
* corresponding data register is used for the patching event.
*/
typedef union _hw_romc_rompatchnd
{
reg32_t U;
struct _hw_romc_rompatchnd_bitfields
{
unsigned DATAX : 32; //!< [31:0] Data Fix Registers - Stores the data used for 1-word data fix operations.
} B;
} hw_romc_rompatchnd_t;
#endif
/*!
* @name Constants and macros for entire ROMC_ROMPATCHnD register
*/
//@{
//! @brief Number of instances of the ROMC_ROMPATCHnD register.
#define HW_ROMC_ROMPATCHnD_COUNT (8)
#define HW_ROMC_ROMPATCHnD_ADDR(n) (REGS_ROMC_BASE + 0xd4 + (0x4 * (n)))
#ifndef __LANGUAGE_ASM__
#define HW_ROMC_ROMPATCHnD(n) (*(volatile hw_romc_rompatchnd_t *) HW_ROMC_ROMPATCHnD_ADDR(n))
#define HW_ROMC_ROMPATCHnD_RD(n) (HW_ROMC_ROMPATCHnD(n).U)
#define HW_ROMC_ROMPATCHnD_WR(n, v) (HW_ROMC_ROMPATCHnD(n).U = (v))
#define HW_ROMC_ROMPATCHnD_SET(n, v) (HW_ROMC_ROMPATCHnD_WR(n, HW_ROMC_ROMPATCHnD_RD(n) | (v)))
#define HW_ROMC_ROMPATCHnD_CLR(n, v) (HW_ROMC_ROMPATCHnD_WR(n, HW_ROMC_ROMPATCHnD_RD(n) & ~(v)))
#define HW_ROMC_ROMPATCHnD_TOG(n, v) (HW_ROMC_ROMPATCHnD_WR(n, HW_ROMC_ROMPATCHnD_RD(n) ^ (v)))
#endif
//@}
/*
* constants & macros for individual ROMC_ROMPATCHnD bitfields
*/
/*! @name Register ROMC_ROMPATCHnD, field DATAX[31:0] (RW)
*
* Data Fix Registers - Stores the data used for 1-word data fix operations. The values stored
* within these registers do not affect the writes to the memory system. They are selected over the
* read data from ROM when a data fix event occurs. If any part of the 1-word data fix is read, then
* the entire word is replaced. Therefore, a byte or half-word read will cause the ROMC to replace
* the entire word. The word is word address aligned.
*/
//@{
#define BP_ROMC_ROMPATCHnD_DATAX (0) //!< Bit position for ROMC_ROMPATCHnD_DATAX.
#define BM_ROMC_ROMPATCHnD_DATAX (0xffffffff) //!< Bit mask for ROMC_ROMPATCHnD_DATAX.
//! @brief Get value of ROMC_ROMPATCHnD_DATAX from a register value.
#define BG_ROMC_ROMPATCHnD_DATAX(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHnD_DATAX) >> BP_ROMC_ROMPATCHnD_DATAX)
//! @brief Format value for bitfield ROMC_ROMPATCHnD_DATAX.
#define BF_ROMC_ROMPATCHnD_DATAX(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHnD_DATAX) & BM_ROMC_ROMPATCHnD_DATAX)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DATAX field to a new value.
#define BW_ROMC_ROMPATCHnD_DATAX(n, v) (HW_ROMC_ROMPATCHnD_WR(n, (HW_ROMC_ROMPATCHnD_RD(n) & ~BM_ROMC_ROMPATCHnD_DATAX) | BF_ROMC_ROMPATCHnD_DATAX(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_ROMC_ROMPATCHCNTL - ROMC Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_ROMC_ROMPATCHCNTL - ROMC Control Register (RW)
*
* Reset value: 0x08400000
*
* The ROMC control register (ROMC_ROMPATCHCNTL) contains the block disable bit and the data fix
* enable bits. The block disable bit provides a means to disable the ROMC data fix and opcode
* patching functions, even when the address comparators are enabled. The External Boot feature is
* not affected by this bit. The eight data fix enable bits (0 through 7), when set, assign the
* associated address comparators to data fix operations Bits 27 and 22 always read as 1s.
*/
typedef union _hw_romc_rompatchcntl
{
reg32_t U;
struct _hw_romc_rompatchcntl_bitfields
{
unsigned DATAFIX : 8; //!< [7:0] Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for code patch routine.
unsigned RESERVED0 : 21; //!< [28:8] Reserved
unsigned DIS : 1; //!< [29] ROMC Disable -- This bit, when set, disables all ROMC operations.
unsigned RESERVED1 : 2; //!< [31:30] Reserved
} B;
} hw_romc_rompatchcntl_t;
#endif
/*!
* @name Constants and macros for entire ROMC_ROMPATCHCNTL register
*/
//@{
#define HW_ROMC_ROMPATCHCNTL_ADDR (REGS_ROMC_BASE + 0xf4)
#ifndef __LANGUAGE_ASM__
#define HW_ROMC_ROMPATCHCNTL (*(volatile hw_romc_rompatchcntl_t *) HW_ROMC_ROMPATCHCNTL_ADDR)
#define HW_ROMC_ROMPATCHCNTL_RD() (HW_ROMC_ROMPATCHCNTL.U)
#define HW_ROMC_ROMPATCHCNTL_WR(v) (HW_ROMC_ROMPATCHCNTL.U = (v))
#define HW_ROMC_ROMPATCHCNTL_SET(v) (HW_ROMC_ROMPATCHCNTL_WR(HW_ROMC_ROMPATCHCNTL_RD() | (v)))
#define HW_ROMC_ROMPATCHCNTL_CLR(v) (HW_ROMC_ROMPATCHCNTL_WR(HW_ROMC_ROMPATCHCNTL_RD() & ~(v)))
#define HW_ROMC_ROMPATCHCNTL_TOG(v) (HW_ROMC_ROMPATCHCNTL_WR(HW_ROMC_ROMPATCHCNTL_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual ROMC_ROMPATCHCNTL bitfields
*/
/*! @name Register ROMC_ROMPATCHCNTL, field DATAFIX[7:0] (RW)
*
* Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for
* code patch routine.
*
* Values:
* - 0 - Address comparator triggers a opcode patch
* - 1 - Address comparator triggers a data fix
*/
//@{
#define BP_ROMC_ROMPATCHCNTL_DATAFIX (0) //!< Bit position for ROMC_ROMPATCHCNTL_DATAFIX.
#define BM_ROMC_ROMPATCHCNTL_DATAFIX (0x000000ff) //!< Bit mask for ROMC_ROMPATCHCNTL_DATAFIX.
//! @brief Get value of ROMC_ROMPATCHCNTL_DATAFIX from a register value.
#define BG_ROMC_ROMPATCHCNTL_DATAFIX(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHCNTL_DATAFIX) >> BP_ROMC_ROMPATCHCNTL_DATAFIX)
//! @brief Format value for bitfield ROMC_ROMPATCHCNTL_DATAFIX.
#define BF_ROMC_ROMPATCHCNTL_DATAFIX(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHCNTL_DATAFIX) & BM_ROMC_ROMPATCHCNTL_DATAFIX)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DATAFIX field to a new value.
#define BW_ROMC_ROMPATCHCNTL_DATAFIX(v) (HW_ROMC_ROMPATCHCNTL_WR((HW_ROMC_ROMPATCHCNTL_RD() & ~BM_ROMC_ROMPATCHCNTL_DATAFIX) | BF_ROMC_ROMPATCHCNTL_DATAFIX(v)))
#endif
//@}
/*! @name Register ROMC_ROMPATCHCNTL, field DIS[29] (RW)
*
* ROMC Disable -- This bit, when set, disables all ROMC operations. This bit is used to enable
* secure operations.
*
* Values:
* - 0 - Does not affect any ROMC functions (default)
* - 1 - Disable all ROMC functions: data fixing, and opcode patching
*/
//@{
#define BP_ROMC_ROMPATCHCNTL_DIS (29) //!< Bit position for ROMC_ROMPATCHCNTL_DIS.
#define BM_ROMC_ROMPATCHCNTL_DIS (0x20000000) //!< Bit mask for ROMC_ROMPATCHCNTL_DIS.
//! @brief Get value of ROMC_ROMPATCHCNTL_DIS from a register value.
#define BG_ROMC_ROMPATCHCNTL_DIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHCNTL_DIS) >> BP_ROMC_ROMPATCHCNTL_DIS)
//! @brief Format value for bitfield ROMC_ROMPATCHCNTL_DIS.
#define BF_ROMC_ROMPATCHCNTL_DIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHCNTL_DIS) & BM_ROMC_ROMPATCHCNTL_DIS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DIS field to a new value.
#define BW_ROMC_ROMPATCHCNTL_DIS(v) (HW_ROMC_ROMPATCHCNTL_WR((HW_ROMC_ROMPATCHCNTL_RD() & ~BM_ROMC_ROMPATCHCNTL_DIS) | BF_ROMC_ROMPATCHCNTL_DIS(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_ROMC_ROMPATCHENH - ROMC Enable Register High
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_ROMC_ROMPATCHENH - ROMC Enable Register High (RO)
*
* Reset value: 0x00000000
*
* The ROMC enable register high (ROMC_ROMPATCHENH) and ROMC enable register low (ROMC_ROMPATCHENL)
* control whether or not the associated address comparator can trigger a opcode patch or data fix
* event. This implementation of the ROMC only has 16 comparators, therefore ROMC_ROMPATCHENH and
* the upper half of ROMC_OMPATCHENL are read-only. ROMC_ROMPATCHENL[15:0] are associated with
* comparators 15 through 0. ROMC_ROMPATCHENLH[31:0] would have been associated with comparators 63
* through 32.
*/
typedef union _hw_romc_rompatchenh
{
reg32_t U;
struct _hw_romc_rompatchenh_bitfields
{
unsigned RESERVED0 : 32; //!< [31:0] Reserved
} B;
} hw_romc_rompatchenh_t;
#endif
/*!
* @name Constants and macros for entire ROMC_ROMPATCHENH register
*/
//@{
#define HW_ROMC_ROMPATCHENH_ADDR (REGS_ROMC_BASE + 0xf8)
#ifndef __LANGUAGE_ASM__
#define HW_ROMC_ROMPATCHENH (*(volatile hw_romc_rompatchenh_t *) HW_ROMC_ROMPATCHENH_ADDR)
#define HW_ROMC_ROMPATCHENH_RD() (HW_ROMC_ROMPATCHENH.U)
#endif
//@}
/*
* constants & macros for individual ROMC_ROMPATCHENH bitfields
*/
//-------------------------------------------------------------------------------------------
// HW_ROMC_ROMPATCHENL - ROMC Enable Register Low
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_ROMC_ROMPATCHENL - ROMC Enable Register Low (RW)
*
* Reset value: 0x00000000
*
* The ROMC enable register high (ROMC_ROMPATCHENH) and ROMC enable register low (ROMC_ROMPATCHENL)
* control whether or not the associated address comparator can trigger a opcode patch or data fix
* event. This implementation of the ROMC only has 16 comparators, therefore ROMC_ROMPATCHENH and
* the upper half of ROMC_ROMPATCHENL are read-only. ROMC_ROMPATCHENL[15:0] are associated with
* comparators 15 through 0. ROMC_ROMPATCHENLH[31:0] would have been associated with comparators 63
* through 32.
*/
typedef union _hw_romc_rompatchenl
{
reg32_t U;
struct _hw_romc_rompatchenl_bitfields
{
unsigned ENABLE : 16; //!< [15:0] Enable Address Comparator - This bit enables the corresponding address comparator to trigger an event.
unsigned RESERVED0 : 16; //!< [31:16]
} B;
} hw_romc_rompatchenl_t;
#endif
/*!
* @name Constants and macros for entire ROMC_ROMPATCHENL register
*/
//@{
#define HW_ROMC_ROMPATCHENL_ADDR (REGS_ROMC_BASE + 0xfc)
#ifndef __LANGUAGE_ASM__
#define HW_ROMC_ROMPATCHENL (*(volatile hw_romc_rompatchenl_t *) HW_ROMC_ROMPATCHENL_ADDR)
#define HW_ROMC_ROMPATCHENL_RD() (HW_ROMC_ROMPATCHENL.U)
#define HW_ROMC_ROMPATCHENL_WR(v) (HW_ROMC_ROMPATCHENL.U = (v))
#define HW_ROMC_ROMPATCHENL_SET(v) (HW_ROMC_ROMPATCHENL_WR(HW_ROMC_ROMPATCHENL_RD() | (v)))
#define HW_ROMC_ROMPATCHENL_CLR(v) (HW_ROMC_ROMPATCHENL_WR(HW_ROMC_ROMPATCHENL_RD() & ~(v)))
#define HW_ROMC_ROMPATCHENL_TOG(v) (HW_ROMC_ROMPATCHENL_WR(HW_ROMC_ROMPATCHENL_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual ROMC_ROMPATCHENL bitfields
*/
/*! @name Register ROMC_ROMPATCHENL, field ENABLE[15:0] (RW)
*
* Enable Address Comparator - This bit enables the corresponding address comparator to trigger an
* event.
*
* Values:
* - 0 - Address comparator disabled
* - 1 - Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the
* associated address
*/
//@{
#define BP_ROMC_ROMPATCHENL_ENABLE (0) //!< Bit position for ROMC_ROMPATCHENL_ENABLE.
#define BM_ROMC_ROMPATCHENL_ENABLE (0x0000ffff) //!< Bit mask for ROMC_ROMPATCHENL_ENABLE.
//! @brief Get value of ROMC_ROMPATCHENL_ENABLE from a register value.
#define BG_ROMC_ROMPATCHENL_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHENL_ENABLE) >> BP_ROMC_ROMPATCHENL_ENABLE)
//! @brief Format value for bitfield ROMC_ROMPATCHENL_ENABLE.
#define BF_ROMC_ROMPATCHENL_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHENL_ENABLE) & BM_ROMC_ROMPATCHENL_ENABLE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ENABLE field to a new value.
#define BW_ROMC_ROMPATCHENL_ENABLE(v) (HW_ROMC_ROMPATCHENL_WR((HW_ROMC_ROMPATCHENL_RD() & ~BM_ROMC_ROMPATCHENL_ENABLE) | BF_ROMC_ROMPATCHENL_ENABLE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_ROMC_ROMPATCHnA - ROMC Address Registers
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_ROMC_ROMPATCHnA - ROMC Address Registers (RW)
*
* Reset value: 0x00000000
*
* The ROMC address registers (ROMC_ROMPATCHA0 through ROMC_ROMPATCHA15) store the memory addresses
* where opcode patching begins and data fixing occurs. The address registers ROMC_ROMPATCHA0
* through ROMC_ROMPATCHA15 are each 21 bits wide and dedicated to one 4 Mbyte memory space. Bits 21
* through 2 are address bits, to be compared with romc_haddr[21:2] for a match; bit 1 is also an
* address bit used for half word selection. Bit 0 is the mode bit (set to 1 for THUMB mode). 1-word
* data fixing can only be used on the first 8 of the address comparators. ROMC_ROMPATCHA0 through
* ROMC_ROMPATCHA15 are associated each with address comparators 0 through 15.
*/
typedef union _hw_romc_rompatchna
{
reg32_t U;
struct _hw_romc_rompatchna_bitfields
{
unsigned THUMBX : 1; //!< [0] THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an ARM opcode patch.
unsigned ADDRX : 22; //!< [22:1] Address Comparator Registers - Indicates the memory address to be watched.
unsigned RESERVED0 : 9; //!< [31:23] Reserved
} B;
} hw_romc_rompatchna_t;
#endif
/*!
* @name Constants and macros for entire ROMC_ROMPATCHnA register
*/
//@{
//! @brief Number of instances of the ROMC_ROMPATCHnA register.
#define HW_ROMC_ROMPATCHnA_COUNT (16)
#define HW_ROMC_ROMPATCHnA_ADDR(n) (REGS_ROMC_BASE + 0x100 + (0x4 * (n)))
#ifndef __LANGUAGE_ASM__
#define HW_ROMC_ROMPATCHnA(n) (*(volatile hw_romc_rompatchna_t *) HW_ROMC_ROMPATCHnA_ADDR(n))
#define HW_ROMC_ROMPATCHnA_RD(n) (HW_ROMC_ROMPATCHnA(n).U)
#define HW_ROMC_ROMPATCHnA_WR(n, v) (HW_ROMC_ROMPATCHnA(n).U = (v))
#define HW_ROMC_ROMPATCHnA_SET(n, v) (HW_ROMC_ROMPATCHnA_WR(n, HW_ROMC_ROMPATCHnA_RD(n) | (v)))
#define HW_ROMC_ROMPATCHnA_CLR(n, v) (HW_ROMC_ROMPATCHnA_WR(n, HW_ROMC_ROMPATCHnA_RD(n) & ~(v)))
#define HW_ROMC_ROMPATCHnA_TOG(n, v) (HW_ROMC_ROMPATCHnA_WR(n, HW_ROMC_ROMPATCHnA_RD(n) ^ (v)))
#endif
//@}
/*
* constants & macros for individual ROMC_ROMPATCHnA bitfields
*/
/*! @name Register ROMC_ROMPATCHnA, field THUMBX[0] (RW)
*
* THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an ARM
* opcode patch. If this watchpoint is selected to be a data fix, then this bit is ignored as all
* data fixes are 1-word data fixes.
*
* Values:
* - 0 - ARM patch
* - 1 - THUMB patch (ignore if data fix)
*/
//@{
#define BP_ROMC_ROMPATCHnA_THUMBX (0) //!< Bit position for ROMC_ROMPATCHnA_THUMBX.
#define BM_ROMC_ROMPATCHnA_THUMBX (0x00000001) //!< Bit mask for ROMC_ROMPATCHnA_THUMBX.
//! @brief Get value of ROMC_ROMPATCHnA_THUMBX from a register value.
#define BG_ROMC_ROMPATCHnA_THUMBX(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHnA_THUMBX) >> BP_ROMC_ROMPATCHnA_THUMBX)
//! @brief Format value for bitfield ROMC_ROMPATCHnA_THUMBX.
#define BF_ROMC_ROMPATCHnA_THUMBX(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHnA_THUMBX) & BM_ROMC_ROMPATCHnA_THUMBX)
#ifndef __LANGUAGE_ASM__
//! @brief Set the THUMBX field to a new value.
#define BW_ROMC_ROMPATCHnA_THUMBX(n, v) (HW_ROMC_ROMPATCHnA_WR(n, (HW_ROMC_ROMPATCHnA_RD(n) & ~BM_ROMC_ROMPATCHnA_THUMBX) | BF_ROMC_ROMPATCHnA_THUMBX(v)))
#endif
//@}
/*! @name Register ROMC_ROMPATCHnA, field ADDRX[22:1] (RW)
*
* Address Comparator Registers - Indicates the memory address to be watched. All 16 registers can
* be used for code patch address comparison. Only the first 8 registers can be used for a 1-word
* data fix address comparison. Bit 1 is ignored if data fix. Only used in code patch
*/
//@{
#define BP_ROMC_ROMPATCHnA_ADDRX (1) //!< Bit position for ROMC_ROMPATCHnA_ADDRX.
#define BM_ROMC_ROMPATCHnA_ADDRX (0x007ffffe) //!< Bit mask for ROMC_ROMPATCHnA_ADDRX.
//! @brief Get value of ROMC_ROMPATCHnA_ADDRX from a register value.
#define BG_ROMC_ROMPATCHnA_ADDRX(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHnA_ADDRX) >> BP_ROMC_ROMPATCHnA_ADDRX)
//! @brief Format value for bitfield ROMC_ROMPATCHnA_ADDRX.
#define BF_ROMC_ROMPATCHnA_ADDRX(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHnA_ADDRX) & BM_ROMC_ROMPATCHnA_ADDRX)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ADDRX field to a new value.
#define BW_ROMC_ROMPATCHnA_ADDRX(n, v) (HW_ROMC_ROMPATCHnA_WR(n, (HW_ROMC_ROMPATCHnA_RD(n) & ~BM_ROMC_ROMPATCHnA_ADDRX) | BF_ROMC_ROMPATCHnA_ADDRX(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_ROMC_ROMPATCHSR - ROMC Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_ROMC_ROMPATCHSR - ROMC Status Register (W1C)
*
* Reset value: 0x00000000
*
* The ROMC status register (ROMC_ROMPATCHSR) indicates the current state of the ROMC and the source
* number of the most recent address comparator event.
*/
typedef union _hw_romc_rompatchsr
{
reg32_t U;
struct _hw_romc_rompatchsr_bitfields
{
unsigned SOURCE : 6; //!< [5:0] ROMC Source Number - Binary encoding of the number of the address comparator which has an address match in the most recent patch event on ROMC AHB.
unsigned RESERVED0 : 11; //!< [16:6] Reserved
unsigned SW : 1; //!< [17] ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address comparator matches occurred.
unsigned RESERVED1 : 14; //!< [31:18] Reserved
} B;
} hw_romc_rompatchsr_t;
#endif
/*!
* @name Constants and macros for entire ROMC_ROMPATCHSR register
*/
//@{
#define HW_ROMC_ROMPATCHSR_ADDR (REGS_ROMC_BASE + 0x208)
#ifndef __LANGUAGE_ASM__
#define HW_ROMC_ROMPATCHSR (*(volatile hw_romc_rompatchsr_t *) HW_ROMC_ROMPATCHSR_ADDR)
#define HW_ROMC_ROMPATCHSR_RD() (HW_ROMC_ROMPATCHSR.U)
#define HW_ROMC_ROMPATCHSR_WR(v) (HW_ROMC_ROMPATCHSR.U = (v))
#define HW_ROMC_ROMPATCHSR_SET(v) (HW_ROMC_ROMPATCHSR_WR(HW_ROMC_ROMPATCHSR_RD() | (v)))
#define HW_ROMC_ROMPATCHSR_CLR(v) (HW_ROMC_ROMPATCHSR_WR(HW_ROMC_ROMPATCHSR_RD() & ~(v)))
#define HW_ROMC_ROMPATCHSR_TOG(v) (HW_ROMC_ROMPATCHSR_WR(HW_ROMC_ROMPATCHSR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual ROMC_ROMPATCHSR bitfields
*/
/*! @name Register ROMC_ROMPATCHSR, field SOURCE[5:0] (RO)
*
* ROMC Source Number - Binary encoding of the number of the address comparator which has an address
* match in the most recent patch event on ROMC AHB. If multiple matches occurred, the highest
* priority source number is used.
*
* Values:
* - 0 - Address Comparator 0 matched
* - 1 - Address Comparator 1 matched
* - 15 - Address Comparator 15 matched
*/
//@{
#define BP_ROMC_ROMPATCHSR_SOURCE (0) //!< Bit position for ROMC_ROMPATCHSR_SOURCE.
#define BM_ROMC_ROMPATCHSR_SOURCE (0x0000003f) //!< Bit mask for ROMC_ROMPATCHSR_SOURCE.
//! @brief Get value of ROMC_ROMPATCHSR_SOURCE from a register value.
#define BG_ROMC_ROMPATCHSR_SOURCE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHSR_SOURCE) >> BP_ROMC_ROMPATCHSR_SOURCE)
//@}
/*! @name Register ROMC_ROMPATCHSR, field SW[17] (W1C)
*
* ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address
* comparator matches occurred. Writing a 1 to this bit will clear this it.
*
* Values:
* - 0 - no event or comparator collisions
* - 1 - a collision has occurred
*/
//@{
#define BP_ROMC_ROMPATCHSR_SW (17) //!< Bit position for ROMC_ROMPATCHSR_SW.
#define BM_ROMC_ROMPATCHSR_SW (0x00020000) //!< Bit mask for ROMC_ROMPATCHSR_SW.
//! @brief Get value of ROMC_ROMPATCHSR_SW from a register value.
#define BG_ROMC_ROMPATCHSR_SW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHSR_SW) >> BP_ROMC_ROMPATCHSR_SW)
//! @brief Format value for bitfield ROMC_ROMPATCHSR_SW.
#define BF_ROMC_ROMPATCHSR_SW(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHSR_SW) & BM_ROMC_ROMPATCHSR_SW)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SW field to a new value.
#define BW_ROMC_ROMPATCHSR_SW(v) (HW_ROMC_ROMPATCHSR_WR((HW_ROMC_ROMPATCHSR_RD() & ~BM_ROMC_ROMPATCHSR_SW) | BF_ROMC_ROMPATCHSR_SW(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_romc_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All ROMC module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_romc
{
reg32_t _reserved0[53];
volatile hw_romc_rompatchnd_t ROMPATCHnD[8]; //!< ROMC Data Registers
volatile hw_romc_rompatchcntl_t ROMPATCHCNTL; //!< ROMC Control Register
volatile hw_romc_rompatchenh_t ROMPATCHENH; //!< ROMC Enable Register High
volatile hw_romc_rompatchenl_t ROMPATCHENL; //!< ROMC Enable Register Low
volatile hw_romc_rompatchna_t ROMPATCHnA[16]; //!< ROMC Address Registers
reg32_t _reserved1[50];
volatile hw_romc_rompatchsr_t ROMPATCHSR; //!< ROMC Status Register
} hw_romc_t;
#pragma pack()
//! @brief Macro to access all ROMC registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_ROMC</code>.
#define HW_ROMC (*(hw_romc_t *) REGS_ROMC_BASE)
#endif
#endif // __HW_ROMC_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_SDMABP_REGISTERS_H__
#define __HW_SDMABP_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ SDMABP
*
* SDMA
*
* Registers defined in this header file:
* - HW_SDMABP_DC0PTR - Channel 0 Pointer
* - HW_SDMABP_INTR - Channel Interrupts
* - HW_SDMABP_STOP_STAT - Channel Stop/Channel Status
* - HW_SDMABP_DSTART - Channel Start
* - HW_SDMABP_EVTERR - DMA Request Error Register
* - HW_SDMABP_INTRMASK - Channel DSP Interrupt Mask
* - HW_SDMABP_EVTERRDBG - DMA Request Error Register
*
* - hw_sdmabp_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_SDMABP_BASE
#define HW_SDMABP_INSTANCE_COUNT (1) //!< Number of instances of the SDMABP module.
#define REGS_SDMABP_BASE (0x020ec000) //!< Base address for SDMABP.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_SDMABP_DC0PTR - Channel 0 Pointer
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SDMABP_DC0PTR - Channel 0 Pointer (RW)
*
* Reset value: 0x00000000
*/
typedef union _hw_sdmabp_dc0ptr
{
reg32_t U;
struct _hw_sdmabp_dc0ptr_bitfields
{
unsigned DC0PTR : 32; //!< [31:0] Channel 0 Pointer contains the 32-bit address, in BP memory, of the array of channel control blocks starting with the one for channel 0 (the control channel).
} B;
} hw_sdmabp_dc0ptr_t;
#endif
/*!
* @name Constants and macros for entire SDMABP_DC0PTR register
*/
//@{
#define HW_SDMABP_DC0PTR_ADDR (REGS_SDMABP_BASE + 0x0)
#ifndef __LANGUAGE_ASM__
#define HW_SDMABP_DC0PTR (*(volatile hw_sdmabp_dc0ptr_t *) HW_SDMABP_DC0PTR_ADDR)
#define HW_SDMABP_DC0PTR_RD() (HW_SDMABP_DC0PTR.U)
#define HW_SDMABP_DC0PTR_WR(v) (HW_SDMABP_DC0PTR.U = (v))
#define HW_SDMABP_DC0PTR_SET(v) (HW_SDMABP_DC0PTR_WR(HW_SDMABP_DC0PTR_RD() | (v)))
#define HW_SDMABP_DC0PTR_CLR(v) (HW_SDMABP_DC0PTR_WR(HW_SDMABP_DC0PTR_RD() & ~(v)))
#define HW_SDMABP_DC0PTR_TOG(v) (HW_SDMABP_DC0PTR_WR(HW_SDMABP_DC0PTR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual SDMABP_DC0PTR bitfields
*/
/*! @name Register SDMABP_DC0PTR, field DC0PTR[31:0] (RW)
*
* Channel 0 Pointer contains the 32-bit address, in BP memory, of the array of channel control
* blocks starting with the one for channel 0 (the control channel). This register should be
* initialized by the BP before it enables a channel (for example, channel 0). See the API document
* SDMA Scripts User Manual for the use of this register. The BP has a read/write access and the
* SDMA has a read-only access.
*/
//@{
#define BP_SDMABP_DC0PTR_DC0PTR (0) //!< Bit position for SDMABP_DC0PTR_DC0PTR.
#define BM_SDMABP_DC0PTR_DC0PTR (0xffffffff) //!< Bit mask for SDMABP_DC0PTR_DC0PTR.
//! @brief Get value of SDMABP_DC0PTR_DC0PTR from a register value.
#define BG_SDMABP_DC0PTR_DC0PTR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_DC0PTR_DC0PTR) >> BP_SDMABP_DC0PTR_DC0PTR)
//! @brief Format value for bitfield SDMABP_DC0PTR_DC0PTR.
#define BF_SDMABP_DC0PTR_DC0PTR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMABP_DC0PTR_DC0PTR) & BM_SDMABP_DC0PTR_DC0PTR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DC0PTR field to a new value.
#define BW_SDMABP_DC0PTR_DC0PTR(v) (HW_SDMABP_DC0PTR_WR((HW_SDMABP_DC0PTR_RD() & ~BM_SDMABP_DC0PTR_DC0PTR) | BF_SDMABP_DC0PTR_DC0PTR(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_SDMABP_INTR - Channel Interrupts
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SDMABP_INTR - Channel Interrupts (W1C)
*
* Reset value: 0x00000000
*/
typedef union _hw_sdmabp_intr
{
reg32_t U;
struct _hw_sdmabp_intr_bitfields
{
unsigned DI : 32; //!< [31:0] The BP Interrupts register contains the 32 DI[i] bits.
} B;
} hw_sdmabp_intr_t;
#endif
/*!
* @name Constants and macros for entire SDMABP_INTR register
*/
//@{
#define HW_SDMABP_INTR_ADDR (REGS_SDMABP_BASE + 0x4)
#ifndef __LANGUAGE_ASM__
#define HW_SDMABP_INTR (*(volatile hw_sdmabp_intr_t *) HW_SDMABP_INTR_ADDR)
#define HW_SDMABP_INTR_RD() (HW_SDMABP_INTR.U)
#define HW_SDMABP_INTR_WR(v) (HW_SDMABP_INTR.U = (v))
#define HW_SDMABP_INTR_SET(v) (HW_SDMABP_INTR_WR(HW_SDMABP_INTR_RD() | (v)))
#define HW_SDMABP_INTR_CLR(v) (HW_SDMABP_INTR_WR(HW_SDMABP_INTR_RD() & ~(v)))
#define HW_SDMABP_INTR_TOG(v) (HW_SDMABP_INTR_WR(HW_SDMABP_INTR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual SDMABP_INTR bitfields
*/
/*! @name Register SDMABP_INTR, field DI[31:0] (W1C)
*
* The BP Interrupts register contains the 32 DI[i] bits. If any bit is set, it will cause an
* interrupt to the BP. This register is a "write-ones" register to the BP. When the BP sets a bit
* in this register, the corresponding DI[i] bit is cleared. The interrupt service routine should
* clear individual channel bits when their interrupts are serviced; failure to do so will cause
* continuous interrupts. The SDMA is responsible for setting the DI[i] bit corresponding to the
* current channel when the corresponding done instruction is executed.
*/
//@{
#define BP_SDMABP_INTR_DI (0) //!< Bit position for SDMABP_INTR_DI.
#define BM_SDMABP_INTR_DI (0xffffffff) //!< Bit mask for SDMABP_INTR_DI.
//! @brief Get value of SDMABP_INTR_DI from a register value.
#define BG_SDMABP_INTR_DI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_INTR_DI) >> BP_SDMABP_INTR_DI)
//! @brief Format value for bitfield SDMABP_INTR_DI.
#define BF_SDMABP_INTR_DI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMABP_INTR_DI) & BM_SDMABP_INTR_DI)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DI field to a new value.
#define BW_SDMABP_INTR_DI(v) (HW_SDMABP_INTR_WR((HW_SDMABP_INTR_RD() & ~BM_SDMABP_INTR_DI) | BF_SDMABP_INTR_DI(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_SDMABP_STOP_STAT - Channel Stop/Channel Status
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SDMABP_STOP_STAT - Channel Stop/Channel Status (RW)
*
* Reset value: 0x00000000
*/
typedef union _hw_sdmabp_stop_stat
{
reg32_t U;
struct _hw_sdmabp_stop_stat_bitfields
{
unsigned DE : 32; //!< [31:0] This 32-bit register gives access to the BP (DSP) Enable bits, DE.
} B;
} hw_sdmabp_stop_stat_t;
#endif
/*!
* @name Constants and macros for entire SDMABP_STOP_STAT register
*/
//@{
#define HW_SDMABP_STOP_STAT_ADDR (REGS_SDMABP_BASE + 0x8)
#ifndef __LANGUAGE_ASM__
#define HW_SDMABP_STOP_STAT (*(volatile hw_sdmabp_stop_stat_t *) HW_SDMABP_STOP_STAT_ADDR)
#define HW_SDMABP_STOP_STAT_RD() (HW_SDMABP_STOP_STAT.U)
#define HW_SDMABP_STOP_STAT_WR(v) (HW_SDMABP_STOP_STAT.U = (v))
#define HW_SDMABP_STOP_STAT_SET(v) (HW_SDMABP_STOP_STAT_WR(HW_SDMABP_STOP_STAT_RD() | (v)))
#define HW_SDMABP_STOP_STAT_CLR(v) (HW_SDMABP_STOP_STAT_WR(HW_SDMABP_STOP_STAT_RD() & ~(v)))
#define HW_SDMABP_STOP_STAT_TOG(v) (HW_SDMABP_STOP_STAT_WR(HW_SDMABP_STOP_STAT_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual SDMABP_STOP_STAT bitfields
*/
/*! @name Register SDMABP_STOP_STAT, field DE[31:0] (W1C)
*
* This 32-bit register gives access to the BP (DSP) Enable bits, DE. There is one bit for every
* channel. This register is a "write-ones" register to the BP. When the BP writes 1 in bit i of
* this register, it clears the DE[i] and DSTART[i] bits. Reading this register yields the current
* state of the DE[i] bits.
*/
//@{
#define BP_SDMABP_STOP_STAT_DE (0) //!< Bit position for SDMABP_STOP_STAT_DE.
#define BM_SDMABP_STOP_STAT_DE (0xffffffff) //!< Bit mask for SDMABP_STOP_STAT_DE.
//! @brief Get value of SDMABP_STOP_STAT_DE from a register value.
#define BG_SDMABP_STOP_STAT_DE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_STOP_STAT_DE) >> BP_SDMABP_STOP_STAT_DE)
//! @brief Format value for bitfield SDMABP_STOP_STAT_DE.
#define BF_SDMABP_STOP_STAT_DE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMABP_STOP_STAT_DE) & BM_SDMABP_STOP_STAT_DE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DE field to a new value.
#define BW_SDMABP_STOP_STAT_DE(v) (HW_SDMABP_STOP_STAT_WR((HW_SDMABP_STOP_STAT_RD() & ~BM_SDMABP_STOP_STAT_DE) | BF_SDMABP_STOP_STAT_DE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_SDMABP_DSTART - Channel Start
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SDMABP_DSTART - Channel Start (RO)
*
* Reset value: 0x00000000
*/
typedef union _hw_sdmabp_dstart
{
reg32_t U;
struct _hw_sdmabp_dstart_bitfields
{
unsigned DSTART_DE : 32; //!< [31:0] The DSTART_DE registers are 32 bits wide with one bit for every channel.
} B;
} hw_sdmabp_dstart_t;
#endif
/*!
* @name Constants and macros for entire SDMABP_DSTART register
*/
//@{
#define HW_SDMABP_DSTART_ADDR (REGS_SDMABP_BASE + 0xc)
#ifndef __LANGUAGE_ASM__
#define HW_SDMABP_DSTART (*(volatile hw_sdmabp_dstart_t *) HW_SDMABP_DSTART_ADDR)
#define HW_SDMABP_DSTART_RD() (HW_SDMABP_DSTART.U)
#endif
//@}
/*
* constants & macros for individual SDMABP_DSTART bitfields
*/
/*! @name Register SDMABP_DSTART, field DSTART_DE[31:0] (RO)
*
* The DSTART_DE registers are 32 bits wide with one bit for every channel. When a bit is written to
* 1, it enables the corresponding channel. Two physical registers are accessed with that address
* (DSTART and DE), which enables the BP to trigger a channel a second time before the first trigger
* was processed. This register is a "write-ones" register to the BP. Neither DSTART[i] bit can be
* set while the corresponding DE[i] bit is cleared. When the BP tries to set the DSTART[i] bit by
* writing a one (if the corresponding DE[i] bit is clear), the bit in the DSTART[i] register will
* remain cleared and the DE[i] bit will be set. If the corresponding DE[i] bit was already set, the
* DSTART[i] bit will be set. The next time the SDMA channel i attempts to clear the DE[i] bit by
* means of a done instruction, the bit in the DSTART[i] register will be cleared and the DE[i] bit
* will take the old value of the DSTART[i] bit. Reading this register yields the current state of
* the DSTART[i] bits. This mechanism enables the BP to pipeline two DSTART commands per channel.
*/
//@{
#define BP_SDMABP_DSTART_DSTART_DE (0) //!< Bit position for SDMABP_DSTART_DSTART_DE.
#define BM_SDMABP_DSTART_DSTART_DE (0xffffffff) //!< Bit mask for SDMABP_DSTART_DSTART_DE.
//! @brief Get value of SDMABP_DSTART_DSTART_DE from a register value.
#define BG_SDMABP_DSTART_DSTART_DE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_DSTART_DSTART_DE) >> BP_SDMABP_DSTART_DSTART_DE)
//@}
//-------------------------------------------------------------------------------------------
// HW_SDMABP_EVTERR - DMA Request Error Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SDMABP_EVTERR - DMA Request Error Register (RO)
*
* Reset value: 0x00000000
*/
typedef union _hw_sdmabp_evterr
{
reg32_t U;
struct _hw_sdmabp_evterr_bitfields
{
unsigned CHNERR : 32; //!< [31:0] This register is used by the SDMA to warn the BP when an incoming DMA request was detected; it then triggers a channel that is already pending or being serviced, which may mean there is an overflow of data for that channel.
} B;
} hw_sdmabp_evterr_t;
#endif
/*!
* @name Constants and macros for entire SDMABP_EVTERR register
*/
//@{
#define HW_SDMABP_EVTERR_ADDR (REGS_SDMABP_BASE + 0x28)
#ifndef __LANGUAGE_ASM__
#define HW_SDMABP_EVTERR (*(volatile hw_sdmabp_evterr_t *) HW_SDMABP_EVTERR_ADDR)
#define HW_SDMABP_EVTERR_RD() (HW_SDMABP_EVTERR.U)
#endif
//@}
/*
* constants & macros for individual SDMABP_EVTERR bitfields
*/
/*! @name Register SDMABP_EVTERR, field CHNERR[31:0] (RO)
*
* This register is used by the SDMA to warn the BP when an incoming DMA request was detected; it
* then triggers a channel that is already pending or being serviced, which may mean there is an
* overflow of data for that channel. An interrupt is sent to the BP if the corresponding channel
* bit is set in the INTRMASK register. This is a "write-ones" register for the scheduler. It is
* only able to set the flags. The flags are cleared when the register is read by the BP or during
* an SDMA reset. The CHNERR[i] bit is set when a DMA request that triggers channel i is received
* through the corresponding input pins and the EP[i] bit is already set. The EVTERR[i] bit is
* unaffected if the BP tries to set the EP[i] bit when that EP[i] bit is already set.
*/
//@{
#define BP_SDMABP_EVTERR_CHNERR (0) //!< Bit position for SDMABP_EVTERR_CHNERR.
#define BM_SDMABP_EVTERR_CHNERR (0xffffffff) //!< Bit mask for SDMABP_EVTERR_CHNERR.
//! @brief Get value of SDMABP_EVTERR_CHNERR from a register value.
#define BG_SDMABP_EVTERR_CHNERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_EVTERR_CHNERR) >> BP_SDMABP_EVTERR_CHNERR)
//@}
//-------------------------------------------------------------------------------------------
// HW_SDMABP_INTRMASK - Channel DSP Interrupt Mask
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SDMABP_INTRMASK - Channel DSP Interrupt Mask (RW)
*
* Reset value: 0x00000000
*/
typedef union _hw_sdmabp_intrmask
{
reg32_t U;
struct _hw_sdmabp_intrmask_bitfields
{
unsigned DIMASK : 32; //!< [31:0] The Interrupt Mask Register contains 32 interrupt generation mask bits.
} B;
} hw_sdmabp_intrmask_t;
#endif
/*!
* @name Constants and macros for entire SDMABP_INTRMASK register
*/
//@{
#define HW_SDMABP_INTRMASK_ADDR (REGS_SDMABP_BASE + 0x2c)
#ifndef __LANGUAGE_ASM__
#define HW_SDMABP_INTRMASK (*(volatile hw_sdmabp_intrmask_t *) HW_SDMABP_INTRMASK_ADDR)
#define HW_SDMABP_INTRMASK_RD() (HW_SDMABP_INTRMASK.U)
#define HW_SDMABP_INTRMASK_WR(v) (HW_SDMABP_INTRMASK.U = (v))
#define HW_SDMABP_INTRMASK_SET(v) (HW_SDMABP_INTRMASK_WR(HW_SDMABP_INTRMASK_RD() | (v)))
#define HW_SDMABP_INTRMASK_CLR(v) (HW_SDMABP_INTRMASK_WR(HW_SDMABP_INTRMASK_RD() & ~(v)))
#define HW_SDMABP_INTRMASK_TOG(v) (HW_SDMABP_INTRMASK_WR(HW_SDMABP_INTRMASK_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual SDMABP_INTRMASK bitfields
*/
/*! @name Register SDMABP_INTRMASK, field DIMASK[31:0] (RW)
*
* The Interrupt Mask Register contains 32 interrupt generation mask bits. If bit DIMASK[i] is set,
* the DI[i] bit is set and an interrupt is sent to the BP when a DMA request error is detected on
* channel i (for example, EVTERR[i] is set).
*/
//@{
#define BP_SDMABP_INTRMASK_DIMASK (0) //!< Bit position for SDMABP_INTRMASK_DIMASK.
#define BM_SDMABP_INTRMASK_DIMASK (0xffffffff) //!< Bit mask for SDMABP_INTRMASK_DIMASK.
//! @brief Get value of SDMABP_INTRMASK_DIMASK from a register value.
#define BG_SDMABP_INTRMASK_DIMASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_INTRMASK_DIMASK) >> BP_SDMABP_INTRMASK_DIMASK)
//! @brief Format value for bitfield SDMABP_INTRMASK_DIMASK.
#define BF_SDMABP_INTRMASK_DIMASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMABP_INTRMASK_DIMASK) & BM_SDMABP_INTRMASK_DIMASK)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DIMASK field to a new value.
#define BW_SDMABP_INTRMASK_DIMASK(v) (HW_SDMABP_INTRMASK_WR((HW_SDMABP_INTRMASK_RD() & ~BM_SDMABP_INTRMASK_DIMASK) | BF_SDMABP_INTRMASK_DIMASK(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_SDMABP_EVTERRDBG - DMA Request Error Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SDMABP_EVTERRDBG - DMA Request Error Register (RO)
*
* Reset value: 0x00000000
*/
typedef union _hw_sdmabp_evterrdbg
{
reg32_t U;
struct _hw_sdmabp_evterrdbg_bitfields
{
unsigned CHNERR : 32; //!< [31:0] This register is the same as EVTERR except reading it does not clear its contents.
} B;
} hw_sdmabp_evterrdbg_t;
#endif
/*!
* @name Constants and macros for entire SDMABP_EVTERRDBG register
*/
//@{
#define HW_SDMABP_EVTERRDBG_ADDR (REGS_SDMABP_BASE + 0x34)
#ifndef __LANGUAGE_ASM__
#define HW_SDMABP_EVTERRDBG (*(volatile hw_sdmabp_evterrdbg_t *) HW_SDMABP_EVTERRDBG_ADDR)
#define HW_SDMABP_EVTERRDBG_RD() (HW_SDMABP_EVTERRDBG.U)
#endif
//@}
/*
* constants & macros for individual SDMABP_EVTERRDBG bitfields
*/
/*! @name Register SDMABP_EVTERRDBG, field CHNERR[31:0] (RO)
*
* This register is the same as EVTERR except reading it does not clear its contents. This address
* is meant to be used in debug mode. The BP OnCE may check this register value without modifying
* it.
*/
//@{
#define BP_SDMABP_EVTERRDBG_CHNERR (0) //!< Bit position for SDMABP_EVTERRDBG_CHNERR.
#define BM_SDMABP_EVTERRDBG_CHNERR (0xffffffff) //!< Bit mask for SDMABP_EVTERRDBG_CHNERR.
//! @brief Get value of SDMABP_EVTERRDBG_CHNERR from a register value.
#define BG_SDMABP_EVTERRDBG_CHNERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_EVTERRDBG_CHNERR) >> BP_SDMABP_EVTERRDBG_CHNERR)
//@}
//-------------------------------------------------------------------------------------------
// hw_sdmabp_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All SDMABP module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_sdmabp
{
volatile hw_sdmabp_dc0ptr_t DC0PTR; //!< Channel 0 Pointer
volatile hw_sdmabp_intr_t INTR; //!< Channel Interrupts
volatile hw_sdmabp_stop_stat_t STOP_STAT; //!< Channel Stop/Channel Status
volatile hw_sdmabp_dstart_t DSTART; //!< Channel Start
reg32_t _reserved0[6];
volatile hw_sdmabp_evterr_t EVTERR; //!< DMA Request Error Register
volatile hw_sdmabp_intrmask_t INTRMASK; //!< Channel DSP Interrupt Mask
reg32_t _reserved1;
volatile hw_sdmabp_evterrdbg_t EVTERRDBG; //!< DMA Request Error Register
} hw_sdmabp_t;
#pragma pack()
//! @brief Macro to access all SDMABP registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_SDMABP</code>.
#define HW_SDMABP (*(hw_sdmabp_t *) REGS_SDMABP_BASE)
#endif
#endif // __HW_SDMABP_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_SJC_REGISTERS_H__
#define __HW_SJC_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ SJC
*
* SJC Registers
*
* Registers defined in this header file:
* - HW_SJC_GPUSR1 - General Purpose Unsecured Status Register 1
* - HW_SJC_GPUSR2 - General Purpose Unsecured Status Register 2
* - HW_SJC_GPUSR3 - General Purpose Unsecured Status Register 3
* - HW_SJC_GPSSR - General Purpose Secured Status Register
* - HW_SJC_DCR - Debug Control Register
* - HW_SJC_SSR - Security Status Register
* - HW_SJC_GPCCR - General Purpose Clocks Control Register
*
* - hw_sjc_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_SJC_BASE
#define HW_SJC_INSTANCE_COUNT (1) //!< Number of instances of the SJC module.
#define REGS_SJC_BASE (0x00000000) //!< Base address for SJC.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_SJC_GPUSR1 - General Purpose Unsecured Status Register 1
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SJC_GPUSR1 - General Purpose Unsecured Status Register 1 (RO)
*
* Reset value: 0x00000000
*
* The General Purpose Unsecured Status Register 1 is a read only registers used to check the status
* of the different Cores and of the PLL. The rest of its bits are for general purpose use.
*/
typedef union _hw_sjc_gpusr1
{
reg32_t U;
struct _hw_sjc_gpusr1_bitfields
{
unsigned A_DBG : 1; //!< [0] ARM core debug status bit
unsigned A_WFI : 1; //!< [1] ARM core wait-for interrupt bit
unsigned S_STAT : 3; //!< [4:2] 3 LSBits of SDMA core statusH.
unsigned RESERVED0 : 3; //!< [7:5] Reserved.
unsigned PLL_LOCK : 1; //!< [8] PLL_LOCK
unsigned RESERVED1 : 23; //!< [31:9] Reserved.
} B;
} hw_sjc_gpusr1_t;
#endif
/*!
* @name Constants and macros for entire SJC_GPUSR1 register
*/
//@{
#define HW_SJC_GPUSR1_ADDR (REGS_SJC_BASE + 0x0)
#ifndef __LANGUAGE_ASM__
#define HW_SJC_GPUSR1 (*(volatile hw_sjc_gpusr1_t *) HW_SJC_GPUSR1_ADDR)
#define HW_SJC_GPUSR1_RD() (HW_SJC_GPUSR1.U)
#endif
//@}
/*
* constants & macros for individual SJC_GPUSR1 bitfields
*/
/*! @name Register SJC_GPUSR1, field A_DBG[0] (RO)
*
* ARM core debug status bit Bit 0 is the ARM core DBGACK (debug acknowledge) DBGACK can be
* overwritten in the ARM core DCR to force a particular DBGACK value. Consequently interpretation
* of the DBGACK value is highly dependent on the debug sequence. When this bit is HIGH, ARM core is
* in debug.
*/
//@{
#define BP_SJC_GPUSR1_A_DBG (0) //!< Bit position for SJC_GPUSR1_A_DBG.
#define BM_SJC_GPUSR1_A_DBG (0x00000001) //!< Bit mask for SJC_GPUSR1_A_DBG.
//! @brief Get value of SJC_GPUSR1_A_DBG from a register value.
#define BG_SJC_GPUSR1_A_DBG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_GPUSR1_A_DBG) >> BP_SJC_GPUSR1_A_DBG)
//@}
/*! @name Register SJC_GPUSR1, field A_WFI[1] (RO)
*
* ARM core wait-for interrupt bit Bit 1 is the ARM core standbywfi (stand by wait-for interrupt).
* When this bit is HIGH, ARM core is in wait for interrupt mode.
*/
//@{
#define BP_SJC_GPUSR1_A_WFI (1) //!< Bit position for SJC_GPUSR1_A_WFI.
#define BM_SJC_GPUSR1_A_WFI (0x00000002) //!< Bit mask for SJC_GPUSR1_A_WFI.
//! @brief Get value of SJC_GPUSR1_A_WFI from a register value.
#define BG_SJC_GPUSR1_A_WFI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_GPUSR1_A_WFI) >> BP_SJC_GPUSR1_A_WFI)
//@}
/*! @name Register SJC_GPUSR1, field S_STAT[4:2] (RO)
*
* 3 LSBits of SDMA core statusH.
*/
//@{
#define BP_SJC_GPUSR1_S_STAT (2) //!< Bit position for SJC_GPUSR1_S_STAT.
#define BM_SJC_GPUSR1_S_STAT (0x0000001c) //!< Bit mask for SJC_GPUSR1_S_STAT.
//! @brief Get value of SJC_GPUSR1_S_STAT from a register value.
#define BG_SJC_GPUSR1_S_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_GPUSR1_S_STAT) >> BP_SJC_GPUSR1_S_STAT)
//@}
/*! @name Register SJC_GPUSR1, field PLL_LOCK[8] (RO)
*
* PLL_LOCK A Combined PLL-Lock flag indicator, for all the PLL's.
*/
//@{
#define BP_SJC_GPUSR1_PLL_LOCK (8) //!< Bit position for SJC_GPUSR1_PLL_LOCK.
#define BM_SJC_GPUSR1_PLL_LOCK (0x00000100) //!< Bit mask for SJC_GPUSR1_PLL_LOCK.
//! @brief Get value of SJC_GPUSR1_PLL_LOCK from a register value.
#define BG_SJC_GPUSR1_PLL_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_GPUSR1_PLL_LOCK) >> BP_SJC_GPUSR1_PLL_LOCK)
//@}
//-------------------------------------------------------------------------------------------
// HW_SJC_GPUSR2 - General Purpose Unsecured Status Register 2
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SJC_GPUSR2 - General Purpose Unsecured Status Register 2 (RO)
*
* Reset value: 0x00000000
*/
typedef union _hw_sjc_gpusr2
{
reg32_t U;
struct _hw_sjc_gpusr2_bitfields
{
unsigned STBYWFI : 4; //!< [3:0] STBYWFI[3:0]
unsigned S_STAT : 4; //!< [7:4] S_STAT[3:0]
unsigned STBYWFE : 4; //!< [11:8] STBYWFE[3:0]
unsigned RESERVED0 : 20; //!< [31:12] Reserved
} B;
} hw_sjc_gpusr2_t;
#endif
/*!
* @name Constants and macros for entire SJC_GPUSR2 register
*/
//@{
#define HW_SJC_GPUSR2_ADDR (REGS_SJC_BASE + 0x1)
#ifndef __LANGUAGE_ASM__
#define HW_SJC_GPUSR2 (*(volatile hw_sjc_gpusr2_t *) HW_SJC_GPUSR2_ADDR)
#define HW_SJC_GPUSR2_RD() (HW_SJC_GPUSR2.U)
#endif
//@}
/*
* constants & macros for individual SJC_GPUSR2 bitfields
*/
/*! @name Register SJC_GPUSR2, field STBYWFI[3:0] (RO)
*
* STBYWFI[3:0] These bits provide status of "Standby Wait-For-Interrupt" state of all ARM cores.
*/
//@{
#define BP_SJC_GPUSR2_STBYWFI (0) //!< Bit position for SJC_GPUSR2_STBYWFI.
#define BM_SJC_GPUSR2_STBYWFI (0x0000000f) //!< Bit mask for SJC_GPUSR2_STBYWFI.
//! @brief Get value of SJC_GPUSR2_STBYWFI from a register value.
#define BG_SJC_GPUSR2_STBYWFI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_GPUSR2_STBYWFI) >> BP_SJC_GPUSR2_STBYWFI)
//@}
/*! @name Register SJC_GPUSR2, field S_STAT[7:4] (RO)
*
* S_STAT[3:0] SDMA debug status bits: debug_core_state[3:0]
*/
//@{
#define BP_SJC_GPUSR2_S_STAT (4) //!< Bit position for SJC_GPUSR2_S_STAT.
#define BM_SJC_GPUSR2_S_STAT (0x000000f0) //!< Bit mask for SJC_GPUSR2_S_STAT.
//! @brief Get value of SJC_GPUSR2_S_STAT from a register value.
#define BG_SJC_GPUSR2_S_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_GPUSR2_S_STAT) >> BP_SJC_GPUSR2_S_STAT)
//@}
/*! @name Register SJC_GPUSR2, field STBYWFE[11:8] (RO)
*
* STBYWFE[3:0] Reflecting the "Standby Wait For Event" signals of all cores.
*/
//@{
#define BP_SJC_GPUSR2_STBYWFE (8) //!< Bit position for SJC_GPUSR2_STBYWFE.
#define BM_SJC_GPUSR2_STBYWFE (0x00000f00) //!< Bit mask for SJC_GPUSR2_STBYWFE.
//! @brief Get value of SJC_GPUSR2_STBYWFE from a register value.
#define BG_SJC_GPUSR2_STBYWFE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_GPUSR2_STBYWFE) >> BP_SJC_GPUSR2_STBYWFE)
//@}
//-------------------------------------------------------------------------------------------
// HW_SJC_GPUSR3 - General Purpose Unsecured Status Register 3
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SJC_GPUSR3 - General Purpose Unsecured Status Register 3 (RO)
*
* Reset value: 0x00000000
*/
typedef union _hw_sjc_gpusr3
{
reg32_t U;
struct _hw_sjc_gpusr3_bitfields
{
unsigned IPG_WAIT : 1; //!< [0] IPG_WAIT
unsigned IPG_STOP : 1; //!< [1] IPG_STOP
unsigned SYS_WAIT : 1; //!< [2] System In wait
unsigned RESERVED0 : 29; //!< [31:3] Reserved
} B;
} hw_sjc_gpusr3_t;
#endif
/*!
* @name Constants and macros for entire SJC_GPUSR3 register
*/
//@{
#define HW_SJC_GPUSR3_ADDR (REGS_SJC_BASE + 0x2)
#ifndef __LANGUAGE_ASM__
#define HW_SJC_GPUSR3 (*(volatile hw_sjc_gpusr3_t *) HW_SJC_GPUSR3_ADDR)
#define HW_SJC_GPUSR3_RD() (HW_SJC_GPUSR3.U)
#endif
//@}
/*
* constants & macros for individual SJC_GPUSR3 bitfields
*/
/*! @name Register SJC_GPUSR3, field IPG_WAIT[0] (RO)
*
* IPG_WAIT CCM's "ipg_wait" signal indication
*/
//@{
#define BP_SJC_GPUSR3_IPG_WAIT (0) //!< Bit position for SJC_GPUSR3_IPG_WAIT.
#define BM_SJC_GPUSR3_IPG_WAIT (0x00000001) //!< Bit mask for SJC_GPUSR3_IPG_WAIT.
//! @brief Get value of SJC_GPUSR3_IPG_WAIT from a register value.
#define BG_SJC_GPUSR3_IPG_WAIT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_GPUSR3_IPG_WAIT) >> BP_SJC_GPUSR3_IPG_WAIT)
//@}
/*! @name Register SJC_GPUSR3, field IPG_STOP[1] (RO)
*
* IPG_STOP CCM's "ipg_stop" signal indication
*/
//@{
#define BP_SJC_GPUSR3_IPG_STOP (1) //!< Bit position for SJC_GPUSR3_IPG_STOP.
#define BM_SJC_GPUSR3_IPG_STOP (0x00000002) //!< Bit mask for SJC_GPUSR3_IPG_STOP.
//! @brief Get value of SJC_GPUSR3_IPG_STOP from a register value.
#define BG_SJC_GPUSR3_IPG_STOP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_GPUSR3_IPG_STOP) >> BP_SJC_GPUSR3_IPG_STOP)
//@}
/*! @name Register SJC_GPUSR3, field SYS_WAIT[2] (RO)
*
* System In wait Indication on System in wait mode (from CCM).
*/
//@{
#define BP_SJC_GPUSR3_SYS_WAIT (2) //!< Bit position for SJC_GPUSR3_SYS_WAIT.
#define BM_SJC_GPUSR3_SYS_WAIT (0x00000004) //!< Bit mask for SJC_GPUSR3_SYS_WAIT.
//! @brief Get value of SJC_GPUSR3_SYS_WAIT from a register value.
#define BG_SJC_GPUSR3_SYS_WAIT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_GPUSR3_SYS_WAIT) >> BP_SJC_GPUSR3_SYS_WAIT)
//@}
//-------------------------------------------------------------------------------------------
// HW_SJC_GPSSR - General Purpose Secured Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SJC_GPSSR - General Purpose Secured Status Register (RO)
*
* Reset value: 0x00000000
*
* The General Purpose Secured Status Register is a read-only register used to check the status of
* the different critical information in the SoC. This register cannot be accessed in secure modes.
*/
typedef union _hw_sjc_gpssr
{
reg32_t U;
struct _hw_sjc_gpssr_bitfields
{
unsigned GPSSR : 32; //!< [31:0] General Purpose Secured Status Register
} B;
} hw_sjc_gpssr_t;
#endif
/*!
* @name Constants and macros for entire SJC_GPSSR register
*/
//@{
#define HW_SJC_GPSSR_ADDR (REGS_SJC_BASE + 0x3)
#ifndef __LANGUAGE_ASM__
#define HW_SJC_GPSSR (*(volatile hw_sjc_gpssr_t *) HW_SJC_GPSSR_ADDR)
#define HW_SJC_GPSSR_RD() (HW_SJC_GPSSR.U)
#endif
//@}
/*
* constants & macros for individual SJC_GPSSR bitfields
*/
/*! @name Register SJC_GPSSR, field GPSSR[31:0] (RO)
*
* General Purpose Secured Status Register Register is used for testing and debug.
*/
//@{
#define BP_SJC_GPSSR_GPSSR (0) //!< Bit position for SJC_GPSSR_GPSSR.
#define BM_SJC_GPSSR_GPSSR (0xffffffff) //!< Bit mask for SJC_GPSSR_GPSSR.
//! @brief Get value of SJC_GPSSR_GPSSR from a register value.
#define BG_SJC_GPSSR_GPSSR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_GPSSR_GPSSR) >> BP_SJC_GPSSR_GPSSR)
//@}
//-------------------------------------------------------------------------------------------
// HW_SJC_DCR - Debug Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SJC_DCR - Debug Control Register (RW)
*
* Reset value: 0x00000000
*
* This register is used to control propagation of debug request from DE_B pad to the cores and
* debug signals from internal logic to the DE_B pad.
*/
typedef union _hw_sjc_dcr
{
reg32_t U;
struct _hw_sjc_dcr_bitfields
{
unsigned DE_TO_ARM : 1; //!< [0] ARM platform debug request input propagation
unsigned DE_TO_SDMA : 1; //!< [1] SDMA debug request input propagation
unsigned RESERVED0 : 1; //!< [2] Reserved
unsigned DEBUG_OBS : 1; //!< [3] Debug observability
unsigned RESERVED1 : 1; //!< [4] Reserved
unsigned DIRECT_SDMA_REQ_EN : 1; //!< [5] Debug enable of the sdma debug request
unsigned DIRECT_ARM_REQ_EN : 1; //!< [6] Pass Debug Enable event from DE_B pin to ARM platform debug request signal(s).
unsigned RESERVED2 : 25; //!< [31:7] Reserved
} B;
} hw_sjc_dcr_t;
#endif
/*!
* @name Constants and macros for entire SJC_DCR register
*/
//@{
#define HW_SJC_DCR_ADDR (REGS_SJC_BASE + 0x4)
#ifndef __LANGUAGE_ASM__
#define HW_SJC_DCR (*(volatile hw_sjc_dcr_t *) HW_SJC_DCR_ADDR)
#define HW_SJC_DCR_RD() (HW_SJC_DCR.U)
#define HW_SJC_DCR_WR(v) (HW_SJC_DCR.U = (v))
#define HW_SJC_DCR_SET(v) (HW_SJC_DCR_WR(HW_SJC_DCR_RD() | (v)))
#define HW_SJC_DCR_CLR(v) (HW_SJC_DCR_WR(HW_SJC_DCR_RD() & ~(v)))
#define HW_SJC_DCR_TOG(v) (HW_SJC_DCR_WR(HW_SJC_DCR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual SJC_DCR bitfields
*/
/*! @name Register SJC_DCR, field DE_TO_ARM[0] (RW)
*
* ARM platform debug request input propagation This bit controls the propagation of debug request
* to ARM platform ("dbgreq"), when the JTAG state machine is put in "ENTER_DEBUG" IR instruction.
*
* Values:
* - 0 - Disable propagation of debug request to ARM platform
* - 1 - Enable propagation of debug request to ARM platform
*/
//@{
#define BP_SJC_DCR_DE_TO_ARM (0) //!< Bit position for SJC_DCR_DE_TO_ARM.
#define BM_SJC_DCR_DE_TO_ARM (0x00000001) //!< Bit mask for SJC_DCR_DE_TO_ARM.
//! @brief Get value of SJC_DCR_DE_TO_ARM from a register value.
#define BG_SJC_DCR_DE_TO_ARM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_DCR_DE_TO_ARM) >> BP_SJC_DCR_DE_TO_ARM)
//! @brief Format value for bitfield SJC_DCR_DE_TO_ARM.
#define BF_SJC_DCR_DE_TO_ARM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SJC_DCR_DE_TO_ARM) & BM_SJC_DCR_DE_TO_ARM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DE_TO_ARM field to a new value.
#define BW_SJC_DCR_DE_TO_ARM(v) (HW_SJC_DCR_WR((HW_SJC_DCR_RD() & ~BM_SJC_DCR_DE_TO_ARM) | BF_SJC_DCR_DE_TO_ARM(v)))
#endif
//@}
/*! @name Register SJC_DCR, field DE_TO_SDMA[1] (RW)
*
* SDMA debug request input propagation This bit controls the propagation of debug request to SDMA,
* when the JTAG state machine is put in "ENTER_DEBUG" IR instruction..
*
* Values:
* - 0 - Disable propagation of debug request to SDMA
* - 1 - Enable propagation of debug request to SDMA
*/
//@{
#define BP_SJC_DCR_DE_TO_SDMA (1) //!< Bit position for SJC_DCR_DE_TO_SDMA.
#define BM_SJC_DCR_DE_TO_SDMA (0x00000002) //!< Bit mask for SJC_DCR_DE_TO_SDMA.
//! @brief Get value of SJC_DCR_DE_TO_SDMA from a register value.
#define BG_SJC_DCR_DE_TO_SDMA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_DCR_DE_TO_SDMA) >> BP_SJC_DCR_DE_TO_SDMA)
//! @brief Format value for bitfield SJC_DCR_DE_TO_SDMA.
#define BF_SJC_DCR_DE_TO_SDMA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SJC_DCR_DE_TO_SDMA) & BM_SJC_DCR_DE_TO_SDMA)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DE_TO_SDMA field to a new value.
#define BW_SJC_DCR_DE_TO_SDMA(v) (HW_SJC_DCR_WR((HW_SJC_DCR_RD() & ~BM_SJC_DCR_DE_TO_SDMA) | BF_SJC_DCR_DE_TO_SDMA(v)))
#endif
//@}
/*! @name Register SJC_DCR, field DEBUG_OBS[3] (RW)
*
* Debug observability This bit controls the propagation of the "system debug" input to SJC For i.MX
* 6x, the SJC's "system_debug" input is tied to logic HIGH value, therefore, set of "debug_obs"
* bit, will result in unconditional assertion of DE_B pad.
*
* Values:
* - 0 - Disable propagation of system debug to DE pin
* - 1 - unconditional assertion of pad. DE_B
*/
//@{
#define BP_SJC_DCR_DEBUG_OBS (3) //!< Bit position for SJC_DCR_DEBUG_OBS.
#define BM_SJC_DCR_DEBUG_OBS (0x00000008) //!< Bit mask for SJC_DCR_DEBUG_OBS.
//! @brief Get value of SJC_DCR_DEBUG_OBS from a register value.
#define BG_SJC_DCR_DEBUG_OBS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_DCR_DEBUG_OBS) >> BP_SJC_DCR_DEBUG_OBS)
//! @brief Format value for bitfield SJC_DCR_DEBUG_OBS.
#define BF_SJC_DCR_DEBUG_OBS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SJC_DCR_DEBUG_OBS) & BM_SJC_DCR_DEBUG_OBS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DEBUG_OBS field to a new value.
#define BW_SJC_DCR_DEBUG_OBS(v) (HW_SJC_DCR_WR((HW_SJC_DCR_RD() & ~BM_SJC_DCR_DEBUG_OBS) | BF_SJC_DCR_DEBUG_OBS(v)))
#endif
//@}
/*! @name Register SJC_DCR, field DIRECT_SDMA_REQ_EN[5] (RW)
*
* Debug enable of the sdma debug request This bit controls the propagation of debug request DE_B to
* the sdma.
*
* Values:
* - 0 - Disable propagation of system debug to (DE pin) to sdma.
* - 1 - Enable propagation of system debug to (DE pin) to sdma.
*/
//@{
#define BP_SJC_DCR_DIRECT_SDMA_REQ_EN (5) //!< Bit position for SJC_DCR_DIRECT_SDMA_REQ_EN.
#define BM_SJC_DCR_DIRECT_SDMA_REQ_EN (0x00000020) //!< Bit mask for SJC_DCR_DIRECT_SDMA_REQ_EN.
//! @brief Get value of SJC_DCR_DIRECT_SDMA_REQ_EN from a register value.
#define BG_SJC_DCR_DIRECT_SDMA_REQ_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_DCR_DIRECT_SDMA_REQ_EN) >> BP_SJC_DCR_DIRECT_SDMA_REQ_EN)
//! @brief Format value for bitfield SJC_DCR_DIRECT_SDMA_REQ_EN.
#define BF_SJC_DCR_DIRECT_SDMA_REQ_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SJC_DCR_DIRECT_SDMA_REQ_EN) & BM_SJC_DCR_DIRECT_SDMA_REQ_EN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DIRECT_SDMA_REQ_EN field to a new value.
#define BW_SJC_DCR_DIRECT_SDMA_REQ_EN(v) (HW_SJC_DCR_WR((HW_SJC_DCR_RD() & ~BM_SJC_DCR_DIRECT_SDMA_REQ_EN) | BF_SJC_DCR_DIRECT_SDMA_REQ_EN(v)))
#endif
//@}
/*! @name Register SJC_DCR, field DIRECT_ARM_REQ_EN[6] (RW)
*
* Pass Debug Enable event from DE_B pin to ARM platform debug request signal(s). This bit controls
* the propagation of debug request DE_B to the Arm platform.
*
* Values:
* - 0 - Disable propagation of system debug to (DE pin) to Arm platform.
* - 1 - Enable propagation of system debug to (DE pin) to Arm platform.
*/
//@{
#define BP_SJC_DCR_DIRECT_ARM_REQ_EN (6) //!< Bit position for SJC_DCR_DIRECT_ARM_REQ_EN.
#define BM_SJC_DCR_DIRECT_ARM_REQ_EN (0x00000040) //!< Bit mask for SJC_DCR_DIRECT_ARM_REQ_EN.
//! @brief Get value of SJC_DCR_DIRECT_ARM_REQ_EN from a register value.
#define BG_SJC_DCR_DIRECT_ARM_REQ_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_DCR_DIRECT_ARM_REQ_EN) >> BP_SJC_DCR_DIRECT_ARM_REQ_EN)
//! @brief Format value for bitfield SJC_DCR_DIRECT_ARM_REQ_EN.
#define BF_SJC_DCR_DIRECT_ARM_REQ_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SJC_DCR_DIRECT_ARM_REQ_EN) & BM_SJC_DCR_DIRECT_ARM_REQ_EN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DIRECT_ARM_REQ_EN field to a new value.
#define BW_SJC_DCR_DIRECT_ARM_REQ_EN(v) (HW_SJC_DCR_WR((HW_SJC_DCR_RD() & ~BM_SJC_DCR_DIRECT_ARM_REQ_EN) | BF_SJC_DCR_DIRECT_ARM_REQ_EN(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_SJC_SSR - Security Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SJC_SSR - Security Status Register (RO)
*
* Reset value: 0x100eeeaeefeceaecaeadefedbafade10feeeebfeddecfdeaadae
*/
typedef union _hw_sjc_ssr
{
reg32_t U;
struct _hw_sjc_ssr_bitfields
{
unsigned KTF : 1; //!< [0] Kill Trace Enable fuse value
unsigned KTA : 1; //!< [1] Kill Trace is active
unsigned SWF : 1; //!< [2] Software JTAG enable fuse
unsigned SWE : 1; //!< [3] SW enable
unsigned EBF : 1; //!< [4] External Boot fuse
unsigned EBG : 1; //!< [5] External boot granted
unsigned RESERVED0 : 2; //!< [7:6] Reserved.
unsigned FT : 1; //!< [8] Fuse type
unsigned SJM : 2; //!< [10:9] SJC Secure mode
unsigned RSSTAT : 2; //!< [12:11] Response status
unsigned RESERVED1 : 1; //!< [13] Reserved
unsigned BOOTIND : 1; //!< [14] Boot Indication
unsigned RESERVED2 : 17; //!< [31:15] Reserved.
} B;
} hw_sjc_ssr_t;
#endif
/*!
* @name Constants and macros for entire SJC_SSR register
*/
//@{
#define HW_SJC_SSR_ADDR (REGS_SJC_BASE + 0x5)
#ifndef __LANGUAGE_ASM__
#define HW_SJC_SSR (*(volatile hw_sjc_ssr_t *) HW_SJC_SSR_ADDR)
#define HW_SJC_SSR_RD() (HW_SJC_SSR.U)
#endif
//@}
/*
* constants & macros for individual SJC_SSR bitfields
*/
/*! @name Register SJC_SSR, field KTF[0] (RO)
*
* Kill Trace Enable fuse value
*
* Values:
* - 0 - (intact) - kill trace is never active
* - 1 - (burned) - kill trace functionality enabled
*/
//@{
#define BP_SJC_SSR_KTF (0) //!< Bit position for SJC_SSR_KTF.
#define BM_SJC_SSR_KTF (0x00000001) //!< Bit mask for SJC_SSR_KTF.
//! @brief Get value of SJC_SSR_KTF from a register value.
#define BG_SJC_SSR_KTF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_SSR_KTF) >> BP_SJC_SSR_KTF)
//@}
/*! @name Register SJC_SSR, field KTA[1] (RO)
*
* Kill Trace is active
*
* Values:
* - 0 - not active
* - 1 - active
*/
//@{
#define BP_SJC_SSR_KTA (1) //!< Bit position for SJC_SSR_KTA.
#define BM_SJC_SSR_KTA (0x00000002) //!< Bit mask for SJC_SSR_KTA.
//! @brief Get value of SJC_SSR_KTA from a register value.
#define BG_SJC_SSR_KTA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_SSR_KTA) >> BP_SJC_SSR_KTA)
//@}
/*! @name Register SJC_SSR, field SWF[2] (RO)
*
* Software JTAG enable fuse Status of the no SW disable JTAG fuse
*
* Values:
* - 0 - (intact) - SW enable possible
* - 1 - (intact) - no SW enable possible
*/
//@{
#define BP_SJC_SSR_SWF (2) //!< Bit position for SJC_SSR_SWF.
#define BM_SJC_SSR_SWF (0x00000004) //!< Bit mask for SJC_SSR_SWF.
//! @brief Get value of SJC_SSR_SWF from a register value.
#define BG_SJC_SSR_SWF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_SSR_SWF) >> BP_SJC_SSR_SWF)
//@}
/*! @name Register SJC_SSR, field SWE[3] (RO)
*
* SW enable SW JTAG enable status
*
* Values:
* - 0 - disabled
* - 1 - enabled
*/
//@{
#define BP_SJC_SSR_SWE (3) //!< Bit position for SJC_SSR_SWE.
#define BM_SJC_SSR_SWE (0x00000008) //!< Bit mask for SJC_SSR_SWE.
//! @brief Get value of SJC_SSR_SWE from a register value.
#define BG_SJC_SSR_SWE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_SSR_SWE) >> BP_SJC_SSR_SWE)
//@}
/*! @name Register SJC_SSR, field EBF[4] (RO)
*
* External Boot fuse Status of the external boot disable fuse
*
* Values:
* - 0 - (intact) - external boot is allowed
* - 1 - (burned) - external boot is disabled
*/
//@{
#define BP_SJC_SSR_EBF (4) //!< Bit position for SJC_SSR_EBF.
#define BM_SJC_SSR_EBF (0x00000010) //!< Bit mask for SJC_SSR_EBF.
//! @brief Get value of SJC_SSR_EBF from a register value.
#define BG_SJC_SSR_EBF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_SSR_EBF) >> BP_SJC_SSR_EBF)
//@}
/*! @name Register SJC_SSR, field EBG[5] (RO)
*
* External boot granted External boot enabled, requested and granted
*
* Values:
* - 0 - not granted
* - 1 - granted
*/
//@{
#define BP_SJC_SSR_EBG (5) //!< Bit position for SJC_SSR_EBG.
#define BM_SJC_SSR_EBG (0x00000020) //!< Bit mask for SJC_SSR_EBG.
//! @brief Get value of SJC_SSR_EBG from a register value.
#define BG_SJC_SSR_EBG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_SSR_EBG) >> BP_SJC_SSR_EBG)
//@}
/*! @name Register SJC_SSR, field FT[8] (RO)
*
* Fuse type Fuse type bit - e-fuse or laser fuse
*
* Values:
* - 0 - E-fuse technology
* - 1 - Laser fuse technology
*/
//@{
#define BP_SJC_SSR_FT (8) //!< Bit position for SJC_SSR_FT.
#define BM_SJC_SSR_FT (0x00000100) //!< Bit mask for SJC_SSR_FT.
//! @brief Get value of SJC_SSR_FT from a register value.
#define BG_SJC_SSR_FT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_SSR_FT) >> BP_SJC_SSR_FT)
//@}
/*! @name Register SJC_SSR, field SJM[10:9] (RO)
*
* SJC Secure mode Secure JTAG mode, as set by external fuses.
*
* Values:
* - 00 - No debug (#1)
* - 01 - Secure JTAG (#2)
* - 10 - Reserved
* - 11 - JTAG enabled (#3)
*/
//@{
#define BP_SJC_SSR_SJM (9) //!< Bit position for SJC_SSR_SJM.
#define BM_SJC_SSR_SJM (0x00000600) //!< Bit mask for SJC_SSR_SJM.
//! @brief Get value of SJC_SSR_SJM from a register value.
#define BG_SJC_SSR_SJM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_SSR_SJM) >> BP_SJC_SSR_SJM)
//@}
/*! @name Register SJC_SSR, field RSSTAT[12:11] (RO)
*
* Response status Response status bits
*
* Values:
* - 00 - Response wasn't entered
* - 01 - Response was entered but not verified
* - 10 - Response was entered and is incorrect
* - 11 - Response is correct
*/
//@{
#define BP_SJC_SSR_RSSTAT (11) //!< Bit position for SJC_SSR_RSSTAT.
#define BM_SJC_SSR_RSSTAT (0x00001800) //!< Bit mask for SJC_SSR_RSSTAT.
//! @brief Get value of SJC_SSR_RSSTAT from a register value.
#define BG_SJC_SSR_RSSTAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_SSR_RSSTAT) >> BP_SJC_SSR_RSSTAT)
//@}
/*! @name Register SJC_SSR, field BOOTIND[14] (RO)
*
* Boot Indication Inverted Internal Boot indication, i.e inverse of SRC: "src_int_boot" signal
*/
//@{
#define BP_SJC_SSR_BOOTIND (14) //!< Bit position for SJC_SSR_BOOTIND.
#define BM_SJC_SSR_BOOTIND (0x00004000) //!< Bit mask for SJC_SSR_BOOTIND.
//! @brief Get value of SJC_SSR_BOOTIND from a register value.
#define BG_SJC_SSR_BOOTIND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_SSR_BOOTIND) >> BP_SJC_SSR_BOOTIND)
//@}
//-------------------------------------------------------------------------------------------
// HW_SJC_GPCCR - General Purpose Clocks Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SJC_GPCCR - General Purpose Clocks Control Register (RW)
*
* Reset value: 0x00000000
*
* This register is used to configure clock related modes in SOC, see System Configuration chapter
* for more information. Those bits are directly connected to JTAG outputs. Bit 0 of GPCCR controls
* SDMA clocks invocation. When out of reset, the SDMA is in sleep mode with no SDMA clock running.
* Unlike events, debug requests does not wake SDMA if it is in sleep mode. The debug request is
* recognized by the SDMA only when it exits sleep mode upon reception of an event. To be able to
* enter debug mode even if no event is triggered, the SDMA clock on bit needs to be set prior to
* sending the debug request (clear at reset).
*/
typedef union _hw_sjc_gpccr
{
reg32_t U;
struct _hw_sjc_gpccr_bitfields
{
unsigned SCLKR : 1; //!< [0] SDMA Clock ON Register - This bit forces the clock on of the SDMA
unsigned ACLKOFFDIS : 1; //!< [1] Disable/prevent ARM platform clock/power shutdown
unsigned RESERVED0 : 30; //!< [31:2] Reserved
} B;
} hw_sjc_gpccr_t;
#endif
/*!
* @name Constants and macros for entire SJC_GPCCR register
*/
//@{
#define HW_SJC_GPCCR_ADDR (REGS_SJC_BASE + 0x7)
#ifndef __LANGUAGE_ASM__
#define HW_SJC_GPCCR (*(volatile hw_sjc_gpccr_t *) HW_SJC_GPCCR_ADDR)
#define HW_SJC_GPCCR_RD() (HW_SJC_GPCCR.U)
#define HW_SJC_GPCCR_WR(v) (HW_SJC_GPCCR.U = (v))
#define HW_SJC_GPCCR_SET(v) (HW_SJC_GPCCR_WR(HW_SJC_GPCCR_RD() | (v)))
#define HW_SJC_GPCCR_CLR(v) (HW_SJC_GPCCR_WR(HW_SJC_GPCCR_RD() & ~(v)))
#define HW_SJC_GPCCR_TOG(v) (HW_SJC_GPCCR_WR(HW_SJC_GPCCR_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual SJC_GPCCR bitfields
*/
/*! @name Register SJC_GPCCR, field SCLKR[0] (RW)
*
* SDMA Clock ON Register - This bit forces the clock on of the SDMA
*/
//@{
#define BP_SJC_GPCCR_SCLKR (0) //!< Bit position for SJC_GPCCR_SCLKR.
#define BM_SJC_GPCCR_SCLKR (0x00000001) //!< Bit mask for SJC_GPCCR_SCLKR.
//! @brief Get value of SJC_GPCCR_SCLKR from a register value.
#define BG_SJC_GPCCR_SCLKR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_GPCCR_SCLKR) >> BP_SJC_GPCCR_SCLKR)
//! @brief Format value for bitfield SJC_GPCCR_SCLKR.
#define BF_SJC_GPCCR_SCLKR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SJC_GPCCR_SCLKR) & BM_SJC_GPCCR_SCLKR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SCLKR field to a new value.
#define BW_SJC_GPCCR_SCLKR(v) (HW_SJC_GPCCR_WR((HW_SJC_GPCCR_RD() & ~BM_SJC_GPCCR_SCLKR) | BF_SJC_GPCCR_SCLKR(v)))
#endif
//@}
/*! @name Register SJC_GPCCR, field ACLKOFFDIS[1] (RW)
*
* Disable/prevent ARM platform clock/power shutdown
*/
//@{
#define BP_SJC_GPCCR_ACLKOFFDIS (1) //!< Bit position for SJC_GPCCR_ACLKOFFDIS.
#define BM_SJC_GPCCR_ACLKOFFDIS (0x00000002) //!< Bit mask for SJC_GPCCR_ACLKOFFDIS.
//! @brief Get value of SJC_GPCCR_ACLKOFFDIS from a register value.
#define BG_SJC_GPCCR_ACLKOFFDIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SJC_GPCCR_ACLKOFFDIS) >> BP_SJC_GPCCR_ACLKOFFDIS)
//! @brief Format value for bitfield SJC_GPCCR_ACLKOFFDIS.
#define BF_SJC_GPCCR_ACLKOFFDIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SJC_GPCCR_ACLKOFFDIS) & BM_SJC_GPCCR_ACLKOFFDIS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ACLKOFFDIS field to a new value.
#define BW_SJC_GPCCR_ACLKOFFDIS(v) (HW_SJC_GPCCR_WR((HW_SJC_GPCCR_RD() & ~BM_SJC_GPCCR_ACLKOFFDIS) | BF_SJC_GPCCR_ACLKOFFDIS(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_sjc_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All SJC module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_sjc
{
volatile hw_sjc_gpusr1_t GPUSR1; //!< General Purpose Unsecured Status Register 1
volatile hw_sjc_gpusr2_t GPUSR2; //!< General Purpose Unsecured Status Register 2
volatile hw_sjc_gpusr3_t GPUSR3; //!< General Purpose Unsecured Status Register 3
volatile hw_sjc_gpssr_t GPSSR; //!< General Purpose Secured Status Register
volatile hw_sjc_dcr_t DCR; //!< Debug Control Register
volatile hw_sjc_ssr_t SSR; //!< Security Status Register
volatile hw_sjc_gpccr_t GPCCR; //!< General Purpose Clocks Control Register
} hw_sjc_t;
#pragma pack()
//! @brief Macro to access all SJC registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_SJC</code>.
#define HW_SJC (*(hw_sjc_t *) REGS_SJC_BASE)
#endif
#endif // __HW_SJC_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_SPBA_REGISTERS_H__
#define __HW_SPBA_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ SPBA
*
* Temperature Monitor
*
* Registers defined in this header file:
* - HW_SPBA_PRRn - Peripheral Rights Register
*
* - hw_spba_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_SPBA_BASE
#define HW_SPBA_INSTANCE_COUNT (1) //!< Number of instances of the SPBA module.
#define REGS_SPBA_BASE (0x0203c000) //!< Base address for SPBA.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_SPBA_PRRn - Peripheral Rights Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SPBA_PRRn - Peripheral Rights Register (RW)
*
* Reset value: 0x00000007
*
* This register controls master ownership and access for a peripheral.
*/
typedef union _hw_spba_prrn
{
reg32_t U;
struct _hw_spba_prrn_bitfields
{
unsigned RARA : 1; //!< [0] Resource Access Right.
unsigned RARB : 1; //!< [1] Resource Access Right.
unsigned RARC : 1; //!< [2] Resource Access Right.
unsigned RESERVED0 : 13; //!< [15:3] Reserved
unsigned ROI : 2; //!< [17:16] Resource Owner ID.
unsigned RESERVED1 : 12; //!< [29:18] Reserved
unsigned RMO : 2; //!< [31:30] Requesting Master Owner.
} B;
} hw_spba_prrn_t;
#endif
/*!
* @name Constants and macros for entire SPBA_PRRn register
*/
//@{
//! @brief Number of instances of the SPBA_PRRn register.
#define HW_SPBA_PRRn_COUNT (32)
#define HW_SPBA_PRRn_ADDR(n) (REGS_SPBA_BASE + 0x0 + (0x4 * (n)))
#ifndef __LANGUAGE_ASM__
#define HW_SPBA_PRRn(n) (*(volatile hw_spba_prrn_t *) HW_SPBA_PRRn_ADDR(n))
#define HW_SPBA_PRRn_RD(n) (HW_SPBA_PRRn(n).U)
#define HW_SPBA_PRRn_WR(n, v) (HW_SPBA_PRRn(n).U = (v))
#define HW_SPBA_PRRn_SET(n, v) (HW_SPBA_PRRn_WR(n, HW_SPBA_PRRn_RD(n) | (v)))
#define HW_SPBA_PRRn_CLR(n, v) (HW_SPBA_PRRn_WR(n, HW_SPBA_PRRn_RD(n) & ~(v)))
#define HW_SPBA_PRRn_TOG(n, v) (HW_SPBA_PRRn_WR(n, HW_SPBA_PRRn_RD(n) ^ (v)))
#endif
//@}
/*
* constants & macros for individual SPBA_PRRn bitfields
*/
/*! @name Register SPBA_PRRn, field RARA[0] (RW)
*
* Resource Access Right. Control and Status bit for master A. This field indicates whether master A
* can access the peripheral. From 0 up to 3 masters can have permission to access a resource (all
* the master can be granted on a peripheral, but only one access at a time will be granted by
* SPBA).
*
* Values:
* - PROHIBITED = 0 - Access to peripheral is not allowed.
* - ALLOWED = 1 - Access to peripheral is granted.
*/
//@{
#define BP_SPBA_PRRn_RARA (0) //!< Bit position for SPBA_PRRn_RARA.
#define BM_SPBA_PRRn_RARA (0x00000001) //!< Bit mask for SPBA_PRRn_RARA.
//! @brief Get value of SPBA_PRRn_RARA from a register value.
#define BG_SPBA_PRRn_RARA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_RARA) >> BP_SPBA_PRRn_RARA)
//! @brief Format value for bitfield SPBA_PRRn_RARA.
#define BF_SPBA_PRRn_RARA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SPBA_PRRn_RARA) & BM_SPBA_PRRn_RARA)
#ifndef __LANGUAGE_ASM__
//! @brief Set the RARA field to a new value.
#define BW_SPBA_PRRn_RARA(n, v) (HW_SPBA_PRRn_WR(n, (HW_SPBA_PRRn_RD(n) & ~BM_SPBA_PRRn_RARA) | BF_SPBA_PRRn_RARA(v)))
#endif
//! @brief Macro to simplify usage of value macros.
#define BF_SPBA_PRRn_RARA_V(v) BF_SPBA_PRRn_RARA(BV_SPBA_PRRn_RARA__##v)
#define BV_SPBA_PRRn_RARA__PROHIBITED (0x0) //!< Access to peripheral is not allowed.
#define BV_SPBA_PRRn_RARA__ALLOWED (0x1) //!< Access to peripheral is granted.
//@}
/*! @name Register SPBA_PRRn, field RARB[1] (RW)
*
* Resource Access Right. Control and Status bit for master B. This field indicates whether master B
* can access the peripheral. From 0 up to 3 masters can have permission to access a resource (all
* the master can be granted on a peripheral, but only one access at a time will be granted by
* SPBA).
*
* Values:
* - PROHIBITED = 0 - Access to peripheral is not allowed.
* - ALLOWED = 1 - Access to peripheral is granted.
*/
//@{
#define BP_SPBA_PRRn_RARB (1) //!< Bit position for SPBA_PRRn_RARB.
#define BM_SPBA_PRRn_RARB (0x00000002) //!< Bit mask for SPBA_PRRn_RARB.
//! @brief Get value of SPBA_PRRn_RARB from a register value.
#define BG_SPBA_PRRn_RARB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_RARB) >> BP_SPBA_PRRn_RARB)
//! @brief Format value for bitfield SPBA_PRRn_RARB.
#define BF_SPBA_PRRn_RARB(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SPBA_PRRn_RARB) & BM_SPBA_PRRn_RARB)
#ifndef __LANGUAGE_ASM__
//! @brief Set the RARB field to a new value.
#define BW_SPBA_PRRn_RARB(n, v) (HW_SPBA_PRRn_WR(n, (HW_SPBA_PRRn_RD(n) & ~BM_SPBA_PRRn_RARB) | BF_SPBA_PRRn_RARB(v)))
#endif
//! @brief Macro to simplify usage of value macros.
#define BF_SPBA_PRRn_RARB_V(v) BF_SPBA_PRRn_RARB(BV_SPBA_PRRn_RARB__##v)
#define BV_SPBA_PRRn_RARB__PROHIBITED (0x0) //!< Access to peripheral is not allowed.
#define BV_SPBA_PRRn_RARB__ALLOWED (0x1) //!< Access to peripheral is granted.
//@}
/*! @name Register SPBA_PRRn, field RARC[2] (RW)
*
* Resource Access Right. Control and Status bit for master C. This field indicates whether master C
* can access the peripheral. From 0 up to 3 masters can have permission to access a resource (all
* the master can be granted on a peripheral, but only one access at a time will be granted by
* SPBA).
*
* Values:
* - PROHIBITED = 0 - Access to peripheral is not allowed.
* - ALLOWED = 1 - Access to peripheral is granted.
*/
//@{
#define BP_SPBA_PRRn_RARC (2) //!< Bit position for SPBA_PRRn_RARC.
#define BM_SPBA_PRRn_RARC (0x00000004) //!< Bit mask for SPBA_PRRn_RARC.
//! @brief Get value of SPBA_PRRn_RARC from a register value.
#define BG_SPBA_PRRn_RARC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_RARC) >> BP_SPBA_PRRn_RARC)
//! @brief Format value for bitfield SPBA_PRRn_RARC.
#define BF_SPBA_PRRn_RARC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SPBA_PRRn_RARC) & BM_SPBA_PRRn_RARC)
#ifndef __LANGUAGE_ASM__
//! @brief Set the RARC field to a new value.
#define BW_SPBA_PRRn_RARC(n, v) (HW_SPBA_PRRn_WR(n, (HW_SPBA_PRRn_RD(n) & ~BM_SPBA_PRRn_RARC) | BF_SPBA_PRRn_RARC(v)))
#endif
//! @brief Macro to simplify usage of value macros.
#define BF_SPBA_PRRn_RARC_V(v) BF_SPBA_PRRn_RARC(BV_SPBA_PRRn_RARC__##v)
#define BV_SPBA_PRRn_RARC__PROHIBITED (0x0) //!< Access to peripheral is not allowed.
#define BV_SPBA_PRRn_RARC__ALLOWED (0x1) //!< Access to peripheral is granted.
//@}
/*! @name Register SPBA_PRRn, field ROI[17:16] (RO)
*
* Resource Owner ID. This field indicates which master (one at a time) can access to the PRR for
* rights modification. This is a read-only register. After reset, ROI bits are cleared ("00" -> un-
* owned resource). A master performing a write access to the an un-owned PRR will get its ID
* automatically written into ROI, while modifying RARx bits. It can then read back the RMO, RAR,
* ROI bits to make sure RMO returns the right value, ROI bits contain its ID and RARx bits are
* correctly asserted. Then no other master (whom ID is different from the one stored in ROI) will
* be able to modify RAR fields. Owner master of a peripheral can assert its dead_owner signal, or
* write 1'b0 in the RARx to release the ownership (ROI[1:0] reset to 2'b0).
*
* Values:
* - UNOWNED = 00 - Unowned resource.
* - MASTER_A = 01 - The resource is owned by master A port.
* - MASTER_B = 10 - The resource is owned by master B port.
* - MASTER_C = 11 - The resource is owned by master C port.
*/
//@{
#define BP_SPBA_PRRn_ROI (16) //!< Bit position for SPBA_PRRn_ROI.
#define BM_SPBA_PRRn_ROI (0x00030000) //!< Bit mask for SPBA_PRRn_ROI.
//! @brief Get value of SPBA_PRRn_ROI from a register value.
#define BG_SPBA_PRRn_ROI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_ROI) >> BP_SPBA_PRRn_ROI)
//! @brief Macro to simplify usage of value macros.
#define BF_SPBA_PRRn_ROI_V(v) BF_SPBA_PRRn_ROI(BV_SPBA_PRRn_ROI__##v)
#define BV_SPBA_PRRn_ROI__UNOWNED (0x0) //!< Unowned resource.
#define BV_SPBA_PRRn_ROI__MASTER_A (0x1) //!< The resource is owned by master A port.
#define BV_SPBA_PRRn_ROI__MASTER_B (0x2) //!< The resource is owned by master B port.
#define BV_SPBA_PRRn_ROI__MASTER_C (0x3) //!< The resource is owned by master C port.
//@}
/*! @name Register SPBA_PRRn, field RMO[31:30] (RO)
*
* Requesting Master Owner. This 2-bit register field indicates if the corresponding resource is
* owned by the requesting master or not. This register is reset to 2'b0 if ROI = 2'b0.
*
* Values:
* - UNOWNED = 00 - The resource is unowned.
* - 01 - Reserved.
* - ANOTHER_MASTER = 10 - The resource is owned by another master.
* - REQUESTING_MASTER = 11 - The resource is owned by the requesting master.
*/
//@{
#define BP_SPBA_PRRn_RMO (30) //!< Bit position for SPBA_PRRn_RMO.
#define BM_SPBA_PRRn_RMO (0xc0000000) //!< Bit mask for SPBA_PRRn_RMO.
//! @brief Get value of SPBA_PRRn_RMO from a register value.
#define BG_SPBA_PRRn_RMO(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_RMO) >> BP_SPBA_PRRn_RMO)
//! @brief Macro to simplify usage of value macros.
#define BF_SPBA_PRRn_RMO_V(v) BF_SPBA_PRRn_RMO(BV_SPBA_PRRn_RMO__##v)
#define BV_SPBA_PRRn_RMO__UNOWNED (0x0) //!< The resource is unowned.
#define BV_SPBA_PRRn_RMO__ANOTHER_MASTER (0x2) //!< The resource is owned by another master.
#define BV_SPBA_PRRn_RMO__REQUESTING_MASTER (0x3) //!< The resource is owned by the requesting master.
//@}
//-------------------------------------------------------------------------------------------
// hw_spba_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All SPBA module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_spba
{
volatile hw_spba_prrn_t PRRn[32]; //!< Peripheral Rights Register
} hw_spba_t;
#pragma pack()
//! @brief Macro to access all SPBA registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_SPBA</code>.
#define HW_SPBA (*(hw_spba_t *) REGS_SPBA_BASE)
#endif
#endif // __HW_SPBA_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_TEMPMON_REGISTERS_H__
#define __HW_TEMPMON_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ TEMPMON
*
* Temperature Monitor
*
* Registers defined in this header file:
* - HW_TEMPMON_TEMPSENSE0 - Tempsensor Control Register 0
* - HW_TEMPMON_TEMPSENSE1 - Tempsensor Control Register 1
*
* - hw_tempmon_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_TEMPMON_BASE
#define HW_TEMPMON_INSTANCE_COUNT (1) //!< Number of instances of the TEMPMON module.
#define REGS_TEMPMON_BASE (0x020c8000) //!< Base address for TEMPMON.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_TEMPMON_TEMPSENSE0 - Tempsensor Control Register 0
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_TEMPMON_TEMPSENSE0 - Tempsensor Control Register 0 (RW)
*
* Reset value: 0x00000001
*
* This register defines the basic controls for the temperature sensor minus the frequency of
* automatic sampling which is defined in the tempsensor.
*/
typedef union _hw_tempmon_tempsense0
{
reg32_t U;
struct _hw_tempmon_tempsense0_bitfields
{
unsigned POWER_DOWN : 1; //!< [0] This bit powers down the temperature sensor.
unsigned MEASURE_TEMP : 1; //!< [1] Starts the measurement process.
unsigned FINISHED : 1; //!< [2] Indicates that the latest temp is valid.
unsigned RESERVED1 : 5; //!< [7:3] Reserved.
unsigned TEMP_CNT : 12; //!< [19:8] This bit field contains the last measured temperature count.
unsigned ALARM_VALUE : 12; //!< [31:20] This bit field contains the temperature count (raw sensor output) that will generate an alarm interrupt.
} B;
} hw_tempmon_tempsense0_t;
#endif
/*!
* @name Constants and macros for entire TEMPMON_TEMPSENSE0 register
*/
//@{
#define HW_TEMPMON_TEMPSENSE0_ADDR (REGS_TEMPMON_BASE + 0x180)
#define HW_TEMPMON_TEMPSENSE0_SET_ADDR (HW_TEMPMON_TEMPSENSE0_ADDR + 0x4)
#define HW_TEMPMON_TEMPSENSE0_CLR_ADDR (HW_TEMPMON_TEMPSENSE0_ADDR + 0x8)
#define HW_TEMPMON_TEMPSENSE0_TOG_ADDR (HW_TEMPMON_TEMPSENSE0_ADDR + 0xC)
#ifndef __LANGUAGE_ASM__
#define HW_TEMPMON_TEMPSENSE0 (*(volatile hw_tempmon_tempsense0_t *) HW_TEMPMON_TEMPSENSE0_ADDR)
#define HW_TEMPMON_TEMPSENSE0_RD() (HW_TEMPMON_TEMPSENSE0.U)
#define HW_TEMPMON_TEMPSENSE0_WR(v) (HW_TEMPMON_TEMPSENSE0.U = (v))
#define HW_TEMPMON_TEMPSENSE0_SET(v) ((*(volatile reg32_t *) HW_TEMPMON_TEMPSENSE0_SET_ADDR) = (v))
#define HW_TEMPMON_TEMPSENSE0_CLR(v) ((*(volatile reg32_t *) HW_TEMPMON_TEMPSENSE0_CLR_ADDR) = (v))
#define HW_TEMPMON_TEMPSENSE0_TOG(v) ((*(volatile reg32_t *) HW_TEMPMON_TEMPSENSE0_TOG_ADDR) = (v))
#endif
//@}
/*
* constants & macros for individual TEMPMON_TEMPSENSE0 bitfields
*/
/*! @name Register TEMPMON_TEMPSENSE0, field POWER_DOWN[0] (RW)
*
* This bit powers down the temperature sensor.
*
* Values:
* - POWER_UP = 0 - Enable power to the temperature sensor.
* - POWER_DOWN = 1 - Power down the temperature sensor.
*/
//@{
#define BP_TEMPMON_TEMPSENSE0_POWER_DOWN (0) //!< Bit position for TEMPMON_TEMPSENSE0_POWER_DOWN.
#define BM_TEMPMON_TEMPSENSE0_POWER_DOWN (0x00000001) //!< Bit mask for TEMPMON_TEMPSENSE0_POWER_DOWN.
//! @brief Get value of TEMPMON_TEMPSENSE0_POWER_DOWN from a register value.
#define BG_TEMPMON_TEMPSENSE0_POWER_DOWN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_TEMPMON_TEMPSENSE0_POWER_DOWN) >> BP_TEMPMON_TEMPSENSE0_POWER_DOWN)
//! @brief Format value for bitfield TEMPMON_TEMPSENSE0_POWER_DOWN.
#define BF_TEMPMON_TEMPSENSE0_POWER_DOWN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_TEMPMON_TEMPSENSE0_POWER_DOWN) & BM_TEMPMON_TEMPSENSE0_POWER_DOWN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the POWER_DOWN field to a new value.
#define BW_TEMPMON_TEMPSENSE0_POWER_DOWN(v) BF_CS1(TEMPMON_TEMPSENSE0, POWER_DOWN, v)
#endif
//! @brief Macro to simplify usage of value macros.
#define BF_TEMPMON_TEMPSENSE0_POWER_DOWN_V(v) BF_TEMPMON_TEMPSENSE0_POWER_DOWN(BV_TEMPMON_TEMPSENSE0_POWER_DOWN__##v)
#define BV_TEMPMON_TEMPSENSE0_POWER_DOWN__POWER_UP (0x0) //!< Enable power to the temperature sensor.
#define BV_TEMPMON_TEMPSENSE0_POWER_DOWN__POWER_DOWN (0x1) //!< Power down the temperature sensor.
//@}
/*! @name Register TEMPMON_TEMPSENSE0, field MEASURE_TEMP[1] (RW)
*
* Starts the measurement process. If the measurement frequency is zero in the TEMPSENSE1 register,
* this results in a single conversion.
*
* Values:
* - STOP = 0 - Do not start the measurement process.
* - START = 1 - Start the measurement process.
*/
//@{
#define BP_TEMPMON_TEMPSENSE0_MEASURE_TEMP (1) //!< Bit position for TEMPMON_TEMPSENSE0_MEASURE_TEMP.
#define BM_TEMPMON_TEMPSENSE0_MEASURE_TEMP (0x00000002) //!< Bit mask for TEMPMON_TEMPSENSE0_MEASURE_TEMP.
//! @brief Get value of TEMPMON_TEMPSENSE0_MEASURE_TEMP from a register value.
#define BG_TEMPMON_TEMPSENSE0_MEASURE_TEMP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_TEMPMON_TEMPSENSE0_MEASURE_TEMP) >> BP_TEMPMON_TEMPSENSE0_MEASURE_TEMP)
//! @brief Format value for bitfield TEMPMON_TEMPSENSE0_MEASURE_TEMP.
#define BF_TEMPMON_TEMPSENSE0_MEASURE_TEMP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_TEMPMON_TEMPSENSE0_MEASURE_TEMP) & BM_TEMPMON_TEMPSENSE0_MEASURE_TEMP)
#ifndef __LANGUAGE_ASM__
//! @brief Set the MEASURE_TEMP field to a new value.
#define BW_TEMPMON_TEMPSENSE0_MEASURE_TEMP(v) BF_CS1(TEMPMON_TEMPSENSE0, MEASURE_TEMP, v)
#endif
//! @brief Macro to simplify usage of value macros.
#define BF_TEMPMON_TEMPSENSE0_MEASURE_TEMP_V(v) BF_TEMPMON_TEMPSENSE0_MEASURE_TEMP(BV_TEMPMON_TEMPSENSE0_MEASURE_TEMP__##v)
#define BV_TEMPMON_TEMPSENSE0_MEASURE_TEMP__STOP (0x0) //!< Do not start the measurement process.
#define BV_TEMPMON_TEMPSENSE0_MEASURE_TEMP__START (0x1) //!< Start the measurement process.
//@}
/*! @name Register TEMPMON_TEMPSENSE0, field FINISHED[2] (RO)
*
* Indicates that the latest temp is valid. This bit should be cleared by the sensor after the start
* of each measurement.
*
* Values:
* - INVALID = 0 - Last measurement is not ready yet.
* - VALID = 1 - Last measurement is valid.
*/
//@{
#define BP_TEMPMON_TEMPSENSE0_FINISHED (2) //!< Bit position for TEMPMON_TEMPSENSE0_FINISHED.
#define BM_TEMPMON_TEMPSENSE0_FINISHED (0x00000004) //!< Bit mask for TEMPMON_TEMPSENSE0_FINISHED.
//! @brief Get value of TEMPMON_TEMPSENSE0_FINISHED from a register value.
#define BG_TEMPMON_TEMPSENSE0_FINISHED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_TEMPMON_TEMPSENSE0_FINISHED) >> BP_TEMPMON_TEMPSENSE0_FINISHED)
//! @brief Macro to simplify usage of value macros.
#define BF_TEMPMON_TEMPSENSE0_FINISHED_V(v) BF_TEMPMON_TEMPSENSE0_FINISHED(BV_TEMPMON_TEMPSENSE0_FINISHED__##v)
#define BV_TEMPMON_TEMPSENSE0_FINISHED__INVALID (0x0) //!< Last measurement is not ready yet.
#define BV_TEMPMON_TEMPSENSE0_FINISHED__VALID (0x1) //!< Last measurement is valid.
//@}
/*! @name Register TEMPMON_TEMPSENSE0, field TEMP_CNT[19:8] (RO)
*
* This bit field contains the last measured temperature count.
*/
//@{
#define BP_TEMPMON_TEMPSENSE0_TEMP_CNT (8) //!< Bit position for TEMPMON_TEMPSENSE0_TEMP_CNT.
#define BM_TEMPMON_TEMPSENSE0_TEMP_CNT (0x000fff00) //!< Bit mask for TEMPMON_TEMPSENSE0_TEMP_CNT.
//! @brief Get value of TEMPMON_TEMPSENSE0_TEMP_CNT from a register value.
#define BG_TEMPMON_TEMPSENSE0_TEMP_CNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_TEMPMON_TEMPSENSE0_TEMP_CNT) >> BP_TEMPMON_TEMPSENSE0_TEMP_CNT)
//@}
/*! @name Register TEMPMON_TEMPSENSE0, field ALARM_VALUE[31:20] (RW)
*
* This bit field contains the temperature count (raw sensor output) that will generate an alarm
* interrupt.
*/
//@{
#define BP_TEMPMON_TEMPSENSE0_ALARM_VALUE (20) //!< Bit position for TEMPMON_TEMPSENSE0_ALARM_VALUE.
#define BM_TEMPMON_TEMPSENSE0_ALARM_VALUE (0xfff00000) //!< Bit mask for TEMPMON_TEMPSENSE0_ALARM_VALUE.
//! @brief Get value of TEMPMON_TEMPSENSE0_ALARM_VALUE from a register value.
#define BG_TEMPMON_TEMPSENSE0_ALARM_VALUE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_TEMPMON_TEMPSENSE0_ALARM_VALUE) >> BP_TEMPMON_TEMPSENSE0_ALARM_VALUE)
//! @brief Format value for bitfield TEMPMON_TEMPSENSE0_ALARM_VALUE.
#define BF_TEMPMON_TEMPSENSE0_ALARM_VALUE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_TEMPMON_TEMPSENSE0_ALARM_VALUE) & BM_TEMPMON_TEMPSENSE0_ALARM_VALUE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ALARM_VALUE field to a new value.
#define BW_TEMPMON_TEMPSENSE0_ALARM_VALUE(v) BF_CS1(TEMPMON_TEMPSENSE0, ALARM_VALUE, v)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_TEMPMON_TEMPSENSE1 - Tempsensor Control Register 1
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_TEMPMON_TEMPSENSE1 - Tempsensor Control Register 1 (RW)
*
* Reset value: 0x00000001
*
* This register defines the automatic repeat time of the temperature sensor.
*/
typedef union _hw_tempmon_tempsense1
{
reg32_t U;
struct _hw_tempmon_tempsense1_bitfields
{
unsigned MEASURE_FREQ : 16; //!< [15:0] This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement.
unsigned RESERVED0 : 16; //!< [31:16] Reserved.
} B;
} hw_tempmon_tempsense1_t;
#endif
/*!
* @name Constants and macros for entire TEMPMON_TEMPSENSE1 register
*/
//@{
#define HW_TEMPMON_TEMPSENSE1_ADDR (REGS_TEMPMON_BASE + 0x190)
#define HW_TEMPMON_TEMPSENSE1_SET_ADDR (HW_TEMPMON_TEMPSENSE1_ADDR + 0x4)
#define HW_TEMPMON_TEMPSENSE1_CLR_ADDR (HW_TEMPMON_TEMPSENSE1_ADDR + 0x8)
#define HW_TEMPMON_TEMPSENSE1_TOG_ADDR (HW_TEMPMON_TEMPSENSE1_ADDR + 0xC)
#ifndef __LANGUAGE_ASM__
#define HW_TEMPMON_TEMPSENSE1 (*(volatile hw_tempmon_tempsense1_t *) HW_TEMPMON_TEMPSENSE1_ADDR)
#define HW_TEMPMON_TEMPSENSE1_RD() (HW_TEMPMON_TEMPSENSE1.U)
#define HW_TEMPMON_TEMPSENSE1_WR(v) (HW_TEMPMON_TEMPSENSE1.U = (v))
#define HW_TEMPMON_TEMPSENSE1_SET(v) ((*(volatile reg32_t *) HW_TEMPMON_TEMPSENSE1_SET_ADDR) = (v))
#define HW_TEMPMON_TEMPSENSE1_CLR(v) ((*(volatile reg32_t *) HW_TEMPMON_TEMPSENSE1_CLR_ADDR) = (v))
#define HW_TEMPMON_TEMPSENSE1_TOG(v) ((*(volatile reg32_t *) HW_TEMPMON_TEMPSENSE1_TOG_ADDR) = (v))
#endif
//@}
/*
* constants & macros for individual TEMPMON_TEMPSENSE1 bitfields
*/
/*! @name Register TEMPMON_TEMPSENSE1, field MEASURE_FREQ[15:0] (RW)
*
* This bits determines how many RTC clocks to wait before automatically repeating a temperature
* measurement. The pause time before remeasuring is the field value multiplied by the RTC period.
*
* Values:
* - 0x0000 - Defines a single measurement with no repeat.
* - . . . -
* - 0x0001 - Updates the temperature value at a RTC clock rate.
* - 0x0002 - Updates the temperature value at a RTC/2 clock rate.
* - 0xFFFF - Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the
* accuracy of the RTC clock.
*/
//@{
#define BP_TEMPMON_TEMPSENSE1_MEASURE_FREQ (0) //!< Bit position for TEMPMON_TEMPSENSE1_MEASURE_FREQ.
#define BM_TEMPMON_TEMPSENSE1_MEASURE_FREQ (0x0000ffff) //!< Bit mask for TEMPMON_TEMPSENSE1_MEASURE_FREQ.
//! @brief Get value of TEMPMON_TEMPSENSE1_MEASURE_FREQ from a register value.
#define BG_TEMPMON_TEMPSENSE1_MEASURE_FREQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_TEMPMON_TEMPSENSE1_MEASURE_FREQ) >> BP_TEMPMON_TEMPSENSE1_MEASURE_FREQ)
//! @brief Format value for bitfield TEMPMON_TEMPSENSE1_MEASURE_FREQ.
#define BF_TEMPMON_TEMPSENSE1_MEASURE_FREQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_TEMPMON_TEMPSENSE1_MEASURE_FREQ) & BM_TEMPMON_TEMPSENSE1_MEASURE_FREQ)
#ifndef __LANGUAGE_ASM__
//! @brief Set the MEASURE_FREQ field to a new value.
#define BW_TEMPMON_TEMPSENSE1_MEASURE_FREQ(v) BF_CS1(TEMPMON_TEMPSENSE1, MEASURE_FREQ, v)
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_tempmon_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All TEMPMON module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_tempmon
{
reg32_t _reserved0[96];
volatile hw_tempmon_tempsense0_t TEMPSENSE0; //!< Tempsensor Control Register 0
volatile reg32_t TEMPSENSE0_SET; //!< Tempsensor Control Register 0 Set
volatile reg32_t TEMPSENSE0_CLR; //!< Tempsensor Control Register 0 Clear
volatile reg32_t TEMPSENSE0_TOG; //!< Tempsensor Control Register 0 Toggle
volatile hw_tempmon_tempsense1_t TEMPSENSE1; //!< Tempsensor Control Register 1
volatile reg32_t TEMPSENSE1_SET; //!< Tempsensor Control Register 1 Set
volatile reg32_t TEMPSENSE1_CLR; //!< Tempsensor Control Register 1 Clear
volatile reg32_t TEMPSENSE1_TOG; //!< Tempsensor Control Register 1 Toggle
} hw_tempmon_t;
#pragma pack()
//! @brief Macro to access all TEMPMON registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_TEMPMON</code>.
#define HW_TEMPMON (*(hw_tempmon_t *) REGS_TEMPMON_BASE)
#endif
#endif // __HW_TEMPMON_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_VPU_REGISTERS_H__
#define __HW_VPU_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ VPU
*
* vpu
*
* Registers defined in this header file:
* - HW_VPU_CODERUN - BIT Processor run start
* - HW_VPU_CODEDOWN - BIT Boot Code Download Data register
* - HW_VPU_HOSTINTREQ - Host Interrupt Request to BIT
* - HW_VPU_BITINTCLEAR - BIT Interrupt Clear
* - HW_VPU_BITINTSTS - BIT Interrupt Status
* - HW_VPU_BITCURPC - BIT Current PC
* - HW_VPU_BITCODECBUSY - BIT CODEC Busy
*
* - hw_vpu_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_VPU_BASE
#define HW_VPU_INSTANCE_COUNT (1) //!< Number of instances of the VPU module.
#define REGS_VPU_BASE (0x02040000) //!< Base address for VPU.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_VPU_CODERUN - BIT Processor run start
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_VPU_CODERUN - BIT Processor run start (WO)
*
* Reset value: 0x00000000
*
* See the figure below for illustration of valid bits in VPU Code Run Register and the table below
* for description of the bit fields in the register.
*/
typedef union _hw_vpu_coderun
{
reg32_t U;
struct _hw_vpu_coderun_bitfields
{
unsigned CODERUN : 1; //!< [0] VPU_CodeRun.
unsigned RESERVED0 : 31; //!< [31:1] Reserved
} B;
} hw_vpu_coderun_t;
#endif
/*!
* @name Constants and macros for entire VPU_CODERUN register
*/
//@{
#define HW_VPU_CODERUN_ADDR (REGS_VPU_BASE + 0x0)
#ifndef __LANGUAGE_ASM__
#define HW_VPU_CODERUN (*(volatile hw_vpu_coderun_t *) HW_VPU_CODERUN_ADDR)
#define HW_VPU_CODERUN_WR(v) (HW_VPU_CODERUN.U = (v))
#endif
//@}
/*
* constants & macros for individual VPU_CODERUN bitfields
*/
/*! @name Register VPU_CODERUN, field CODERUN[0] (WO)
*
* VPU_CodeRun. BIT processor run start bit.
*
* Values:
* - 0 - BIT Processor stop execution.
* - 1 - BIT Processor start execution.
*/
//@{
#define BP_VPU_CODERUN_CODERUN (0) //!< Bit position for VPU_CODERUN_CODERUN.
#define BM_VPU_CODERUN_CODERUN (0x00000001) //!< Bit mask for VPU_CODERUN_CODERUN.
//! @brief Get value of VPU_CODERUN_CODERUN from a register value.
#define BG_VPU_CODERUN_CODERUN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_VPU_CODERUN_CODERUN) >> BP_VPU_CODERUN_CODERUN)
//! @brief Format value for bitfield VPU_CODERUN_CODERUN.
#define BF_VPU_CODERUN_CODERUN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_VPU_CODERUN_CODERUN) & BM_VPU_CODERUN_CODERUN)
//@}
//-------------------------------------------------------------------------------------------
// HW_VPU_CODEDOWN - BIT Boot Code Download Data register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_VPU_CODEDOWN - BIT Boot Code Download Data register (WO)
*
* Reset value: 0x00000000
*
* See the figure below for illustration of valid bits in VPU BIT Boot Code Download Data Register
* and the following table for description of the bit fields in the register.
*/
typedef union _hw_vpu_codedown
{
reg32_t U;
struct _hw_vpu_codedown_bitfields
{
unsigned CODEDATA : 16; //!< [15:0] CodeData[15:0]
unsigned CODEADDR : 13; //!< [28:16] CodeAddr[12:0]
unsigned RESERVED0 : 3; //!< [31:29] Reserved
} B;
} hw_vpu_codedown_t;
#endif
/*!
* @name Constants and macros for entire VPU_CODEDOWN register
*/
//@{
#define HW_VPU_CODEDOWN_ADDR (REGS_VPU_BASE + 0x4)
#ifndef __LANGUAGE_ASM__
#define HW_VPU_CODEDOWN (*(volatile hw_vpu_codedown_t *) HW_VPU_CODEDOWN_ADDR)
#define HW_VPU_CODEDOWN_WR(v) (HW_VPU_CODEDOWN.U = (v))
#endif
//@}
/*
* constants & macros for individual VPU_CODEDOWN bitfields
*/
/*! @name Register VPU_CODEDOWN, field CODEDATA[15:0] (WO)
*
* CodeData[15:0] Download data of VPU BIT boot code.
*/
//@{
#define BP_VPU_CODEDOWN_CODEDATA (0) //!< Bit position for VPU_CODEDOWN_CODEDATA.
#define BM_VPU_CODEDOWN_CODEDATA (0x0000ffff) //!< Bit mask for VPU_CODEDOWN_CODEDATA.
//! @brief Get value of VPU_CODEDOWN_CODEDATA from a register value.
#define BG_VPU_CODEDOWN_CODEDATA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_VPU_CODEDOWN_CODEDATA) >> BP_VPU_CODEDOWN_CODEDATA)
//! @brief Format value for bitfield VPU_CODEDOWN_CODEDATA.
#define BF_VPU_CODEDOWN_CODEDATA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_VPU_CODEDOWN_CODEDATA) & BM_VPU_CODEDOWN_CODEDATA)
//@}
/*! @name Register VPU_CODEDOWN, field CODEADDR[28:16] (WO)
*
* CodeAddr[12:0] Download address of VPU BIT boot code, which is VPU internal address of BIT
* processor.
*/
//@{
#define BP_VPU_CODEDOWN_CODEADDR (16) //!< Bit position for VPU_CODEDOWN_CODEADDR.
#define BM_VPU_CODEDOWN_CODEADDR (0x1fff0000) //!< Bit mask for VPU_CODEDOWN_CODEADDR.
//! @brief Get value of VPU_CODEDOWN_CODEADDR from a register value.
#define BG_VPU_CODEDOWN_CODEADDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_VPU_CODEDOWN_CODEADDR) >> BP_VPU_CODEDOWN_CODEADDR)
//! @brief Format value for bitfield VPU_CODEDOWN_CODEADDR.
#define BF_VPU_CODEDOWN_CODEADDR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_VPU_CODEDOWN_CODEADDR) & BM_VPU_CODEDOWN_CODEADDR)
//@}
//-------------------------------------------------------------------------------------------
// HW_VPU_HOSTINTREQ - Host Interrupt Request to BIT
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_VPU_HOSTINTREQ - Host Interrupt Request to BIT (WO)
*
* Reset value: 0x00000000
*
* See the figure below for illustration of valid bits in VPU Host Interrupt Request Register and
* the following table for description of the bit fields in the register.
*/
typedef union _hw_vpu_hostintreq
{
reg32_t U;
struct _hw_vpu_hostintreq_bitfields
{
unsigned INTREQ : 1; //!< [0] IntReq.
unsigned RESERVED0 : 31; //!< [31:1] Reserved
} B;
} hw_vpu_hostintreq_t;
#endif
/*!
* @name Constants and macros for entire VPU_HOSTINTREQ register
*/
//@{
#define HW_VPU_HOSTINTREQ_ADDR (REGS_VPU_BASE + 0x8)
#ifndef __LANGUAGE_ASM__
#define HW_VPU_HOSTINTREQ (*(volatile hw_vpu_hostintreq_t *) HW_VPU_HOSTINTREQ_ADDR)
#define HW_VPU_HOSTINTREQ_WR(v) (HW_VPU_HOSTINTREQ.U = (v))
#endif
//@}
/*
* constants & macros for individual VPU_HOSTINTREQ bitfields
*/
/*! @name Register VPU_HOSTINTREQ, field INTREQ[0] (WO)
*
* IntReq. The host interrupt request bit.
*
* Values:
* - 0 - No host interrupt is requested.
* - 1 - The host processor request interrupt to the BIT processor.
*/
//@{
#define BP_VPU_HOSTINTREQ_INTREQ (0) //!< Bit position for VPU_HOSTINTREQ_INTREQ.
#define BM_VPU_HOSTINTREQ_INTREQ (0x00000001) //!< Bit mask for VPU_HOSTINTREQ_INTREQ.
//! @brief Get value of VPU_HOSTINTREQ_INTREQ from a register value.
#define BG_VPU_HOSTINTREQ_INTREQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_VPU_HOSTINTREQ_INTREQ) >> BP_VPU_HOSTINTREQ_INTREQ)
//! @brief Format value for bitfield VPU_HOSTINTREQ_INTREQ.
#define BF_VPU_HOSTINTREQ_INTREQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_VPU_HOSTINTREQ_INTREQ) & BM_VPU_HOSTINTREQ_INTREQ)
//@}
//-------------------------------------------------------------------------------------------
// HW_VPU_BITINTCLEAR - BIT Interrupt Clear
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_VPU_BITINTCLEAR - BIT Interrupt Clear (WO)
*
* Reset value: 0x00000000
*
* See the figure below for illustration of valid bits in VPU BIT Interrupt Clear Register and the
* following table for description of the bit fields in the register.
*/
typedef union _hw_vpu_bitintclear
{
reg32_t U;
struct _hw_vpu_bitintclear_bitfields
{
unsigned INTCLEAR : 1; //!< [0] IntClear.
unsigned RESERVED0 : 31; //!< [31:1] Reserved
} B;
} hw_vpu_bitintclear_t;
#endif
/*!
* @name Constants and macros for entire VPU_BITINTCLEAR register
*/
//@{
#define HW_VPU_BITINTCLEAR_ADDR (REGS_VPU_BASE + 0xc)
#ifndef __LANGUAGE_ASM__
#define HW_VPU_BITINTCLEAR (*(volatile hw_vpu_bitintclear_t *) HW_VPU_BITINTCLEAR_ADDR)
#define HW_VPU_BITINTCLEAR_WR(v) (HW_VPU_BITINTCLEAR.U = (v))
#endif
//@}
/*
* constants & macros for individual VPU_BITINTCLEAR bitfields
*/
/*! @name Register VPU_BITINTCLEAR, field INTCLEAR[0] (WO)
*
* IntClear. BIT interrupt clear bit.
*
* Values:
* - 0 - No operation is issued.
* - 1 - Clear the BIT interrupt to the host.
*/
//@{
#define BP_VPU_BITINTCLEAR_INTCLEAR (0) //!< Bit position for VPU_BITINTCLEAR_INTCLEAR.
#define BM_VPU_BITINTCLEAR_INTCLEAR (0x00000001) //!< Bit mask for VPU_BITINTCLEAR_INTCLEAR.
//! @brief Get value of VPU_BITINTCLEAR_INTCLEAR from a register value.
#define BG_VPU_BITINTCLEAR_INTCLEAR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_VPU_BITINTCLEAR_INTCLEAR) >> BP_VPU_BITINTCLEAR_INTCLEAR)
//! @brief Format value for bitfield VPU_BITINTCLEAR_INTCLEAR.
#define BF_VPU_BITINTCLEAR_INTCLEAR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_VPU_BITINTCLEAR_INTCLEAR) & BM_VPU_BITINTCLEAR_INTCLEAR)
//@}
//-------------------------------------------------------------------------------------------
// HW_VPU_BITINTSTS - BIT Interrupt Status
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_VPU_BITINTSTS - BIT Interrupt Status (RO)
*
* Reset value: 0x00000000
*
* See the figure below for illustration of valid bits in VPU BIT Interrupt Status Register and the
* following table for description of the bit fields in the register.
*/
typedef union _hw_vpu_bitintsts
{
reg32_t U;
struct _hw_vpu_bitintsts_bitfields
{
unsigned INTSTS : 1; //!< [0] IntSts.
unsigned RESERVED0 : 31; //!< [31:1] Reserved
} B;
} hw_vpu_bitintsts_t;
#endif
/*!
* @name Constants and macros for entire VPU_BITINTSTS register
*/
//@{
#define HW_VPU_BITINTSTS_ADDR (REGS_VPU_BASE + 0x10)
#ifndef __LANGUAGE_ASM__
#define HW_VPU_BITINTSTS (*(volatile hw_vpu_bitintsts_t *) HW_VPU_BITINTSTS_ADDR)
#define HW_VPU_BITINTSTS_RD() (HW_VPU_BITINTSTS.U)
#endif
//@}
/*
* constants & macros for individual VPU_BITINTSTS bitfields
*/
/*! @name Register VPU_BITINTSTS, field INTSTS[0] (RO)
*
* IntSts. BIT interrupt status bit.
*
* Values:
* - 0 - No BIT interrupt is asserted.
* - 1 - The BIT interrupt is asserted to the host. It is cleared when the host processor write "1" to
* VPU_BitIntClear register.
*/
//@{
#define BP_VPU_BITINTSTS_INTSTS (0) //!< Bit position for VPU_BITINTSTS_INTSTS.
#define BM_VPU_BITINTSTS_INTSTS (0x00000001) //!< Bit mask for VPU_BITINTSTS_INTSTS.
//! @brief Get value of VPU_BITINTSTS_INTSTS from a register value.
#define BG_VPU_BITINTSTS_INTSTS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_VPU_BITINTSTS_INTSTS) >> BP_VPU_BITINTSTS_INTSTS)
//@}
//-------------------------------------------------------------------------------------------
// HW_VPU_BITCURPC - BIT Current PC
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_VPU_BITCURPC - BIT Current PC (RO)
*
* Reset value: 0x00000000
*
* See the figure below for illustration of valid bits in VPU BIT Current PC Register and the
* following table for description of the bit fields in the register.
*/
typedef union _hw_vpu_bitcurpc
{
reg32_t U;
struct _hw_vpu_bitcurpc_bitfields
{
unsigned CURPC : 14; //!< [13:0] CurPc[13:0].
unsigned RESERVED0 : 18; //!< [31:14] Reserved
} B;
} hw_vpu_bitcurpc_t;
#endif
/*!
* @name Constants and macros for entire VPU_BITCURPC register
*/
//@{
#define HW_VPU_BITCURPC_ADDR (REGS_VPU_BASE + 0x18)
#ifndef __LANGUAGE_ASM__
#define HW_VPU_BITCURPC (*(volatile hw_vpu_bitcurpc_t *) HW_VPU_BITCURPC_ADDR)
#define HW_VPU_BITCURPC_RD() (HW_VPU_BITCURPC.U)
#endif
//@}
/*
* constants & macros for individual VPU_BITCURPC bitfields
*/
/*! @name Register VPU_BITCURPC, field CURPC[13:0] (RO)
*
* CurPc[13:0]. BIT current PC value. Returns the current program counter of BIT processor by
* reading this register.
*/
//@{
#define BP_VPU_BITCURPC_CURPC (0) //!< Bit position for VPU_BITCURPC_CURPC.
#define BM_VPU_BITCURPC_CURPC (0x00003fff) //!< Bit mask for VPU_BITCURPC_CURPC.
//! @brief Get value of VPU_BITCURPC_CURPC from a register value.
#define BG_VPU_BITCURPC_CURPC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_VPU_BITCURPC_CURPC) >> BP_VPU_BITCURPC_CURPC)
//@}
//-------------------------------------------------------------------------------------------
// HW_VPU_BITCODECBUSY - BIT CODEC Busy
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_VPU_BITCODECBUSY - BIT CODEC Busy (RO)
*
* Reset value: 0x00000000
*
* See the figure below for illustration of valid bits in VPU BIT Codec Busy Register and the
* following table for description of the bit fields in the register.
*/
typedef union _hw_vpu_bitcodecbusy
{
reg32_t U;
struct _hw_vpu_bitcodecbusy_bitfields
{
unsigned CODECBUSY : 1; //!< [0] Codec busy flag for Bit processor.BIT processor write "1"to this register when the processor is running."0"means processor is waiting for a command.This value is connected to the o_vpu_idle.
unsigned RESERVED0 : 31; //!< [31:1] Reserved
} B;
} hw_vpu_bitcodecbusy_t;
#endif
/*!
* @name Constants and macros for entire VPU_BITCODECBUSY register
*/
//@{
#define HW_VPU_BITCODECBUSY_ADDR (REGS_VPU_BASE + 0x20)
#ifndef __LANGUAGE_ASM__
#define HW_VPU_BITCODECBUSY (*(volatile hw_vpu_bitcodecbusy_t *) HW_VPU_BITCODECBUSY_ADDR)
#define HW_VPU_BITCODECBUSY_RD() (HW_VPU_BITCODECBUSY.U)
#endif
//@}
/*
* constants & macros for individual VPU_BITCODECBUSY bitfields
*/
/*! @name Register VPU_BITCODECBUSY, field CODECBUSY[0] (RO)
*
* Codec busy flag for Bit processor.BIT processor write "1"to this register when the processor is
* running."0"means processor is waiting for a command.This value is connected to the o_vpu_idle.
*/
//@{
#define BP_VPU_BITCODECBUSY_CODECBUSY (0) //!< Bit position for VPU_BITCODECBUSY_CODECBUSY.
#define BM_VPU_BITCODECBUSY_CODECBUSY (0x00000001) //!< Bit mask for VPU_BITCODECBUSY_CODECBUSY.
//! @brief Get value of VPU_BITCODECBUSY_CODECBUSY from a register value.
#define BG_VPU_BITCODECBUSY_CODECBUSY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_VPU_BITCODECBUSY_CODECBUSY) >> BP_VPU_BITCODECBUSY_CODECBUSY)
//@}
//-------------------------------------------------------------------------------------------
// hw_vpu_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All VPU module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_vpu
{
volatile hw_vpu_coderun_t CODERUN; //!< BIT Processor run start
volatile hw_vpu_codedown_t CODEDOWN; //!< BIT Boot Code Download Data register
volatile hw_vpu_hostintreq_t HOSTINTREQ; //!< Host Interrupt Request to BIT
volatile hw_vpu_bitintclear_t BITINTCLEAR; //!< BIT Interrupt Clear
volatile hw_vpu_bitintsts_t BITINTSTS; //!< BIT Interrupt Status
reg32_t _reserved0;
volatile hw_vpu_bitcurpc_t BITCURPC; //!< BIT Current PC
reg32_t _reserved1;
volatile hw_vpu_bitcodecbusy_t BITCODECBUSY; //!< BIT CODEC Busy
} hw_vpu_t;
#pragma pack()
//! @brief Macro to access all VPU registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_VPU</code>.
#define HW_VPU (*(hw_vpu_t *) REGS_VPU_BASE)
#endif
#endif // __HW_VPU_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_WDOG_REGISTERS_H__
#define __HW_WDOG_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ WDOG
*
* WDOG
*
* Registers defined in this header file:
* - HW_WDOG_WCR - Watchdog Control Register
* - HW_WDOG_WSR - Watchdog Service Register
* - HW_WDOG_WRSR - Watchdog Reset Status Register
* - HW_WDOG_WICR - Watchdog Interrupt Control Register
* - HW_WDOG_WMCR - Watchdog Miscellaneous Control Register
*
* - hw_wdog_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_WDOG_BASE
#define HW_WDOG_INSTANCE_COUNT (2) //!< Number of instances of the WDOG module.
#define HW_WDOG1 (1) //!< Instance number for WDOG1.
#define HW_WDOG2 (2) //!< Instance number for WDOG2.
#define REGS_WDOG1_BASE (0x020bc000) //!< Base address for WDOG instance number 1.
#define REGS_WDOG2_BASE (0x020c0000) //!< Base address for WDOG instance number 2.
//! @brief Get the base address of WDOG by instance number.
//! @param x WDOG instance number, from 1 through 2.
#define REGS_WDOG_BASE(x) ( (x) == HW_WDOG1 ? REGS_WDOG1_BASE : (x) == HW_WDOG2 ? REGS_WDOG2_BASE : 0x00d00000)
//! @brief Get the instance number given a base address.
//! @param b Base address for an instance of WDOG.
#define REGS_WDOG_INSTANCE(b) ( (b) == REGS_WDOG1_BASE ? HW_WDOG1 : (b) == REGS_WDOG2_BASE ? HW_WDOG2 : 0)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_WDOG_WCR - Watchdog Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_WDOG_WCR - Watchdog Control Register (RW)
*
* Reset value: 0x0030
*
* The Watchdog Control Register (WDOG_WCR) controls the WDOG operation. WDZST, WDBG and WDW are
* write-once only bits. Once the software does a write access to these bits, they will be locked
* and cannot be reprogrammed until the next system reset assertion. WDE is a write one once only
* bit. Once software performs a write "1" operation to this bit it cannot be reset/cleared until
* the next system reset. WDT is also a write one once only bit. Once software performs a write "1"
* operation to this bit it cannot be reset/cleared until the next POR. This bit does not get
* reset/cleared due to any system reset.
*/
typedef union _hw_wdog_wcr
{
reg16_t U;
struct _hw_wdog_wcr_bitfields
{
unsigned short WDZST : 1; //!< [0] Watchdog Low Power.
unsigned short WDBG : 1; //!< [1] Watchdog DEBUG Enable.
unsigned short WDE : 1; //!< [2] Watchdog Enable.
unsigned short WDT : 1; //!< [3] WDOG Time-out assertion.
unsigned short SRS : 1; //!< [4] Software Reset Signal.
unsigned short WDA : 1; //!< [5] WDOG assertion.
unsigned short RESERVED0 : 1; //!< [6] Reserved
unsigned short WDW : 1; //!< [7] Watchdog Disable for Wait.
unsigned short WT : 8; //!< [15:8] Watchdog Time-out Field.
} B;
} hw_wdog_wcr_t;
#endif
/*!
* @name Constants and macros for entire WDOG_WCR register
*/
//@{
#define HW_WDOG_WCR_ADDR(x) (REGS_WDOG_BASE(x) + 0x0)
#ifndef __LANGUAGE_ASM__
#define HW_WDOG_WCR(x) (*(volatile hw_wdog_wcr_t *) HW_WDOG_WCR_ADDR(x))
#define HW_WDOG_WCR_RD(x) (HW_WDOG_WCR(x).U)
#define HW_WDOG_WCR_WR(x, v) (HW_WDOG_WCR(x).U = (v))
#define HW_WDOG_WCR_SET(x, v) (HW_WDOG_WCR_WR(x, HW_WDOG_WCR_RD(x) | (v)))
#define HW_WDOG_WCR_CLR(x, v) (HW_WDOG_WCR_WR(x, HW_WDOG_WCR_RD(x) & ~(v)))
#define HW_WDOG_WCR_TOG(x, v) (HW_WDOG_WCR_WR(x, HW_WDOG_WCR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual WDOG_WCR bitfields
*/
/*! @name Register WDOG_WCR, field WDZST[0] (RW)
*
* Watchdog Low Power. Determines the operation of the WDOG during low-power modes. This bit is
* write once-only. The WDOG can continue/suspend the timer operation in the low-power modes (STOP
* and DOZE mode).
*
* Values:
* - 0 - Continue timer operation (Default).
* - 1 - Suspend the watchdog timer.
*/
//@{
#define BP_WDOG_WCR_WDZST (0) //!< Bit position for WDOG_WCR_WDZST.
#define BM_WDOG_WCR_WDZST (0x00000001) //!< Bit mask for WDOG_WCR_WDZST.
//! @brief Get value of WDOG_WCR_WDZST from a register value.
#define BG_WDOG_WCR_WDZST(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WCR_WDZST) >> BP_WDOG_WCR_WDZST)
//! @brief Format value for bitfield WDOG_WCR_WDZST.
#define BF_WDOG_WCR_WDZST(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_WDOG_WCR_WDZST) & BM_WDOG_WCR_WDZST)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WDZST field to a new value.
#define BW_WDOG_WCR_WDZST(x, v) (HW_WDOG_WCR_WR(x, (HW_WDOG_WCR_RD(x) & ~BM_WDOG_WCR_WDZST) | BF_WDOG_WCR_WDZST(v)))
#endif
//@}
/*! @name Register WDOG_WCR, field WDBG[1] (RW)
*
* Watchdog DEBUG Enable. Determines the operation of the WDOG during DEBUG mode. This bit is write
* once only.
*
* Values:
* - 0 - Continue WDOG timer operation (Default).
* - 1 - Suspend the watchdog timer.
*/
//@{
#define BP_WDOG_WCR_WDBG (1) //!< Bit position for WDOG_WCR_WDBG.
#define BM_WDOG_WCR_WDBG (0x00000002) //!< Bit mask for WDOG_WCR_WDBG.
//! @brief Get value of WDOG_WCR_WDBG from a register value.
#define BG_WDOG_WCR_WDBG(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WCR_WDBG) >> BP_WDOG_WCR_WDBG)
//! @brief Format value for bitfield WDOG_WCR_WDBG.
#define BF_WDOG_WCR_WDBG(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_WDOG_WCR_WDBG) & BM_WDOG_WCR_WDBG)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WDBG field to a new value.
#define BW_WDOG_WCR_WDBG(x, v) (HW_WDOG_WCR_WR(x, (HW_WDOG_WCR_RD(x) & ~BM_WDOG_WCR_WDBG) | BF_WDOG_WCR_WDBG(v)))
#endif
//@}
/*! @name Register WDOG_WCR, field WDE[2] (RW)
*
* Watchdog Enable. Enables or disables the WDOG block. This is a write one once only bit. It is not
* possible to clear this bit by a software write, once the bit is set. This bit can be set/reset in
* debug mode (exception).
*
* Values:
* - 0 - Disable the Watchdog (Default).
* - 1 - Enable the Watchdog.
*/
//@{
#define BP_WDOG_WCR_WDE (2) //!< Bit position for WDOG_WCR_WDE.
#define BM_WDOG_WCR_WDE (0x00000004) //!< Bit mask for WDOG_WCR_WDE.
//! @brief Get value of WDOG_WCR_WDE from a register value.
#define BG_WDOG_WCR_WDE(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WCR_WDE) >> BP_WDOG_WCR_WDE)
//! @brief Format value for bitfield WDOG_WCR_WDE.
#define BF_WDOG_WCR_WDE(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_WDOG_WCR_WDE) & BM_WDOG_WCR_WDE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WDE field to a new value.
#define BW_WDOG_WCR_WDE(x, v) (HW_WDOG_WCR_WR(x, (HW_WDOG_WCR_RD(x) & ~BM_WDOG_WCR_WDE) | BF_WDOG_WCR_WDE(v)))
#endif
//@}
/*! @name Register WDOG_WCR, field WDT[3] (RW)
*
* WDOG Time-out assertion. Determines if the WDOG gets asserted upon a Watchdog Time-out Event.
* This is a write-one once only bit. There is no effect on wdog_rst (WDOG Reset) upon writing on
* this bit. WDOG gets asserted along with wdog_rst if this bit is set.
*
* Values:
* - 0 - No effect on WDOG (Default).
* - 1 - Assert WDOG upon a Watchdog Time-out event.
*/
//@{
#define BP_WDOG_WCR_WDT (3) //!< Bit position for WDOG_WCR_WDT.
#define BM_WDOG_WCR_WDT (0x00000008) //!< Bit mask for WDOG_WCR_WDT.
//! @brief Get value of WDOG_WCR_WDT from a register value.
#define BG_WDOG_WCR_WDT(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WCR_WDT) >> BP_WDOG_WCR_WDT)
//! @brief Format value for bitfield WDOG_WCR_WDT.
#define BF_WDOG_WCR_WDT(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_WDOG_WCR_WDT) & BM_WDOG_WCR_WDT)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WDT field to a new value.
#define BW_WDOG_WCR_WDT(x, v) (HW_WDOG_WCR_WR(x, (HW_WDOG_WCR_RD(x) & ~BM_WDOG_WCR_WDT) | BF_WDOG_WCR_WDT(v)))
#endif
//@}
/*! @name Register WDOG_WCR, field SRS[4] (RW)
*
* Software Reset Signal. Controls the software assertion of the WDOG-generated reset signal
* wdog_rst . This bit automatically resets to "1" after it has been asserted to "0". This bit does
* not generate the software reset to the block.
*
* Values:
* - 0 - Assert system reset signal.
* - 1 - No effect on the system (Default).
*/
//@{
#define BP_WDOG_WCR_SRS (4) //!< Bit position for WDOG_WCR_SRS.
#define BM_WDOG_WCR_SRS (0x00000010) //!< Bit mask for WDOG_WCR_SRS.
//! @brief Get value of WDOG_WCR_SRS from a register value.
#define BG_WDOG_WCR_SRS(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WCR_SRS) >> BP_WDOG_WCR_SRS)
//! @brief Format value for bitfield WDOG_WCR_SRS.
#define BF_WDOG_WCR_SRS(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_WDOG_WCR_SRS) & BM_WDOG_WCR_SRS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SRS field to a new value.
#define BW_WDOG_WCR_SRS(x, v) (HW_WDOG_WCR_WR(x, (HW_WDOG_WCR_RD(x) & ~BM_WDOG_WCR_SRS) | BF_WDOG_WCR_SRS(v)))
#endif
//@}
/*! @name Register WDOG_WCR, field WDA[5] (RW)
*
* WDOG assertion. Controls the software assertion of the WDOG signal.
*
* Values:
* - 0 - Assert WDOG output.
* - 1 - No effect on system (Default).
*/
//@{
#define BP_WDOG_WCR_WDA (5) //!< Bit position for WDOG_WCR_WDA.
#define BM_WDOG_WCR_WDA (0x00000020) //!< Bit mask for WDOG_WCR_WDA.
//! @brief Get value of WDOG_WCR_WDA from a register value.
#define BG_WDOG_WCR_WDA(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WCR_WDA) >> BP_WDOG_WCR_WDA)
//! @brief Format value for bitfield WDOG_WCR_WDA.
#define BF_WDOG_WCR_WDA(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_WDOG_WCR_WDA) & BM_WDOG_WCR_WDA)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WDA field to a new value.
#define BW_WDOG_WCR_WDA(x, v) (HW_WDOG_WCR_WR(x, (HW_WDOG_WCR_RD(x) & ~BM_WDOG_WCR_WDA) | BF_WDOG_WCR_WDA(v)))
#endif
//@}
/*! @name Register WDOG_WCR, field WDW[7] (RW)
*
* Watchdog Disable for Wait. This bit determines the operation of WDOG during Low Power WAIT mode.
* This is a write once only bit.
*
* Values:
* - 0 - Continue WDOG timer operation (Default).
* - 1 - Suspend WDOG timer operation.
*/
//@{
#define BP_WDOG_WCR_WDW (7) //!< Bit position for WDOG_WCR_WDW.
#define BM_WDOG_WCR_WDW (0x00000080) //!< Bit mask for WDOG_WCR_WDW.
//! @brief Get value of WDOG_WCR_WDW from a register value.
#define BG_WDOG_WCR_WDW(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WCR_WDW) >> BP_WDOG_WCR_WDW)
//! @brief Format value for bitfield WDOG_WCR_WDW.
#define BF_WDOG_WCR_WDW(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_WDOG_WCR_WDW) & BM_WDOG_WCR_WDW)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WDW field to a new value.
#define BW_WDOG_WCR_WDW(x, v) (HW_WDOG_WCR_WR(x, (HW_WDOG_WCR_RD(x) & ~BM_WDOG_WCR_WDW) | BF_WDOG_WCR_WDW(v)))
#endif
//@}
/*! @name Register WDOG_WCR, field WT[15:8] (RW)
*
* Watchdog Time-out Field. This 8-bit field contains the time-out value that is loaded into the
* Watchdog counter after the service routine has been performed or after the Watchdog is enabled.
* After reset, WT[7:0] must have a value written to it before enabling the Watchdog otherwise count
* value of zero which is 0.5 seconds is loaded into the counter. The time-out value can be written
* at any point of time but it is loaded to the counter at the time when WDOG is enabled or after
* the service routine has been performed. For more information see .
*
* Values:
* - 0x00 - - 0.5 Seconds (Default).
* - 0x01 - - 1.0 Seconds.
* - 0x02 - - 1.5 Seconds.
* - 0x03 - - 2.0 Seconds.
* - 0xff - - 128 Seconds.
*/
//@{
#define BP_WDOG_WCR_WT (8) //!< Bit position for WDOG_WCR_WT.
#define BM_WDOG_WCR_WT (0x0000ff00) //!< Bit mask for WDOG_WCR_WT.
//! @brief Get value of WDOG_WCR_WT from a register value.
#define BG_WDOG_WCR_WT(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WCR_WT) >> BP_WDOG_WCR_WT)
//! @brief Format value for bitfield WDOG_WCR_WT.
#define BF_WDOG_WCR_WT(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_WDOG_WCR_WT) & BM_WDOG_WCR_WT)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WT field to a new value.
#define BW_WDOG_WCR_WT(x, v) (HW_WDOG_WCR_WR(x, (HW_WDOG_WCR_RD(x) & ~BM_WDOG_WCR_WT) | BF_WDOG_WCR_WT(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_WDOG_WSR - Watchdog Service Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_WDOG_WSR - Watchdog Service Register (RW)
*
* Reset value: 0x0000
*
* When enabled, the WDOG requires that a service sequence be written to the Watchdog Service
* Register (WSR) to prevent the timeout condition. Executing the service sequence will reload the
* WDOG timeout counter.
*/
typedef union _hw_wdog_wsr
{
reg16_t U;
struct _hw_wdog_wsr_bitfields
{
unsigned short WSR : 16; //!< [15:0] Watchdog Service Register.
} B;
} hw_wdog_wsr_t;
#endif
/*!
* @name Constants and macros for entire WDOG_WSR register
*/
//@{
#define HW_WDOG_WSR_ADDR(x) (REGS_WDOG_BASE(x) + 0x2)
#ifndef __LANGUAGE_ASM__
#define HW_WDOG_WSR(x) (*(volatile hw_wdog_wsr_t *) HW_WDOG_WSR_ADDR(x))
#define HW_WDOG_WSR_RD(x) (HW_WDOG_WSR(x).U)
#define HW_WDOG_WSR_WR(x, v) (HW_WDOG_WSR(x).U = (v))
#define HW_WDOG_WSR_SET(x, v) (HW_WDOG_WSR_WR(x, HW_WDOG_WSR_RD(x) | (v)))
#define HW_WDOG_WSR_CLR(x, v) (HW_WDOG_WSR_WR(x, HW_WDOG_WSR_RD(x) & ~(v)))
#define HW_WDOG_WSR_TOG(x, v) (HW_WDOG_WSR_WR(x, HW_WDOG_WSR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual WDOG_WSR bitfields
*/
/*! @name Register WDOG_WSR, field WSR[15:0] (RW)
*
* Watchdog Service Register. This 16-bit field contains the Watchdog service sequence. Both writes
* must occur in the order listed prior to the time-out, but any number of instructions can be
* executed between the two writes. The service sequence must be performed as follows:
*
* Values:
* - 0x5555 - Write to the Watchdog Service Register (WDOG_WSR).
* - 0xAAAA - Write to the Watchdog Service Register (WDOG_WSR).
*/
//@{
#define BP_WDOG_WSR_WSR (0) //!< Bit position for WDOG_WSR_WSR.
#define BM_WDOG_WSR_WSR (0x0000ffff) //!< Bit mask for WDOG_WSR_WSR.
//! @brief Get value of WDOG_WSR_WSR from a register value.
#define BG_WDOG_WSR_WSR(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WSR_WSR) >> BP_WDOG_WSR_WSR)
//! @brief Format value for bitfield WDOG_WSR_WSR.
#define BF_WDOG_WSR_WSR(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_WDOG_WSR_WSR) & BM_WDOG_WSR_WSR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WSR field to a new value.
#define BW_WDOG_WSR_WSR(x, v) (HW_WDOG_WSR_WR(x, (HW_WDOG_WSR_RD(x) & ~BM_WDOG_WSR_WSR) | BF_WDOG_WSR_WSR(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_WDOG_WRSR - Watchdog Reset Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_WDOG_WRSR - Watchdog Reset Status Register (RO)
*
* Reset value: 0x0000
*
* The WRSR is a read-only register that records the source of the output reset assertion. It is not
* cleared by a hard reset. Therefore, only one bit in the WRSR will always be asserted high. The
* register will always indicate the source of the last reset generated due to WDOG. Read access to
* this register is with one wait state. Any write performed on this register will generate a
* Peripheral Bus Error . A reset can be generated by the following sources, as listed in priority
* from highest to lowest: Watchdog Time-out Software Reset
*/
typedef union _hw_wdog_wrsr
{
reg16_t U;
struct _hw_wdog_wrsr_bitfields
{
unsigned short SFTW : 1; //!< [0] Software Reset.
unsigned short TOUT : 1; //!< [1] Timeout.
unsigned short RESERVED0 : 2; //!< [3:2] Reserved.
unsigned short POR : 1; //!< [4] Power On Reset.
unsigned short RESERVED1 : 11; //!< [15:5] Reserved.
} B;
} hw_wdog_wrsr_t;
#endif
/*!
* @name Constants and macros for entire WDOG_WRSR register
*/
//@{
#define HW_WDOG_WRSR_ADDR(x) (REGS_WDOG_BASE(x) + 0x4)
#ifndef __LANGUAGE_ASM__
#define HW_WDOG_WRSR(x) (*(volatile hw_wdog_wrsr_t *) HW_WDOG_WRSR_ADDR(x))
#define HW_WDOG_WRSR_RD(x) (HW_WDOG_WRSR(x).U)
#endif
//@}
/*
* constants & macros for individual WDOG_WRSR bitfields
*/
/*! @name Register WDOG_WRSR, field SFTW[0] (RO)
*
* Software Reset. Indicates whether the reset is the result of a WDOG software reset by asserting
* SRS bit
*
* Values:
* - 0 - Reset is not the result of a software reset.
* - 1 - Reset is the result of a software reset.
*/
//@{
#define BP_WDOG_WRSR_SFTW (0) //!< Bit position for WDOG_WRSR_SFTW.
#define BM_WDOG_WRSR_SFTW (0x00000001) //!< Bit mask for WDOG_WRSR_SFTW.
//! @brief Get value of WDOG_WRSR_SFTW from a register value.
#define BG_WDOG_WRSR_SFTW(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WRSR_SFTW) >> BP_WDOG_WRSR_SFTW)
//@}
/*! @name Register WDOG_WRSR, field TOUT[1] (RO)
*
* Timeout. Indicates whether the reset is the result of a WDOG timeout.
*
* Values:
* - 0 - Reset is not the result of a WDOG timeout.
* - 1 - Reset is the result of a WDOG timeout.
*/
//@{
#define BP_WDOG_WRSR_TOUT (1) //!< Bit position for WDOG_WRSR_TOUT.
#define BM_WDOG_WRSR_TOUT (0x00000002) //!< Bit mask for WDOG_WRSR_TOUT.
//! @brief Get value of WDOG_WRSR_TOUT from a register value.
#define BG_WDOG_WRSR_TOUT(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WRSR_TOUT) >> BP_WDOG_WRSR_TOUT)
//@}
/*! @name Register WDOG_WRSR, field POR[4] (RO)
*
* Power On Reset. Indicates whether the reset is the result of a power on reset.
*
* Values:
* - 0 - Reset is not the result of a power on reset.
* - 1 - Reset is the result of a power on reset.
*/
//@{
#define BP_WDOG_WRSR_POR (4) //!< Bit position for WDOG_WRSR_POR.
#define BM_WDOG_WRSR_POR (0x00000010) //!< Bit mask for WDOG_WRSR_POR.
//! @brief Get value of WDOG_WRSR_POR from a register value.
#define BG_WDOG_WRSR_POR(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WRSR_POR) >> BP_WDOG_WRSR_POR)
//@}
//-------------------------------------------------------------------------------------------
// HW_WDOG_WICR - Watchdog Interrupt Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_WDOG_WICR - Watchdog Interrupt Control Register (RW)
*
* Reset value: 0x0004
*
* The WDOG_WICR controls the WDOG interrupt generation.
*/
typedef union _hw_wdog_wicr
{
reg16_t U;
struct _hw_wdog_wicr_bitfields
{
unsigned short WICT : 8; //!< [7:0] Watchdog Interrupt Count Time-out (WICT) field determines, how long before the counter time-out must the interrupt occur.
unsigned short RESERVED0 : 6; //!< [13:8] Reserved.
unsigned short WTIS : 1; //!< [14] Watchdog TImer Interrupt Status bit will reflect the timer interrupt status, whether interrupt has occurred or not.
unsigned short WIE : 1; //!< [15] Watchdog Timer Interrupt enable bit.
} B;
} hw_wdog_wicr_t;
#endif
/*!
* @name Constants and macros for entire WDOG_WICR register
*/
//@{
#define HW_WDOG_WICR_ADDR(x) (REGS_WDOG_BASE(x) + 0x6)
#ifndef __LANGUAGE_ASM__
#define HW_WDOG_WICR(x) (*(volatile hw_wdog_wicr_t *) HW_WDOG_WICR_ADDR(x))
#define HW_WDOG_WICR_RD(x) (HW_WDOG_WICR(x).U)
#define HW_WDOG_WICR_WR(x, v) (HW_WDOG_WICR(x).U = (v))
#define HW_WDOG_WICR_SET(x, v) (HW_WDOG_WICR_WR(x, HW_WDOG_WICR_RD(x) | (v)))
#define HW_WDOG_WICR_CLR(x, v) (HW_WDOG_WICR_WR(x, HW_WDOG_WICR_RD(x) & ~(v)))
#define HW_WDOG_WICR_TOG(x, v) (HW_WDOG_WICR_WR(x, HW_WDOG_WICR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual WDOG_WICR bitfields
*/
/*! @name Register WDOG_WICR, field WICT[7:0] (RW)
*
* Watchdog Interrupt Count Time-out (WICT) field determines, how long before the counter time-out
* must the interrupt occur. The reset value is 0x04 implies interrupt will occur 2 seconds before
* time-out. The maximum value that can be programmed to WICT field is 127.5 seconds with a
* resolution of 0.5 seconds. This field is write once only. Once the software does a write access
* to this field, it will get locked and cannot be reprogrammed until the next system reset
* assertion.
*
* Values:
* - 0x00 - WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
* - 0x01 - WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
* - 0x04 - WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
* - 0xff - WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
*/
//@{
#define BP_WDOG_WICR_WICT (0) //!< Bit position for WDOG_WICR_WICT.
#define BM_WDOG_WICR_WICT (0x000000ff) //!< Bit mask for WDOG_WICR_WICT.
//! @brief Get value of WDOG_WICR_WICT from a register value.
#define BG_WDOG_WICR_WICT(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WICR_WICT) >> BP_WDOG_WICR_WICT)
//! @brief Format value for bitfield WDOG_WICR_WICT.
#define BF_WDOG_WICR_WICT(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_WDOG_WICR_WICT) & BM_WDOG_WICR_WICT)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WICT field to a new value.
#define BW_WDOG_WICR_WICT(x, v) (HW_WDOG_WICR_WR(x, (HW_WDOG_WICR_RD(x) & ~BM_WDOG_WICR_WICT) | BF_WDOG_WICR_WICT(v)))
#endif
//@}
/*! @name Register WDOG_WICR, field WTIS[14] (W1C)
*
* Watchdog TImer Interrupt Status bit will reflect the timer interrupt status, whether interrupt
* has occurred or not. Once the interrupt has been triggered software must clear this bit by
* writing 1 to it.
*
* Values:
* - 0 - No interrupt has occurred (Default).
* - 1 - Interrupt has occurred
*/
//@{
#define BP_WDOG_WICR_WTIS (14) //!< Bit position for WDOG_WICR_WTIS.
#define BM_WDOG_WICR_WTIS (0x00004000) //!< Bit mask for WDOG_WICR_WTIS.
//! @brief Get value of WDOG_WICR_WTIS from a register value.
#define BG_WDOG_WICR_WTIS(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WICR_WTIS) >> BP_WDOG_WICR_WTIS)
//! @brief Format value for bitfield WDOG_WICR_WTIS.
#define BF_WDOG_WICR_WTIS(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_WDOG_WICR_WTIS) & BM_WDOG_WICR_WTIS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WTIS field to a new value.
#define BW_WDOG_WICR_WTIS(x, v) (HW_WDOG_WICR_WR(x, (HW_WDOG_WICR_RD(x) & ~BM_WDOG_WICR_WTIS) | BF_WDOG_WICR_WTIS(v)))
#endif
//@}
/*! @name Register WDOG_WICR, field WIE[15] (RW)
*
* Watchdog Timer Interrupt enable bit. Reset value is 0. This bit is a write once only bit. Once
* the software does a write access to this bit, it will get locked and cannot be reprogrammed until
* the next system reset assertion
*
* Values:
* - 0 - Disable Interrupt (Default).
* - 1 - Enable Interrupt.
*/
//@{
#define BP_WDOG_WICR_WIE (15) //!< Bit position for WDOG_WICR_WIE.
#define BM_WDOG_WICR_WIE (0x00008000) //!< Bit mask for WDOG_WICR_WIE.
//! @brief Get value of WDOG_WICR_WIE from a register value.
#define BG_WDOG_WICR_WIE(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WICR_WIE) >> BP_WDOG_WICR_WIE)
//! @brief Format value for bitfield WDOG_WICR_WIE.
#define BF_WDOG_WICR_WIE(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_WDOG_WICR_WIE) & BM_WDOG_WICR_WIE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WIE field to a new value.
#define BW_WDOG_WICR_WIE(x, v) (HW_WDOG_WICR_WR(x, (HW_WDOG_WICR_RD(x) & ~BM_WDOG_WICR_WIE) | BF_WDOG_WICR_WIE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_WDOG_WMCR - Watchdog Miscellaneous Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_WDOG_WMCR - Watchdog Miscellaneous Control Register (RW)
*
* Reset value: 0x0001
*
* WDOG_WMCR Controls the Power Down counter operation.
*/
typedef union _hw_wdog_wmcr
{
reg16_t U;
struct _hw_wdog_wmcr_bitfields
{
unsigned short PDE : 1; //!< [0] Power Down Enable bit.
unsigned short RESERVED0 : 15; //!< [15:1] Reserved.
} B;
} hw_wdog_wmcr_t;
#endif
/*!
* @name Constants and macros for entire WDOG_WMCR register
*/
//@{
#define HW_WDOG_WMCR_ADDR(x) (REGS_WDOG_BASE(x) + 0x8)
#ifndef __LANGUAGE_ASM__
#define HW_WDOG_WMCR(x) (*(volatile hw_wdog_wmcr_t *) HW_WDOG_WMCR_ADDR(x))
#define HW_WDOG_WMCR_RD(x) (HW_WDOG_WMCR(x).U)
#define HW_WDOG_WMCR_WR(x, v) (HW_WDOG_WMCR(x).U = (v))
#define HW_WDOG_WMCR_SET(x, v) (HW_WDOG_WMCR_WR(x, HW_WDOG_WMCR_RD(x) | (v)))
#define HW_WDOG_WMCR_CLR(x, v) (HW_WDOG_WMCR_WR(x, HW_WDOG_WMCR_RD(x) & ~(v)))
#define HW_WDOG_WMCR_TOG(x, v) (HW_WDOG_WMCR_WR(x, HW_WDOG_WMCR_RD(x) ^ (v)))
#endif
//@}
/*
* constants & macros for individual WDOG_WMCR bitfields
*/
/*! @name Register WDOG_WMCR, field PDE[0] (RW)
*
* Power Down Enable bit. Reset value of this bit is 1, which means the power down counter inside
* the WDOG is enabled after reset. The software must write 0 to this bit to disable the counter
* within 16 seconds of reset de-assertion. Once disabled this counter cannot be enabled again. See
* for operation of this counter. This bit is write-one once only bit. Once software sets this bit
* it cannot be reset until the next system reset.
*
* Values:
* - 0 - Power Down Counter of WDOG is disabled.
* - 1 - Power Down Counter of WDOG is enabled (Default).
*/
//@{
#define BP_WDOG_WMCR_PDE (0) //!< Bit position for WDOG_WMCR_PDE.
#define BM_WDOG_WMCR_PDE (0x00000001) //!< Bit mask for WDOG_WMCR_PDE.
//! @brief Get value of WDOG_WMCR_PDE from a register value.
#define BG_WDOG_WMCR_PDE(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_WDOG_WMCR_PDE) >> BP_WDOG_WMCR_PDE)
//! @brief Format value for bitfield WDOG_WMCR_PDE.
#define BF_WDOG_WMCR_PDE(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_WDOG_WMCR_PDE) & BM_WDOG_WMCR_PDE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PDE field to a new value.
#define BW_WDOG_WMCR_PDE(x, v) (HW_WDOG_WMCR_WR(x, (HW_WDOG_WMCR_RD(x) & ~BM_WDOG_WMCR_PDE) | BF_WDOG_WMCR_PDE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_wdog_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All WDOG module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_wdog
{
volatile hw_wdog_wcr_t WCR; //!< Watchdog Control Register
volatile hw_wdog_wsr_t WSR; //!< Watchdog Service Register
volatile hw_wdog_wrsr_t WRSR; //!< Watchdog Reset Status Register
volatile hw_wdog_wicr_t WICR; //!< Watchdog Interrupt Control Register
volatile hw_wdog_wmcr_t WMCR; //!< Watchdog Miscellaneous Control Register
} hw_wdog_t;
#pragma pack()
//! @brief Macro to access all WDOG registers.
//! @param x WDOG instance number.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_WDOG(0)</code>.
#define HW_WDOG(x) (*(hw_wdog_t *) REGS_WDOG_BASE(x))
#endif
#endif // __HW_WDOG_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_XTALOSC24M_REGISTERS_H__
#define __HW_XTALOSC24M_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ XTALOSC24M
*
* XTALOSC24M
*
* Registers defined in this header file:
* - HW_XTALOSC24M_MISC0 - Miscellaneous Register 0
*
* - hw_xtalosc24m_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_XTALOSC24M_BASE
#define HW_XTALOSC24M_INSTANCE_COUNT (1) //!< Number of instances of the XTALOSC24M module.
#define REGS_XTALOSC24M_BASE (0x020c8000) //!< Base address for XTALOSC24M.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_XTALOSC24M_MISC0 - Miscellaneous Register 0
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_XTALOSC24M_MISC0 - Miscellaneous Register 0 (RW)
*
* Reset value: 0x04000000
*
* This register defines the control and status bits for miscellaneous analog blocks.
*/
typedef union _hw_xtalosc24m_misc0
{
reg32_t U;
struct _hw_xtalosc24m_misc0_bitfields
{
unsigned REFTOP_PWD : 1; //!< [0] Control bit to power-down the analog bandgap reference circuitry.
unsigned RESERVED0 : 2; //!< [2:1] Reserved
unsigned REFTOP_SELFBIASOFF : 1; //!< [3] Control bit to disable the self-bias circuit in the analog bandgap.
unsigned REFTOP_VBGADJ : 3; //!< [6:4] Not related to oscillator.
unsigned REFTOP_VBGUP : 1; //!< [7] Status bit which signals that the analog bandgap voltage is up and stable.
unsigned RESERVED1 : 4; //!< [11:8] Reserved
unsigned STOP_MODE_CONFIG : 1; //!< [12] Configure the analog behavior in stop mode.
unsigned RESERVED2 : 1; //!< [13] Reserved.
unsigned OSC_I : 2; //!< [15:14] This bit field determines the bias current in the 24MHz oscillator.
unsigned OSC_XTALOK : 1; //!< [16] Status bit which signals that the output of the 24MHz crystal oscillator is stable.
unsigned OSC_XTALOK_EN : 1; //!< [17] Enable bit for the xtal_ok module(24 MHz)
unsigned WBCP_VPW_THRESH : 2; //!< [19:18] This signal alters the voltage that the pwell is charged pumped to.
unsigned RESERVED3 : 5; //!< [24:20] Reserved.
unsigned CLKGATE_CTRL : 1; //!< [25] This bit allows disabling the clock gate (always un-gated) for the xtal 24MHz clock that clocks the digital logic in the analog block.
unsigned CLKGATE_DELAY : 3; //!< [28:26] This field specifies the delay between powering up the XTAL 24MHz clock and release the clock to the digital logic inside the analog block.
unsigned RESERVED4 : 3; //!< [31:29] Reserved
} B;
} hw_xtalosc24m_misc0_t;
#endif
/*!
* @name Constants and macros for entire XTALOSC24M_MISC0 register
*/
//@{
#define HW_XTALOSC24M_MISC0_ADDR (REGS_XTALOSC24M_BASE + 0x150)
#ifndef __LANGUAGE_ASM__
#define HW_XTALOSC24M_MISC0 (*(volatile hw_xtalosc24m_misc0_t *) HW_XTALOSC24M_MISC0_ADDR)
#define HW_XTALOSC24M_MISC0_RD() (HW_XTALOSC24M_MISC0.U)
#define HW_XTALOSC24M_MISC0_WR(v) (HW_XTALOSC24M_MISC0.U = (v))
#define HW_XTALOSC24M_MISC0_SET(v) (HW_XTALOSC24M_MISC0_WR(HW_XTALOSC24M_MISC0_RD() | (v)))
#define HW_XTALOSC24M_MISC0_CLR(v) (HW_XTALOSC24M_MISC0_WR(HW_XTALOSC24M_MISC0_RD() & ~(v)))
#define HW_XTALOSC24M_MISC0_TOG(v) (HW_XTALOSC24M_MISC0_WR(HW_XTALOSC24M_MISC0_RD() ^ (v)))
#endif
//@}
/*
* constants & macros for individual XTALOSC24M_MISC0 bitfields
*/
/*! @name Register XTALOSC24M_MISC0, field REFTOP_PWD[0] (RW)
*
* Control bit to power-down the analog bandgap reference circuitry. Not related to oscillator.
* CAUTION - The bandgap reference is necessary for correct operation of most of the LDOs, PLLs, and
* other analog functions on the die.
*
* Values:
* - 0 - Bandgap reference is enabled.
* - 1 - Bandgap reference is disabled. Current consumption is removed from the supply via internal
* configuration.
*/
//@{
#define BP_XTALOSC24M_MISC0_REFTOP_PWD (0) //!< Bit position for XTALOSC24M_MISC0_REFTOP_PWD.
#define BM_XTALOSC24M_MISC0_REFTOP_PWD (0x00000001) //!< Bit mask for XTALOSC24M_MISC0_REFTOP_PWD.
//! @brief Get value of XTALOSC24M_MISC0_REFTOP_PWD from a register value.
#define BG_XTALOSC24M_MISC0_REFTOP_PWD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_XTALOSC24M_MISC0_REFTOP_PWD) >> BP_XTALOSC24M_MISC0_REFTOP_PWD)
//! @brief Format value for bitfield XTALOSC24M_MISC0_REFTOP_PWD.
#define BF_XTALOSC24M_MISC0_REFTOP_PWD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_XTALOSC24M_MISC0_REFTOP_PWD) & BM_XTALOSC24M_MISC0_REFTOP_PWD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the REFTOP_PWD field to a new value.
#define BW_XTALOSC24M_MISC0_REFTOP_PWD(v) (HW_XTALOSC24M_MISC0_WR((HW_XTALOSC24M_MISC0_RD() & ~BM_XTALOSC24M_MISC0_REFTOP_PWD) | BF_XTALOSC24M_MISC0_REFTOP_PWD(v)))
#endif
//@}
/*! @name Register XTALOSC24M_MISC0, field REFTOP_SELFBIASOFF[3] (RW)
*
* Control bit to disable the self-bias circuit in the analog bandgap. The self-bias circuit is used
* by the bandgap during startup. This bit should be set after the bandgap has stabilized and is
* necessary for best noise performance of analog blocks using the outputs of the bandgap. Not
* related to oscillator. Value should be returned to zero before removing vddhigh_in or asserting
* bit 0 of this register (REFTOP_PWD) to assure proper restart of the circuit.
*
* Values:
* - 0 - Uses coarse bias currents for startup
* - 1 - Uses bandgap based bias currents for best performance.
*/
//@{
#define BP_XTALOSC24M_MISC0_REFTOP_SELFBIASOFF (3) //!< Bit position for XTALOSC24M_MISC0_REFTOP_SELFBIASOFF.
#define BM_XTALOSC24M_MISC0_REFTOP_SELFBIASOFF (0x00000008) //!< Bit mask for XTALOSC24M_MISC0_REFTOP_SELFBIASOFF.
//! @brief Get value of XTALOSC24M_MISC0_REFTOP_SELFBIASOFF from a register value.
#define BG_XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_XTALOSC24M_MISC0_REFTOP_SELFBIASOFF) >> BP_XTALOSC24M_MISC0_REFTOP_SELFBIASOFF)
//! @brief Format value for bitfield XTALOSC24M_MISC0_REFTOP_SELFBIASOFF.
#define BF_XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_XTALOSC24M_MISC0_REFTOP_SELFBIASOFF) & BM_XTALOSC24M_MISC0_REFTOP_SELFBIASOFF)
#ifndef __LANGUAGE_ASM__
//! @brief Set the REFTOP_SELFBIASOFF field to a new value.
#define BW_XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(v) (HW_XTALOSC24M_MISC0_WR((HW_XTALOSC24M_MISC0_RD() & ~BM_XTALOSC24M_MISC0_REFTOP_SELFBIASOFF) | BF_XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(v)))
#endif
//@}
/*! @name Register XTALOSC24M_MISC0, field REFTOP_VBGADJ[6:4] (RW)
*
* Not related to oscillator.
*
* Values:
* - 000 - Nominal VBG
* - 001 - VBG+0.78%
* - 010 - VBG+1.56%
* - 011 - VBG+2.34%
* - 100 - VBG-0.78%
* - 101 - VBG-1.56%
* - 110 - VBG-2.34%
* - 111 - VBG-3.12%
*/
//@{
#define BP_XTALOSC24M_MISC0_REFTOP_VBGADJ (4) //!< Bit position for XTALOSC24M_MISC0_REFTOP_VBGADJ.
#define BM_XTALOSC24M_MISC0_REFTOP_VBGADJ (0x00000070) //!< Bit mask for XTALOSC24M_MISC0_REFTOP_VBGADJ.
//! @brief Get value of XTALOSC24M_MISC0_REFTOP_VBGADJ from a register value.
#define BG_XTALOSC24M_MISC0_REFTOP_VBGADJ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_XTALOSC24M_MISC0_REFTOP_VBGADJ) >> BP_XTALOSC24M_MISC0_REFTOP_VBGADJ)
//! @brief Format value for bitfield XTALOSC24M_MISC0_REFTOP_VBGADJ.
#define BF_XTALOSC24M_MISC0_REFTOP_VBGADJ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_XTALOSC24M_MISC0_REFTOP_VBGADJ) & BM_XTALOSC24M_MISC0_REFTOP_VBGADJ)
#ifndef __LANGUAGE_ASM__
//! @brief Set the REFTOP_VBGADJ field to a new value.
#define BW_XTALOSC24M_MISC0_REFTOP_VBGADJ(v) (HW_XTALOSC24M_MISC0_WR((HW_XTALOSC24M_MISC0_RD() & ~BM_XTALOSC24M_MISC0_REFTOP_VBGADJ) | BF_XTALOSC24M_MISC0_REFTOP_VBGADJ(v)))
#endif
//@}
/*! @name Register XTALOSC24M_MISC0, field REFTOP_VBGUP[7] (RW)
*
* Status bit which signals that the analog bandgap voltage is up and stable. 0 - Bandgap voltage
* not stable 1- Bandgap voltage stable Not related to oscillator.
*/
//@{
#define BP_XTALOSC24M_MISC0_REFTOP_VBGUP (7) //!< Bit position for XTALOSC24M_MISC0_REFTOP_VBGUP.
#define BM_XTALOSC24M_MISC0_REFTOP_VBGUP (0x00000080) //!< Bit mask for XTALOSC24M_MISC0_REFTOP_VBGUP.
//! @brief Get value of XTALOSC24M_MISC0_REFTOP_VBGUP from a register value.
#define BG_XTALOSC24M_MISC0_REFTOP_VBGUP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_XTALOSC24M_MISC0_REFTOP_VBGUP) >> BP_XTALOSC24M_MISC0_REFTOP_VBGUP)
//! @brief Format value for bitfield XTALOSC24M_MISC0_REFTOP_VBGUP.
#define BF_XTALOSC24M_MISC0_REFTOP_VBGUP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_XTALOSC24M_MISC0_REFTOP_VBGUP) & BM_XTALOSC24M_MISC0_REFTOP_VBGUP)
#ifndef __LANGUAGE_ASM__
//! @brief Set the REFTOP_VBGUP field to a new value.
#define BW_XTALOSC24M_MISC0_REFTOP_VBGUP(v) (HW_XTALOSC24M_MISC0_WR((HW_XTALOSC24M_MISC0_RD() & ~BM_XTALOSC24M_MISC0_REFTOP_VBGUP) | BF_XTALOSC24M_MISC0_REFTOP_VBGUP(v)))
#endif
//@}
/*! @name Register XTALOSC24M_MISC0, field STOP_MODE_CONFIG[12] (RW)
*
* Configure the analog behavior in stop mode.
*
* Values:
* - 0 - All the analog domain except the RTC is powered down on STOP mode assertion
* - 1 - All the analog domain except the LDO_1P1 and LDO_2P5 regulators are powered down on STOP mode
* assertion. If required the CCM can be configured to not power down the oscillator (XTALOSC).
*/
//@{
#define BP_XTALOSC24M_MISC0_STOP_MODE_CONFIG (12) //!< Bit position for XTALOSC24M_MISC0_STOP_MODE_CONFIG.
#define BM_XTALOSC24M_MISC0_STOP_MODE_CONFIG (0x00001000) //!< Bit mask for XTALOSC24M_MISC0_STOP_MODE_CONFIG.
//! @brief Get value of XTALOSC24M_MISC0_STOP_MODE_CONFIG from a register value.
#define BG_XTALOSC24M_MISC0_STOP_MODE_CONFIG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_XTALOSC24M_MISC0_STOP_MODE_CONFIG) >> BP_XTALOSC24M_MISC0_STOP_MODE_CONFIG)
//! @brief Format value for bitfield XTALOSC24M_MISC0_STOP_MODE_CONFIG.
#define BF_XTALOSC24M_MISC0_STOP_MODE_CONFIG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_XTALOSC24M_MISC0_STOP_MODE_CONFIG) & BM_XTALOSC24M_MISC0_STOP_MODE_CONFIG)
#ifndef __LANGUAGE_ASM__
//! @brief Set the STOP_MODE_CONFIG field to a new value.
#define BW_XTALOSC24M_MISC0_STOP_MODE_CONFIG(v) (HW_XTALOSC24M_MISC0_WR((HW_XTALOSC24M_MISC0_RD() & ~BM_XTALOSC24M_MISC0_STOP_MODE_CONFIG) | BF_XTALOSC24M_MISC0_STOP_MODE_CONFIG(v)))
#endif
//@}
/*! @name Register XTALOSC24M_MISC0, field OSC_I[15:14] (RW)
*
* This bit field determines the bias current in the 24MHz oscillator. The idea is to start up with
* the highest bias current which can be decreased after startup if determined to be acceptable.
* Acceptable meaning that the oscillation signal amplitudes are still substantially full scale over
* the product operating conditions. It only makes sense to lower the current to the oscillator if
* the oscillator's power consumption is significant relative to the consumption of the system as a
* whole. If the oscillator is subsequently powered down by programming or removal of its supply,
* this field must be returned to the nominal value to guarantee proper startup.
*
* Values:
* - 00 - Nominal
* - 01 - Decrease current by 12.5%
* - 10 - Decrease current by 25.0%
* - 11 - Decrease current by 37.5%
*/
//@{
#define BP_XTALOSC24M_MISC0_OSC_I (14) //!< Bit position for XTALOSC24M_MISC0_OSC_I.
#define BM_XTALOSC24M_MISC0_OSC_I (0x0000c000) //!< Bit mask for XTALOSC24M_MISC0_OSC_I.
//! @brief Get value of XTALOSC24M_MISC0_OSC_I from a register value.
#define BG_XTALOSC24M_MISC0_OSC_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_XTALOSC24M_MISC0_OSC_I) >> BP_XTALOSC24M_MISC0_OSC_I)
//! @brief Format value for bitfield XTALOSC24M_MISC0_OSC_I.
#define BF_XTALOSC24M_MISC0_OSC_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_XTALOSC24M_MISC0_OSC_I) & BM_XTALOSC24M_MISC0_OSC_I)
#ifndef __LANGUAGE_ASM__
//! @brief Set the OSC_I field to a new value.
#define BW_XTALOSC24M_MISC0_OSC_I(v) (HW_XTALOSC24M_MISC0_WR((HW_XTALOSC24M_MISC0_RD() & ~BM_XTALOSC24M_MISC0_OSC_I) | BF_XTALOSC24M_MISC0_OSC_I(v)))
#endif
//@}
/*! @name Register XTALOSC24M_MISC0, field OSC_XTALOK[16] (RO)
*
* Status bit which signals that the output of the 24MHz crystal oscillator is stable. Generated
* from a timer and active detection of the actual frequency.
*
* Values:
* - 0 - Xtal clock not ok for use.
* - 1 - Xtal clock ok for use.
*/
//@{
#define BP_XTALOSC24M_MISC0_OSC_XTALOK (16) //!< Bit position for XTALOSC24M_MISC0_OSC_XTALOK.
#define BM_XTALOSC24M_MISC0_OSC_XTALOK (0x00010000) //!< Bit mask for XTALOSC24M_MISC0_OSC_XTALOK.
//! @brief Get value of XTALOSC24M_MISC0_OSC_XTALOK from a register value.
#define BG_XTALOSC24M_MISC0_OSC_XTALOK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_XTALOSC24M_MISC0_OSC_XTALOK) >> BP_XTALOSC24M_MISC0_OSC_XTALOK)
//@}
/*! @name Register XTALOSC24M_MISC0, field OSC_XTALOK_EN[17] (RW)
*
* Enable bit for the xtal_ok module(24 MHz)
*
* Values:
* - 0 - Xtal_ok function disabled
* - 1 - Xtal_ok function enabled
*/
//@{
#define BP_XTALOSC24M_MISC0_OSC_XTALOK_EN (17) //!< Bit position for XTALOSC24M_MISC0_OSC_XTALOK_EN.
#define BM_XTALOSC24M_MISC0_OSC_XTALOK_EN (0x00020000) //!< Bit mask for XTALOSC24M_MISC0_OSC_XTALOK_EN.
//! @brief Get value of XTALOSC24M_MISC0_OSC_XTALOK_EN from a register value.
#define BG_XTALOSC24M_MISC0_OSC_XTALOK_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_XTALOSC24M_MISC0_OSC_XTALOK_EN) >> BP_XTALOSC24M_MISC0_OSC_XTALOK_EN)
//! @brief Format value for bitfield XTALOSC24M_MISC0_OSC_XTALOK_EN.
#define BF_XTALOSC24M_MISC0_OSC_XTALOK_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_XTALOSC24M_MISC0_OSC_XTALOK_EN) & BM_XTALOSC24M_MISC0_OSC_XTALOK_EN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the OSC_XTALOK_EN field to a new value.
#define BW_XTALOSC24M_MISC0_OSC_XTALOK_EN(v) (HW_XTALOSC24M_MISC0_WR((HW_XTALOSC24M_MISC0_RD() & ~BM_XTALOSC24M_MISC0_OSC_XTALOK_EN) | BF_XTALOSC24M_MISC0_OSC_XTALOK_EN(v)))
#endif
//@}
/*! @name Register XTALOSC24M_MISC0, field WBCP_VPW_THRESH[19:18] (RW)
*
* This signal alters the voltage that the pwell is charged pumped to. Default value should not be
* changed without guidance from Freescale Not related to oscillator.
*
* Values:
* - 00 - Nominal output pwell bias voltage.
* - 01 - Increase pwell output voltage by 25mV.
* - 10 - Decrease pwell output pwell voltage by 25mV.
* - 11 - Decrease pwell output pwell voltage by 50mV.
*/
//@{
#define BP_XTALOSC24M_MISC0_WBCP_VPW_THRESH (18) //!< Bit position for XTALOSC24M_MISC0_WBCP_VPW_THRESH.
#define BM_XTALOSC24M_MISC0_WBCP_VPW_THRESH (0x000c0000) //!< Bit mask for XTALOSC24M_MISC0_WBCP_VPW_THRESH.
//! @brief Get value of XTALOSC24M_MISC0_WBCP_VPW_THRESH from a register value.
#define BG_XTALOSC24M_MISC0_WBCP_VPW_THRESH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_XTALOSC24M_MISC0_WBCP_VPW_THRESH) >> BP_XTALOSC24M_MISC0_WBCP_VPW_THRESH)
//! @brief Format value for bitfield XTALOSC24M_MISC0_WBCP_VPW_THRESH.
#define BF_XTALOSC24M_MISC0_WBCP_VPW_THRESH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_XTALOSC24M_MISC0_WBCP_VPW_THRESH) & BM_XTALOSC24M_MISC0_WBCP_VPW_THRESH)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WBCP_VPW_THRESH field to a new value.
#define BW_XTALOSC24M_MISC0_WBCP_VPW_THRESH(v) (HW_XTALOSC24M_MISC0_WR((HW_XTALOSC24M_MISC0_RD() & ~BM_XTALOSC24M_MISC0_WBCP_VPW_THRESH) | BF_XTALOSC24M_MISC0_WBCP_VPW_THRESH(v)))
#endif
//@}
/*! @name Register XTALOSC24M_MISC0, field CLKGATE_CTRL[25] (RW)
*
* This bit allows disabling the clock gate (always un-gated) for the xtal 24MHz clock that clocks
* the digital logic in the analog block. Do not change the field during a low power event. This is
* not a field that the user would normally need to modify
*
* Values:
* - 0 - Allow the logic to automatically gate the clock when the XTAL is powered down.
* - 1 - Prevent the logic from ever gating off the clock.
*/
//@{
#define BP_XTALOSC24M_MISC0_CLKGATE_CTRL (25) //!< Bit position for XTALOSC24M_MISC0_CLKGATE_CTRL.
#define BM_XTALOSC24M_MISC0_CLKGATE_CTRL (0x02000000) //!< Bit mask for XTALOSC24M_MISC0_CLKGATE_CTRL.
//! @brief Get value of XTALOSC24M_MISC0_CLKGATE_CTRL from a register value.
#define BG_XTALOSC24M_MISC0_CLKGATE_CTRL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_XTALOSC24M_MISC0_CLKGATE_CTRL) >> BP_XTALOSC24M_MISC0_CLKGATE_CTRL)
//! @brief Format value for bitfield XTALOSC24M_MISC0_CLKGATE_CTRL.
#define BF_XTALOSC24M_MISC0_CLKGATE_CTRL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_XTALOSC24M_MISC0_CLKGATE_CTRL) & BM_XTALOSC24M_MISC0_CLKGATE_CTRL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CLKGATE_CTRL field to a new value.
#define BW_XTALOSC24M_MISC0_CLKGATE_CTRL(v) (HW_XTALOSC24M_MISC0_WR((HW_XTALOSC24M_MISC0_RD() & ~BM_XTALOSC24M_MISC0_CLKGATE_CTRL) | BF_XTALOSC24M_MISC0_CLKGATE_CTRL(v)))
#endif
//@}
/*! @name Register XTALOSC24M_MISC0, field CLKGATE_DELAY[28:26] (RW)
*
* This field specifies the delay between powering up the XTAL 24MHz clock and release the clock to
* the digital logic inside the analog block. Do not change the field during a low power event. This
* is not a field that the user would normally need to modify
*
* Values:
* - 000 - 0.5ms
* - 001 - 1.0ms
* - 010 - 2.0ms
* - 011 - 3.0ms
* - 100 - 4.0ms
* - 101 - 5.0ms
* - 110 - 6.0ms
* - 111 - 7.0ms
*/
//@{
#define BP_XTALOSC24M_MISC0_CLKGATE_DELAY (26) //!< Bit position for XTALOSC24M_MISC0_CLKGATE_DELAY.
#define BM_XTALOSC24M_MISC0_CLKGATE_DELAY (0x1c000000) //!< Bit mask for XTALOSC24M_MISC0_CLKGATE_DELAY.
//! @brief Get value of XTALOSC24M_MISC0_CLKGATE_DELAY from a register value.
#define BG_XTALOSC24M_MISC0_CLKGATE_DELAY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_XTALOSC24M_MISC0_CLKGATE_DELAY) >> BP_XTALOSC24M_MISC0_CLKGATE_DELAY)
//! @brief Format value for bitfield XTALOSC24M_MISC0_CLKGATE_DELAY.
#define BF_XTALOSC24M_MISC0_CLKGATE_DELAY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_XTALOSC24M_MISC0_CLKGATE_DELAY) & BM_XTALOSC24M_MISC0_CLKGATE_DELAY)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CLKGATE_DELAY field to a new value.
#define BW_XTALOSC24M_MISC0_CLKGATE_DELAY(v) (HW_XTALOSC24M_MISC0_WR((HW_XTALOSC24M_MISC0_RD() & ~BM_XTALOSC24M_MISC0_CLKGATE_DELAY) | BF_XTALOSC24M_MISC0_CLKGATE_DELAY(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_xtalosc24m_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All XTALOSC24M module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_xtalosc24m
{
reg32_t _reserved0[84];
volatile hw_xtalosc24m_misc0_t MISC0; //!< Miscellaneous Register 0
} hw_xtalosc24m_t;
#pragma pack()
//! @brief Macro to access all XTALOSC24M registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_XTALOSC24M</code>.
#define HW_XTALOSC24M (*(hw_xtalosc24m_t *) REGS_XTALOSC24M_BASE)
#endif
#endif // __HW_XTALOSC24M_REGISTERS_H__
// v18/121106/1.2.2
// EOF

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