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2021-04-28 17:49:18 +08:00
commit 6001051eb7
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arch/arm/Makefile
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#公共部分
SRC_DIR := shared cortex-m4
include $(KERNEL_ROOT)/compiler.mk
arch/arm/cortex-m0/Makefile
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arch/arm/cortex-m4/Makefile
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SRC_FILES := system_init.c boot.S interrupt_vector.S coreclock.c interrupt.c svc_entry.S
ifeq ($(CONFIG_TASK_ISOLATION),y)
SRC_FILES += svc_handle.c mpu.c
endif
include $(KERNEL_ROOT)/compiler.mk
arch/arm/cortex-m4/arch_interrupt.h
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#ifndef ARCH_INTERRUPT_H__
#define ARCH_INTERRUPT_H__
#include <xs_base.h>
#define ARCH_MAX_IRQ_NUM (256 + 16)
#define ARCH_IRQ_NUM_OFFSET 16
int32 ArchEnableHwIrq(uint32 irq_num);
int32 ArchDisableHwIrq(uint32 irq_num);
#endif
arch/arm/cortex-m4/boot.S
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/**
******************************************************************************
* @file startup_stm32f407xx.s
* @author MCD Application Team
* @brief STM32F407xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/**
* @file coreclock.c
* @brief derived from ST standard peripheral library
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.word _sidata
.word _sdata
.word _edata
.word __bss_start
.word __bss_end
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =__stack_tp
movs r1, #0
/* Copy the data segment initializers from flash to SRAM */
DataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcs DataInitEnd
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
b DataInit
DataInitEnd:
ldr r2, =__bss_start
/* Zero fill the bss segment. */
BSSInit:
ldr r3, = __bss_end
cmp r2, r3
bcs BSSInitEnd
movs r3, #0
str r3, [r2], #4
b BSSInit
BSSInitEnd:
bl SystemInit
bl stm32f407_start
bx lr
.size Reset_Handler, .-Reset_Handler
arch/arm/cortex-m4/coreclock.c
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/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/**
* @file coreclock.c
* @brief derived from ST standard peripheral library
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
#include "stm32f4xx.h"
uint32_t system_core_clock = 16000000;
const uint8_t ahb_presc_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t apb_presc_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp) {
case 0x00:
system_core_clock = HSI_VALUE;
break;
case 0x04:
system_core_clock = HSE_VALUE;
break;
case 0x08:
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
else
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
system_core_clock = pllvco/pllp;
break;
default:
system_core_clock = HSI_VALUE;
break;
}
tmp = ahb_presc_table[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
system_core_clock >>= tmp;
}
arch/arm/cortex-m4/interrupt.c
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include <xs_base.h>
#include <xs_isr.h>
#include <misc.h>
#include <stm32f4xx.h>
x_base __attribute__((naked)) DisableLocalInterrupt()
{
asm volatile ("MRS r0, PRIMASK");
asm volatile ("CPSID I");
asm volatile ("BX LR ");
}
void __attribute__((naked)) EnableLocalInterrupt(x_base level)
{
asm volatile ("MSR PRIMASK, r0");
asm volatile ("BX LR");
}
int32 ArchEnableHwIrq(uint32 irq_num)
{
NVIC_InitTypeDef nvic_init;
nvic_init.NVIC_IRQChannel = irq_num;
nvic_init.NVIC_IRQChannelPreemptionPriority = 0;
nvic_init.NVIC_IRQChannelSubPriority = 0;
nvic_init.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&nvic_init);
return EOK;
}
int32 ArchDisableHwIrq(uint32 irq_num)
{
NVIC_InitTypeDef nvic_init;
nvic_init.NVIC_IRQChannel = irq_num;
nvic_init.NVIC_IRQChannelPreemptionPriority = 0;
nvic_init.NVIC_IRQChannelSubPriority = 0;
nvic_init.NVIC_IRQChannelCmd = DISABLE;
NVIC_Init(&nvic_init);
return EOK;
}
extern void KTaskOsAssignAfterIrq(void *context);
void IsrEntry()
{
uint32 ipsr;
__asm__ volatile("MRS %0, IPSR" : "=r"(ipsr));
isrManager.done->incCounter();
isrManager.done->handleIrq(ipsr);
KTaskOsAssignAfterIrq(NONE);
isrManager.done->decCounter();
}
uintptr_t *Svcall(unsigned int ipsr , uintptr_t* contex )
{
#ifdef TASK_ISOLATION
__svcall(contex);
#endif
return contex;
}
arch/arm/cortex-m4/interrupt_vector.S
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/**
******************************************************************************
* @file startup_stm32f407xx.s
* @author MCD Application Team
* @brief STM32F407xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/**
* @file coreclock.c
* @brief derived from ST standard peripheral library
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
.globl InterruptVectors
/******************************************************************************
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type InterruptVectors, %object
.size InterruptVectors, .-InterruptVectors
InterruptVectors:
.word __stack_end__
.word Reset_Handler
.word NMI_Handler
.word HardFaultHandler
.word MemFaultHandler
.word BusFault_Handler
.word UsageFault_Handler
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word IsrEntry
.word SVC_Entry /* SVC */
.word IsrEntry /* DebugMon */
.word IsrEntry
.word PendSV_Handler
.word IsrEntry /* SysTick */
.word IsrEntry /* Window WatchDog */
.word IsrEntry /* PVD through EXTI Line detection */
.word IsrEntry /* Tamper and TimeStamps through the EXTI line */
.word IsrEntry /* RTC Wakeup through the EXTI line */
.word IsrEntry /* FLASH */
.word IsrEntry /* RCC */
.word IsrEntry /* EXTI Line0 */
.word IsrEntry /* EXTI Line1 */
.word IsrEntry /* EXTI Line2 */
.word IsrEntry /* EXTI Line3 */
.word IsrEntry /* EXTI Line4 */
.word IsrEntry /* DMA1 Stream 0 */
.word IsrEntry /* DMA1 Stream 1 */
.word IsrEntry /* DMA1 Stream 2 */
.word IsrEntry /* DMA1 Stream 3 */
.word IsrEntry /* DMA1 Stream 4 */
.word IsrEntry /* DMA1 Stream 5 */
.word IsrEntry /* DMA1 Stream 6 */
.word IsrEntry /* ADC1, ADC2 and ADC3s */
.word IsrEntry /* CAN1 TX */
.word IsrEntry /* CAN1 RX0 */
.word IsrEntry /* CAN1 RX1 */
.word IsrEntry /* CAN1 SCE */
.word IsrEntry /* External Line[9:5]s */
.word IsrEntry /* TIM1 Break and TIM9 */
.word IsrEntry /* TIM1 Update and TIM10 */
.word IsrEntry /* TIM1 Trigger and Commutation and TIM11 */
.word IsrEntry /* TIM1 Capture Compare */
.word IsrEntry /* TIM2 */
.word IsrEntry /* TIM3 */
.word IsrEntry /* TIM4 */
.word IsrEntry /* I2C1 Event */
.word IsrEntry /* I2C1 Error */
.word IsrEntry /* I2C2 Event */
.word IsrEntry /* I2C2 Error */
.word IsrEntry /* SPI1 */
.word IsrEntry /* SPI2 */
.word IsrEntry /* USART1 */
.word IsrEntry /* USART2 */
.word IsrEntry /* USART3 */
.word IsrEntry /* External Line[15:10]s */
.word IsrEntry /* RTC Alarm (A and B) through EXTI Line */
.word IsrEntry /* USB OTG FS Wakeup through EXTI line */
.word IsrEntry /* TIM8 Break and TIM12 */
.word IsrEntry /* TIM8 Update and TIM13 */
.word IsrEntry /* TIM8 Trigger and Commutation and TIM14 */
.word IsrEntry /* TIM8 Capture Compare */
.word IsrEntry /* DMA1 Stream7 */
.word IsrEntry /* FSMC */
.word IsrEntry /* SDIO */
.word IsrEntry /* TIM5 */
.word IsrEntry /* SPI3 */
.word IsrEntry /* UART4 */
.word IsrEntry /* UART5 */
.word IsrEntry /* TIM6 and DAC1&2 underrun errors */
.word IsrEntry /* TIM7 */
.word IsrEntry /* DMA2 Stream 0 */
.word IsrEntry /* DMA2 Stream 1 */
.word IsrEntry /* DMA2 Stream 2 */
.word IsrEntry /* DMA2 Stream 3 */
.word IsrEntry /* DMA2 Stream 4 */
.word IsrEntry /* Ethernet */
.word IsrEntry /* Ethernet Wakeup through EXTI line */
.word IsrEntry /* CAN2 TX */
.word IsrEntry /* CAN2 RX0 */
.word IsrEntry /* CAN2 RX1 */
.word IsrEntry /* CAN2 SCE */
.word IsrEntry /* USB OTG FS */
.word IsrEntry /* DMA2 Stream 5 */
.word IsrEntry /* DMA2 Stream 6 */
.word IsrEntry /* DMA2 Stream 7 */
.word IsrEntry /* USART6 */
.word IsrEntry /* I2C3 event */
.word IsrEntry /* I2C3 error */
.word IsrEntry /* USB OTG HS End Point 1 Out */
.word IsrEntry /* USB OTG HS End Point 1 In */
.word IsrEntry /* USB OTG HS Wakeup through EXTI */
.word IsrEntry /* USB OTG HS */
.word IsrEntry /* DCMI */
.word IsrEntry /* CRYP crypto */
.word IsrEntry /* Hash and Rng */
.word IsrEntry /* FPU */
arch/arm/cortex-m4/kswitch.h
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/****************************************************************************
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file kswitch.h
* @brief risc-v ecall function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
/*************************************************
File name: kswitch.h
Description: arm svc function
Others: take incubator-nuttx arch/arm/include/armv7-m/syscall.h for references
https://github.com/apache/incubator-nuttx/tree/master/arch/arm/include/armv7-m/syscall.h
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. Modify function name for a unified
2. Add some functions when there is no system call
*************************************************/
#ifndef __XS_ARM_M4_KSWITCH_H__
#define __XS_ARM_M4_KSWITCH_H__
#include <stdint.h>
// #include <xs_service.h>
#include "../../../kernel/include/xs_service.h"
#ifdef TASK_ISOLATION
#define KERNEL_SWITCH 0x00
/****************************************************************************
* kernel switch functions
****************************************************************************/
/* SVC call with call number and no parameters */
static inline unsigned long KSwitch0(unsigned int nbr)
{
register long reg0 __asm__("r0") = (long)(nbr);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(KERNEL_SWITCH), "r"(reg0)
: "memory"
);
return reg0;
}
/* SVC call with call number and one parameter */
static inline unsigned long KSwitch1(unsigned int nbr, unsigned long parm1)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(KERNEL_SWITCH), "r"(reg0), "r"(reg1)
: "memory"
);
return reg0;
}
/* SVC call with call number and two parameters */
static inline unsigned long KSwitch2(unsigned int nbr, unsigned long parm1,
unsigned long parm2)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(KERNEL_SWITCH), "r"(reg0), "r"(reg1), "r"(reg2)
: "memory"
);
return reg0;
}
/* SVC call with call number and four parameters.
*
*/
static inline unsigned long KSwitch3(unsigned int nbr, unsigned long parm1,
unsigned long parm2, unsigned long parm3)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg1 __asm__("r1") = (long)(parm1);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg3 __asm__("r3") = (long)(parm3);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(KERNEL_SWITCH), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3)
: "memory"
);
return reg0;
}
static inline unsigned long KSwitch4(unsigned int nbr, unsigned long parm1,
unsigned long parm2, unsigned long parm3,
unsigned long parm4)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(KERNEL_SWITCH), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4)
: "memory"
);
return reg0;
}
/* SVC call with call number and five parameters.
*
*/
static inline unsigned long KSwitch5(unsigned int nbr, unsigned long parm1,
unsigned long parm2, unsigned long parm3,
unsigned long parm4, unsigned long parm5)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg5 __asm__("r5") = (long)(parm5);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(KERNEL_SWITCH), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4), "r"(reg5)
: "memory"
);
return reg0;
}
/* SVC call with call number and six parameters.
*
*/
static inline unsigned long KSwitch6(unsigned int nbr, unsigned long parm1,
unsigned long parm2, unsigned long parm3,
unsigned long parm4, unsigned long parm5,
unsigned long parm6)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg6 __asm__("r6") = (long)(parm6);
register long reg5 __asm__("r5") = (long)(parm5);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(KERNEL_SWITCH), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
: "memory"
);
return reg0;
}
#else
static inline unsigned long KSwitch0(unsigned int knum)
{
uintptr_t param[1] = {0};
uint8_t num = 0;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch1(unsigned int knum, unsigned long arg1)
{
uintptr_t param[1] = {0};
uint8_t num = 1;
param[0] = arg1;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch2(unsigned int knum, unsigned long arg1,
unsigned long arg2)
{
uintptr_t param[2] = {0};
uint8_t num = 2;
param[0] = arg1;
param[1] = arg2;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch3(unsigned int knum, unsigned long arg1,
unsigned long arg2, unsigned long arg3)
{
uintptr_t param[3] = {0};
uint8_t num = 3;
param[0] = arg1;
param[1] = arg2;
param[2] = arg3;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch4(unsigned int knum, unsigned long arg1,
unsigned long arg2, unsigned long arg3,
unsigned long arg4)
{
uintptr_t param[4] = {0};
uint8_t num = 4;
param[0] = arg1;
param[1] = arg2;
param[2] = arg3;
param[3] = arg4;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch5(unsigned int knum, unsigned long arg1,
unsigned long arg2, unsigned long arg3,
unsigned long arg4, unsigned long arg5)
{
uintptr_t param[5] = {0};
uint8_t num = 5;
param[0] = arg1;
param[1] = arg2;
param[2] = arg3;
param[3] = arg4;
param[4] = arg5;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch6(unsigned int knum, unsigned long arg1,
unsigned long arg2, unsigned long arg3,
unsigned long arg4, unsigned long arg5,
unsigned long arg6)
{
uintptr_t param[6] = {0};
uint8_t num = 6;
param[0] = arg1;
param[1] = arg2;
param[2] = arg3;
param[3] = arg4;
param[4] = arg5;
param[5] = arg6;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
}
#endif
#endif
arch/arm/cortex-m4/mpu.c
+204
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@@ -0,0 +1,204 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include "stm32f4xx.h"
#include "mpu.h"
#include "board.h"
#include <xs_isolation.h>
void MpuEnable(uint32_t option)
{
MPU->CTRL = MPU_ENABLE | option;
__DSB();
__ISB();
return ;
}
void MpuDisable(void)
{
__DMB();
MPU->CTRL = 0;
return;
}
void MpuClearRegion(uint8_t region)
{
__DMB();
MPU->RNR = region;
MPU->RBAR = 0;
MPU->RASR = 0;
return;
}
void MpuClearAllRegion(void)
{
__DMB();
for (int i = 0 ; i < 8 ; i++) {
MPU->RNR = i;
MPU->RBAR = 0;
MPU->RASR = 0;
}
return;
}
int8_t MpuAllocateRegion(void *task_mpu)
{
if(task_mpu == NONE)
return -1;
struct Mpu *mpu = (struct Mpu *)task_mpu;
int8_t free_region;
if ( mpu->count < MPU_MAX_REGION_NUM - 1) {
free_region = mpu->count;
mpu->count ++;
}
else
free_region = -1;
return free_region ;
}
size_t MpuLog2Ceil(size_t size)
{
size_t csize = 0;
while (size > 0) {
size >>= 1;
csize ++;
}
return csize;
}
int8_t MpuAddRegion(void *task_mpu, x_base addr , size_t size , uint8_t type)
{
if(task_mpu == NONE)
return -1;
struct Mpu *mpu = (struct Mpu *)task_mpu;
uint32_t l2size;
int8_t region ;
region = MpuAllocateRegion(mpu);
if (region < 0 ) {
// KPrintf("MPU region full \n");
return region;
}
uint32_t flag = 0;
switch (type)
{
case REGION_TYPE_CODE:
flag = MPU_RASR_AP_RO_RO | MPU_RASR_TEX_0 | MPU_RASR_C | MPU_RASR_S;
break;
case REGION_TYPE_DATA:
flag = MPU_RASR_AP_RW_RW | MPU_RASR_TEX_0 | MPU_RASR_C | MPU_RASR_S ;
break;
case REGION_TYPE_BSS:
flag = MPU_RASR_AP_RW_RW | MPU_RASR_TEX_0 | MPU_RASR_C | MPU_RASR_S ;
break;
case REGION_TYPE_HEAP:
flag = MPU_RASR_AP_RW_RW | MPU_RASR_TEX_0 | MPU_RASR_C | MPU_RASR_S ;
break;
default:
break;
}
l2size = MpuLog2Ceil(size);
addr = MPU_ALIGN(addr , 1 << l2size );
// KPrintf( "region:%d , size : 0x%08x, l2size: %d , mpu_size : 0x%08x \n",region, size, l2size , MPU_RASR_REGION_SIZE(l2size) );
mpu->region[region].config.rasr = flag |MPU_RASR_REGION_SIZE(l2size) | MPU_ENABLE;
mpu->region[region].config.rbar = addr | MPU_RBAR_VALID | region ; //rbar must set region number
return region;
}
x_err_t MpuInit(void **task_mpu)
{
x_base addr_start;
uint32_t addr_size;
uint32_t flag;
if (MPU->TYPE == 0) {
KPrintf("mpu not surport \n");
return -1 ;
}
// KPrintf("mpu init ...\n");
struct Mpu *mpu;
mpu = (struct Mpu *)malloc(sizeof(struct Mpu));
memset(mpu, 0, sizeof(struct Mpu));
if (mpu == NONE)
return -ENOMEMORY;
MpuDisable();
MpuClearAllRegion(); //clear
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
//user flash
addr_start = USER_TEXT_START;
addr_size = USER_TEXT_END - USER_TEXT_START;
MpuAddRegion(mpu, addr_start , addr_size, REGION_TYPE_CODE);
//user sram
addr_start = USER_SRAM_START;
addr_size = USER_SRAM_END - USER_SRAM_START;
MpuAddRegion(mpu, addr_start , addr_size, REGION_TYPE_HEAP);
*task_mpu = mpu;
return EOK;
}
void MpuFree(void *task_mpu)
{
if(task_mpu == NONE)
return;
MpuDisable();
MpuClearAllRegion(); //clear
x_free(task_mpu);
}
void MpuLoad(void *task_mpu)
{
// KPrintf("MPU load .. \n");
MpuDisable();
MpuClearAllRegion(); //clear
if(task_mpu == NONE)
return;
struct Mpu *mpu = (struct Mpu *)task_mpu;
uint8_t region = 0 ;
#if 0
for ( region = 0 ; region <= mpu->count -1 ; region ++ ){
KPrintf("region: %d\n",region);
KPrintf("rasr 0x%08x \n",mpu->region[region].config.rasr);
KPrintf("rbar 0x%08x \n",mpu->region[region].config.rbar);
KPrintf("\n");
}
#endif
for ( region = 0 ; region <= mpu->count -1 ; region ++ ){
MPU->RNR = region;
MPU->RBAR = mpu->region[region].config.rbar;
MPU->RASR = mpu->region[region].config.rasr;
}
__DSB();
__ISB();
MpuEnable(MPU_PRIVDEFENA);
}
arch/arm/cortex-m4/mpu.h
+98
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#ifndef MPU_H
#define MPU_H
#include <xs_base.h>
#include <xs_klist.h>
#define MPU_ALIGN(size, align) (((size)) & ~((align) - 1))
#define USER_TEXT_START (uintptr_t)( USERSPACE )
#define USER_TEXT_END (uintptr_t)( USERSPACE->us_textend )
#define USER_SRAM_START (uintptr_t)( USERSPACE->us_datastart )
#define USER_SRAM_END (uintptr_t)( USER_MEMORY_END_ADDRESS )
#define MPU_MAX_REGION_NUM 8
#define MPU_SYS_REGION_RESERVER 8
/* MPU Control Register Bit Definitions */
#define MPU_ENABLE (1 << 0) /* Bit 0: Enable the MPU */
#define MPU_HFNMIENA (1 << 1) /* Bit 1: Enable MPU during hard fault, NMI, and FAULTMAS */
#define MPU_PRIVDEFENA (1 << 2) /* Bit 2: Enable privileged access to default memory map */
#define MPU_RBAR_VALID (1 << 4)
#define MPU_RASR_ENABLE (1 << 0) /* Bit 0: Region enable */
#define MPU_RASR_REGION_SIZE(n) ((n-1) << 1)
#define MPU_RASR_AP_NO_NO (0 << 24) /* P:None U:None */
#define MPU_RASR_AP_RW_NO (1 << 24) /* P:RW U:None */
#define MPU_RASR_AP_RW_RO (2 << 24) /* P:RW U:RO */
#define MPU_RASR_AP_RW_RW (3 << 24) /* P:RW U:RW */
#define MPU_RASR_AP_RO_NO (5 << 24) /* P:RO U:None */
#define MPU_RASR_AP_RO_RO (6 << 24) /* P:RO U:RO */
#define MPU_RASR_RASR_XN (1 << 28) /* Bit 28: Instruction access disable */
#define MPU_RASR_SRD_MASK (0xff << 8)
#define MPU_RASR_SRD_0 (0x01 << 8)
#define MPU_RASR_SRD_1 (0x02 << 8)
#define MPU_RASR_SRD_2 (0x04 << 8)
#define MPU_RASR_SRD_3 (0x08 << 8)
#define MPU_RASR_SRD_4 (0x10 << 8)
#define MPU_RASR_SRD_5 (0x20 << 8)
#define MPU_RASR_SRD_6 (0x40 << 8)
#define MPU_RASR_SRD_7 (0x80 << 8)
#define MPU_RASR_TEX_SHIFT (19) /* Bits 19-21: TEX Address Permission */
#define MPU_RASR_TEX_MASK (7 << 19)
#define MPU_RASR_TEX_0 (0 << 19) /* Strongly Ordered */
#define MPU_RASR_TEX_1 (1 << 19) /* Normal */
#define MPU_RASR_TEX_2 (2 << 19) /* Device */
#define MPU_RASR_TEX_BB(bb) ((4|(bb)) << 19)
#define MPU_RASR_B (1 << 16) /* Bit 16: Bufferable */
#define MPU_RASR_C (1 << 17) /* Bit 17: Cacheable */
#define MPU_RASR_S (1 << 18) /* Bit 18: Shareable */
struct MpuConfig
{
uint32_t rasr;
uint32_t rbar;
};
struct MpuRegion
{
x_base start;
x_base size;
struct MpuConfig config;
};
struct Mpu
{
uint8_t count;
struct MpuRegion region[MPU_MAX_REGION_NUM];
};
void MpuEnable( uint32_t option);
void MpuDisable(void);
x_err_t MpuInit(void **task_mpu);
void MpuLoad(void *task_mpu);
#endif
arch/arm/cortex-m4/svc_entry.S
+82
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@@ -0,0 +1,82 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include <xsconfig.h>
.globl SVC_Entry
.syntax unified
.thumb
.file "svc_entry.S"
.text
.type SVC_Entry, %function
.thumb_func
SVC_Entry:
MRS r3, PRIMASK
CPSID I
MRS r0, ipsr
MRS r1, psp /* R1=The process stack pointer (PSP) */
STMDB r1!, {r3-r11} /* Save the remaining registers plus the SP/PRIMASK values */
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
MOV r2, #0x00
TST lr, #0x10
MOVEQ r2, #0x01
STMFD r1!, {r2}
#endif
//LDR sp, =__stack_tp
PUSH {lr}
BL Svcall /* R0=IRQ, R1=register save (msp) */
POP {lr}
MOV r1, r0
#ifdef TASK_ISOLATION
PUSH {lr}
BL GetTaskPrivilege
POP {lr}
#endif
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
LDMFD r1!, {r2}
#endif
LDMIA r1!, {r3-r11} /* Recover R4-R11, FPU flag and PRIMASK*/
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
ORR lr, lr, #0x10
CMP r2, #0
BICNE lr, lr, #0x10
#endif
MSR psp, r1
MRS r2, control
#ifdef TASK_ISOLATION
CMP r0, #1
BEQ unprivilege
privilege:
BIC r2, r2, #0x01
B exit
unprivilege:
ORR r2, r2, #0x01
#else
BIC r2, r2, #0x01
#endif
exit:
MSR control, r2
ORR lr, lr, #0x04
MSR PRIMASK, r3
BX lr
arch/arm/cortex-m4/svc_handle.c
+97
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@@ -0,0 +1,97 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include <xs_base.h>
#include <stdint.h>
#include "svc_handle.h"
#include <xs_service.h>
#include <xs_ktask.h>
static void SvcDispatch(void) __attribute__ ((naked, no_instrument_function));
static void SvcDispatch(void)
{
__asm__ __volatile__
(
" mov r12, sp\n" /* Calculate (orig_SP - new_SP) */
" sub r12, r12, #36\n"
" and r12, r12, #7\n"
" add r12, r12, #36\n"
" sub sp, sp, r12\n"
" str r0, [sp, #0]\n"
" str r1, [sp, #4]\n"
" str r2, [sp, #8]\n"
" str r3, [sp, #12]\n"
" str r4, [sp, #16]\n"
" str r5, [sp, #20]\n"
" str r6, [sp, #24]\n"
" str lr, [sp, #28]\n"
" str r12, [sp, #32]\n"
" mov r0, sp\n"
" ldr r12, =SvcHandle\n"
" blx r12\n"
" ldr lr, [sp, #28]\n"
" ldr r2, [sp, #32]\n"
" add sp, sp, r2\n"
" svc 1"
);
}
void __svcall(uintptr_t* contex)
{
uint32_t svc_number;
KTaskDescriptorType tid;
tid = GetKTaskDescriptor();
svc_number = ((char *)contex[REG_INT_PC ])[-2];
switch (svc_number) {
case 0: //svc handler
tid->task_dync_sched_member.svc_return = contex[REG_INT_PC];
//tid->task_dync_sched_member.exc_return = contex[REG_INT_EXC_RETURN];
tid->task_dync_sched_member.isolation_status = 1;
contex[REG_INT_PC] = (uint32_t)SvcDispatch & ~1;
//contex[REG_INT_EXC_RETURN] = EXC_RETURN_PRIVTHR;
break;
case 1: // svc return
contex[REG_INT_PC] = tid->task_dync_sched_member.svc_return;
//contex[REG_INT_EXC_RETURN] = tid->task_dync_sched_member.exc_return;
tid->task_dync_sched_member.isolation_status = 0;
break;
default:
KPrintf("unsurport svc call number :%d\n",svc_number);
break;
}
}
uintptr_t SvcHandle(uintptr_t *sp)
{
uint32_t service_num = 0;
service_num = ((uint32_t) sp[0]); //r0
//KPrintf("SvcHandle service_num :%d\n ",service_num);
uint8_t param_num = g_service_table[service_num].param_num;
uintptr_t *param = sp + 1;
return g_service_table[service_num].fun(service_num,param,param_num) ;
}
uint32_t GetTaskPrivilege(void){
uint32_t unprivileg = 0;
struct TaskDescriptor *task = GetKTaskDescriptor();
//KPrintf("GetTaskPrivilege : %s\n", task->task_base_info.name);
if (task->task_dync_sched_member.isolation_flag == 1 && task->task_dync_sched_member.isolation_status == 0) {
unprivileg = 1;
} else {
unprivileg = 0;
}
return unprivileg;
}
arch/arm/cortex-m4/svc_handle.h
+69
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@@ -0,0 +1,69 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#ifndef __INC_SVC_HANDLE_H__
#define __INC_SVC_HANDLE_H__
#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__)
#define INT_FPU_REGS (1)
#else
#define INT_FPU_REGS (0)
#endif
#define HW_INT_REGS (8)
#define SW_INT_REGS (9 + INT_FPU_REGS)
#define REG_INT_R0 (SW_INT_REGS + 0) /* R0 */
#define REG_INT_R1 (SW_INT_REGS + 1) /* R1 */
#define REG_INT_R2 (SW_INT_REGS + 2) /* R2 */
#define REG_INT_R3 (SW_INT_REGS + 3) /* R3 */
#define REG_INT_R12 (SW_INT_REGS + 4) /* R12 */
#define REG_INT_R14 (SW_INT_REGS + 5) /* R14 = LR */
#define REG_INT_PC (SW_INT_REGS + 6) /* R15 = PC */
#define REG_INT_XPSR (SW_INT_REGS + 7) /* xPSR */
#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__)
#define REG_INT_FPU_FLAG (0) /* fpu flag */
#define REG_INT_PRIMASK (1) /* PRIMASK */
#define REG_INT_R4 (2) /* R4 */
#define REG_INT_R5 (3) /* R5 */
#define REG_INT_R6 (4) /* R6 */
#define REG_INT_R7 (5) /* R7 */
#define REG_INT_R8 (6) /* R8 */
#define REG_INT_R9 (7) /* R9 */
#define REG_INT_R10 (8) /* R10 */
#define REG_INT_R11 (9) /* R11 */
//#define REG_INT_EXC_RETURN (10) /* EXC_RETURN */
#else
#define REG_INT_PRIMASK (0) /* PRIMASK */
#define REG_INT_R4 (1) /* R4 */
#define REG_INT_R5 (2) /* R5 */
#define REG_INT_R6 (3) /* R6 */
#define REG_INT_R7 (4) /* R7 */
#define REG_INT_R8 (5) /* R8 */
#define REG_INT_R9 (6) /* R9 */
#define REG_INT_R10 (7) /* R10 */
#define REG_INT_R11 (8) /* R11 */
//#define REG_INT_EXC_RETURN (9) /* EXC_RETURN */
#endif
#define EXC_RETURN_BASE 0xffffffe1
#define EXC_RETURN_PROCESS_STACK (1 << 2)
#define EXC_RETURN_THREAD_MODE (1 << 3)
#define EXC_RETURN_STD_CONTEXT (1 << 4)
#define EXC_RETURN_PRIVTHR (EXC_RETURN_BASE | EXC_RETURN_STD_CONTEXT | EXC_RETURN_THREAD_MODE |EXC_RETURN_PROCESS_STACK)
#define EXC_RETURN_UNPRIVTHR (EXC_RETURN_BASE | EXC_RETURN_STD_CONTEXT | EXC_RETURN_THREAD_MODE |EXC_RETURN_PROCESS_STACK)
#endif
arch/arm/cortex-m4/system_init.c
+92
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@@ -0,0 +1,92 @@
/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/**
* @file coreclock.c
* @brief derived from ST standard peripheral library
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
#include "stm32f4xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
#define VECT_TAB_OFFSET 0x00
void SystemInit(void)
{
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));
RCC->CR |= (uint32_t)0x00000001;
RCC->CFGR = 0x00000000;
RCC->CR &= (uint32_t)0xFEF6FFFF;
RCC->PLLCFGR = 0x24003010;
RCC->CR &= (uint32_t)0xFFFBFFFF;
RCC->CIR = 0x00000000;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInitExtMemCtl();
#endif
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET;
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET;
#endif
}
arch/arm/cortex-m7/Makefile
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arch/arm/shared/Makefile
+4
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@@ -0,0 +1,4 @@
SRC_FILES := pendsv.S prepare_ahwstack.c arm32_switch.c
include $(KERNEL_ROOT)/compiler.mk
arch/arm/shared/arm32_switch.c
+154
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@@ -0,0 +1,154 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include <xs_base.h>
#include <xs_ktask.h>
#define SCB_VTOR "0xE000ED08"
#define NVIC_INT_CTRL "0xE000ED04"
#define NVIC_SYSPRI2 "0xE000ED20"
#define NVIC_PENDSV_PRI "0x00FF0000"
#define NVIC_PENDSVSET "0x10000000"
void __attribute__((naked)) HwInterruptcontextSwitch(x_ubase from, x_ubase to, struct TaskDescriptor *to_task, void *context)
{
asm volatile ("LDR r4, =KtaskSwitchInterruptFlag");
asm volatile ("LDR r5, [r4]");
asm volatile ("CMP r5, #1");
asm volatile ("BEQ Arm32SwitchReswitch");
asm volatile ("MOV r5, #1");
asm volatile ("STR r5, [r4]");
asm volatile ("LDR r4, =InterruptFromKtask");
asm volatile ("STR r0, [r4]");
asm volatile ("B Arm32SwitchReswitch");
}
void __attribute__((naked)) Arm32SwitchReswitch()
{
asm volatile ("LDR r4, =InterruptToKtask");
asm volatile ("STR r1, [r4]");
asm volatile ("LDR r4, =InterruptToKtaskDescriptor");
asm volatile ("STR r2, [r4]");
asm volatile ("LDR r0, =" NVIC_INT_CTRL);
asm volatile ("LDR r1, =" NVIC_PENDSVSET);
asm volatile ("STR r1, [r0]");
asm volatile ("BX LR");
}
void __attribute__((naked)) SwitchKtaskContext(x_ubase from, x_ubase to, struct TaskDescriptor *to_task)
{
asm volatile("B HwInterruptcontextSwitch");
}
void __attribute__((naked)) SwitchKtaskContextTo(x_ubase to, struct TaskDescriptor *to_task)
{
asm volatile ("LDR r2, =InterruptToKtask");
asm volatile ("STR r0, [r2]");
asm volatile ("LDR r2, =InterruptToKtaskDescriptor");
asm volatile ("STR r1, [r2]");
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
asm volatile ("MRS r2, CONTROL");
asm volatile ("BIC r2, #0x04");
asm volatile ("MSR CONTROL, r2");
#endif
asm volatile ("LDR r1, =InterruptFromKtask");
asm volatile ("MOV r0, #0x0");
asm volatile ("STR r0, [r1]");
asm volatile ("LDR r1, =KtaskSwitchInterruptFlag");
asm volatile ("MOV r0, #1");
asm volatile ("STR r0, [r1]");
asm volatile ("LDR r0, =" NVIC_SYSPRI2);
asm volatile ("LDR r1, =" NVIC_PENDSV_PRI);
asm volatile ("LDR.W r2, [r0,#0x00]");
asm volatile ("ORR r1,r1,r2");
asm volatile ("STR r1, [r0]");
asm volatile ("LDR r0, =" NVIC_INT_CTRL);
asm volatile ("LDR r1, =" NVIC_PENDSVSET);
asm volatile ("STR r1, [r0]");
asm volatile ("LDR r0, =" SCB_VTOR);
asm volatile ("LDR r0, [r0]");
asm volatile ("LDR r0, [r0]");
asm volatile ("NOP");
asm volatile ("MSR msp, r0");
asm volatile ("CPSIE F");
asm volatile ("CPSIE I");
asm volatile ("BX lr");
}
void __attribute__((naked)) HardFaultHandler()
{
asm volatile ("MRS r0, msp");
asm volatile ("TST lr, #0x04");
asm volatile ("BEQ Arm32SwitchGetSpDone");
asm volatile ("MRS r0, psp");
asm volatile ("B Arm32SwitchGetSpDone");
}
void __attribute__((naked)) Arm32SwitchGetSpDone()
{
asm volatile ("MRS r3, primask");
asm volatile ("STMFD r0!, {r3 - r11}");
asm volatile ("STMFD r0!, {lr}");
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
asm volatile ("MOV r4, #0x00");
asm volatile ("TST lr, #0x10");
asm volatile ("MOVEQ r4, #0x01");
asm volatile ("STMFD r0!, {r4}");
#endif
asm volatile ("TST lr, #0x04");
asm volatile ("BEQ Arm32SwitchUpdateMsp");
asm volatile ("MSR psp, r0");
asm volatile ("B Arm32SwitchUpdateDone");
asm volatile ("B Arm32SwitchUpdateMsp");
}
void __attribute__((naked)) Arm32SwitchUpdateMsp()
{
asm volatile ("MSR msp, r0");
asm volatile ("B Arm32SwitchUpdateDone");
}
void __attribute__((naked)) Arm32SwitchUpdateDone()
{
asm volatile ("PUSH {LR}");
asm volatile ("BL HwHardFaultException");
asm volatile ("POP {LR}");
asm volatile ("ORR lr, lr, #0x04");
asm volatile ("BX lr");
}
void __attribute__((naked)) MemFaultHandler()
{
asm volatile ("MRS r0, msp");
asm volatile ("TST lr, #0x04");
asm volatile ("BEQ Arm32Switch1");
asm volatile ("MRS r0, psp");
asm volatile ("B Arm32Switch1");
}
void __attribute__((naked)) Arm32Switch1()
{
asm volatile ("MRS r3, primask");
asm volatile ("STMFD r0!, {r3 - r11}");
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
asm volatile ("MOV r4, #0x00");
asm volatile ("TST lr, #0x10");
asm volatile ("MOVEQ r4, #0x01");
asm volatile ("STMFD r0!, {r4}");
#endif
asm volatile ("STMFD r0!, {lr}");
asm volatile ("PUSH {LR}");
asm volatile ("BL MemFaultHandle");
asm volatile ("POP {LR}");
asm volatile ("ORR lr, lr, #0x04");
asm volatile ("BX lr");
}
arch/arm/shared/pendsv.S
+118
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@@ -0,0 +1,118 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2009-10-11 Bernard first version
* 2012-01-01 aozima support context switch load/store FPU register.
* 2013-06-18 aozima add restore MSP feature.
* 2013-06-23 aozima support lazy stack optimized.
* 2018-07-24 aozima enhancement hard fault exception handler.
*/
/*************************************************
File name: pendsv.S
Description: PendSV interrupt handler
Others: take RT-Thread v4.0.2/libcpu/arm/cortex-m4/context_gcc.S for references
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
*************************************************/
#include <xsconfig.h>
.cpu cortex-m4
.syntax unified
.thumb
.text
.equ SCB_VTOR, 0xE000ED08
.equ NVIC_INT_CTRL, 0xE000ED04
.equ NVIC_SYSPRI2, 0xE000ED20
.equ NVIC_PENDSV_PRI, 0x00FF0000
.equ NVIC_PENDSVSET, 0x10000000
.globl PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
MRS r3, PRIMASK
CPSID I
LDR r0, =KtaskSwitchInterruptFlag
LDR r1, [r0]
CBZ r1, pendsv_exit
MOV r1, #0x00
STR r1, [r0]
LDR r0, =InterruptFromKtask
LDR r1, [r0]
CBZ r1, switch_to_task
MRS r1, psp
STMFD r1!, {r3 - r11}
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
MOV r4, #0x00
TST lr, #0x10
MOVEQ r4, #0x01
STMFD r1!, {r4}
#endif
LDR r0, [r0]
STR r1, [r0]
switch_to_task:
PUSH {lr}
BL UpdateRunningTask
POP {lr}
#ifdef TASK_ISOLATION
PUSH {lr}
BL GetTaskPrivilege
POP {lr}
#endif
LDR r1, =InterruptToKtask
LDR r1, [r1]
LDR r1, [r1]
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
LDMFD r1!, {r2}
#endif
LDMFD r1!, {r3 - r11}
MSR psp, r1
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
ORR lr, lr, #0x10
CMP r2, #0
BICNE lr, lr, #0x10
#endif
MRS r2, control
#ifdef TASK_ISOLATION
CMP r0, #1
BEQ unprivilege
privilege:
BIC r2, r2, #0x01
B exit
unprivilege:
ORR r2, r2, #0x01
#else
BIC r2, r2, #0x01
#endif
exit:
MSR control, r2
pendsv_exit:
ORR lr, lr, #0x04
MSR PRIMASK, r3
BX lr
arch/arm/shared/prepare_ahwstack.c
+425
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@@ -0,0 +1,425 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include <xs_base.h>
#include <xs_ktask.h>
#include <xs_assign.h>
#include "svc_handle.h"
#include "stm32f4xx.h"
#include <board.h>
#if (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__))
#define USE_FPU 1
#else
#define USE_FPU 0
#endif
uint32 InterruptFromKtask;
uint32 InterruptToKtask;
uint32 KtaskSwitchInterruptFlag;
uint32 InterruptToKtaskDescriptor;
#define RunningKTask Assign.os_running_task
static x_err_t (*ExceptionHook)(void *context) = NONE;
struct ExceptionStackRegister
{
uint32 r0;
uint32 r1;
uint32 r2;
uint32 r3;
uint32 r12;
uint32 lr;
uint32 pc;
uint32 psr;
};
struct StackRegisterContent
{
#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__)
uint32 flag;
#endif
uint32 primask;
uint32 r4;
uint32 r5;
uint32 r6;
uint32 r7;
uint32 r8;
uint32 r9;
uint32 r10;
uint32 r11;
// uint32 exc_ret;
struct ExceptionStackRegister ExErrorStackContex;
};
struct ExceptionStackFrameFpu
{
uint32 r0;
uint32 r1;
uint32 r2;
uint32 r3;
uint32 r12;
uint32 lr;
uint32 pc;
uint32 psr;
#if USE_FPU
uint32 S0;
uint32 S1;
uint32 S2;
uint32 S3;
uint32 S4;
uint32 S5;
uint32 S6;
uint32 S7;
uint32 S8;
uint32 S9;
uint32 S10;
uint32 S11;
uint32 S12;
uint32 S13;
uint32 S14;
uint32 S15;
uint32 FPSCR;
uint32 NO_NAME;
#endif
};
struct StackFrameFpu
{
uint32 flag;
uint32 r4;
uint32 r5;
uint32 r6;
uint32 r7;
uint32 r8;
uint32 r9;
uint32 r10;
uint32 r11;
#if USE_FPU
uint32 s16;
uint32 s17;
uint32 s18;
uint32 s19;
uint32 s20;
uint32 s21;
uint32 s22;
uint32 s23;
uint32 s24;
uint32 s25;
uint32 s26;
uint32 s27;
uint32 s28;
uint32 s29;
uint32 s30;
uint32 s31;
#endif
struct ExceptionStackFrameFpu ExErrorStackContex;
};
uint8 KTaskStackSetup(struct TaskDescriptor *task)
{
struct StackRegisterContent* StackContex;
int i = 0;
task->stack_point = (uint8 *)ALIGN_MEN_DOWN((x_ubase)(task->task_base_info.stack_start + task->task_base_info.stack_depth), 8);
task->stack_point -= sizeof(struct StackRegisterContent);
StackContex = (struct StackRegisterContent*)task->stack_point;
for (i = 0; i < sizeof(struct StackRegisterContent) / sizeof(uint32); i++)
((uint32 *)StackContex)[i] = 0xfadeface;
StackContex->ExErrorStackContex.r0 = (unsigned long)task->task_base_info.func_param;
StackContex->ExErrorStackContex.pc = (unsigned long)task->task_base_info.func_entry ;
StackContex->ExErrorStackContex.psr = 0x01000000L;
StackContex->primask = 0x00000000L;
#ifdef SEPARATE_COMPILE
if(task->task_dync_sched_member.isolation_flag == 1 ) {
//StackContex->exc_ret = EXC_RETURN_UNPRIVTHR;
StackContex->ExErrorStackContex.lr = (unsigned long)USERSPACE->us_taskquit;
} else {
//StackContex->exc_ret = EXC_RETURN_PRIVTHR;
StackContex->ExErrorStackContex.lr = (unsigned long)KTaskQuit;
}
#else
//StackContex->exc_ret = EXC_RETURN_PRIVTHR;
StackContex->ExErrorStackContex.lr = (unsigned long)KTaskQuit;
#endif
#if USE_FPU
StackContex->flag = 0;
#endif
return EOK;
}
void HwExceptionInstall(x_err_t (*exception_handle)(void *context))
{
ExceptionHook = exception_handle;
}
#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28)
#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C)
#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34)
#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38)
#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C)
#define SCB_RESET_VALUE 0x05FA0004
#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28)
#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29)
#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A)
#ifdef TOOL_SHELL
static void UsageFaultTrack(void)
{
KPrintf("usage fault:\n");
KPrintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR);
if(SCB_CFSR_UFSR & (1<<0))
KPrintf("UNDEFINSTR ");
if(SCB_CFSR_UFSR & (1<<1))
KPrintf("INVSTATE ");
if(SCB_CFSR_UFSR & (1<<2))
KPrintf("INVPC ");
if(SCB_CFSR_UFSR & (1<<3))
KPrintf("NOCP ");
if(SCB_CFSR_UFSR & (1<<8))
KPrintf("UNALIGNED ");
if(SCB_CFSR_UFSR & (1<<9))
KPrintf("DIVBYZERO ");
KPrintf("\n");
}
static void BusFaultTrack(void)
{
KPrintf("bus fault:\n");
KPrintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR);
if(SCB_CFSR_BFSR & (1<<0))
KPrintf("IBUSERR ");
if(SCB_CFSR_BFSR & (1<<1))
KPrintf("PRECISERR ");
if(SCB_CFSR_BFSR & (1<<2))
KPrintf("IMPRECISERR ");
if(SCB_CFSR_BFSR & (1<<3))
KPrintf("UNSTKERR ");
if(SCB_CFSR_BFSR & (1<<4))
KPrintf("STKERR ");
if(SCB_CFSR_BFSR & (1<<7))
KPrintf("SCB->BFAR:%08X\n", SCB_BFAR);
else
KPrintf("\n");
}
static void MemManageFaultTrack(void)
{
KPrintf("mem manage fault:\n");
KPrintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR);
if(SCB_CFSR_MFSR & (1<<0))
KPrintf("IACCVIOL ");
if(SCB_CFSR_MFSR & (1<<1))
KPrintf("DACCVIOL ");
if(SCB_CFSR_MFSR & (1<<3))
KPrintf("MUNSTKERR ");
if(SCB_CFSR_MFSR & (1<<4))
KPrintf("MSTKERR ");
if(SCB_CFSR_MFSR & (1<<7))
KPrintf("SCB->MMAR:%08X\n", SCB_MMAR);
else
KPrintf("\n");
}
static void HardFaultTrack(void)
{
if(SCB_HFSR & (1UL<<1))
KPrintf("failed vector fetch\n");
if(SCB_HFSR & (1UL<<30)) {
if(SCB_CFSR_BFSR)
BusFaultTrack();
if(SCB_CFSR_MFSR)
MemManageFaultTrack();
if(SCB_CFSR_UFSR)
UsageFaultTrack();
}
if(SCB_HFSR & (1UL<<31))
KPrintf("debug event\n");
}
#endif
struct ExceptionInfo
{
uint32 ExcReturn;
struct StackRegisterContent stackframe;
};
void HwHardFaultException(struct ExceptionInfo *ExceptionInfo)
{
extern long ShowTask(void);
struct ExErrorStackContex* ExceptionStack = &ExceptionInfo->stackframe.ExErrorStackContex;
struct StackRegisterContent* context = &ExceptionInfo->stackframe;
if (ExceptionHook != NONE) {
x_err_t result = ExceptionHook(ExceptionStack);
if (result == EOK) return;
}
KPrintf("psr: 0x%08x\n", context->ExErrorStackContex.psr);
KPrintf("r00: 0x%08x\n", context->ExErrorStackContex.r0);
KPrintf("r01: 0x%08x\n", context->ExErrorStackContex.r1);
KPrintf("r02: 0x%08x\n", context->ExErrorStackContex.r2);
KPrintf("r03: 0x%08x\n", context->ExErrorStackContex.r3);
KPrintf("r04: 0x%08x\n", context->r4);
KPrintf("r05: 0x%08x\n", context->r5);
KPrintf("r06: 0x%08x\n", context->r6);
KPrintf("r07: 0x%08x\n", context->r7);
KPrintf("r08: 0x%08x\n", context->r8);
KPrintf("r09: 0x%08x\n", context->r9);
KPrintf("r10: 0x%08x\n", context->r10);
KPrintf("r11: 0x%08x\n", context->r11);
//KPrintf("exc_ret: 0x%08x\n", context->exc_ret);
KPrintf("r12: 0x%08x\n", context->ExErrorStackContex.r12);
KPrintf(" lr: 0x%08x\n", context->ExErrorStackContex.lr);
KPrintf(" pc: 0x%08x\n", context->ExErrorStackContex.pc);
if (ExceptionInfo->ExcReturn & (1 << 2)) {
KPrintf("hard fault on task: %s\r\n\r\n", GetKTaskDescriptor()->task_base_info.name);
#ifdef TOOL_SHELL
ShowTask();
#endif
} else {
KPrintf("hard fault on handler\r\n\r\n");
}
if ( (ExceptionInfo->ExcReturn & 0x10) == 0)
KPrintf("FPU active!\r\n");
#ifdef TOOL_SHELL
HardFaultTrack();
#endif
while (1);
}
void UpdateRunningTask(void)
{
RunningKTask = (struct TaskDescriptor *)InterruptToKtaskDescriptor;
}
void MemFaultExceptionPrint(struct ExceptionInfo *ExceptionInfo)
{
extern long ShowTask(void);
struct ExErrorStackContex* ExceptionStack = &ExceptionInfo->stackframe.ExErrorStackContex;
struct StackRegisterContent* context = &ExceptionInfo->stackframe;
if (ExceptionHook != NONE) {
x_err_t result = ExceptionHook(ExceptionStack);
if (result == EOK) return;
}
KPrintf("psr: 0x%08x\n", context->ExErrorStackContex.psr);
KPrintf("r00: 0x%08x\n", context->ExErrorStackContex.r0);
KPrintf("r01: 0x%08x\n", context->ExErrorStackContex.r1);
KPrintf("r02: 0x%08x\n", context->ExErrorStackContex.r2);
KPrintf("r03: 0x%08x\n", context->ExErrorStackContex.r3);
KPrintf("r04: 0x%08x\n", context->r4);
KPrintf("r05: 0x%08x\n", context->r5);
KPrintf("r06: 0x%08x\n", context->r6);
KPrintf("r07: 0x%08x\n", context->r7);
KPrintf("r08: 0x%08x\n", context->r8);
KPrintf("r09: 0x%08x\n", context->r9);
KPrintf("r10: 0x%08x\n", context->r10);
KPrintf("r11: 0x%08x\n", context->r11);
KPrintf("exc_ret: 0x%08x\n", ExceptionInfo->ExcReturn);
KPrintf("r12: 0x%08x\n", context->ExErrorStackContex.r12);
KPrintf(" lr: 0x%08x\n", context->ExErrorStackContex.lr);
KPrintf(" pc: 0x%08x\n", context->ExErrorStackContex.pc);
if (ExceptionInfo->ExcReturn & (1 << 2)) {
KPrintf("hard fault on task: %s\r\n\r\n", GetKTaskDescriptor()->task_base_info.name);
#ifdef TOOL_SHELL
ShowTask();
#endif
} else {
KPrintf("hard fault on handler\r\n\r\n");
}
if ((ExceptionInfo->ExcReturn & 0x10) == 0)
KPrintf("FPU active!\r\n");
KPrintf("CFSR: 0x%08x \n", (*((volatile unsigned long *)(SCB->CFSR))) );
KPrintf("HFSR: 0x%08x \n", (*((volatile unsigned long *)(SCB->HFSR))) );
KPrintf("DFSR: 0x%08x \n",(*((volatile unsigned long *)(SCB->DFSR))) );
KPrintf("MMFAR: 0x%08x \n",(*((volatile unsigned long *)(SCB->MMFAR))));
KPrintf("BFAR: 0x%08x \n",(*((volatile unsigned long *)(SCB->BFAR))));
KPrintf("AFSR: 0x%08x \n",(*((volatile unsigned long *)(SCB->AFSR))));
#ifdef TOOL_SHELL
HardFaultTrack();
#endif
while (1);
}
void MemFaultHandle(uintptr_t *sp)
{
#ifdef TASK_ISOLATION
struct TaskDescriptor *task;
task = GetKTaskDescriptor();
if( task->task_dync_sched_member.isolation_flag == 1){
KPrintf("\nSegmentation fault, task: %s\n", task->task_base_info.name);
KTaskQuit();
}
else
#endif
{
MemFaultExceptionPrint((struct ExceptionInfo *)sp);
}
}
void ShutdownCpu(void)
{
KPrintf("shutdown...\n");
CHECK(0);
}
__attribute__((weak)) void HwCpuReset(void)
{
SCB_AIRCR = SCB_RESET_VALUE;
}