From 5de4b9eec037fae64f9a9f5d3c9d0d578a1a241c Mon Sep 17 00:00:00 2001 From: Liu_Weichao Date: Thu, 1 Sep 2022 09:20:15 +0800 Subject: [PATCH] add ch438 for xidatong-riscv64 board --- .../include/connect_ch438.h | 343 ++++---- .../third_party_driver/ch438/connect_ch438.c | 4 +- .../include/connect_ch438.h | 282 +++---- .../third_party_driver/ch438/connect_ch438.c | 2 +- .../XiZi/board/xidatong-riscv64/board.c | 11 +- .../third_party_driver/Kconfig | 9 +- .../third_party_driver/Makefile | 4 + .../third_party_driver/ch438/Kconfig | 39 + .../third_party_driver/ch438/Makefile | 4 + .../third_party_driver/ch438/connect_ch438.c | 776 ++++++++++++++++++ .../third_party_driver/gpio/drv_io_config.c | 23 +- .../include/connect_ch438.h | 257 ++++++ .../third_party_driver/include/connect_gpio.h | 4 +- .../third_party_driver/include/connect_i2c.h | 4 +- .../include/connect_touch.h | 13 +- .../third_party_driver/include/connect_uart.h | 4 +- .../include/drv_io_config.h | 32 +- Ubiquitous/XiZi/resources/serial/dev_serial.c | 3 +- 18 files changed, 1466 insertions(+), 348 deletions(-) create mode 100644 Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/Kconfig create mode 100644 Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/Makefile create mode 100755 Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/connect_ch438.c create mode 100755 Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_ch438.h diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_ch438.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_ch438.h index 05942f5fb..86bb0fa35 100755 --- a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_ch438.h +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_ch438.h @@ -31,260 +31,245 @@ /* chip definition */ /* CH438serial port0 register address */ -#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */ -#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */ -#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */ -#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */ -#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */ -#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */ -#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */ -#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */ -#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */ -#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */ -#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */ +#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */ +#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */ +#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */ +#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */ +#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */ +#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */ +#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */ +#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */ +#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */ +#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port1 register address */ -#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */ -#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */ -#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */ -#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */ -#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */ -#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */ -#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */ -#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */ -#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */ -#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */ -#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */ +#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */ +#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */ +#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */ +#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */ +#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */ +#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */ +#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */ +#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */ +#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */ +#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port2 register address */ -#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */ -#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */ -#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */ -#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */ -#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */ -#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */ -#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */ -#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */ -#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */ -#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */ -#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */ +#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */ +#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */ +#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */ +#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */ +#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */ +#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */ +#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */ +#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */ +#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */ +#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port3 register address */ -#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */ -#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */ -#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */ -#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */ -#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */ -#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */ -#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */ -#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */ -#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */ -#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */ -#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */ +#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */ +#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */ +#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */ +#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */ +#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */ +#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */ +#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */ +#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */ +#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */ +#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port4 register address */ -#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */ -#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */ -#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */ -#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */ -#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */ -#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */ -#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */ -#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */ -#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */ -#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */ -#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */ +#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */ +#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */ +#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */ +#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */ +#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */ +#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */ +#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */ +#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */ +#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */ +#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port5 register address */ -#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */ -#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */ -#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */ -#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */ -#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */ -#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */ -#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */ -#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */ -#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */ -#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */ -#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */ +#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */ +#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */ +#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */ +#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */ +#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */ +#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */ +#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */ +#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */ +#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */ +#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port6 register address */ -#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */ -#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */ -#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */ -#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */ -#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */ -#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */ -#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */ -#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */ -#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */ -#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */ -#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */ +#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */ +#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */ +#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */ +#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */ +#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */ +#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */ +#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */ +#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */ +#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */ +#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port7 register address */ -#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */ -#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */ -#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */ -#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */ -#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */ -#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */ -#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */ -#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */ -#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */ -#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */ -#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */ +#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */ +#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */ +#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */ +#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */ +#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */ +#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */ +#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */ +#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */ +#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */ +#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */ -#define REG_SSR_ADDR 0x4F /* pecial status register address */ +#define REG_SSR_ADDR 0x4F /* pecial status register address */ /* IER register bit */ -#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */ -#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */ -#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */ -#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */ -#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */ -#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */ -#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */ -#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */ +#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */ +#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */ +#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */ +#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */ +#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */ +#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */ +#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */ +#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */ /* IIR register bit */ -#define BIT_IIR_FIFOENS1 0x80 -#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */ +#define BIT_IIR_FIFOENS1 0x80 +#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */ /* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted, 1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */ -#define BIT_IIR_IID3 0x08 -#define BIT_IIR_IID2 0x04 -#define BIT_IIR_IID1 0x02 -#define BIT_IIR_NOINT 0x01 +#define BIT_IIR_IID3 0x08 +#define BIT_IIR_IID2 0x04 +#define BIT_IIR_IID1 0x02 +#define BIT_IIR_NOINT 0x01 /* FCR register bit */ /* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */ -#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ -#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ +#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ +#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ -#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */ -#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */ -#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */ +#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */ /* LCR register bit */ -#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */ -#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/ +#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */ +#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/ /* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */ -#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */ -#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */ +#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */ +#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */ -#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */ -#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */ +#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */ +#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */ /* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */ -#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */ -#define BIT_LCR_WORDSZ0 0x01 +#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */ +#define BIT_LCR_WORDSZ0 0x01 /* MCR register bit */ -#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */ -#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */ -#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */ -#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */ -#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */ -#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */ +#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */ +#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */ +#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */ +#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */ +#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */ +#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */ /* LSR register bit */ -#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */ +#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */ #define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */ -#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/ -#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/ -#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */ -#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */ -#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */ -#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */ +#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/ +#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/ +#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */ +#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */ +#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */ +#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */ /* MSR register bit */ -#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */ -#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */ -#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */ -#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */ -#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */ -#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */ -#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */ -#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */ +#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */ +#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */ +#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */ +#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */ +#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */ +#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */ +#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */ +#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */ /* Interrupt status code */ -#define INT_NOINT 0x01 /* There is no interruption */ -#define INT_THR_EMPTY 0x02 /* THR empty interruption */ -#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */ -#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */ -#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */ -#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */ +#define INT_NOINT 0x01 /* There is no interruption */ +#define INT_THR_EMPTY 0x02 /* THR empty interruption */ +#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */ +#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */ +#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */ +#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */ -#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */ +#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */ -#define Fpclk 1843200 /* Define the internal clock frequency */ +#define Fpclk 1843200 /* Define the internal clock frequency */ -#if 0 -#define CH438_D0_PIN GET_PIN(E,2) -#define CH438_D1_PIN GET_PIN(E,3) -#define CH438_D2_PIN GET_PIN(E,4) -#define CH438_D3_PIN GET_PIN(E,5) -#define CH438_D4_PIN GET_PIN(E,6) -#define CH438_D5_PIN GET_PIN(F,6) -#define CH438_D6_PIN GET_PIN(F,7) -#define CH438_D7_PIN GET_PIN(F,8) -#define CH438_NWR_PIN GET_PIN(C,4) -#define CH438_NRD_PIN GET_PIN(C,5) -#define CH438_NCS_PIN GET_PIN(B,1) -#define CH438_ALE_PIN GET_PIN(B,2) -#define CH438_INT_PIN GET_PIN(C,13) -#endif #define CH438_D0_PIN 1 #define CH438_D1_PIN 2 #define CH438_D2_PIN 3 #define CH438_D3_PIN 4 #define CH438_D4_PIN 5 -#define CH438_D5_PIN 18 -#define CH438_D6_PIN 19 -#define CH438_D7_PIN 20 -#define CH438_NWR_PIN 44 -#define CH438_NRD_PIN 45 -#define CH438_NCS_PIN 47 -#define CH438_ALE_PIN 48 -#define CH438_INT_PIN 7 -#define DIR_485CH1_PIN 22 //485ch1 = ext_uart3 -#define DIR_485CH2_PIN 21 //485ch2 = ext_uart2 -#define DIR_485CH3_PIN 123 //485ch3 = ext_uart7 +#define CH438_D5_PIN 18 +#define CH438_D6_PIN 19 +#define CH438_D7_PIN 20 +#define CH438_NWR_PIN 44 +#define CH438_NRD_PIN 45 +#define CH438_NCS_PIN 47 +#define CH438_ALE_PIN 48 +#define CH438_INT_PIN 7 +#define DIR_485CH1_PIN 22 //485ch1 = ext_uart3 +#define DIR_485CH2_PIN 21 //485ch2 = ext_uart2 +#define DIR_485CH3_PIN 123 //485ch3 = ext_uart7 void CH438RegTest(unsigned char num); void Set485Input(uint8 ch_no); diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/connect_ch438.c b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/connect_ch438.c index 81d2d15ac..46ee058b5 100755 --- a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/connect_ch438.c +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/connect_ch438.c @@ -917,7 +917,7 @@ static uint32 Ch438Init(struct SerialDriver *serial_drv, struct SerialCfgParam * return ERROR; } - /* config ALE pin as output*/ + /* config 485 DIR pin as output*/ pin_cfg.pin = BSP_485_dir; ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); if (ret != EOK) { @@ -925,7 +925,7 @@ static uint32 Ch438Init(struct SerialDriver *serial_drv, struct SerialCfgParam * return ERROR; } - /* config ALE pin as input pullup*/ + /* config INT pin as input pullup*/ pin_cfg.pin = BSP_CH438_INT_PIN; pin_cfg.mode = GPIO_CFG_INPUT_PULLUP; ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_ch438.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_ch438.h index 09e005da1..6a6772670 100755 --- a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_ch438.h +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_ch438.h @@ -29,226 +29,226 @@ /* CH438serial port0 register address */ -#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */ -#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */ -#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */ -#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */ -#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */ -#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */ -#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */ +#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */ +#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */ +#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */ +#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */ +#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */ +#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */ +#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */ #define REG_LSR0_ADDR 0x05 /* serial port0line status register address */ -#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */ -#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */ -#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */ +#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */ +#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port1 register address */ -#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */ -#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */ +#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */ +#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */ #define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */ -#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */ -#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */ -#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */ -#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */ -#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */ -#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */ -#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */ -#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */ +#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */ +#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */ +#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */ +#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */ +#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */ +#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */ +#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port2 register address */ -#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */ -#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */ +#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */ +#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */ #define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */ -#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */ -#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */ -#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */ -#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */ -#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */ -#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */ -#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */ -#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */ +#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */ +#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */ +#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */ +#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */ +#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */ +#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */ +#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port3 register address */ -#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */ -#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */ +#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */ +#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */ #define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */ -#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */ -#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */ -#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */ -#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */ -#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */ -#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */ -#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */ -#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */ +#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */ +#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */ +#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */ +#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */ +#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */ +#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */ +#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port4 register address */ -#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */ -#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */ +#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */ +#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */ #define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */ -#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */ -#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */ -#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */ -#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */ -#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */ -#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */ -#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */ -#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */ +#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */ +#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */ +#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */ +#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */ +#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */ +#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */ +#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port5 register address */ -#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */ -#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */ -#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */ +#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */ +#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */ +#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */ #define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */ -#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */ -#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */ -#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */ -#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */ -#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */ -#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */ -#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */ +#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */ +#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */ +#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */ +#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */ +#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */ +#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port6 register address */ -#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */ -#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */ -#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */ +#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */ +#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */ +#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */ #define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */ -#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */ -#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */ -#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */ -#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */ -#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */ -#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */ -#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */ +#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */ +#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */ +#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */ +#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */ +#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */ +#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */ /* CH438serial port7 register address */ -#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */ -#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */ -#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */ +#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */ +#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */ +#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */ #define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */ -#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */ -#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */ -#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */ -#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */ -#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */ -#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */ -#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */ -#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */ +#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */ +#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */ +#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */ +#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */ +#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */ +#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */ +#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */ -#define REG_SSR_ADDR 0x4F /* pecial status register address */ +#define REG_SSR_ADDR 0x4F /* pecial status register address */ /* IER register bit */ -#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */ -#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */ -#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */ -#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */ -#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */ -#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */ -#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */ -#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */ +#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */ +#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */ +#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */ +#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */ +#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */ +#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */ +#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */ +#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */ /* IIR register bit */ -#define BIT_IIR_FIFOENS1 0x80 -#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */ +#define BIT_IIR_FIFOENS1 0x80 +#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */ /* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted, 1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */ -#define BIT_IIR_IID3 0x08 -#define BIT_IIR_IID2 0x04 -#define BIT_IIR_IID1 0x02 -#define BIT_IIR_NOINT 0x01 +#define BIT_IIR_IID3 0x08 +#define BIT_IIR_IID2 0x04 +#define BIT_IIR_IID1 0x02 +#define BIT_IIR_NOINT 0x01 /* FCR register bit */ /* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */ -#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ -#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ +#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ +#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ -#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */ -#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */ #define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */ /* LCR register bit */ -#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */ -#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/ +#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */ +#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/ /* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */ -#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */ -#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */ +#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */ +#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */ -#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */ -#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */ +#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */ +#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */ /* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */ -#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */ -#define BIT_LCR_WORDSZ0 0x01 +#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */ +#define BIT_LCR_WORDSZ0 0x01 /* MCR register bit */ -#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */ -#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */ -#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */ -#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */ -#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */ -#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */ +#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */ +#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */ +#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */ +#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */ +#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */ +#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */ /* LSR register bit */ -#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */ -#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */ -#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/ -#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/ -#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */ -#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */ +#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */ +#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */ +#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/ +#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/ +#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */ +#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */ #define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */ -#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */ +#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */ /* MSR register bit */ -#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */ +#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */ #define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */ -#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */ -#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */ -#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */ -#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */ -#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */ -#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */ +#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */ +#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */ +#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */ +#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */ +#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */ +#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */ /* Interrupt status code */ -#define INT_NOINT 0x01 /* There is no interruption */ -#define INT_THR_EMPTY 0x02 /* THR empty interruption */ +#define INT_NOINT 0x01 /* There is no interruption */ +#define INT_THR_EMPTY 0x02 /* THR empty interruption */ #define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */ -#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */ -#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */ -#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */ +#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */ +#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */ +#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */ -#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */ +#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */ #define Fpclk 1843200 /* Define the internal clock frequency */ diff --git a/Ubiquitous/XiZi/board/xidatong-arm32/third_party_driver/ch438/connect_ch438.c b/Ubiquitous/XiZi/board/xidatong-arm32/third_party_driver/ch438/connect_ch438.c index 4932bcf7b..2fb9645d5 100644 --- a/Ubiquitous/XiZi/board/xidatong-arm32/third_party_driver/ch438/connect_ch438.c +++ b/Ubiquitous/XiZi/board/xidatong-arm32/third_party_driver/ch438/connect_ch438.c @@ -33,7 +33,7 @@ static void Ch438Irq(void *parameter) /** * The time delay function. * - * @param microseconds. + * @param us. */ static void ImxrtUdelay(uint32 us) { diff --git a/Ubiquitous/XiZi/board/xidatong-riscv64/board.c b/Ubiquitous/XiZi/board/xidatong-riscv64/board.c index 08ad3ac16..337c5e468 100644 --- a/Ubiquitous/XiZi/board/xidatong-riscv64/board.c +++ b/Ubiquitous/XiZi/board/xidatong-riscv64/board.c @@ -56,8 +56,8 @@ extern void entry(void); extern void SecondaryCpuCStart(void); extern int IoConfigInit(void); extern int HwI2cInit(void); -extern int HwLcdInit(void); extern int HwTouchInit(void); +extern int HwCh438Init(void); #if defined(FS_VFS) && defined (MOUNT_SDCARD) #include @@ -158,12 +158,12 @@ struct InitSequenceDesc _board_init[] = { "hw_pin", HwGpioInit }, { "io_config", IoConfigInit }, #endif +#ifdef BSP_USING_CH438 + { "hw_extuart", HwCh438Init }, +#endif #ifdef BSP_USING_I2C { "hw_i2c", HwI2cInit }, #endif -#ifdef BSP_USING_LCD - { "hw_lcd", HwLcdInit }, -#endif #ifdef BSP_USING_TOUCH {"touch", HwTouchInit }, #endif @@ -222,7 +222,4 @@ void HwCpuReset(void) sysctl->soft_reset.soft_reset = 1; while(RET_TRUE); } - SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),Reboot, HwCpuReset, reset machine ); - - diff --git a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/Kconfig index 38b1d80b7..c15389bf5 100755 --- a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/Kconfig +++ b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/Kconfig @@ -1,3 +1,10 @@ +menuconfig BSP_USING_CH438 +bool "Using CH438 device" +default n +if BSP_USING_CH438 +source "$BSP_DIR/third_party_driver/ch438/Kconfig" +endif + menuconfig BSP_USING_DMA bool "Using DMA device" default y @@ -32,7 +39,7 @@ endif menuconfig BSP_USING_PLIC bool "Using PLIC device" -default n +default y if BSP_USING_PLIC source "$BSP_DIR/third_party_driver/plic/Kconfig" endif diff --git a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/Makefile b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/Makefile index f7eb56e6e..4c330f3b3 100644 --- a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/Makefile +++ b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/Makefile @@ -1,5 +1,9 @@ SRC_FILES := sleep.c +ifeq ($(CONFIG_BSP_USING_CH438),y) + SRC_DIR += ch438 +endif + ifeq ($(CONFIG_BSP_USING_DMA),y) SRC_DIR += dma endif diff --git a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/Kconfig b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/Kconfig new file mode 100644 index 000000000..389b67525 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/Kconfig @@ -0,0 +1,39 @@ +config CH438_BUS_NAME + string + default "extuart" + +config CH438_DRIVER_NAME + string + default "extuart_drv" + +config CH438_DEVICE_NAME_0 + string + default "extuart_dev0" + +config CH438_DEVICE_NAME_1 + string + default "extuart_dev1" + +config CH438_DEVICE_NAME_2 + string + default "extuart_dev2" + +config CH438_DEVICE_NAME_3 + string + default "extuart_dev3" + +config CH438_DEVICE_NAME_4 + string + default "extuart_dev4" + +config CH438_DEVICE_NAME_5 + string + default "extuart_dev5" + +config CH438_DEVICE_NAME_6 + string + default "extuart_dev6" + +config CH438_DEVICE_NAME_7 + string + default "extuart_dev7" diff --git a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/Makefile b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/Makefile new file mode 100644 index 000000000..47968574c --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := connect_ch438.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/connect_ch438.c b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/connect_ch438.c new file mode 100755 index 000000000..033ca65e9 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/connect_ch438.c @@ -0,0 +1,776 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ch438.c +* @brief support to register ch438 pointer and function +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-08-24 +*/ + +#include +#include +#include +#include + +static uint8 offset_addr[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38}; /* Offset address of serial port number */ +static uint8 interrupt_num[8] = {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80}; + +static void CH438SetOutput(void) +{ + gpiohs_set_drive_mode(FPIOA_CH438_D0, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D1, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D2, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D3, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D4, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D5, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D6, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D7, GPIO_DM_OUTPUT); +} + +static void CH438SetInput(void) +{ + gpiohs_set_drive_mode(FPIOA_CH438_D0, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D1, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D2, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D3, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D4, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D5, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D6, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D7, GPIO_DM_INPUT_PULL_UP); +} + +uint8 ReadCH438Data( uint8 addr ) +{ + uint8 dat = 0; + + gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH); + + CH438SetOutput(); + usleep(1); + + if(addr &0x80) gpiohs_set_pin(FPIOA_CH438_D7, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7, GPIO_PV_LOW); + if(addr &0x40) gpiohs_set_pin(FPIOA_CH438_D6, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6, GPIO_PV_LOW); + if(addr &0x20) gpiohs_set_pin(FPIOA_CH438_D5, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5, GPIO_PV_LOW); + if(addr &0x10) gpiohs_set_pin(FPIOA_CH438_D4, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4, GPIO_PV_LOW); + if(addr &0x08) gpiohs_set_pin(FPIOA_CH438_D3, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3, GPIO_PV_LOW); + if(addr &0x04) gpiohs_set_pin(FPIOA_CH438_D2, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2, GPIO_PV_LOW); + if(addr &0x02) gpiohs_set_pin(FPIOA_CH438_D1, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1, GPIO_PV_LOW); + if(addr &0x01) gpiohs_set_pin(FPIOA_CH438_D0, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0, GPIO_PV_LOW); + + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_LOW); + + usleep(1); + + CH438SetInput(); + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_LOW); + + usleep(1); + + dat = 0; + if (gpiohs_get_pin(FPIOA_CH438_D7)) dat |= 0x80; + if (gpiohs_get_pin(FPIOA_CH438_D6)) dat |= 0x40; + if (gpiohs_get_pin(FPIOA_CH438_D5)) dat |= 0x20; + if (gpiohs_get_pin(FPIOA_CH438_D4)) dat |= 0x10; + if (gpiohs_get_pin(FPIOA_CH438_D3)) dat |= 0x08; + if (gpiohs_get_pin(FPIOA_CH438_D2)) dat |= 0x04; + if (gpiohs_get_pin(FPIOA_CH438_D1)) dat |= 0x02; + if (gpiohs_get_pin(FPIOA_CH438_D0)) dat |= 0x01; + + gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH); + + usleep(1); + + return dat; +} + +static void WriteCH438Data(uint8 addr, uint8 dat) +{ + gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH); + + CH438SetOutput(); + usleep(1); + + if(addr &0x80) gpiohs_set_pin(FPIOA_CH438_D7, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7, GPIO_PV_LOW); + if(addr &0x40) gpiohs_set_pin(FPIOA_CH438_D6, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6, GPIO_PV_LOW); + if(addr &0x20) gpiohs_set_pin(FPIOA_CH438_D5, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5, GPIO_PV_LOW); + if(addr &0x10) gpiohs_set_pin(FPIOA_CH438_D4, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4, GPIO_PV_LOW); + if(addr &0x08) gpiohs_set_pin(FPIOA_CH438_D3, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3, GPIO_PV_LOW); + if(addr &0x04) gpiohs_set_pin(FPIOA_CH438_D2, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2, GPIO_PV_LOW); + if(addr &0x02) gpiohs_set_pin(FPIOA_CH438_D1, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1, GPIO_PV_LOW); + if(addr &0x01) gpiohs_set_pin(FPIOA_CH438_D0, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0, GPIO_PV_LOW); + + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_LOW); + usleep(1); + + if(dat &0x80) gpiohs_set_pin(FPIOA_CH438_D7, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7, GPIO_PV_LOW); + if(dat &0x40) gpiohs_set_pin(FPIOA_CH438_D6, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6, GPIO_PV_LOW); + if(dat &0x20) gpiohs_set_pin(FPIOA_CH438_D5, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5, GPIO_PV_LOW); + if(dat &0x10) gpiohs_set_pin(FPIOA_CH438_D4, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4, GPIO_PV_LOW); + if(dat &0x08) gpiohs_set_pin(FPIOA_CH438_D3, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3, GPIO_PV_LOW); + if(dat &0x04) gpiohs_set_pin(FPIOA_CH438_D2, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2, GPIO_PV_LOW); + if(dat &0x02) gpiohs_set_pin(FPIOA_CH438_D1, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1, GPIO_PV_LOW); + if(dat &0x01) gpiohs_set_pin(FPIOA_CH438_D0, GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0, GPIO_PV_LOW); + + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_LOW); + + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH); + + usleep(1); + + CH438SetInput(); + + return; +} + +static void WriteCH438Block( uint8 mAddr, uint8 mLen, uint8 *mBuf ) +{ + while (mLen--) { + WriteCH438Data(mAddr, *mBuf++); + } +} + +void CH438UartSend( uint8 ext_uart_no,uint8 *Data, uint8 Num ) +{ + uint8 REG_LSR_ADDR,REG_THR_ADDR; + + REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + + while (1) { + while((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_TEMT) == 0); + + if (Num <= 128) { + WriteCH438Block(REG_THR_ADDR, Num, Data); + break; + } else { + WriteCH438Block(REG_THR_ADDR, 128, Data); + Num -= 128; + Data += 128; + } + } +} + +uint8 CH438UartRecv(uint8 ext_uart_no, uint8 *buf, x_size_t size ) +{ + x_size_t rcv_num = 0; + uint8 dat = 0; + uint8 REG_LSR_ADDR, REG_RBR_ADDR; + uint8 *read_buffer; + x_size_t buffer_index = 0; + + REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + + read_buffer = buf; + + while ((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0); + + while (((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) && (size != 0)) { + dat = ReadCH438Data(REG_RBR_ADDR); + + *read_buffer = dat; + read_buffer++; + buffer_index++; + + if (BUFFSIZE == buffer_index) { + buffer_index = 0; + read_buffer = buf; + } + + rcv_num = rcv_num + 1; + --size; + } + + return rcv_num; +} + +void CH438PortInit( uint8 ext_uart_no, uint32 BaudRate ) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* Reset the serial port */ + MdelayKTask(50); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = (Fpclk >> 4) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL);/* Set baud rate */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN);/* Set FIFO mode */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0); + + WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV); + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2); + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR) | BIT_FCR_TFIFORST); +} + +void CH438PortInitParityCheck(uint8 ext_uart_no,uint32 BaudRate) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET);/* Reset the serial port */ + MdelayKTask(50); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = (Fpclk >> 4) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL);/* Set baud rate */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_FIFOEN);/* Set FIFO mode */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0 | BIT_LCR_PAREN | BIT_LCR_PARMODE0); + + WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV); + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2); + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR) | BIT_FCR_TFIFORST); +} + +void CH438PortDisable(uint8 ext_uart_no, uint32 BaudRate) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* Reset the serial port */ + MdelayKTask(50); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = (Fpclk >> 4) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL);/* Set baud rate */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN );/* Set FIFO mode */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0); + + WriteCH438Data(REG_IER_ADDR, 0); + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2); + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR) | BIT_FCR_TFIFORST); +} + +void CH438Port6Init(uint8 ext_uart_no, uint32 BaudRate) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET);/* Reset the serial port */ + MdelayKTask(50); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; + WriteCH438Data(REG_LCR_ADDR, dlab); + + //div = ( 22118400 >> 4 ) / BaudRate; + div = ( 44236800 >> 4 ) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL);/* Set baud rate */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN);/* Set FIFO mode */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0); + + WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV | BIT_IER1_CK2X); + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2); + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR) | BIT_FCR_TFIFORST); +} + +static uint32 Ch438Configure(struct SerialCfgParam *ext_serial_cfg) +{ + NULL_PARAM_CHECK(ext_serial_cfg); + + switch (ext_serial_cfg->data_cfg.port_configure) + { + case PORT_CFG_INIT: + CH438PortInit(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + case PORT_CFG_PARITY_CHECK: + CH438PortInitParityCheck(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + case PORT_CFG_DISABLE: + CH438PortDisable(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + case PORT_CFG_DIV: + CH438Port6Init(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + default: + KPrintf("Ch438Configure do not support configure %d\n", ext_serial_cfg->data_cfg.port_configure); + return ERROR; + break; + } + + return EOK; +} + +static uint32 Ch438Init(struct SerialDriver *serial_drv, struct SerialCfgParam *ext_serial_cfg) +{ + NULL_PARAM_CHECK(serial_drv); + + gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH); + + return Ch438Configure(ext_serial_cfg); +} + +static uint32 Ch438DrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + struct SerialCfgParam *ext_serial_cfg = (struct SerialCfgParam *)configure_info->private_data; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = Ch438Init(serial_drv, ext_serial_cfg); + break; + default: + break; + } + + return ret; +} + +static uint32 Ch438WriteData(void *dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(write_param); + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + CH438UartSend(dev_param->ext_uart_no, (uint8 *)write_param->buffer, write_param->size); + + return EOK; +} + +static uint32 Ch438ReadData(void *dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(read_param); + + uint32 rcv_cnt = 0; + uint8 rcv_num = 0; + uint8 gInterruptStatus; + uint8 InterruptStatus; + static uint8 dat; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + uint8 REG_LSR_ADDR; + uint8 REG_MSR_ADDR; + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->private_data; + + do { + rcv_cnt++; + gInterruptStatus = ReadCH438Data(REG_SSR_ADDR); + + if(!gInterruptStatus) { + dat = ReadCH438Data(REG_LCR0_ADDR); + dat = ReadCH438Data(REG_IER0_ADDR); + dat = ReadCH438Data(REG_MCR0_ADDR); + dat = ReadCH438Data(REG_LSR0_ADDR); + dat = ReadCH438Data(REG_MSR0_ADDR); + dat = ReadCH438Data(REG_RBR0_ADDR); + dat = ReadCH438Data(REG_THR0_ADDR); + dat = ReadCH438Data(REG_IIR0_ADDR); + dat = dat; + } else { + KPrintf("gInterruptStatus 0x%x dev_param %p ext_uart_no %d interrupt_num 0x%x cnt %d\n", + gInterruptStatus, dev_param, dev_param->ext_uart_no, interrupt_num[dev_param->ext_uart_no], rcv_cnt); + if ( gInterruptStatus & interrupt_num[dev_param->ext_uart_no]) { /* Detect which serial port is interrupted */ + REG_LCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IIR0_ADDR; + REG_LSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LSR0_ADDR; + REG_MSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MSR0_ADDR; + + /* The interrupted state of a read serial port */ + InterruptStatus = ReadCH438Data(REG_IIR_ADDR) & 0x0f; + + switch( InterruptStatus ) + { + case INT_NOINT: + break; + case INT_THR_EMPTY: + break; + case INT_RCV_OVERTIME: /* Receiving timeout interruption, triggered when no further data is available four data times after receiving a frame*/ + case INT_RCV_SUCCESS: /* Interrupts are available to receive data */ + rcv_num = CH438UartRecv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size); + read_param->read_length = rcv_num; + KPrintf("recv data length %d\n", rcv_num); + for (int i = 0; i < rcv_num; i ++) { + KPrintf("idx %d data 0x%x\n", i, ((uint8 *)read_param->buffer)[i]); + } + break; + case INT_RCV_LINES: /* Receiving line status interrupted */ + ReadCH438Data(REG_LSR_ADDR); + break; + case INT_MODEM_CHANGE: /* MODEM input changes interrupt */ + ReadCH438Data(REG_MSR_ADDR); + break; + default: + break; + } + } + } + } while ((0 == (gInterruptStatus & interrupt_num[dev_param->ext_uart_no])) || (rcv_cnt < CH438_RECV_TIMEOUT)); + + return rcv_num; +} + +static const struct SerialDevDone dev_done = +{ + NONE, + NONE, + Ch438WriteData, + Ch438ReadData, +}; + +static void Ch438InitDefault(struct SerialDriver *serial_drv) +{ + CH438SetOutput(); + + gpiohs_set_drive_mode(FPIOA_CH438_NWR, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_NRD, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_ALE, GPIO_DM_OUTPUT); + // gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP); + + // gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP); + // gpiohs_set_pin_edge(FPIOA_CH438_INT, GPIO_PE_FALLING); + // gpiohs_irq_register(FPIOA_CH438_INT, 1, Ch438Irq, NONE); + + gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH); +} + +static uint32 Ch438DevRegister(struct SerialHardwareDevice *serial_dev, char *dev_name) +{ + x_err_t ret = EOK; + serial_dev->dev_done = &dev_done; + serial_dev->ext_serial_mode = RET_TRUE; + ret = SerialDeviceRegister(serial_dev, NONE, dev_name); + if (ret != EOK) { + KPrintf("HwCh438Init Serial device %s register error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("HwCh438Init Serial device %s register error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int HwCh438Init(void) +{ + static struct SerialBus serial_bus; + static struct SerialDriver serial_drv; + + x_err_t ret = EOK; + + ret = SerialBusInit(&serial_bus, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("HwCh438Init Serial bus init error %d\n", ret); + return ERROR; + } + + serial_drv.configure = &Ch438DrvConfigure; + ret = SerialDriverInit(&serial_drv, CH438_DRIVER_NAME); + if (ret != EOK) { + KPrintf("HwCh438Init Serial driver init error %d\n", ret); + return ERROR; + } + + ret = SerialDriverAttachToBus(CH438_DRIVER_NAME, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("HwCh438Init Serial driver attach error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_0; + static struct SerialDevParam dev_param_0; + dev_param_0.ext_uart_no = 0; + serial_dev_0.haldev.private_data = (void *)&dev_param_0; + ret = Ch438DevRegister(&serial_dev_0, CH438_DEVICE_NAME_0); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_1; + static struct SerialDevParam dev_param_1; + dev_param_1.ext_uart_no = 1; + serial_dev_1.haldev.private_data = (void *)&dev_param_1; + ret = Ch438DevRegister(&serial_dev_1, CH438_DEVICE_NAME_1); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_2; + static struct SerialDevParam dev_param_2; + dev_param_2.ext_uart_no = 2; + serial_dev_2.haldev.private_data = (void *)&dev_param_2; + ret = Ch438DevRegister(&serial_dev_2, CH438_DEVICE_NAME_2); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_3; + static struct SerialDevParam dev_param_3; + dev_param_3.ext_uart_no = 3; + serial_dev_3.haldev.private_data = (void *)&dev_param_3; + ret = Ch438DevRegister(&serial_dev_3, CH438_DEVICE_NAME_3); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_4; + static struct SerialDevParam dev_param_4; + dev_param_4.ext_uart_no = 4; + serial_dev_4.haldev.private_data = (void *)&dev_param_4; + ret = Ch438DevRegister(&serial_dev_4, CH438_DEVICE_NAME_4); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_5; + static struct SerialDevParam dev_param_5; + dev_param_5.ext_uart_no = 5; + serial_dev_5.haldev.private_data = (void *)&dev_param_5; + ret = Ch438DevRegister(&serial_dev_5, CH438_DEVICE_NAME_5); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_6; + static struct SerialDevParam dev_param_6; + dev_param_6.ext_uart_no = 6; + serial_dev_6.private_data = (void *)&dev_param_6; + ret = Ch438DevRegister(&serial_dev_6, CH438_DEVICE_NAME_6); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_7; + static struct SerialDevParam dev_param_7; + dev_param_7.ext_uart_no = 7; + serial_dev_7.private_data = (void *)&dev_param_7; + ret = Ch438DevRegister(&serial_dev_7, CH438_DEVICE_NAME_7); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + Ch438InitDefault(&serial_drv); + + return ret; +} + +void CH438RegTest()//for test +{ + uint8 rcv_num = 0; + uint8 buffer[32]; + memset(buffer, 0, 32); + + KPrintf("IER: %x\r\n",ReadCH438Data(REG_IER0_ADDR));//?IER + KPrintf("IIR: %x\r\n",ReadCH438Data(REG_IIR0_ADDR));//?IIR + KPrintf("LCR: %x\r\n",ReadCH438Data(REG_LCR0_ADDR));//?LCR + KPrintf("MCR: %x\r\n",ReadCH438Data(REG_MCR0_ADDR));//?MCR + KPrintf("LSR: %x\r\n",ReadCH438Data(REG_LSR0_ADDR));//?LSR + KPrintf("MSR: %x\r\n",ReadCH438Data(REG_MSR0_ADDR));//?MSR + KPrintf("FCR: %x\r\n",ReadCH438Data(REG_FCR0_ADDR));//?FCR + KPrintf("SSR: %x\r\n",ReadCH438Data(REG_SSR_ADDR ));//?SSR + + uint8 REG_IIR_ADDR = offset_addr[6] | REG_IIR0_ADDR; + uint8 InterruptStatus = ReadCH438Data(REG_IIR_ADDR) & 0x0f; + + switch( InterruptStatus ) + { + case INT_NOINT: + break; + case INT_THR_EMPTY: + break; + case INT_RCV_OVERTIME: /* Receiving timeout interruption, triggered when no further data is available four data times after receiving a frame*/ + case INT_RCV_SUCCESS: /* Interrupts are available to receive data */ + rcv_num = CH438UartRecv(6, buffer, 7); + KPrintf("recv data length %d\n", rcv_num); + for (int i = 0; i < rcv_num; i ++) { + KPrintf("idx %d data 0x%x\n", i, buffer[i]); + } + break; + default: + break; + } +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + CH438RegTest, CH438RegTest, CH438RegTest ); + diff --git a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/gpio/drv_io_config.c b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/gpio/drv_io_config.c index 6c5bf264d..38389e29b 100644 --- a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/gpio/drv_io_config.c +++ b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/gpio/drv_io_config.c @@ -11,7 +11,7 @@ /** * @file drv_io_config.c * @brief support xidatong-riscv64-board io configure -* @version 1.0 +* @version 2.0 * @author AIIT XUOS Lab * @date 2022-07-25 */ @@ -79,7 +79,22 @@ static struct io_config IOCONFIG(BSP_I2C_SCL, FUNC_GPIO4), #endif #ifdef BSP_USING_TOUCH - IOCONFIG(BSP_TOUCH_TP_INT, HS_GPIO(FPIOA_TOUCH_TP_INT)) + IOCONFIG(BSP_TOUCH_TP_INT, HS_GPIO(FPIOA_TOUCH_TP_INT)), +#endif + +#ifdef BSP_USING_CH438 + IOCONFIG(BSP_CH438_ALE_PIN, HS_GPIO(FPIOA_CH438_ALE)), + IOCONFIG(BSP_CH438_NWR_PIN, HS_GPIO(FPIOA_CH438_NWR)), + IOCONFIG(BSP_CH438_NRD_PIN, HS_GPIO(FPIOA_CH438_NRD)), + IOCONFIG(BSP_CH438_INT_PIN, HS_GPIO(FPIOA_CH438_INT)), + IOCONFIG(BSP_CH438_D0_PIN, HS_GPIO(FPIOA_CH438_D0)), + IOCONFIG(BSP_CH438_D1_PIN, HS_GPIO(FPIOA_CH438_D1)), + IOCONFIG(BSP_CH438_D2_PIN, HS_GPIO(FPIOA_CH438_D2)), + IOCONFIG(BSP_CH438_D3_PIN, HS_GPIO(FPIOA_CH438_D3)), + IOCONFIG(BSP_CH438_D4_PIN, HS_GPIO(FPIOA_CH438_D4)), + IOCONFIG(BSP_CH438_D5_PIN, HS_GPIO(FPIOA_CH438_D5)), + IOCONFIG(BSP_CH438_D6_PIN, HS_GPIO(FPIOA_CH438_D6)), + IOCONFIG(BSP_CH438_D7_PIN, HS_GPIO(FPIOA_CH438_D7)) #endif }; @@ -97,13 +112,9 @@ static int PrintIoConfig() KPrintf("└───────┴────────────────────────┘\n"); return 0; } - - - SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), io,PrintIoConfig,print io config); - int IoConfigInit(void) { int count = sizeof(io_config) / sizeof(io_config[0]); diff --git a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_ch438.h b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_ch438.h new file mode 100755 index 000000000..d39d32104 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_ch438.h @@ -0,0 +1,257 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ch438.h +* @brief define xidatong-riscv64-board ch438 function and struct +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-08-26 +*/ + +#ifndef CONNECT_CH438_H +#define CONNECT_CH438_H + +#include + +#define BUFFSIZE 255 + +/******************************************************************************************/ + +/* CH438serial port0 register address */ + +#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */ +#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */ +#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */ +#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */ +#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */ +#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */ +#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */ +#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */ +#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */ +#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */ +#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */ + +/* CH438serial port1 register address */ + +#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */ +#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */ +#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */ +#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */ +#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */ +#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */ +#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */ +#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */ +#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */ +#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */ +#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port2 register address */ + +#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */ +#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */ +#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */ +#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */ +#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */ +#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */ +#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */ +#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */ +#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */ +#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */ +#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port3 register address */ + +#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */ +#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */ +#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */ +#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */ +#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */ +#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */ +#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */ +#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */ +#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */ +#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */ +#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port4 register address */ + +#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */ +#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */ +#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */ +#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */ +#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */ +#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */ +#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */ +#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */ +#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */ +#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */ +#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port5 register address */ + +#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */ +#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */ +#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */ +#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */ +#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */ +#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */ +#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */ +#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */ +#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */ +#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */ +#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port6 register address */ + +#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */ +#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */ +#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */ +#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */ +#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */ +#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */ +#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */ +#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */ +#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */ +#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */ +#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port7 register address */ + +#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */ +#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */ +#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */ +#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */ +#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */ +#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */ +#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */ +#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */ +#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */ +#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */ +#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */ + + +#define REG_SSR_ADDR 0x4F /* pecial status register address */ + + +/* IER register bit */ + +#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */ +#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */ +#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */ +#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */ +#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */ +#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */ +#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */ +#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */ + +/* IIR register bit */ + +#define BIT_IIR_FIFOENS1 0x80 +#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */ + +/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted, +1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */ +#define BIT_IIR_IID3 0x08 +#define BIT_IIR_IID2 0x04 +#define BIT_IIR_IID1 0x02 +#define BIT_IIR_NOINT 0x01 + +/* FCR register bit */ + +/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */ +#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ +#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ + +#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */ + +/* LCR register bit */ + +#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */ +#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/ + +/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */ +#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */ +#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */ + +#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */ +#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */ + +/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */ +#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */ +#define BIT_LCR_WORDSZ0 0x01 + +/* MCR register bit */ + +#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */ +#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */ +#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */ +#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */ +#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */ +#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */ + +/* LSR register bit */ + +#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */ +#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */ +#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/ +#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/ +#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */ +#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */ +#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */ +#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */ + +/* MSR register bit */ + +#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */ +#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */ +#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */ +#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */ +#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */ +#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */ +#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */ +#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */ + +/* Interrupt status code */ + +#define INT_NOINT 0x01 /* There is no interruption */ +#define INT_THR_EMPTY 0x02 /* THR empty interruption */ +#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */ +#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */ +#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */ +#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */ + +#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */ + +#define Fpclk 1843200 /* Define the internal clock frequency */ + +#define CH438_RECV_TIMEOUT 1000000 * 1000 + +#endif diff --git a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_gpio.h b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_gpio.h index 67069e5a0..d3f7caa0a 100644 --- a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_gpio.h +++ b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_gpio.h @@ -12,8 +12,8 @@ /** * @file connect_gpio.h -* @brief define kd233-board gpio function and struct -* @version 1.0 +* @brief define xidatong-riscv64-board gpio function and struct +* @version 2.0 * @author AIIT XUOS Lab * @date 2022-07-25 */ diff --git a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_i2c.h b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_i2c.h index bf53c1343..d059e12ec 100644 --- a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_i2c.h +++ b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_i2c.h @@ -12,8 +12,8 @@ /** * @file connect_i2c.h -* @brief define kd233-board i2c function and struct -* @version 1.0 +* @brief define xidatong-riscv64-board i2c function and struct +* @version 2.0 * @author AIIT XUOS Lab * @date 2022-07-25 */ diff --git a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_touch.h b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_touch.h index 49bea5813..d2d206495 100644 --- a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_touch.h +++ b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_touch.h @@ -1,8 +1,19 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ /** * @file connect_touch.h * @brief support xidatong-riscv64 touch function and register to bus framework -* @version 1.0 +* @version 2.0 * @author AIIT XiUOS Lab * @date 2022-04-25 */ diff --git a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_uart.h b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_uart.h index fa4206e78..7adfbe3dd 100644 --- a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_uart.h +++ b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_uart.h @@ -12,8 +12,8 @@ /** * @file connect_uart.h -* @brief define kd233-board uart function and struct -* @version 1.0 +* @brief define xidatong-riscv64-board uart function and struct +* @version 2.0 * @author AIIT XUOS Lab * @date 2022-07-25 */ diff --git a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/drv_io_config.h b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/drv_io_config.h index 069f7f09d..4e247e955 100644 --- a/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/drv_io_config.h +++ b/Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/drv_io_config.h @@ -10,8 +10,8 @@ /** * @file drv_io_config.h -* @brief define kd233-board io configure -* @version 1.0 +* @brief define xidatong-riscv64-board io configure +* @version 2.0 * @author AIIT XUOS Lab * @date 2022-07-25 */ @@ -50,6 +50,34 @@ enum HS_GPIO_CONFIG GPIO_ALLOC_START /* index of gpio driver start */ }; +#ifdef BSP_USING_CH438 +#define FPIOA_CH438_ALE 12 +#define FPIOA_CH438_NWR 13 +#define FPIOA_CH438_NRD 14 +#define FPIOA_CH438_D0 15 +#define FPIOA_CH438_D1 16 +#define FPIOA_CH438_D2 17 +#define FPIOA_CH438_D3 18 +#define FPIOA_CH438_D4 19 +#define FPIOA_CH438_D5 20 +#define FPIOA_CH438_D6 21 +#define FPIOA_CH438_D7 22 +#define FPIOA_CH438_INT 23 + +#define BSP_CH438_ALE_PIN 24 +#define BSP_CH438_NWR_PIN 25 +#define BSP_CH438_NRD_PIN 26 +#define BSP_CH438_D0_PIN 27 +#define BSP_CH438_D1_PIN 28 +#define BSP_CH438_D2_PIN 29 +#define BSP_CH438_D3_PIN 30 +#define BSP_CH438_D4_PIN 31 +#define BSP_CH438_D5_PIN 32 +#define BSP_CH438_D6_PIN 33 +#define BSP_CH438_D7_PIN 34 +#define BSP_CH438_INT_PIN 35 +#endif + extern int IoConfigInit(void); #endif diff --git a/Ubiquitous/XiZi/resources/serial/dev_serial.c b/Ubiquitous/XiZi/resources/serial/dev_serial.c index 5cce9bee1..43c94addd 100644 --- a/Ubiquitous/XiZi/resources/serial/dev_serial.c +++ b/Ubiquitous/XiZi/resources/serial/dev_serial.c @@ -829,9 +829,8 @@ int SerialDeviceRegister(struct SerialHardwareDevice *serial_device, void *seria serial_device->haldev.dev_done = (struct HalDevDone *)serial_device->dev_done; } else { serial_device->haldev.dev_done = (struct HalDevDone *)&dev_done; + serial_device->private_data = serial_param; } - - serial_device->private_data = serial_param; DoubleLinkListInsertNodeAfter(&serialdev_linklist, &(serial_device->haldev.dev_link)); } else {