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Merge branch 'prepare_for_master' of https://git.trustie.net/xuos/xiuos into develop

This commit is contained in:
Wang_Weigen 2022-04-21 16:46:15 +08:00
parent 85ff8877d4 7b3f1dc95f
commit 587c2d595e
157 changed files with 25274 additions and 1029 deletions
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3
.gitmodules vendored
View File

@ -13,3 +13,6 @@
[submodule "Ubiquitous/Nuttx_Fusion_XiUOS/nuttx"]
path = Ubiquitous/Nuttx_Fusion_XiUOS/nuttx
url = https://code.gitlink.org.cn/wgzAIIT/incubator-nuttx.git
[submodule "Ubiquitous/XiZi/fs/lwext4/lwext4_submodule"]
path = Ubiquitous/XiZi/fs/lwext4/lwext4_submodule
url = https://gitlink.org.cn/xuos/lwext4_filesystem_support_XiUOS.git

98
APP_Framework/Applications/control_app/opcua_demo/opcua_demo.c
View File

@ -21,7 +21,6 @@
#include <list.h>
#include <transform.h>
#include "board.h"
#include <lwip/altcp.h>
#include "open62541.h"
#include "ua_api.h"
@ -40,6 +39,9 @@
/*******************************************************************************
* Variables
******************************************************************************/
// to count test
static int test_cnt = 0;
static int fail_cnt = 0; // count failure times
char test_ua_ip[] = {192, 168, 250, 2};
@ -50,37 +52,56 @@ char test_ua_ip[] = {192, 168, 250, 2};
static void UaConnectTestTask(void* arg)
{
struct netif net;
UA_StatusCode retval;
char ua_uri[UA_URL_SIZE];
memset(ua_uri, 0, sizeof(ua_uri));
UA_StatusCode ret;
char url[UA_URL_SIZE];
memset(url, 0, sizeof(url));
UA_Client* client = UA_Client_new();
if(client == NULL)
{
ua_print("ua: [%s] tcp client null\n", __func__);
ua_error("ua: [%s] tcp client null\n", __func__);
return;
}
UA_ClientConfig* config = UA_Client_getConfig(client);
UA_ClientConfig_setDefault(config);
snprintf(ua_uri, sizeof(ua_uri), "opc.tcp://%d.%d.%d.%d:4840",
test_ua_ip[0], test_ua_ip[1], test_ua_ip[2], test_ua_ip[3]);
ua_notice("ua uri: %d %s\n", strlen(ua_uri), ua_uri);
retval = UA_Client_connect(client,ua_uri);
if(retval != UA_STATUSCODE_GOOD)
UA_ClientConfig_setDefault(config);
snprintf(url, sizeof(url), "opc.tcp://%d.%d.%d.%d:4840",
test_ua_ip[0], test_ua_ip[1], test_ua_ip[2], test_ua_ip[3]);
ua_notice("ua connect cnt %d fail %d\n", test_cnt++, fail_cnt ++);
ua_notice("ua connect uri: %.*s\n", strlen(url), url);
ret = UA_Client_connect(client, url);
if(ret != UA_STATUSCODE_GOOD)
{
ua_notice("ua: [%s] connected failed %x\n", __func__, retval);
ua_error("ua: [%s] connected failed %x\n", __func__, ret);
UA_Client_delete(client);
fail_cnt++;
return;
}
ua_notice("ua: [%s] connected ok!\n", __func__);
ua_notice("ua connected ok!\n");
UA_Client_delete(client);
}
void UaConnectTest(void* arg)
static void UaConnectTest(int argc, char *argv[])
{
if(argc == 2)
{
if(isdigit(argv[1][0]))
{
if(sscanf(argv[1], "%d.%d.%d.%d", &test_ua_ip[0], &test_ua_ip[1], &test_ua_ip[2], &test_ua_ip[3]) == EOF)
{
lw_notice("input wrong ip\n");
return;
}
}
}
lwip_config_tcp(lwip_ipaddr, lwip_netmask, test_ua_ip);
sys_thread_new("ua test", UaConnectTestTask, NULL, UA_STACK_SIZE, UA_TASK_PRIO);
}
@ -90,10 +111,10 @@ SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) |
void UaBrowserObjectsTestTask(void* param)
{
static int test_cnt = 0;
UA_Client* client = UA_Client_new();
ua_notice("ua: [%s] start %d ...\n", __func__, test_cnt++);
UA_Client* client = UA_Client_new();
if(client == NULL)
{
ua_error("ua: [%s] tcp client NULL\n", __func__);
@ -102,25 +123,26 @@ void UaBrowserObjectsTestTask(void* param)
UA_ClientConfig* config = UA_Client_getConfig(client);
UA_ClientConfig_setDefault(config);
UA_StatusCode retval = UA_Client_connect(client, opc_server_url);
UA_StatusCode ret = UA_Client_connect(client, opc_server_url);
if(retval != UA_STATUSCODE_GOOD)
if(ret != UA_STATUSCODE_GOOD)
{
ua_error("ua: [%s] connect failed %#x\n", __func__, retval);
ua_error("ua: [%s] connect failed %#x\n", __func__, ret);
UA_Client_delete(client);
return;
}
ua_notice("--- start read time ---\n", __func__);
ua_read_time(client);
UaGetServerTime(client);
ua_notice("--- get server info ---\n", __func__);
ua_test_browser_objects(client);
UaTestBrowserObjects(client);
/* Clean up */
UA_Client_delete(client); /* Disconnects the client internally */
}
void* UaBrowserObjectsTest(int argc, char* argv[])
static void* UaBrowserObjectsTest(int argc, char* argv[])
{
if(argc == 2)
{
@ -140,35 +162,33 @@ void* UaBrowserObjectsTest(int argc, char* argv[])
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
UaObj, UaBrowserObjectsTest, UaObj [IP]);
UaObject, UaBrowserObjectsTest, UaObject [IP]);
void UaGetInfoTestTask(void* param)
{
UA_Client* client = UA_Client_new();
ua_notice("ua: [%s] start ...\n", __func__);
ua_notice("--- Get OPUCA objects ---\n", __func__);
if(client == NULL)
{
ua_print("ua: [%s] tcp client null\n", __func__);
ua_error("ua: [%s] tcp client null\n", __func__);
return;
}
UA_ClientConfig* config = UA_Client_getConfig(client);
UA_ClientConfig_setDefault(config);
UA_StatusCode retval = UA_Client_connect(client, opc_server_url);
UA_StatusCode ret = UA_Client_connect(client, opc_server_url);
if(retval != UA_STATUSCODE_GOOD)
if(ret != UA_STATUSCODE_GOOD)
{
ua_print("ua: [%s] connect failed %#x\n", __func__, retval);
ua_error("ua: [%s] connect failed %#x\n", __func__, ret);
UA_Client_delete(client);
return;
}
ua_print("ua: [%s] connect ok!\n", __func__);
ua_notice("--- interactive server ---\n", __func__);
ua_test_interact_server(client);
/* Clean up */
UA_Client_disconnect(client);
UaTestInteractServer(client);
UA_Client_delete(client); /* Disconnects the client internally */
}
@ -201,26 +221,24 @@ void UaAddNodesTask(void* param)
if(client == NULL)
{
ua_print("ua: [%s] tcp client null\n", __func__);
ua_error("ua: [%s] client null\n", __func__);
return;
}
UA_ClientConfig* config = UA_Client_getConfig(client);
UA_ClientConfig_setDefault(config);
UA_StatusCode retval = UA_Client_connect(client, opc_server_url);
UA_StatusCode ret = UA_Client_connect(client, opc_server_url);
if(retval != UA_STATUSCODE_GOOD)
if(ret != UA_STATUSCODE_GOOD)
{
ua_print("ua: [%s] connect failed %#x\n", __func__, retval);
ua_print("ua: [%s] connect failed %#x\n", __func__, ret);
UA_Client_delete(client);
return;
}
ua_print("ua: [%s] connect ok!\n", __func__);
ua_notice("--- add nodes ---\n", __func__);
ua_add_nodes(client);
/* Clean up */
UA_Client_disconnect(client);
UaAddNodes(client);
UA_Client_delete(client); /* Disconnects the client internally */
}

265
APP_Framework/Applications/control_app/plc_demo/plc_control_demo.c
View File

@ -30,12 +30,49 @@ struct PlcChannel plc_demo_ch;
struct PlcDriver plc_demo_drv;
struct PlcDevice plc_demo_dev;
int plc_test_flag = 0;
PlcCtrlParamType plc_ctrl_param;
UA_NodeId test_nodeid = {4, UA_NODEIDTYPE_NUMERIC, 5};
/******************************************************************************/
void PlcDelay(int sec)
{
volatile uint32_t i = 0;
for (i = 0; i < 100000000 * sec; ++i)
{
__asm("NOP"); /* delay */
}
}
// get NodeId from str
void PlcGetTestNodeId(char *str, UA_NodeId *id)
{
static char node_str[UA_NODE_LEN];
memset(node_str, 0, sizeof(node_str));
plc_print("plc: arg %s\n", str);
if(sscanf(str, PLC_NS_FORMAT, &id->namespaceIndex, node_str) != EOF)
{
if(isdigit(node_str[0]))
{
id->identifierType = UA_NODEIDTYPE_NUMERIC;
id->identifier.numeric = atoi(node_str);
plc_print("ns %d num %d\n", id->namespaceIndex, id->identifier.numeric);
}
else
{
id->identifierType = UA_NODEIDTYPE_STRING;
id->identifier.string.length = strlen(node_str);
id->identifier.string.data = node_str;
plc_print("ns %d str %s\n", id->namespaceIndex, id->identifier.string.data);
}
}
}
void PlcDemoChannelDrvInit(void)
{
static uint8_t init_flag = 0;
@ -52,33 +89,42 @@ void PlcDemoChannelDrvInit(void)
memset(&plc_demo_dev, 0, sizeof(plc_demo_dev));
}
static void PlcGetDemoDev(PlcDeviceType *dev, UA_NodeId *id)
{
// register plc device
dev->state = CHDEV_INIT;
strcpy(dev->name, "UA Demo");
dev->info.product = "CPU 1215C";
dev->info.vendor = "SIEMENS";
dev->info.model = "S7-1200";
dev->info.id = 123;
dev->net = PLC_IND_ENET_OPCUA;
// register UA parameter
if(!dev->priv_data)
{
dev->priv_data = (UaParamType*)malloc(sizeof(UaParamType));
}
UaParamType* ua_ptr = dev->priv_data;
memset(ua_ptr, 0, sizeof(UaParamType));
strcpy(ua_ptr->ua_remote_ip, opc_server_url);
ua_ptr->act = UA_ACT_ATTR;
memcpy(&ua_ptr->ua_id, id, sizeof(*id));
}
static void PlcCtrlDemoInit(void)
{
static uint8_t init_flag = 0;
PlcDemoChannelDrvInit();
// register plc device
plc_demo_dev.state = CHDEV_INIT;
strcpy(plc_demo_dev.name, "UA Demo");
plc_demo_dev.info.product = "CPU 1215C";
plc_demo_dev.info.vendor = "SIEMENS";
plc_demo_dev.info.model = "S7-1200";
plc_demo_dev.info.id = 123;
plc_demo_dev.net = PLC_IND_ENET_OPCUA;
// register UA parameter
if(!plc_demo_dev.priv_data)
{
plc_demo_dev.priv_data = (UaParamType*)malloc(sizeof(UaParamType));
}
UaParamType* ua_ptr = plc_demo_dev.priv_data;
memset(ua_ptr, 0, sizeof(UaParamType));
strcpy(ua_ptr->ua_remote_ip, opc_server_url);
ua_ptr->act = UA_ACT_ATTR;
memcpy(&ua_ptr->ua_id, &test_nodeid, sizeof(test_nodeid));
// register plc device
PlcGetDemoDev(&plc_demo_dev, &test_nodeid);
if(init_flag)
{
return;
}
init_flag = 1;
if(PlcDevRegister(&plc_demo_dev, NULL, plc_demo_dev.name) != EOK)
@ -114,38 +160,21 @@ void PlcReadUATask(void* arg)
ops->close(&plc_demo_dev);
}
void PlcReadTest(int argc, char* argv[])
void PlcReadTestShell(int argc, char* argv[])
{
static char node_str[UA_NODE_LEN];
memset(node_str, 0, sizeof(node_str));
if(argc > 1)
{
plc_print("plc: arg %s\n", argv[1]);
if(sscanf(argv[1], PLC_NS_FORMAT, &test_nodeid.namespaceIndex, node_str) != EOF)
{
if(isdigit(node_str[0]))
{
test_nodeid.identifierType = UA_NODEIDTYPE_NUMERIC;
test_nodeid.identifier.numeric = atoi(node_str);
plc_print("ns %d num %d\n", test_nodeid.namespaceIndex, test_nodeid.identifier.numeric);
}
else
{
test_nodeid.identifierType = UA_NODEIDTYPE_STRING;
test_nodeid.identifier.string.length = strlen(node_str);
test_nodeid.identifier.string.data = node_str;
plc_print("ns %d str %s\n", test_nodeid.namespaceIndex, test_nodeid.identifier.string.data);
}
}
PlcGetTestNodeId(argv[1], &test_nodeid);
}
sys_thread_new("plc read", PlcReadUATask, NULL, PLC_STACK_SIZE, PLC_TASK_PRIO);
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
PlcRead, PlcReadTest, Read PLC);
PlcRead, PlcReadTestShell, Read PLC);
void PlcWriteUATask(void* arg)
{
@ -168,13 +197,13 @@ void PlcWriteUATask(void* arg)
if(EOK != ret)
{
plc_print("plc: [%s] read failed\n", __func__);
plc_print("plc: [%s] write failed\n", __func__);
}
ops->close(&plc_demo_dev);
}
void PlcWriteTest(int argc, char* argv[])
void PlcWriteTestShell(int argc, char* argv[])
{
static char node_str[UA_NODE_LEN];
static char val_param[UA_NODE_LEN];
@ -183,35 +212,143 @@ void PlcWriteTest(int argc, char* argv[])
if(argc > 1)
{
plc_print("plc: arg %s\n", argv[1]);
PlcGetTestNodeId(argv[1], &test_nodeid);
}
if(sscanf(argv[1], PLC_NS_FORMAT, &test_nodeid.namespaceIndex, node_str) != EOF)
{
if(isdigit(node_str[0]))
{
test_nodeid.identifierType = UA_NODEIDTYPE_NUMERIC;
test_nodeid.identifier.numeric = atoi(node_str);
plc_print("ns %d num %d\n", test_nodeid.namespaceIndex, test_nodeid.identifier.numeric);
}
else
{
test_nodeid.identifierType = UA_NODEIDTYPE_STRING;
test_nodeid.identifier.string.length = strlen(node_str);
test_nodeid.identifier.string.data = node_str;
plc_print("ns %d str %s\n", test_nodeid.namespaceIndex, test_nodeid.identifier.string.data);
}
}
if(argc > 2)
{
strcpy(val_param, argv[2]);
plc_print("write value %s\n", val_param);
}
if(argc > 2)
{
strcpy(val_param, argv[2]);
plc_print("write value %s\n", val_param);
}
sys_thread_new("plc write", PlcWriteUATask, val_param, PLC_STACK_SIZE, PLC_TASK_PRIO);
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
PlcWrite, PlcWriteTest, Read PLC);
PlcWrite, PlcWriteTestShell, Read PLC);
// test motor
// clear parameter
// PlcWrite n4,2 0b
// PlcWrite n4,3 0b
// PlcWrite n4,4 0b
// PlcWrite n4,5 0b
//
// enable
// PlcWrite n4,2 1b
//
// set rotate speed
// PlcWrite n4,3 50
//
// positive turn
// PlcWrite n4,4 1b
//
// reversal turn
// PlcWrite n4,5 1b
static int plc_test_speed = 50;
static int plc_test_dir = 1; // direction positive: 1 reversal: 0
void PlcMotorTestTask(void* arg)
{
//support node id
char *test_nodeid[] = {"n4,2", "n4,3", "n4,4", "n4,5", "n4,7"};
// enable -> speed -> positive dir or inversal dir -> stop -> enable
char test_sort[] = {0, 4, 2, 1, 0};
char test_cmd[][4] = {"1b", "50", "1b", "1b", "0b"};
char *test_notice[] = {"Enable Motor", "Set Speed", "Set Forward", "Set Reverse", "Stop Motor"};
int ret = 0;
struct PlcOps* ops = NULL;
char buf[PLC_BUF_SIZE];
memset(buf, 0, sizeof(buf));
PlcCtrlDemoInit();
ops = plc_demo_dev.ops;
ret = ops->open(&plc_demo_dev);
if(EOK != ret)
{
plc_print("plc: [%s] open failed %#x\n", __func__, ret);
return;
}
UaParamType* ua_ptr = plc_demo_dev.priv_data;
// initialize step
for(int i = 0; i < 5; i++)
{
plc_print("###\n### Clear %s\n###\n", test_notice[i]);
PlcGetTestNodeId(test_nodeid[i], &ua_ptr->ua_id);
ret = ops->write(&plc_demo_dev, "0b", PLC_BUF_SIZE);
if(EOK != ret)
{
plc_print("plc: [%s] %d write failed\n", __func__, __LINE__);
}
PlcDelay(1);
}
if(plc_test_speed != 50)
{
snprintf(test_cmd[1], 4, "%d", plc_test_speed);
}
if(plc_test_dir == 0) // if not postive, next running
test_sort[2] = 3;
for(int i = 0; i < sizeof(test_sort)/sizeof(test_sort[0]); i++)
{
PlcGetTestNodeId(test_nodeid[test_sort[i]], &ua_ptr->ua_id);
plc_print("###\n### %s\n###\n", test_notice[i]);
ret = ops->write(&plc_demo_dev, test_cmd[i], PLC_BUF_SIZE);
if(EOK != ret)
{
plc_print("plc: [%s] %d write failed\n", __func__, __LINE__);
}
PlcDelay(1);
if(i == 2) // postive
{
PlcDelay(10);
}
}
ops->close(&plc_demo_dev);
plc_test_flag = 0;
}
// get parameter from
void PlcGetMotorParam(char *str)
{
static char node_str[UA_NODE_LEN];
memset(node_str, 0, sizeof(node_str));
plc_print("plc: arg %s\n", str);
sscanf(str, "speed=%d", &plc_test_speed);
sscanf(str, "dir=%d", &plc_test_dir);
plc_print("speed is %d\n", plc_test_speed);
plc_print("dir is %d\n", plc_test_dir);
}
void PlcMotorTestShell(int argc, char* argv[])
{
if(plc_test_flag)
{
plc_print("PLC Motor testing!\n");
return;
}
plc_test_flag = 1;
if(argc > 1)
{
for(int i = 0; i < argc; i++)
{
PlcGetMotorParam(argv[i]);
}
}
sys_thread_new("plc motor", PlcMotorTestTask, NULL, PLC_STACK_SIZE, PLC_TASK_PRIO);
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
PlcMotorTest, PlcMotorTestShell, Run motor);

2
APP_Framework/Applications/sensor_app/pm10_0_ps5308.c
View File

@ -11,7 +11,7 @@
*/
/**
* @filepm10_0_ps5308
* @file pm10_0_ps5308.c
* @brief PS5308 PM10.0 example
* @version 1.0
* @author AIIT XUOS Lab

2
APP_Framework/Applications/sensor_app/pm2_5_ps5308.c
View File

@ -11,7 +11,7 @@
*/
/**
* @file pm2_5_ps5308
* @file pm2_5_ps5308.c
* @brief PS5308 PM2.5 example
* @version 1.0
* @author AIIT XUOS Lab

6
APP_Framework/Framework/connection/Kconfig
View File

@ -62,12 +62,6 @@ if SUPPORT_CONNECTION_FRAMEWORK
default n
if CONNECTION_ADAPTER_ETHERNET
source "$APP_DIR/Framework/connection/ethernet/Kconfig"
config CONNECTION_ADAPTER_ETHERCAT
bool "Using ethercat on ethernet adapter device"
default n
if CONNECTION_ADAPTER_ETHERCAT
source "$APP_DIR/Framework/connection/ethercat/Kconfig"
endif
endif
menuconfig CONNECTION_ADAPTER_BLUETOOTH

4
APP_Framework/Framework/connection/Makefile
View File

@ -41,10 +41,6 @@ ifeq ($(CONFIG_ADD_XIZI_FETURES),y)
SRC_DIR += ethernet
endif
ifeq ($(CONFIG_CONNECTION_ADAPTER_ETHERCAT),y)
SRC_DIR += ethercat
endif
ifeq ($(CONFIG_CONNECTION_ADAPTER_BLUETOOTH),y)
SRC_DIR += bluetooth
endif

7
APP_Framework/Framework/connection/industrial_ethernet/Kconfig
View File

@ -0,0 +1,7 @@
config CONNECTION_ADAPTER_ETHERCAT
bool "Using ethercat on industrial_ethernet adapter device"
default n
if CONNECTION_ADAPTER_ETHERCAT
source "$APP_DIR/Framework/connection/industrial_ethernet/ethercat/Kconfig"
endif

3
APP_Framework/Framework/connection/industrial_ethernet/Makefile
View File

@ -1,2 +1,5 @@
ifeq ($(CONFIG_CONNECTION_ADAPTER_ETHERCAT),y)
SRC_DIR += ethercat
endif
include $(KERNEL_ROOT)/compiler.mk

7
APP_Framework/Framework/connection/ethercat/Kconfig → APP_Framework/Framework/connection/industrial_ethernet/ethercat/Kconfig
View File

@ -5,6 +5,7 @@ config ADAPTER_HFA21_ETHERCAT
bool "Using ethercat on ethernet adapter device HFA21"
default n
if ADAPTER_HFA21_ETHERCAT
source "$APP_DIR/Framework/connection/ethercat/hfa21_ethercat/Kconfig"
endif
if ADAPTER_HFA21_ETHERCAT
source "$APP_DIR/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/Kconfig"
endif

0
APP_Framework/Framework/connection/ethercat/Makefile → APP_Framework/Framework/connection/industrial_ethernet/ethercat/Makefile
View File

0
APP_Framework/Framework/connection/ethercat/adapter_ethercat.c → APP_Framework/Framework/connection/industrial_ethernet/ethercat/adapter_ethercat.c
View File

0
APP_Framework/Framework/connection/ethercat/ethercat.h → APP_Framework/Framework/connection/industrial_ethernet/ethercat/ethercat.h
View File

0
APP_Framework/Framework/connection/ethercat/hfa21_ethercat/Kconfig → APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/Kconfig
View File

0
APP_Framework/Framework/connection/ethercat/hfa21_ethercat/Makefile → APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/Makefile
View File

0
APP_Framework/Framework/connection/ethercat/hfa21_ethercat/hfa21_ethercat.c → APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/hfa21_ethercat.c
View File

217
APP_Framework/Framework/control/plc/interoperability/opcua/open62541.c
View File

@ -23,6 +23,19 @@
* @date 2021.12.15
*/
/*************************************************
File name: open62541.c
Description: Support OPCUA protocol
Others: take https://github.com/open62541/open62541.git
History:
1. Date: 2021-12-15
Author: AIIT XUOS Lab
Modification:
1. added debug information for locate
2. avoid calling client NEW at same time
3. fixed the bug of free twice when receiveResponse timeout
*************************************************/
#ifndef UA_DYNAMIC_LINKING_EXPORT
# define UA_DYNAMIC_LINKING_EXPORT
# define MDNSD_DYNAMIC_LINKING
@ -36,6 +49,8 @@
#include "open62541.h"
#include "ua_api.h"
int ua_run_flag = 0;
#if LWIP_DNS
#else
@ -7482,10 +7497,6 @@ Array_encodeBinary(const void *src, size_t length, const UA_DataType *type, Ctx
}
UA_assert(ret != UA_STATUSCODE_BADENCODINGLIMITSEXCEEDED);
//tst by wly
ua_debug("ua: [%s] src %p len %d %d type %p <%d> <%d> %p ret %d\n", __func__,
src, length, signed_length, *type, type->typeKind, type->overlayable, ctx, ret);
return ret;
}
@ -8330,24 +8341,9 @@ encodeBinaryStruct(const void *src, const UA_DataType *type, Ctx *ctx) {
if(mt->typeKind > UA_DATATYPEKINDS)
{
ua_debug("ua: [%s] %d type %d %p ptr %p failed\n", __func__, i, mt->typeKind, m->memberType, ptr);
return ret;
}
ua_debug("ua: [%s] > %d < %d mt %p %d %d dep %d msg %p %p:<%x> <%d> isArry %d ret %d\n", __func__,
i,
type->membersSize,
mt,
mt->typeKind,
mt->memSize,
ctx->depth,
ptr,
src,
((UA_TcpMessageHeader *)src)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)src)->messageSize,
m->isArray,
ret);
/* Array. Buffer-exchange is done inside Array_encodeBinary if required. */
if(m->isArray) {
const size_t length = *((const size_t*)ptr);
@ -8362,20 +8358,6 @@ encodeBinaryStruct(const void *src, const UA_DataType *type, Ctx *ctx) {
ret = encodeWithExchangeBuffer((const void*)ptr, mt, ctx);
UA_assert(ret != UA_STATUSCODE_BADENCODINGLIMITSEXCEEDED);
ua_debug("ua: [%s] >> %d < %d mt %p %d %d dep %d msg %p %p:<%x> <%d> isArry %d ret %d\n", __func__,
i,
type->membersSize,
mt,
mt->typeKind,
mt->memSize,
ctx->depth,
ptr,
src,
((UA_TcpMessageHeader *)src)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)src)->messageSize,
m->isArray,
ret);
ptr += mt->memSize;
}
@ -8614,68 +8596,23 @@ decodeBinaryStructure(void *dst, const UA_DataType *type, Ctx *ctx) {
if(mt->typeKind >= UA_DATATYPEKINDS)
{
ua_debug("ua: [%s] fail %d < %d mt %p %d %d dep %d msg %p %p:<%x> <%d>\n", __func__,
i,
membersSize,
mt,
mt->typeKind,
mt->memSize,
ctx->depth,
ptr,
dst,
((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize);
return ret;
}
ua_debug("ua: [%s] > %d < %d mt %p %d %d dep %d msg %p %p:<%x> <%d> isArry %d ret %d\n", __func__,
i,
membersSize,
mt,
mt->typeKind,
mt->memSize,
ctx->depth,
ptr,
dst,
((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize,
m->isArray,
ret);
/* Array */
if(m->isArray) {
size_t *length = (size_t*)ptr;
ptr += sizeof(size_t);
ret = Array_decodeBinary((void *UA_RESTRICT *UA_RESTRICT)ptr, length, mt , ctx);
ptr += sizeof(void*);
ua_debug("ua: [%s] %d ret %d ptr %p len %d\n", __func__, i, ret, ptr, length);
continue;
}
/* Scalar */
ret = decodeBinaryJumpTable[mt->typeKind]((void *UA_RESTRICT)ptr, mt, ctx);
ptr += mt->memSize;
ua_debug("ua: [%s] >> %d < %d dep %d msg %p %p:<%x> <%d> ret %d\n", __func__,
i,
membersSize,
ctx->depth,
ptr,
dst,
((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize,
ret);
}
ua_debug("ua: [%s] >>> dep %d msg %p %p:<%x> <%d> ret %d\n", __func__,
ctx->depth,
ptr,
dst,
((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize,
ret);
ctx->depth--;
return ret;
}
@ -8818,17 +8755,8 @@ UA_decodeBinaryInternal(const UA_ByteString *src, size_t *offset,
/* Decode */
memset(dst, 0, type->memSize); /* Initialize the value */
ua_debug("ua: [%s] t %d mem %d len %d off %d pos %d end %d dst %p type %x size %x\n", __func__,
type->typeKind, type->memSize, src->length, *offset, *ctx.pos, *ctx.end,
dst, ((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize);
status ret = decodeBinaryJumpTable[type->typeKind](dst, type, &ctx);
ua_debug("ua: [%s] -> t %d dst %p type %x size %x ret %d\n", __func__,
type->typeKind, dst, ((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize, ret);
if(UA_LIKELY(ret == UA_STATUSCODE_GOOD)) {
/* Set the new offset */
*offset = (size_t)(ctx.pos - src->data) / sizeof(u8);
@ -8836,16 +8764,8 @@ UA_decodeBinaryInternal(const UA_ByteString *src, size_t *offset,
/* Clean up */
UA_clear(dst, type);
memset(dst, 0, type->memSize);
ua_debug("ua: [%s] => t %d dst %p type %x size %x\n", __func__,
type->typeKind, dst, ((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize);
}
ua_debug("ua: [%s] #> off %d %p %p t %d dst %p type %x size %x\n", __func__, *offset,
ctx.pos, src->data,
type->typeKind, dst, ((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize);
return ret;
}
@ -17969,6 +17889,11 @@ UA_SecureChannel_close(UA_SecureChannel *channel) {
/* Set the status to closed */
channel->state = UA_SECURECHANNELSTATE_CLOSED;
if(channel->connection == 0)
{
ua_error("ua: [%s] conn null return!\n", __func__);
return;
}
/* Detach from the connection and close the connection */
if(channel->connection) {
if(channel->connection->state != UA_CONNECTIONSTATE_CLOSED)
@ -18613,12 +18538,6 @@ processChunks(UA_SecureChannel *channel, void *application,
channel->decryptedChunksCount > channel->config.localMaxChunkCount) ||
(channel->config.localMaxMessageSize != 0 &&
channel->decryptedChunksLength > channel->config.localMaxMessageSize)) {
ua_print("ua: [%s] count %d max %d len %d mess %d\n",
channel->decryptedChunksCount,
channel->config.localMaxChunkCount,
channel->decryptedChunksLength,
channel->config.localMaxMessageSize
);
return UA_STATUSCODE_BADTCPMESSAGETOOLARGE;
}
@ -18656,9 +18575,6 @@ extractCompleteChunk(UA_SecureChannel *channel, const UA_ByteString *buffer,
UA_decodeBinaryInternal(buffer, &initial_offset, &hdr,
&UA_TRANSPORT[UA_TRANSPORT_TCPMESSAGEHEADER], NULL);
ua_debug("ua: [%s] res %d buf %p offset %d hdr %d size %d\n", __func__, res, buffer, *offset,
hdr.messageTypeAndChunkType, hdr.messageSize);
UA_assert(res == UA_STATUSCODE_GOOD);
(void)res; /* pacify compilers if assert is ignored */
UA_MessageType msgType = (UA_MessageType)
@ -18671,7 +18587,6 @@ extractCompleteChunk(UA_SecureChannel *channel, const UA_ByteString *buffer,
return UA_STATUSCODE_BADTCPMESSAGETYPEINVALID;
if(hdr.messageSize > channel->config.recvBufferSize)
{
ua_debug("lw: [%s] msg size %d rec %d\n", __func__, hdr.messageSize, channel->config.recvBufferSize);
return UA_STATUSCODE_BADTCPMESSAGETOOLARGE;
}
@ -43657,6 +43572,8 @@ UA_Client_delete(UA_Client* client) {
UA_Client_clear(client);
UA_ClientConfig_clear(&client->config);
UA_free(client);
client = NULL;
ua_run_flag = 0;
}
void
@ -43976,7 +43893,7 @@ receiveResponse(UA_Client *client, void *response, const UA_DataType *responseTy
"Receiving the response failed with StatusCode %s",
UA_StatusCode_name(retval));
ua_print("ua: [%s] state %d ret %d %#x\n", __func__, client->channel.state, retval, retval);
closeSecureChannel(client);
// closeSecureChannel(client);
retval = UA_STATUSCODE_BADCONNECTIONCLOSED;
break;
}
@ -44244,7 +44161,7 @@ UA_Client_run_iterate(UA_Client *client, UA_UInt32 timeout) {
client->sessionState < UA_SESSIONSTATE_ACTIVATED) {
retval = connectIterate(client, timeout);
notifyClientState(client);
ua_print("lw: [%s] ret %d timeout %d state %d ch %d\n", __func__, retval, timeout,
ua_print("lw: [%s] ret %x timeout %d state %d ch %d\n", __func__, retval, timeout,
client->sessionState, client->channel.state);
return retval;
}
@ -45187,9 +45104,6 @@ connectIterate(UA_Client *client, UA_UInt32 timeout) {
return UA_STATUSCODE_BADCONNECTIONCLOSED;
}
ua_debug("ua: [%s] conn %d state %d handle %p\n", __func__, client->connectStatus,
client->connection.state, client->connection.handle);
/* The connection is closed. Reset the SecureChannel and open a new TCP
* connection */
if(client->connection.state == UA_CONNECTIONSTATE_CLOSED)
@ -45200,11 +45114,6 @@ connectIterate(UA_Client *client, UA_UInt32 timeout) {
client->connectStatus =
client->config.pollConnectionFunc(&client->connection, timeout,
&client->config.logger);
ua_debug("ua: [%s] exit conn %x %d time %d handle %p\n", __func__,
client->connectStatus,
client->connection.state, timeout, client->connection.handle);
return client->connectStatus;
}
@ -45399,8 +45308,6 @@ connectSync(UA_Client *client) {
UA_DateTime now = UA_DateTime_nowMonotonic();
UA_DateTime maxDate = now + ((UA_DateTime)client->config.timeout * UA_DATETIME_MSEC);
ua_print("ua; [%s] time %d\n", __func__, (UA_DateTime)client->config.timeout);
UA_StatusCode retval = initConnect(client);
if(retval != UA_STATUSCODE_GOOD)
return retval;
@ -70300,16 +70207,30 @@ UA_ServerConfig_setDefaultWithSecurityPolicies(UA_ServerConfig *conf,
UA_Client * UA_Client_new() {
UA_ClientConfig config;
UA_Client *ret = NULL;
if(ua_run_flag)
{
return NULL;
}
memset(&config, 0, sizeof(UA_ClientConfig));
config.logger.log = UA_Log_Stdout_log;
config.logger.context = NULL;
config.logger.clear = UA_Log_Stdout_clear;
return UA_Client_newWithConfig(&config);
ret = UA_Client_newWithConfig(&config);
if(ret)
{
ua_run_flag = 1;
}
return ret;
}
UA_StatusCode
UA_ClientConfig_setDefault(UA_ClientConfig *config) {
config->timeout = 20000;
config->timeout = 5000;
config->secureChannelLifeTime = 10 * 60 * 1000; /* 10 minutes */
if(!config->logger.log) {
@ -71205,7 +71126,6 @@ ServerNetworkLayerTCP_add(UA_ServerNetworkLayer *nl, ServerNetworkLayerTCP *laye
static UA_StatusCode
addServerSocket(ServerNetworkLayerTCP *layer, struct addrinfo *ai) {
/* Create the server socket */
ua_print("ua: [%s] %d %d %d\n", __func__, ai->ai_family, ai->ai_socktype, ai->ai_protocol);
UA_SOCKET newsock = UA_socket(ai->ai_family, ai->ai_socktype, ai->ai_protocol);
if(newsock == UA_INVALID_SOCKET)
{
@ -71341,18 +71261,12 @@ ServerNetworkLayerTCP_start(UA_ServerNetworkLayer *nl, const UA_Logger *logger,
int retcode = UA_getaddrinfo(customHostname->length ? hostname : NULL,
portno, &hints, &res);
ua_print("ua: [%s] host %s pro %d ret %d\n", __func__, hostname, portno, retcode);
if(retcode != 0) {
UA_LOG_SOCKET_ERRNO_GAI_WRAP(UA_LOG_WARNING(layer->logger, UA_LOGCATEGORY_NETWORK,
"getaddrinfo lookup of %s failed with error %d - %s", hostname, retcode, errno_str));
return UA_STATUSCODE_BADINTERNALERROR;
}
ua_print("ua: [%s] res %p fam %d len %d %s\n", __func__, res, res->ai_family,
customHostname->length,
customHostname->data);
/* There might be serveral addrinfos (for different network cards,
* IPv4/IPv6). Add a server socket for all of them. */
struct addrinfo *ai = res;
@ -71597,6 +71511,12 @@ typedef struct TCPClientConnection {
static void
ClientNetworkLayerTCP_close(UA_Connection *connection) {
if(connection == NULL)
{
ua_error("connection NULL!\n");
return;
}
if(connection->state == UA_CONNECTIONSTATE_CLOSED)
return;
@ -71637,10 +71557,6 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
return UA_STATUSCODE_BADDISCONNECT;
}
ua_print("ua: [%s] conn handle %p fam %d sa %d\n", __func__,
connection->handle, tcpConnection->server->ai_family,
tcpConnection->server->ai_addr->sa_family);
/* Get a socket and connect (only once) if not already done in a previous
* call. On win32, calling connect multiple times is not recommended on
* non-blocking sockets
@ -71651,27 +71567,17 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
* and getsockopt using SO_ERROR on win32 and posix.
*/
if(connection->sockfd == UA_INVALID_SOCKET) {
ua_print("ua: [%s] start socket %p ai %d sa %d\n", __func__,
tcpConnection->server,
tcpConnection->server->ai_family,
tcpConnection->server->ai_addr->sa_family);
connection->sockfd = UA_socket(tcpConnection->server->ai_family,
tcpConnection->server->ai_socktype,
tcpConnection->server->ai_protocol);
if(connection->sockfd == UA_INVALID_SOCKET) {
ua_print("ua: [%s] %s\n", __func__, strerror(UA_ERRNO));
UA_LOG_WARNING(logger, UA_LOGCATEGORY_NETWORK,
"Could not create client socket: %s", strerror(UA_ERRNO));
ClientNetworkLayerTCP_close(connection);
return UA_STATUSCODE_BADDISCONNECT;
}
ua_print("ua: [%s] socket fd %d %p fam %d sa %d\n", __func__,
connection->sockfd,
tcpConnection->server,
tcpConnection->server->ai_family,
tcpConnection->server->ai_addr->sa_family);
/* Non blocking connect to be able to timeout */
if(UA_socket_set_nonblocking(connection->sockfd) != UA_STATUSCODE_GOOD) {
UA_LOG_WARNING(logger, UA_LOGCATEGORY_NETWORK,
@ -71680,11 +71586,6 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
return UA_STATUSCODE_BADDISCONNECT;
}
ua_print("ua: [%s] check fd %d %p fam %d sa %d\n", __func__,
connection->sockfd,
tcpConnection->server,
tcpConnection->server->ai_family,
tcpConnection->server->ai_addr->sa_family);
/* Don't have the socket create interrupt signals */
#ifdef SO_NOSIGPIPE
int val = 1;
@ -71693,12 +71594,6 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
if(sso_result < 0)
UA_LOG_WARNING(logger, UA_LOGCATEGORY_NETWORK, "Couldn't set SO_NOSIGPIPE");
#endif
ua_print("ua: [%s] connect ai %d sa fam %d len %d %x addr len %d\n", __func__,
tcpConnection->server->ai_family,
tcpConnection->server->ai_addr->sa_family,
tcpConnection->server->ai_addr->sa_len,
tcpConnection->server->ai_addr->sa_data[0],
tcpConnection->server->ai_addrlen);
int error = UA_connect(connection->sockfd, tcpConnection->server->ai_addr,
tcpConnection->server->ai_addrlen);
@ -71708,7 +71603,6 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
connection->state = UA_CONNECTIONSTATE_ESTABLISHED;
return UA_STATUSCODE_GOOD;
}
ua_print("ua: [%s] connected failed %d\n", __func__, error);
/* The connection failed */
if((UA_ERRNO != UA_ERR_CONNECTION_PROGRESS)) {
@ -71772,6 +71666,7 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
(int)tcpConnection->endpointUrl.length,
tcpConnection->endpointUrl.data, strerror(UA_ERRNO));
ClientNetworkLayerTCP_close(connection);
ua_error("ua: [%s] line %d failed\n", __func__, __LINE__);
return UA_STATUSCODE_BADDISCONNECT;
}
@ -71802,6 +71697,7 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
LocalFree(errno_str);
#endif
ClientNetworkLayerTCP_close(connection);
ua_error("ua: [%s] line %d failed\n", __func__, __LINE__);
return UA_STATUSCODE_BADDISCONNECT;
}
@ -71831,14 +71727,11 @@ UA_ClientConnectionTCP_init(UA_ConnectionConfig config, const UA_String endpoint
connection.releaseSendBuffer = connection_releasesendbuffer;
connection.releaseRecvBuffer = connection_releaserecvbuffer;
ua_print("ua: [%s] endpoint url (%d)%.28s %d\n", __func__, endpointUrl.length, endpointUrl.data,
sizeof(TCPClientConnection));
TCPClientConnection *tcpClientConnection = (TCPClientConnection*)
UA_malloc(sizeof(TCPClientConnection));
if(!tcpClientConnection) {
connection.state = UA_CONNECTIONSTATE_CLOSED;
ua_print("ua: [%s] malloc %d failed\n", __func__, sizeof(TCPClientConnection));
ua_error("ua: [%s] malloc %d failed\n", __func__, sizeof(TCPClientConnection));
return connection;
}
memset(tcpClientConnection, 0, sizeof(TCPClientConnection));
@ -71850,8 +71743,6 @@ UA_ClientConnectionTCP_init(UA_ConnectionConfig config, const UA_String endpoint
char hostname[512];
tcpClientConnection->connStart = UA_DateTime_nowMonotonic();
ua_print("ua: [%s] line %d!\n", __func__, __LINE__);
UA_String_copy(&endpointUrl, &tcpClientConnection->endpointUrl);
UA_StatusCode parse_retval =
@ -71864,8 +71755,6 @@ UA_ClientConnectionTCP_init(UA_ConnectionConfig config, const UA_String endpoint
return connection;
}
ua_print("ua: [%s] line %d!\n", __func__, __LINE__);
memcpy(hostname, hostnameString.data, hostnameString.length);
hostname[hostnameString.length] = 0;
@ -71875,22 +71764,16 @@ UA_ClientConnectionTCP_init(UA_ConnectionConfig config, const UA_String endpoint
"No port defined, using default port %" PRIu16, port);
}
ua_print("ua: [%s] line %d!\n", __func__, __LINE__);
memset(&tcpClientConnection->hints, 0, sizeof(tcpClientConnection->hints));
tcpClientConnection->hints.ai_family = AF_UNSPEC;
tcpClientConnection->hints.ai_socktype = SOCK_STREAM;
char portStr[6];
UA_snprintf(portStr, 6, "%d", port);
// ua_print("ua: [%s] host %s port %s fam %d\n", __func__, hostname, portStr,
// tcpClientConnection->server->ai_addr->sa_family);
#if LWIP_DNS
int error = UA_getaddrinfo(hostname, portStr, &tcpClientConnection->hints,
&tcpClientConnection->server);
if(error != 0 || !tcpClientConnection->server) {
ua_print("ua: [%s] host %s error %d\n", __func__, hostname, error);
UA_LOG_SOCKET_ERRNO_GAI_WRAP(UA_LOG_WARNING(logger, UA_LOGCATEGORY_NETWORK,
"DNS lookup of %s failed with error %d - %s",
hostname, error, errno_str));

23
APP_Framework/Framework/control/plc/interoperability/opcua/ua_api.c
View File

@ -22,7 +22,7 @@
#include <stdlib.h>
#include "ua_api.h"
int ua_open(void *dev)
int UaDevOpen(void *dev)
{
UaParamType *param = (UaParamType *)dev;
@ -32,7 +32,7 @@ int ua_open(void *dev)
if (param->client == NULL)
{
ua_print("ua: [%s] tcp client null\n", __func__);
ua_error("ua: [%s] tcp client null\n", __func__);
return EEMPTY;
}
@ -43,28 +43,29 @@ int ua_open(void *dev)
UA_StatusCode retval = UA_Client_connect(param->client, param->ua_remote_ip);
if(retval != UA_STATUSCODE_GOOD) {
ua_notice("ua: [%s] deleted ret %x!\n", __func__, retval);
ua_error("ua: [%s] deleted ret %x!\n", __func__, retval);
return (int)retval;
}
return EOK;
}
void ua_close(void *dev)
void UaDevClose(void *dev)
{
UaParamType *param = (UaParamType *)dev;
ua_notice("ua: [%s] close %s!\n", __func__, param->ua_remote_ip);
UA_Client_delete(param->client); /* Disconnects the client internally */
}
int ua_read(void *dev, void *buf, size_t len)
int UaDevRead(void *dev, void *buf, size_t len)
{
UaParamType *param = (UaParamType *)dev;
switch(param->act)
{
case UA_ACT_ATTR:
ua_read_nodeid_value(param->client, param->ua_id, buf);
UaReadNodeValue(param->client, param->ua_id, buf);
break;
case UA_ACT_OBJ:
ua_test_browser_objects(param->client);
UaTestBrowserObjects(param->client);
break;
default:
break;
@ -72,17 +73,17 @@ int ua_read(void *dev, void *buf, size_t len)
return EOK;
}
int ua_write(void *dev, const void *buf, size_t len)
int UaDevWrite(void *dev, const void *buf, size_t len)
{
UaParamType *param = (UaParamType *)dev;
switch(param->act)
{
case UA_ACT_ATTR:
ua_write_nodeid_value(param->client, param->ua_id, (char *)buf);
UaWriteNodeValue(param->client, param->ua_id, (char *)buf);
break;
case UA_ACT_OBJ:
ua_test_browser_objects(param->client);
UaTestBrowserObjects(param->client);
break;
default:
break;
@ -90,7 +91,7 @@ int ua_write(void *dev, const void *buf, size_t len)
return EOK;
}
int ua_ioctl(void *dev, int cmd, void *arg)
int UaDevIoctl(void *dev, int cmd, void *arg)
{
return EOK;
}

37
APP_Framework/Framework/control/plc/interoperability/opcua/ua_api.h
View File

@ -42,32 +42,31 @@ typedef struct UaParam
}UaParamType;
#define ua_print //KPrintf
#define ua_trace() //KPrintf("ua: [%s] line %d checked!\n", __func__, __LINE__)
#define ua_notice KPrintf
#define ua_debug //KPrintf
#define ua_error KPrintf
extern const char *opc_server_url;
extern char test_ua_ip[];
int ua_server_connect(void);
void ua_browser_nodes(UA_Client *client);
void ua_browser_id(UA_Client *client, UA_NodeId id);
void ua_read_time(UA_Client *client);
void ua_add_nodes(UA_Client *client);
int UaServerRun(void);
void UaBrowserNodes(UA_Client *client);
void UaBrowserNodeId(UA_Client *client, UA_NodeId id);
void UaGetServerTime(UA_Client *client);
void UaAddNodes(UA_Client *client);
int ua_open(void *dev); // open and connect PLC device
void ua_close(void* dev); // close and disconnect PLC device
int ua_read(void* dev, void *buf, size_t len); // read data from PLC
int ua_write(void* dev, const void *buf, size_t len); // write data from PLC
int ua_ioctl(void* dev, int cmd, void *arg); // send control command to PLC
int UaDevOpen(void *dev); // open and connect PLC device
void UaDevClose(void* dev); // close and disconnect PLC device
int UaDevRead(void* dev, void *buf, size_t len); // read data from PLC
int UaDevWrite(void* dev, const void *buf, size_t len); // write data from PLC
int UaDevIoctl(void* dev, int cmd, void *arg); // send control command to PLC
char *ua_get_nodeid_str(UA_NodeId *node_id);
void ua_read_nodeid_value(UA_Client *client, UA_NodeId id, UA_Int32 *value);
void ua_write_nodeid_value(UA_Client *client, UA_NodeId id, char* value);
void ua_test_attr(UA_Client *client);
UA_StatusCode ua_read_array_value(UA_Client *client, int array_size, UA_ReadValueId *array);
void ua_test_browser_objects(UA_Client *client);
int ua_test_interact_server(UA_Client *client);
char *UaGetNodeIdString(UA_NodeId *node_id);
void UaReadNodeValue(UA_Client *client, UA_NodeId id, UA_Int32 *value);
void UaWriteNodeValue(UA_Client *client, UA_NodeId id, char* value);
UA_StatusCode UaReadArrayValue(UA_Client *client, int array_size, UA_ReadValueId *array);
int UaGetNodeIdArray(UA_Client* client, UA_NodeId id, int array_size, int *id_array);
void UaTestBrowserObjects(UA_Client *client);
int UaTestInteractServer(UA_Client *client);
#endif

138
APP_Framework/Framework/control/plc/interoperability/opcua/ua_client.c
View File

@ -27,14 +27,14 @@
const char *opc_server_url = {"opc.tcp://192.168.250.2:4840"};
#ifdef UA_ENABLE_SUBSCRIPTIONS
static void handler_TheAnswerChanged(UA_Client* client, UA_UInt32 subId, void* subContext,
static void UaAnswerChangedHandler(UA_Client* client, UA_UInt32 subId, void* subContext,
UA_UInt32 monId, void* monContext, UA_DataValue* value)
{
ua_print("The Answer has changed!\n");
ua_notice("Answer changed!\n");
}
#endif
static UA_StatusCode nodeIter(UA_NodeId childId, UA_Boolean isInverse, UA_NodeId referenceTypeId, void* handle)
static UA_StatusCode UaShowNodeIdIterate(UA_NodeId childId, UA_Boolean isInverse, UA_NodeId referenceTypeId, void* handle)
{
if(isInverse)
{
@ -49,7 +49,7 @@ static UA_StatusCode nodeIter(UA_NodeId childId, UA_Boolean isInverse, UA_NodeId
return UA_STATUSCODE_GOOD;
}
int ua_get_points(UA_Client* client)
int UaGetEndPoints(UA_Client* client)
{
/* Listing endpoints */
UA_EndpointDescription* endpointArray = NULL;
@ -76,7 +76,7 @@ int ua_get_points(UA_Client* client)
return EXIT_SUCCESS;
}
void ua_print_value(UA_Variant* val)
static void UaShowNodeValue(UA_Variant* val)
{
if(val->type == &UA_TYPES[UA_TYPES_LOCALIZEDTEXT])
{
@ -103,6 +103,16 @@ void ua_print_value(UA_Variant* val)
UA_Int16* ptr = (UA_Int16*)val->data;
ua_notice("%d (Int16)\n", *ptr);
}
else if(val->type == &UA_TYPES[UA_TYPES_FLOAT])
{
UA_Float* ptr = (UA_Float*)val->data;
printf("%f (Float)\n", *ptr);
}
else if(val->type == &UA_TYPES[UA_TYPES_DOUBLE])
{
UA_Double* ptr = (UA_Double*)val->data;
printf("%f (Double)\n", *ptr);
}
else if(val->type == &UA_TYPES[UA_TYPES_STRING])
{
UA_String* ptr = (UA_String*)val->data;
@ -117,7 +127,7 @@ void ua_print_value(UA_Variant* val)
}
}
char *ua_get_nodeid_str(UA_NodeId *node_id)
char *UaGetNodeIdString(UA_NodeId *node_id)
{
static char nodeid_str[UA_NODE_LEN] = {0};
@ -139,7 +149,7 @@ char *ua_get_nodeid_str(UA_NodeId *node_id)
return nodeid_str;
}
void ua_print_nodeid(UA_NodeId *node_id)
static void UaShowNodeId(UA_NodeId *node_id)
{
switch(node_id->identifierType)
{
@ -158,7 +168,7 @@ void ua_print_nodeid(UA_NodeId *node_id)
}
}
void ua_print_object(UA_BrowseResponse* res)
static void UaShowObject(UA_BrowseResponse* res)
{
ua_notice("%-9s %-16s %-16s %-16s\n", "NAMESPACE", "NODEID", "BROWSE NAME", "DISPLAY NAME");
@ -191,7 +201,7 @@ void ua_print_object(UA_BrowseResponse* res)
ua_notice("\n");
}
UA_StatusCode ua_read_array_value(UA_Client* client, int array_size, UA_ReadValueId* array)
UA_StatusCode UaReadArrayValue(UA_Client* client, int array_size, UA_ReadValueId* array)
{
UA_ReadRequest request;
UA_ReadRequest_init(&request);
@ -209,14 +219,19 @@ UA_StatusCode ua_read_array_value(UA_Client* client, int array_size, UA_ReadValu
}
UA_StatusCode* arr_ret = malloc(array_size * sizeof(UA_StatusCode));
if(arr_ret == NULL)
{
ua_error("ua: [%s] malloc %d failed!\n", __func__, array_size * sizeof(UA_StatusCode));
return UA_STATUSCODE_BADOUTOFMEMORY;
}
for(int i = 0; i < array_size; ++i)
{
if((response.results[i].status == UA_STATUSCODE_GOOD)
&& (response.results[i].hasValue))
{
ua_notice("node %s: ", ua_get_nodeid_str(&array[i].nodeId));
ua_print_value(&response.results[i].value);
ua_notice("node %s: ", UaGetNodeIdString(&array[i].nodeId));
UaShowNodeValue(&response.results[i].value);
}
}
ua_notice("\n");
@ -226,32 +241,82 @@ UA_StatusCode ua_read_array_value(UA_Client* client, int array_size, UA_ReadValu
return UA_STATUSCODE_GOOD;
}
void ua_browser_id(UA_Client* client, UA_NodeId id)
void UaBrowserNodeId(UA_Client* client, UA_NodeId id)
{
UA_BrowseRequest ua_req;
UA_BrowseResponse ua_resp;
/* Browse some objects */
ua_notice("Browsing nodes in objects folder:\n");
UA_BrowseRequest bReq;
UA_BrowseRequest_init(&bReq);
bReq.requestedMaxReferencesPerNode = 0;
bReq.nodesToBrowse = UA_BrowseDescription_new();
bReq.nodesToBrowseSize = 1;
bReq.nodesToBrowse[0].nodeId = id; /* browse objects folder */
bReq.nodesToBrowse[0].resultMask = UA_BROWSERESULTMASK_ALL; /* return everything */
UA_BrowseResponse res = UA_Client_Service_browse(client, bReq);
ua_print_object(&res);
UA_BrowseResponse_clear(&res);
// UA_BrowseRequest_clear(&bReq);
UA_BrowseRequest_init(&ua_req);
ua_req.requestedMaxReferencesPerNode = 0;
ua_req.nodesToBrowse = UA_BrowseDescription_new();
ua_req.nodesToBrowseSize = 1;
ua_req.nodesToBrowse[0].nodeId = id; /* browse objects folder */
ua_req.nodesToBrowse[0].resultMask = UA_BROWSERESULTMASK_ALL; /* return everything */
ua_resp = UA_Client_Service_browse(client, ua_req);
UaShowObject(&ua_resp);
UA_BrowseResponse_clear(&ua_resp);
}
void ua_browser_nodes(UA_Client* client)
int UaGetNodeIdArray(UA_Client* client, UA_NodeId id, int array_size, int *id_array)
{
int i, j;
int array_cnt = 0;// return array number
UA_BrowseRequest ua_req;
UA_BrowseResponse ua_resp;
/* Browse some objects */
ua_notice("Browsing nodes in objects folder:\n");
UA_BrowseRequest_init(&ua_req);
ua_req.requestedMaxReferencesPerNode = 0;
ua_req.nodesToBrowse = UA_BrowseDescription_new();
ua_req.nodesToBrowseSize = 1;
ua_req.nodesToBrowse[0].nodeId = id; /* browse objects folder */
ua_req.nodesToBrowse[0].resultMask = UA_BROWSERESULTMASK_ALL; /* return everything */
ua_resp = UA_Client_Service_browse(client, ua_req);
for(i = 0; i < ua_resp.resultsSize; ++i)
{
for(j = 0; j < ua_resp.results[i].referencesSize; ++j)
{
UA_ReferenceDescription* ref = &(ua_resp.results[i].references[j]);
if(ref->nodeId.nodeId.identifierType == UA_NODEIDTYPE_NUMERIC)
{
*(id_array + array_cnt) = ref->nodeId.nodeId.identifier.numeric;
array_cnt ++;
if(array_cnt >= array_size)
{
UA_BrowseResponse_clear(&ua_resp);
return array_cnt;
}
}
}
}
UA_BrowseResponse_clear(&ua_resp);
return array_cnt;
}
void UaBrowserNodes(UA_Client* client)
{
UA_NodeId* parent = UA_NodeId_new();
*parent = UA_NODEID_NUMERIC(0, UA_NS0ID_OBJECTSFOLDER);
UA_Client_forEachChildNodeCall(client, UA_NODEID_NUMERIC(0, UA_NS0ID_OBJECTSFOLDER), nodeIter, (void*) parent);
UA_Client_forEachChildNodeCall(client, UA_NODEID_NUMERIC(0, UA_NS0ID_OBJECTSFOLDER), UaShowNodeIdIterate, (void*) parent);
UA_NodeId_delete(parent);
}
UA_UInt32 ua_start_sub(UA_Client* client, UA_NodeId node_id)
UA_UInt32 UaStartSubscription(UA_Client* client, UA_NodeId node_id)
{
/* Create a subscription */
UA_CreateSubscriptionRequest request = UA_CreateSubscriptionRequest_default();
@ -274,7 +339,7 @@ UA_UInt32 ua_start_sub(UA_Client* client, UA_NodeId node_id)
UA_MonitoredItemCreateResult monResponse =
UA_Client_MonitoredItems_createDataChange(client, response.subscriptionId,
UA_TIMESTAMPSTORETURN_BOTH,
monRequest, NULL, handler_TheAnswerChanged, NULL);
monRequest, NULL, UaAnswerChangedHandler, NULL);
if(monResponse.statusCode == UA_STATUSCODE_GOOD)
{
@ -290,7 +355,7 @@ UA_UInt32 ua_start_sub(UA_Client* client, UA_NodeId node_id)
return subId;
}
void ua_write_nodeid_value(UA_Client* client, UA_NodeId id, char* value)
void UaWriteNodeValue(UA_Client* client, UA_NodeId id, char* value)
{
UA_Boolean bool_val;
uint32_t integer_val;
@ -332,24 +397,17 @@ void ua_write_nodeid_value(UA_Client* client, UA_NodeId id, char* value)
UA_WriteRequest_clear(&wReq);
UA_WriteResponse_clear(&wResp);
// /* Write node attribute (using the highlevel API) */
// value++;
// UA_Variant *myVariant = UA_Variant_new();
// UA_Variant_setScalarCopy(myVariant, &value, &UA_TYPES[UA_TYPES_INT32]);
// UA_Client_writeValueAttribute(client, UA_NODEID_STRING(1, UA_NODE_STR), myVariant);
// UA_Variant_delete(myVariant);
}
/* Read attribute */
void ua_read_nodeid_value(UA_Client* client, UA_NodeId id, UA_Int32 *value)
void UaReadNodeValue(UA_Client* client, UA_NodeId id, UA_Int32 *value)
{
UA_Variant* val = UA_Variant_new();
UA_StatusCode ret = UA_Client_readValueAttribute(client, id, val);
if(ret == UA_STATUSCODE_GOOD)
{
ua_print_value(val);
UaShowNodeValue(val);
if(UA_Variant_isScalar(val))
{
if(val->type == &UA_TYPES[UA_TYPES_BOOLEAN])
@ -370,7 +428,7 @@ void ua_read_nodeid_value(UA_Client* client, UA_NodeId id, UA_Int32 *value)
UA_Variant_delete(val);
}
void ua_call_remote(UA_Client* client)
void UaCallRemote(UA_Client* client)
{
/* Call a remote method */
UA_Variant input;
@ -397,7 +455,7 @@ void ua_call_remote(UA_Client* client)
}
void ua_add_nodes(UA_Client* client)
void UaAddNodes(UA_Client* client)
{
/* Add new nodes*/
/* New ReferenceType */
@ -477,7 +535,7 @@ void ua_add_nodes(UA_Client* client)
}
}
void ua_read_time(UA_Client* client)
void UaGetServerTime(UA_Client* client)
{
UA_Variant value;
UA_Variant_init(&value);

28
APP_Framework/Framework/control/plc/interoperability/opcua/ua_server.c
View File

@ -10,29 +10,29 @@
* See the Mulan PSL v2 for more details.
*/
/**
* @file ua_server.c
* @brief Server for OpcUa function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021.11.11
*/
#include "open62541.h"
#include <signal.h>
#include <stdlib.h>
UA_Boolean ua_server_flag = true;
UA_Boolean running = true;
static void stopHandler(int sign) {
UA_LOG_INFO(UA_Log_Stdout, UA_LOGCATEGORY_SERVER, "received ctrl-c");
running = false;
}
int ua_server_connect(void)
int UaRunServer(void)
{
signal(SIGINT, stopHandler);
signal(SIGTERM, stopHandler);
UA_StatusCode ret;
UA_Server *server = UA_Server_new();
UA_ServerConfig_setDefault(UA_Server_getConfig(server));
UA_StatusCode retval = UA_Server_run(server, &running);
ret = UA_Server_run(server, &ua_server_flag);
UA_Server_delete(server);
return retval == UA_STATUSCODE_GOOD ? EXIT_SUCCESS : EXIT_FAILURE;
return ret;
}

72
APP_Framework/Framework/control/plc/interoperability/opcua/ua_test.c
View File

@ -27,72 +27,60 @@
#define UA_TEST_BROWSER_NODEID1 UA_NODEID_NUMERIC(4, 1)
#define UA_TEST_WRITE_NODEID UA_NODEID_NUMERIC(4, 5)
#define UA_TEST_NODE_ARRAY_NUM 10
static UA_StatusCode ua_test_read_array(UA_Client *client)
static UA_StatusCode UaTestReadArrayValue(UA_Client *client, UA_NodeId id)
{
const int item_size = 4;
UA_ReadValueId test_item[item_size];
int i;
int array_size = 0;
int test_id[UA_TEST_NODE_ARRAY_NUM];
UA_ReadValueId test_array[UA_TEST_NODE_ARRAY_NUM];
for (int i = 0; i < item_size; i++)
for(i = 0; i < UA_TEST_NODE_ARRAY_NUM; i++)
{
UA_ReadValueId_init(&test_item[i]);
test_item[i].attributeId = UA_ATTRIBUTEID_VALUE;
UA_ReadValueId_init(&test_array[i]);
test_array[i].attributeId = UA_ATTRIBUTEID_VALUE;
}
test_item[0].nodeId = UA_NODEID_NUMERIC(4, 2);
test_item[1].nodeId = UA_NODEID_NUMERIC(4, 3);
test_item[2].nodeId = UA_NODEID_NUMERIC(4, 4);
test_item[3].nodeId = UA_NODEID_NUMERIC(4, 5);
array_size = UaGetNodeIdArray(client, id, UA_TEST_NODE_ARRAY_NUM, test_id);
return ua_read_array_value(client, item_size, test_item);
for(i = 0; i < array_size; i++)
{
test_array[i].nodeId = UA_NODEID_NUMERIC(id.namespaceIndex, test_id[i]);
}
return UaReadArrayValue(client, array_size, test_array);
}
void ua_test_browser_objects(UA_Client *client)
void UaTestBrowserObjects(UA_Client *client)
{
UA_NodeId test_id;
ua_browser_id(client, UA_TEST_BROWSER_NODEID);
ua_browser_id(client, UA_TEST_BROWSER_NODEID1);
UaBrowserNodeId(client, UA_TEST_BROWSER_NODEID);
UaBrowserNodeId(client, UA_TEST_BROWSER_NODEID1);
test_id = UA_TEST_BROWSER_NODEID1;
ua_notice("Show values in %s:\n", ua_get_nodeid_str(&test_id));
ua_test_read_array(client);
ua_notice("Show values in %s:\n", UaGetNodeIdString(&test_id));
UaTestReadArrayValue(client, test_id);
return;
}
void ua_test_write_attr(UA_Client *client)
static void UaTestWriteNodeValue(UA_Client *client)
{
UA_Int32 value;
char val_str[UA_NODE_LEN];
UA_NodeId id = UA_TEST_WRITE_NODEID;
ua_notice("--- Test write %s ---\n", ua_get_nodeid_str(&id));
ua_read_nodeid_value(client, id, &value);
ua_write_nodeid_value(client, id, itoa(value + 1, val_str, 10));
ua_read_nodeid_value(client, id, &value);
ua_notice("--- Test write %s ---\n", UaGetNodeIdString(&id));
UaReadNodeValue(client, id, &value);
UaWriteNodeValue(client, id, itoa(value + 1, val_str, 10));
UaReadNodeValue(client, id, &value);
ua_notice("\n");
}
int ua_test_interact_server(UA_Client *client)
int UaTestInteractServer(UA_Client *client)
{
ua_read_time(client);
ua_test_browser_objects(client);
ua_test_write_attr(client);
return EXIT_SUCCESS;
}
int16 ua_test(void)
{
UA_Client *client = UA_Client_new();
UA_StatusCode retval = UA_Client_connect(client, opc_server_url);
if(retval != UA_STATUSCODE_GOOD) {
UA_Client_delete(client);
return (int)retval;
}
ua_read_time(client);
/* Clean up */
UA_Client_disconnect(client);
UA_Client_delete(client); /* Disconnects the client internally */
UaGetServerTime(client);
UaTestBrowserObjects(client);
UaTestWriteNodeValue(client);
return EXIT_SUCCESS;
}

2
APP_Framework/Framework/control/plc/shared/plc_channel.c
View File

@ -322,7 +322,7 @@ ChDevType ChannelFindDevice(struct Channel *ch, const char *device_name)
* @param dev_recv_callback - callback function
* @return successful:EOK,failed:ERROR
*/
uint32 ChannelDevRecvCallback(struct ChDev *dev, int (*dev_recv_callback) (void *dev, x_size_t length))
uint32 ChannelDevRecvCallback(struct ChDev *dev, int (*dev_recv_callback) (void *dev, size_t length))
{
CHECK_CH_PARAM(dev );

28
APP_Framework/Framework/control/plc/shared/plc_channel.h
View File

@ -12,7 +12,7 @@
/**
* @file plc_channel.h
* @brief define ch driver framework function and common API
* @brief define channel driver framework function and common API
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-01
@ -23,9 +23,6 @@
#include "list.h"
#define x_OffPos uint32
#define x_size_t size_t
#ifdef __cplusplus
extern "C" {
#endif
@ -97,27 +94,19 @@ struct ChConfigInfo
struct ChReadParam
{
x_OffPos pos;
uint32 pos;
void* buffer;
x_size_t size;
x_size_t read_length;
size_t size;
size_t read_length;
};
struct ChWriteParam
{
x_OffPos pos;
uint32 pos;
const void* buffer;
x_size_t size;
size_t size;
};
//struct ChHalDevBlockParam
//{
// uint32 cmd;
////tst by wly
//// struct DeviceBlockArrange dev_block;
//// struct DeviceBlockAddr *dev_addr;
//};
struct ChHalDevDone
{
uint32 (*open) (void *dev);
@ -134,8 +123,7 @@ struct ChDev
const struct ChHalDevDone *dev_done;
int (*dev_recv_callback) (void *dev, x_size_t length);
// int (*dev_block_control) (struct ChDev *dev, struct ChHalDevBlockParam *block_param);
int (*dev_recv_callback) (void *dev, size_t length);
struct Channel *owner_ch;
void *private_data;
@ -220,7 +208,7 @@ ChDrvType ChannelFindDriver(struct Channel *ch, const char *driver_name);
ChDevType ChannelFindDevice(struct Channel *ch, const char *device_name);
/*Dev receive data callback function*/
uint32 ChannelDevRecvCallback(struct ChDev *dev, int (*dev_recv_callback) (void *dev, x_size_t length));
uint32 ChannelDevRecvCallback(struct ChDev *dev, int (*dev_recv_callback) (void *dev, size_t length));
/*Open the device of the channel*/
uint32 ChannelDevOpen(struct ChDev *dev);

8
APP_Framework/Framework/control/plc/shared/plc_device.c
View File

@ -40,7 +40,7 @@ static int PlcDeviceOpen(void *dev)
if(plc_dev->net == PLC_IND_ENET_OPCUA)
{
return ua_open(plc_dev->priv_data);
return UaDevOpen(plc_dev->priv_data);
}
return EOK;
@ -54,7 +54,7 @@ static void PlcDeviceClose(void *dev)
if(plc_dev->net == PLC_IND_ENET_OPCUA)
{
ua_close(plc_dev->priv_data);
UaDevClose(plc_dev->priv_data);
}
}
@ -67,7 +67,7 @@ static int PlcDeviceWrite(void *dev, const void *buf, size_t len)
if(plc_dev->net == PLC_IND_ENET_OPCUA)
{
ret = ua_write(plc_dev->priv_data, buf, len);
ret = UaDevWrite(plc_dev->priv_data, buf, len);
}
return ret;
@ -83,7 +83,7 @@ static int PlcDeviceRead(void *dev, void *buf, size_t len)
if(plc_dev->net == PLC_IND_ENET_OPCUA)
{
ret = ua_read(plc_dev->priv_data, buf, len);
ret = UaDevRead(plc_dev->priv_data, buf, len);
}
return ret;

5
APP_Framework/Framework/transform_layer/nuttx/transform.c
View File

@ -92,10 +92,11 @@ void PrivTaskQuit(void *value_ptr)
int PrivTaskDelay(int32_t ms)
{
return usleep(ms);
return usleep(1000 * ms);
}
uint32_t PrivGetTickTime(){
uint32_t PrivGetTickTime(void)
{
struct timespec ts;
clock_gettime(CLOCK_MONOTONIC, &ts);
return ts.tv_sec * 1000 + ts.tv_nsec / 1000000;

2
APP_Framework/Framework/transform_layer/nuttx/transform.h
View File

@ -192,7 +192,7 @@ int PrivTaskStartup(pthread_t *thread);
int PrivTaskDelete(pthread_t thread, int sig);
void PrivTaskQuit(void *value_ptr);
int PrivTaskDelay(int32_t ms);
uint32_t PrivGetTickTime();
uint32_t PrivGetTickTime(void);
/*********************driver*************************/

60
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/Kconfig
View File

@ -24,4 +24,64 @@ config XIDATONG_SDRAM
---help---
Activate DCD configuration of SDRAM
config XIDATONG_SDIO_AUTOMOUNT
bool "SD card automounter"
default n
depends on FS_AUTOMOUNTER && IMXRT_USDHC
if XIDATONG_SDIO_AUTOMOUNT
config XIDATONG_SDIO_AUTOMOUNT_FSTYPE
string "SD card file system type"
default "vfat"
config XIDATONG_SDIO_AUTOMOUNT_BLKDEV
string "SD card block device"
default "/dev/mmcsd0"
config XIDATONG_SDIO_AUTOMOUNT_MOUNTPOINT
string "SD card mount point"
default "/mnt/sdcard"
config XIDATONG_SDIO_AUTOMOUNT_DDELAY
int "SD card debounce delay (milliseconds)"
default 1000
config XIDATONG_SDIO_AUTOMOUNT_UDELAY
int "SD card unmount retry delay (milliseconds)"
default 2000
endif # XIDATONG_SDIO_AUTOMOUNT
config XIDATONG_USB_AUTOMOUNT
bool "USB Mass Storage automounter"
default n
depends on USBHOST_MSC && USBHOST_MSC_NOTIFIER
if XIDATONG_USB_AUTOMOUNT
config XIDATONG_USB_AUTOMOUNT_FSTYPE
string "USB file system type"
default "vfat"
config XIDATONG_USB_AUTOMOUNT_BLKDEV
string "USB block device prefix"
default "/dev/sd"
config XIDATONG_USB_AUTOMOUNT_MOUNTPOINT
string "USB mount point prefix"
default "/mnt/usb"
config XIDATONG_USB_AUTOMOUNT_NUM_BLKDEV
int "Number of block devices to monitor."
range 1 26
default 4
config XIDATONG_USB_AUTOMOUNT_UDELAY
int "USB unmount retry delay (milliseconds)"
default 2000
endif # XIDATONG_USB_AUTOMOUNT
endif

1
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/knsh/defconfig
View File

@ -44,4 +44,5 @@ CONFIG_START_DAY=8
CONFIG_START_MONTH=6
CONFIG_SYSTEM_NSH=y
CONFIG_SYS_RESERVED=9
CONFIG_DEV_GPIO=y
CONFIG_USER_ENTRYPOINT="nsh_main"

1
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/libcxxtest/defconfig
View File

@ -43,4 +43,5 @@ CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=14
CONFIG_START_MONTH=3
CONFIG_SYSTEM_NSH=y
CONFIG_DEV_GPIO=y
CONFIG_USER_ENTRYPOINT="nsh_main"

1
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/netnsh/defconfig
View File

@ -65,4 +65,5 @@ CONFIG_START_MONTH=3
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_PING6=y
CONFIG_SYSTEM_PING=y
CONFIG_DEV_GPIO=y
CONFIG_USER_ENTRYPOINT="nsh_main"

1
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/nsh/defconfig
View File

@ -41,4 +41,5 @@ CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=14
CONFIG_START_MONTH=3
CONFIG_SYSTEM_NSH=y
CONFIG_DEV_GPIO=y
CONFIG_USER_ENTRYPOINT="nsh_main"

12
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/usdhc/defconfig → Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/sdionsh/defconfig
View File

@ -20,11 +20,6 @@ CONFIG_ARMV7M_ICACHE=y
CONFIG_ARMV7M_USEBASEPRI=y
CONFIG_BOARD_LOOPSPERMSEC=104926
CONFIG_BUILTIN=y
CONFIG_DEBUG_FEATURES=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEV_URANDOM=y
CONFIG_DEV_ZERO=y
CONFIG_FAT_LCNAMES=y
CONFIG_CLOCK_MONOTONIC=y
CONFIG_FAT_LFN=y
@ -32,9 +27,9 @@ CONFIG_FS_FAT=y
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_EXAMPLES_HELLO=y
CONFIG_IMXRT1020_EVK_QSPI_FLASH=y
CONFIG_IMXRT_GPIO1_0_15_IRQ=y
CONFIG_IMXRT_GPIO2_16_31_IRQ=y
CONFIG_IMXRT_GPIO_IRQ=y
CONFIG_DEV_GPIO=y
CONFIG_IMXRT_LPUART1=y
CONFIG_IMXRT_USDHC1=y
CONFIG_IMXRT_USDHC1_WIDTH_D1_D4=y
@ -42,9 +37,7 @@ CONFIG_INTELHEX_BINARY=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_NCHAINS=8
CONFIG_LIBC_STRERROR=y
CONFIG_LPUART1_RXBUFSIZE=1024
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_LPUART1_TXBUFSIZE=1024
CONFIG_MMCSD=y
CONFIG_MMCSD_SDIO=y
CONFIG_MM_IOB=y
@ -69,5 +62,6 @@ CONFIG_START_DAY=14
CONFIG_START_MONTH=3
CONFIG_SYSTEM_CLE_CMD_HISTORY=y
CONFIG_SYSTEM_COLOR_CLE=y
CONFIG_FS_AUTOMOUNTER=y
CONFIG_SYSTEM_NSH=y
CONFIG_USER_ENTRYPOINT="nsh_main"

65
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/usbnsh/defconfig Normal file
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@ -0,0 +1,65 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
CONFIG_ADD_NUTTX_FETURES=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="xidatong"
CONFIG_ARCH_BOARD_XIDATONG=y
CONFIG_ARCH_CHIP="imxrt"
CONFIG_ARCH_CHIP_IMXRT=y
CONFIG_ARCH_CHIP_MIMXRT1052CVL5B=y
CONFIG_ARCH_INTERRUPTSTACK=10240
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARMV7M_DCACHE=y
CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
CONFIG_ARMV7M_ICACHE=y
CONFIG_ARMV7M_USEBASEPRI=y
CONFIG_BOARD_LOOPSPERMSEC=104926
CONFIG_BUILTIN=y
CONFIG_FAT_LCNAMES=y
CONFIG_CLOCK_MONOTONIC=y
CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_EXAMPLES_HELLO=y
CONFIG_IMXRT_LPUART1=y
CONFIG_INTELHEX_BINARY=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_NCHAINS=8
CONFIG_LIBC_STRERROR=y
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_MM_IOB=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_CMDOPT_DD_STATS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_RAM_SIZE=524288
CONFIG_RAM_START=0x20200000
CONFIG_RAW_BINARY=y
CONFIG_SCHED_CHILD_STATUS=y
CONFIG_SCHED_HAVE_PARENT=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_LPWORK=y
CONFIG_SCHED_WAITPID=y
CONFIG_SERIAL_TERMIOS=y
CONFIG_START_DAY=14
CONFIG_START_MONTH=3
CONFIG_SYSTEM_CLE_CMD_HISTORY=y
CONFIG_SYSTEM_COLOR_CLE=y
CONFIG_SYSTEM_NSH=y
CONFIG_IMXRT_USBOTG=y
CONFIG_IMXRT_USBDEV=y
CONFIG_USBDEV=y
CONFIG_USBHOST=y
CONFIG_USBHOST_MSC=y
CONFIG_USBHOST_MSC_NOTIFIER=y
CONFIG_DEV_GPIO=y
CONFIG_USER_ENTRYPOINT="nsh_main"

4
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/include/board.h
View File

@ -128,6 +128,7 @@
#define IMXRT_SYS_PLL_SELECT CCM_ANALOG_PLL_SYS_DIV_SELECT_22
#define IMXRT_USB1_PLL_DIV_SELECT CCM_ANALOG_PLL_USB1_DIV_SELECT_20
#define IMXRT_USB2_PLL_DIV_SELECT CCM_ANALOG_PLL_USB2_DIV_SELECT_20
// #define BOARD_CPU_FREQUENCY \
// (BOARD_XTAL_FREQUENCY * (IMXRT_ARM_PLL_DIV_SELECT / 2)) / IMXRT_ARM_PODF_DIVIDER
@ -214,9 +215,8 @@
#define PIN_USDHC1_D3 (GPIO_USDHC1_DATA3_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B0_05 */
#define PIN_USDHC1_DCLK (GPIO_USDHC1_CLK_1 | IOMUX_USDHC1_CLK_DEFAULT) /* GPIO_SD_B0_01 */
#define PIN_USDHC1_CMD (GPIO_USDHC1_CMD_1 | IOMUX_USDHC1_CMD_DEFAULT) /* GPIO_SD_B0_00 */
//#define PIN_USDHC1_CD (GPIO_USDHC1_CD_2 | IOMUX_USDHC1_CLK_DEFAULT)
#define PIN_USDHC1_CD_GPIO (IOMUX_VSD_DEFAULT | GPIO_PORT2 | GPIO_PIN28) /* GPIO_B1_12 */
#define PIN_USDHC1_CD (GPIO_USDHC1_CD_2 | IOMUX_USDHC1_CLK_DEFAULT) /* GPIO_B1_12 */
/* 386 KHz for initial inquiry stuff */

9
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/readme.md
View File

@ -137,8 +137,9 @@ source build.sh
执行完毕会自动进入./Ubiquitous/Nuttx_Fusion_XiUOS/nuttx下，继续执行
sudo ./tools/configure.sh xidatong:nsh
sudo make menuconfig
./tools/configure.sh xidatong:nsh
make menuconfig
视情况而定，如果需要前面加sudo
```
2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
@ -152,9 +153,9 @@ sudo make menuconfig
3.继续执行以下命令，进行编译
```shell
sudo make
make
或
sudo make -j8
make -j8
```
make时加上V=1参数可以看到较为详细的编译信息，但是编译过程会比较慢。

12
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/Makefile
View File

@ -66,4 +66,16 @@ ifeq ($(CONFIG_XIDATONG_SDRAM),y)
CSRCS += imxrt_sdram_ini_dcd.c
endif
ifeq ($(CONFIG_USBHOST),y)
CSRCS += imxrt_usbhost.c
endif
ifeq ($(CONFIG_IMXRT_USDHC),y)
CSRCS += imxrt_mmcsd.c
endif
ifeq ($(CONFIG_XIDATONG_SDIO_AUTOMOUNT),y)
CSRCS += imxrt_mmcsd_automount.c
endif
include $(TOPDIR)/boards/Board.mk

55
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_bringup.c
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@ -43,8 +43,8 @@
#include <imxrt_lpi2c.h>
#include <imxrt_lpspi.h>
#ifdef CONFIG_IMXRT_USDHC
# include "imxrt_usdhc.h"
#ifdef CONFIG_USBMONITOR
# include <nuttx/usb/usbmonitor.h>
#endif
#include "xidatong.h"
@ -90,38 +90,6 @@ static void imxrt_i2c_register(int bus)
}
#endif
#ifdef CONFIG_IMXRT_USDHC
static int nsh_sdmmc_initialize(void)
{
struct sdio_dev_s *sdmmc;
int ret = 0;
/* Get an instance of the SDIO interface */
sdmmc = imxrt_usdhc_initialize(0);
if (!sdmmc)
{
syslog(LOG_ERR, "ERROR: Failed to initialize SD/MMC\n");
}
else
{
/* Bind the SDIO interface to the MMC/SD driver */
ret = mmcsd_slotinitialize(0, sdmmc);
if (ret != OK)
{
syslog(LOG_ERR,
"ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n",
ret);
}
}
return OK;
}
#else
# define nsh_sdmmc_initialize() (OK)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -175,6 +143,25 @@ int imxrt_bringup(void)
}
#endif
#if defined(CONFIG_IMXRT_USBOTG) || defined(CONFIG_USBHOST)
ret = imxrt_usbhost_initialize();
if (ret != OK)
{
syslog(LOG_ERR, "ERROR: Failed to start USB host services: %d\n", ret);
return ret;
}
#endif
#ifdef CONFIG_USBMONITOR
/* Start the USB Monitor */
ret = usbmonitor_start();
if (ret != OK)
{
syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret);
}
#endif
#ifdef CONFIG_DEV_GPIO
ret = imxrt_gpio_initialize();
if (ret < 0)

10
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_gpio.c
View File

@ -110,10 +110,8 @@ static const struct gpio_operations_s gpout_ops =
static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] =
{
GPIO_GOUT1,
GPIO_GOUT2,
GPIO_GOUT3,
GPIO_GOUT4,
GPIO_E220_M0,
GPIO_E220_M1,
};
static struct imxrtgpio_dev_s g_gpout[BOARD_NGPIOOUT];
@ -177,10 +175,11 @@ static int gpout_write(FAR struct gpio_dev_s *dev, bool value)
int imxrt_gpio_initialize(void)
{
int pincount = 0;
int pincount;
int i;
#if BOARD_NGPIOIN > 0
pincount = 0;
for (i = 0; i < BOARD_NGPIOIN; i++)
{
/* Setup and register the GPIO pin */
@ -200,6 +199,7 @@ int imxrt_gpio_initialize(void)
#endif
#if BOARD_NGPIOOUT > 0
pincount = 0;
for (i = 0; i < BOARD_NGPIOOUT; i++)
{
/* Setup and register the GPIO pin */

79
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_mmcsd.c Normal file
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@ -0,0 +1,79 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file imxrt_sdhc_automount.c
* @brief imxrt board sd card automount
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.04.12
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdio.h>
#include <debug.h>
#include <errno.h>
#include <debug.h>
#include "xidatong.h"
#ifdef CONFIG_IMXRT_USDHC
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: nsh_sdmmc_initialize
*
* Description:
* Initialize the SDHC SD card slot
*
****************************************************************************/
int nsh_sdmmc_initialize(void)
{
struct sdio_dev_s *sdmmc;
int ret = 0;
/* Get an instance of the SDIO interface */
sdmmc = imxrt_usdhc_initialize(0);
if (!sdmmc)
{
syslog(LOG_ERR, "ERROR: Failed to initialize SD/MMC\n");
return -ENODEV;
}
/* Bind the SDIO interface to the MMC/SD driver */
ret = mmcsd_slotinitialize(0, sdmmc);
if (ret != OK)
{
syslog(LOG_ERR, "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
return ret;
}
#ifdef CONFIG_XIDATONG_SDIO_AUTOMOUNT
imxrt_automount_initialize();
imxrt_usdhc_set_sdio_card_isr(sdmmc, imxrt_sdhc_automount_event, NULL);
#else
imxrt_usdhc_set_sdio_card_isr(sdmmc, NULL, NULL);
#endif
return OK;
}
#endif

330
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_mmcsd_automount.c Normal file
View File

@ -0,0 +1,330 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file imxrt_sdhc_automount.c
* @brief imxrt board sd card automount
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.04.07
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_FS_AUTOMOUNTER_DEBUG) && !defined(CONFIG_DEBUG_FS)
# define CONFIG_DEBUG_FS 1
#endif
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/fs/automount.h>
#include "hardware/imxrt_pinmux.h"
#include "xidatong.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef NULL
# define NULL (FAR void *)0
#endif
#ifndef OK
# define OK 0
#endif
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure represents the changeable state of the automounter */
struct imxrt_automount_state_s
{
volatile automount_handler_t handler; /* Upper half handler */
FAR void *arg; /* Handler argument */
bool enable; /* Fake interrupt enable */
bool pending; /* Set if there an event while disabled */
};
/* This structure represents the static configuration of an automounter */
struct imxrt_automount_config_s
{
/* This must be first thing in structure so that we can simply cast from
* struct automount_lower_s to struct imxrt_automount_config_s
*/
struct automount_lower_s lower; /* Publicly visible part */
FAR struct imxrt_automount_state_s *state; /* Changeable state */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int imxrt_sdhc_attach(FAR const struct automount_lower_s *lower,
automount_handler_t isr, FAR void *arg);
static void imxrt_sdhc_enable(FAR const struct automount_lower_s *lower,
bool enable);
static bool imxrt_sdhc_inserted(FAR const struct automount_lower_s *lower);
/****************************************************************************
* Private Data
****************************************************************************/
static struct imxrt_automount_state_s g_sdhc_state;
static const struct imxrt_automount_config_s g_sdhc_config =
{
.lower =
{
.fstype = CONFIG_XIDATONG_SDIO_AUTOMOUNT_FSTYPE,
.blockdev = CONFIG_XIDATONG_SDIO_AUTOMOUNT_BLKDEV,
.mountpoint = CONFIG_XIDATONG_SDIO_AUTOMOUNT_MOUNTPOINT,
.ddelay = MSEC2TICK(CONFIG_XIDATONG_SDIO_AUTOMOUNT_DDELAY),
.udelay = MSEC2TICK(CONFIG_XIDATONG_SDIO_AUTOMOUNT_UDELAY),
.attach = imxrt_sdhc_attach,
.enable = imxrt_sdhc_enable,
.inserted = imxrt_sdhc_inserted
},
.state = &g_sdhc_state
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_sdhc_attach
*
* Description:
* Attach a new SDHC event handler
*
* Input Parameters:
* lower - An instance of the auto-mounter lower half state structure
* isr - The new event handler to be attach
* arg - Client data to be provided when the event handler is invoked.
*
* Returned Value:
* Always returns OK
*
****************************************************************************/
static int imxrt_sdhc_attach(FAR const struct automount_lower_s *lower,
automount_handler_t isr, FAR void *arg)
{
FAR const struct imxrt_automount_config_s *config;
FAR struct imxrt_automount_state_s *state;
/* Recover references to our structure */
config = (FAR struct imxrt_automount_config_s *)lower;
DEBUGASSERT(config != NULL && config->state != NULL);
state = config->state;
/* Save the new handler info (clearing the handler first to eliminate race
* conditions).
*/
state->handler = NULL;
state->pending = false;
state->arg = arg;
state->handler = isr;
return OK;
}
/****************************************************************************
* Name: imxrt_sdhc_enable
*
* Description:
* Enable card insertion/removal event detection
*
* Input Parameters:
* lower - An instance of the auto-mounter lower half state structure
* enable - True: enable event detection; False: disable
*
* Returned Value:
* None
*
****************************************************************************/
static void imxrt_sdhc_enable(FAR const struct automount_lower_s *lower,
bool enable)
{
FAR const struct imxrt_automount_config_s *config;
FAR struct imxrt_automount_state_s *state;
irqstate_t flags;
/* Recover references to our structure */
config = (FAR struct imxrt_automount_config_s *)lower;
DEBUGASSERT(config != NULL && config->state != NULL);
state = config->state;
/* Save the fake enable setting */
flags = enter_critical_section();
state->enable = enable;
/* Did an interrupt occur while interrupts were disabled? */
if (enable && state->pending)
{
/* Yes.. perform the fake interrupt if the interrutp is attached */
if (state->handler)
{
uint8_t inserted = imxrt_gpio_read(PIN_USDHC1_CD);
if (0 == inserted)
{
state->handler(&config->lower, state->arg, true);
}
else
{
state->handler(&config->lower, state->arg, false);
}
}
state->pending = false;
}
leave_critical_section(flags);
}
/****************************************************************************
* Name: imxrt_sdhc_inserted
*
* Description:
* Check if a card is inserted into the slot.
*
* Input Parameters:
* lower - An instance of the auto-mounter lower half state structure
*
* Returned Value:
* True if the card is inserted; False otherwise
*
****************************************************************************/
static bool imxrt_sdhc_inserted(FAR const struct automount_lower_s *lower)
{
uint8_t inserted = imxrt_gpio_read(PIN_USDHC1_CD);
if (0 == inserted)
{
return true;
}
return false;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_sdhc_automount_event
*
* Description:
* The SDHC card detection logic has detected an insertion or removal
* event.
* It has already scheduled the MMC/SD block driver operations.
* Now we need to schedule the auto-mount event which will occur with a
* substantial delay to make sure that everything has settle down.
*
* Input Parameters:
* slotno - Identifies the SDHC0 slot: SDHC0_SLOTNO or SDHC1_SLOTNO.
* There is a terminology problem here: Each SDHC supports two slots,
* slot A and slot B. Only slot A is used.
* So this is not a really a slot, but an HSCMI peripheral number.
* inserted - True if the card is inserted in the slot. False otherwise.
*
* Returned Value:
* None
*
* Assumptions:
* Interrupts are disabled.
*
****************************************************************************/
int imxrt_sdhc_automount_event(void *arg)
{
FAR const struct imxrt_automount_config_s *config = &g_sdhc_config;
FAR struct imxrt_automount_state_s *state = &g_sdhc_state;
/* Is the auto-mounter interrupt attached? */
if (state->handler)
{
/* Yes.. Have we been asked to hold off interrupts? */
if (!state->enable)
{
/* Yes.. just remember that there is a pending interrupt. We will
* deliver the interrupt when interrupts are "re-enabled."
*/
state->pending = true;
}
else
{
/* No.. forward the event to the handler */
uint8_t inserted = imxrt_gpio_read(PIN_USDHC1_CD);
if (0 == inserted)
{
state->handler(&config->lower, state->arg, true);
}
else
{
state->handler(&config->lower, state->arg, false);
}
}
}
return 0;
}
/****************************************************************************
* Name: imxrt_automount_initialize
*
* Description:
* Configure auto-mounters for each enable and so configured SDHC
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void imxrt_automount_initialize(void)
{
FAR void *handle;
finfo("Initializing automounter(s)\n");
/* Initialize the SDHC0 auto-mounter */
handle = automount_initialize(&g_sdhc_config.lower);
if (!handle)
{
ferr("ERROR: Failed to initialize auto-mounter for SDHC0\n");
}
}

468
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_usbhost.c Normal file
View File

@ -0,0 +1,468 @@
/****************************************************************************
* boards/arm/imxrt/imxrt1020-evk/src/imxrt_usbhost.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <sched.h>
#include <errno.h>
#include <assert.h>
#include <debug.h>
#include <sys/mount.h>
#include <nuttx/fs/fs.h>
#include <nuttx/irq.h>
#include <nuttx/kthread.h>
#include <nuttx/usb/usbdev.h>
#include <nuttx/usb/usbhost.h>
#include <nuttx/usb/usbdev_trace.h>
#include <nuttx/usb/ehci.h>
#include <nuttx/wdog.h>
#include <imxrt_ehci.h>
#include "hardware/imxrt_pinmux.h"
#include "hardware/imxrt_usbotg.h"
#include "imxrt_periphclks.h"
#include "xidatong.h"
#include <arch/board/board.h> /* Must always be included last */
#if defined(CONFIG_IMXRT_USBOTG) || defined(CONFIG_USBHOST)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_USBHOST_DEFPRIO
# define CONFIG_USBHOST_DEFPRIO 50
#endif
#ifndef CONFIG_USBHOST_STACKSIZE
# ifdef CONFIG_USBHOST_HUB
# define CONFIG_USBHOST_STACKSIZE 1536
# else
# define CONFIG_USBHOST_STACKSIZE 1024
# endif
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/* Retained device driver handle */
static struct usbhost_connection_s *g_ehciconn;
#ifdef CONFIG_XIDATONG_USB_AUTOMOUNT
/* Unmount retry timer */
static struct wdog_s g_umount_tmr[CONFIG_XIDATONG_USB_AUTOMOUNT_NUM_BLKDEV];
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: ehci_waiter
*
* Description:
* Wait for USB devices to be connected to the EHCI root hub.
*
****************************************************************************/
static int ehci_waiter(int argc, char *argv[])
{
FAR struct usbhost_hubport_s *hport;
uinfo("ehci_waiter: Running\n");
for (; ; )
{
/* Wait for the device to change state */
DEBUGVERIFY(CONN_WAIT(g_ehciconn, &hport));
syslog(LOG_INFO, "ehci_waiter: %s\n",
hport->connected ? "connected" : "disconnected");
/* Did we just become connected? */
if (hport->connected)
{
/* Yes.. enumerate the newly connected device */
CONN_ENUMERATE(g_ehciconn, hport);
}
}
/* Keep the compiler from complaining */
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
#ifdef CONFIG_XIDATONG_USB_AUTOMOUNT
/****************************************************************************
* Name: usb_msc_connect
*
* Description:
* Mount the USB mass storage device
*
****************************************************************************/
static void usb_msc_connect(FAR void *arg)
{
int index = (int)arg;
char sdchar = 'a' + index;
int ret;
char blkdev[32];
char mntpnt[32];
DEBUGASSERT(index >= 0 &&
index < CONFIG_XIDATONG_USB_AUTOMOUNT_NUM_BLKDEV);
wd_cancel(&g_umount_tmr[index]);
/* Resetup the event. */
usbhost_msc_notifier_setup(usb_msc_connect, WORK_USB_MSC_CONNECT,
sdchar, arg);
snprintf(blkdev, sizeof(blkdev), "%s%c",
CONFIG_XIDATONG_USB_AUTOMOUNT_BLKDEV, sdchar);
snprintf(mntpnt, sizeof(mntpnt), "%s%c",
CONFIG_XIDATONG_USB_AUTOMOUNT_MOUNTPOINT, sdchar);
/* Mount */
ret = nx_mount((FAR const char *)blkdev, (FAR const char *)mntpnt,
CONFIG_XIDATONG_USB_AUTOMOUNT_FSTYPE, 0, NULL);
if (ret < 0)
{
ferr("ERROR: Mount failed: %d\n", ret);
}
}
/****************************************************************************
* Name: unmount_retry_timeout
*
* Description:
* A previous unmount failed because the volume was busy... busy meaning
* the volume could not be unmounted because there are open references
* the files or directories in the volume. When this failure occurred,
* the unmount logic setup a delay and this function is called as a result
* of that delay timeout.
*
* This function will attempt the unmount again.
*
* Input Parameters:
* Standard wdog timeout parameters
*
* Returned Value:
* None
*
****************************************************************************/
static void unmount_retry_timeout(wdparm_t arg)
{
int index = arg;
char sdchar = 'a' + index;
finfo("Timeout!\n");
DEBUGASSERT(index >= 0 &&
index < CONFIG_XIDATONG_USB_AUTOMOUNT_NUM_BLKDEV);
/* Resend the notification. */
usbhost_msc_notifier_signal(WORK_USB_MSC_DISCONNECT, sdchar);
}
/****************************************************************************
* Name: usb_msc_disconnect
*
* Description:
* Unmount the USB mass storage device
*
****************************************************************************/
static void usb_msc_disconnect(FAR void *arg)
{
int index = (int)arg;
char sdchar = 'a' + index;
int ret;
char mntpnt[32];
DEBUGASSERT(index >= 0 &&
index < CONFIG_XIDATONG_USB_AUTOMOUNT_NUM_BLKDEV);
wd_cancel(&g_umount_tmr[index]);
/* Resetup the event. */
usbhost_msc_notifier_setup(usb_msc_disconnect, WORK_USB_MSC_DISCONNECT,
sdchar, arg);
snprintf(mntpnt, sizeof(mntpnt), "%s%c",
CONFIG_XIDATONG_USB_AUTOMOUNT_MOUNTPOINT, sdchar);
/* Unmount */
ret = nx_umount2((FAR const char *)mntpnt, MNT_FORCE);
if (ret < 0)
{
/* We expect the error to be EBUSY meaning that the volume could
* not be unmounted because there are currently reference via open
* files or directories.
*/
if (ret == -EBUSY)
{
finfo("WARNING: Volume is busy, try again later\n");
/* Start a timer to retry the umount2 after a delay */
ret = wd_start(&g_umount_tmr[index],
MSEC2TICK(CONFIG_XIDATONG_USB_AUTOMOUNT_UDELAY),
unmount_retry_timeout, index);
if (ret < 0)
{
ferr("ERROR: wd_start failed: %d\n", ret);
}
}
/* Other errors are fatal */
else
{
ferr("ERROR: Unmount failed!\n");
}
}
}
#endif /* CONFIG_XIDATONG_USB_AUTOMOUNT */
/****************************************************************************
* Name: imxrt_usbhost_initialize
*
* Description:
* Called at application startup time to initialize the USB host
* functionality.
* This function will start a thread that will monitor for device
* connection/disconnection events.
*
****************************************************************************/
int imxrt_usbhost_initialize(void)
{
pid_t pid;
int ret;
#ifdef CONFIG_XIDATONG_USB_AUTOMOUNT
int index;
#endif
imxrt_clockall_usboh3();
/* Make sure we don't accidentally switch on USB bus power */
*((uint32_t *)IMXRT_USBNC_USB_OTG2_CTRL) = USBNC_PWR_POL;
*((uint32_t *)0x400d9030) = (1 << 21);
*((uint32_t *)0x400d9000) = 0;
/* Setup pins, with power initially off */
imxrt_config_gpio(GPIO_USBOTG_ID);
/* First, register all of the class drivers needed to support the drivers
* that we care about
*/
#ifdef CONFIG_USBHOST_HUB
/* Initialize USB hub support */
ret = usbhost_hub_initialize();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: usbhost_hub_initialize failed: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_MSC
/* Register the USB host Mass Storage Class */
#ifdef CONFIG_XIDATONG_USB_AUTOMOUNT
/* Initialize the notifier listener for automount */
for (index = 0; index < CONFIG_XIDATONG_USB_AUTOMOUNT_NUM_BLKDEV; index++)
{
char sdchar = 'a' + index;
usbhost_msc_notifier_setup(usb_msc_connect,
WORK_USB_MSC_CONNECT, sdchar, (FAR void *)(intptr_t)index);
usbhost_msc_notifier_setup(usb_msc_disconnect,
WORK_USB_MSC_DISCONNECT, sdchar, (FAR void *)(intptr_t)index);
}
#endif
ret = usbhost_msc_initialize();
if (ret != OK)
{
syslog(LOG_ERR,
"ERROR: Failed to register the mass storage class: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_CDCACM
/* Register the CDC/ACM serial class */
ret = usbhost_cdcacm_initialize();
if (ret != OK)
{
uerr("ERROR: Failed to register the CDC/ACM serial class\n");
}
#endif
#ifdef CONFIG_USBHOST_HIDKBD
/* Register the USB host HID keyboard class driver */
ret = usbhost_kbdinit();
if (ret != OK)
{
uerr("ERROR: Failed to register the KBD class\n");
}
#endif
/* Then get an instance of the USB EHCI interface. */
g_ehciconn = imxrt_ehci_initialize(0);
if (!g_ehciconn)
{
uerr("ERROR: imxrt_ehci_initialize failed\n");
return -ENODEV;
}
/* Start a thread to handle device connection. */
pid = kthread_create("EHCI Monitor", CONFIG_USBHOST_DEFPRIO,
CONFIG_USBHOST_STACKSIZE,
(main_t)ehci_waiter, (FAR char * const *)NULL);
if (pid < 0)
{
uerr("ERROR: Failed to create ehci_waiter task: %d\n", ret);
return -ENODEV;
}
return OK;
}
/****************************************************************************
* Name: imxrt_usbhost_vbusdrive
*
* Description:
* Enable/disable driving of VBUS 5V output. This function must be
* provided by each platform that implements the OHCI or EHCI host
* interface
*
* Input Parameters:
* rhport - Selects root hub port to be powered host interface.
* Since the IMXRT has only a downstream port, zero is
* the only possible value for this parameter.
* enable - true: enable VBUS power; false: disable VBUS power
*
* Returned Value:
* None
*
****************************************************************************/
#define HCOR ((volatile struct ehci_hcor_s *)IMXRT_USBOTG_HCOR_BASE)
void imxrt_usbhost_vbusdrive(int rhport, bool enable)
{
uint32_t regval;
uinfo("RHPort%d: enable=%d\n", rhport + 1, enable);
/* The IMXRT has only a single root hub port */
if (rhport == 0)
{
/* Then enable or disable VBUS power */
regval = HCOR->portsc[rhport];
regval &= ~EHCI_PORTSC_PP;
if (enable)
{
regval |= EHCI_PORTSC_PP;
}
HCOR->portsc[rhport] = regval;
}
}
/****************************************************************************
* Name: imxrt_setup_overcurrent
*
* Description:
* Setup to receive an interrupt-level callback if an overcurrent condition
* is detected.
*
* Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument that will accompany the interrupt
*
* Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
****************************************************************************/
#if 0 /* Not ready yet */
int imxrt_setup_overcurrent(xcpt_t handler, void *arg)
{
irqstate_t flags;
/* Disable interrupts until we are done. This guarantees that the
* following operations are atomic.
*/
flags = enter_critical_section();
/* Configure the interrupt */
#warning Missing logic
leave_critical_section(flags);
return OK;
}
#endif /* 0 */
#endif /* CONFIG_IMXRT_USBOTG || CONFIG_USBHOST */

39
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/xidatong.h
View File

@ -41,9 +41,13 @@
#include <arch/irq.h>
#include <nuttx/irq.h>
#include <nuttx/sdio.h>
#include <nuttx/mmcsd.h>
#include "imxrt_gpio.h"
#include "imxrt_iomuxc.h"
#include "imxrt_usdhc.h"
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
@ -63,21 +67,15 @@
/* Test Pins ****************************************************************/
#define BOARD_NGPIOIN 0 /* Amount of GPIO Input pins */
#define BOARD_NGPIOOUT 4 /* Amount of GPIO Output pins */
#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */
#define BOARD_NGPIOINT 0 /* Amount of GPIO Input w/ Interruption pins */
#define GPIO_GOUT1 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \
GPIO_PORT1 | GPIO_PIN19)
#define GPIO_GOUT2 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \
GPIO_PIN18 | GPIO_PORT1)
#define GPIO_GOUT3 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \
GPIO_PIN10 | GPIO_PORT1)
#define GPIO_GOUT4 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \
#define GPIO_E220_M0 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \
GPIO_PIN9 | GPIO_PORT1)
#define GPIO_E220_M1 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \
GPIO_PIN11 | GPIO_PORT1)
/* Backlight */
#define GPIO_LCD_BL (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT2 | \
@ -119,6 +117,10 @@
#define GPIO_MMCSD_EN (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \
GPIO_PORT3 | GPIO_PIN2 | IOMUX_MMCSD_EN)
/* USB OTG ID Pin： GPIO_AD_B1_01 */
#define GPIO_USBOTG_ID (GPIO_USB_OTG1_ID_2 | IOMUX_USBOTG_ID_DEFAULT) /* GPIO_AD_B1_01 */
/****************************************************************************
* Public Types
****************************************************************************/
@ -198,5 +200,20 @@ void imxrt_autoled_initialize(void);
int imxrt_gpio_initialize(void);
#endif
#if defined(CONFIG_IMXRT_USBOTG) || defined(CONFIG_USBHOST)
int imxrt_usbhost_initialize(void);
#endif
#ifdef CONFIG_IMXRT_USDHC
int nsh_sdmmc_initialize(void);
#else
# define nsh_sdmmc_initialize() (OK)
#endif
#if defined(CONFIG_IMXRT_USDHC) && defined(CONFIG_XIDATONG_SDIO_AUTOMOUNT)
int imxrt_sdhc_automount_event(void *arg);
void imxrt_automount_initialize(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM_IMXRT_XIDATONG_SRC_XIDATONG_H */

2
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/Kconfig
View File

@ -652,7 +652,7 @@ config NSH_DISABLE_RECVZIGBEE
default n
config NSH_DISABLE_ADAPTER_LORATEST
bool "Disable sx128 AdapterLoraTest."
bool "Disable sx1278 AdapterLoraTest."
default n
config NSH_DISABLE_K210_FFT

1
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/build.sh
View File

@ -11,7 +11,6 @@ git submodule update Ubiquitous/Nuttx_Fusion_XiUOS/apps
git submodule update Ubiquitous/Nuttx_Fusion_XiUOS/nuttx
cd $current
chmod -R +x $top
find $top -name Kconfig -exec dos2unix -q {} \;
cp -rf $current/nuttx $nuttx

739
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/hardware/imxrt_usbotg.h Normal file
View File

@ -0,0 +1,739 @@
/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_usbotg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USBOTG_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USBOTG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IMXRT_EHCI_NRHPORT 1 /* There is only a single root hub port */
/* USBOTG register offsets (with respect to IMXRT_USB_BASE) *****************/
/* 0x000 - 0x0ff: Reserved */
/* Device/host capability registers */
#define IMXRT_USBOTG_HCCR_OFFSET 0x100 /* Offset to EHCI Host Controller Capabiliy registers */
#define IMXRT_USBOTG_CAPLENGTH_OFFSET 0x100 /* Capability register length (8-bit) */
#define IMXRT_USBHOST_HCIVERSION_OFFSET 0x102 /* Host interface version number (16-bit) */
#define IMXRT_USBHOST_HCSPARAMS_OFFSET 0x104 /* Host controller structural parameters */
#define IMXRT_USBHOST_HCCPARAMS_OFFSET 0x108 /* Host controller capability parameters */
#define IMXRT_USBDEV_DCIVERSION_OFFSET 0x120 /* Device interface version number */
#define IMXRT_USBDEV_DCCPARAMS_OFFSET 0x124 /* Device controller capability parameters */
/* Device/host/OTG operational registers */
#define IMXRT_USBOTG_HCOR_OFFSET 0x140 /* Offset to EHCI Host Controller Operational Registers */
#define IMXRT_USBOTG_USBCMD_OFFSET 0x140 /* USB command (both) */
#define IMXRT_USBOTG_USBSTS_OFFSET 0x144 /* USB status (both) */
#define IMXRT_USBOTG_USBINTR_OFFSET 0x148 /* USB interrupt enable (both) */
#define IMXRT_USBOTG_FRINDEX_OFFSET 0x14c /* USB frame index (both) */
/* EHCI 4G Segment Selector (not supported) */
#define IMXRT_USBOTG_PERIODICLIST_OFFSET 0x154 /* Frame list base address (host) */
#define IMXRT_USBOTG_DEVICEADDR_OFFSET 0x154 /* USB device address (device) */
#define IMXRT_USBOTG_ASYNCLISTADDR_OFFSET 0x158 /* Next asynchronous list address (host) */
#define IMXRT_USBOTG_ENDPOINTLIST_OFFSET 0x158 /* Address of endpoint list in memory (device) */
#define IMXRT_USBOTG_TTCTRL_OFFSET 0x15c /* Asynchronous buffer status for embedded TT (host) */
#define IMXRT_USBOTG_BURSTSIZE_OFFSET 0x160 /* Programmable burst size (both) */
#define IMXRT_USBOTG_TXFILLTUNING_OFFSET 0x164 /* Host transmit pre-buffer packet tuning (host) */
#define IMXRT_USBOTG_BINTERVAL_OFFSET 0x174 /* Length of virtual frame (both) */
#define IMXRT_USBOTG_ENDPTNAK_OFFSET 0x178 /* Endpoint NAK (device) */
#define IMXRT_USBOTG_ENDPTNAKEN_OFFSET 0x17c /* Endpoint NAK Enable (device) */
#define IMXRT_USBOTG_CONFIGFLAG_OFFSET 0x180 /* Configured flag register (not used in lpc313x) */
#define IMXRT_USBOTG_PORTSC1_OFFSET 0x184 /* Port status/control 1 (both) */
#define IMXRT_USBOTG_OTGSC_OFFSET 0x1a4 /* OTG status and control (otg) */
#define IMXRT_USBOTG_USBMODE_OFFSET 0x1a8 /* USB device mode (both) */
#define IMXRT_USBDEV_USBCMD_OFFSET 0x140 /* USB command (both) */
#define IMXRT_USBDEV_USBSTS_OFFSET 0x144 /* USB status (both) */
#define IMXRT_USBDEV_USBINTR_OFFSET 0x148 /* USB interrupt enable (both) */
#define IMXRT_USBDEV_FRINDEX_OFFSET 0x14c /* USB frame index (both) */
#define IMXRT_USBDEV_DEVICEADDR_OFFSET 0x154 /* USB device address (device) */
#define IMXRT_USBDEV_ENDPOINTLIST_OFFSET 0x158 /* Address of endpoint list in memory (device) */
#define IMXRT_USBDEV_BURSTSIZE_OFFSET 0x160 /* Programmable burst size (both) */
#define IMXRT_USBDEV_BINTERVAL_OFFSET 0x174 /* Length of virtual frame (both) */
#define IMXRT_USBDEV_ENDPTNAK_OFFSET 0x178 /* Endpoint NAK (device) */
#define IMXRT_USBDEV_ENDPTNAKEN_OFFSET 0x17c /* Endpoint NAK Enable (device) */
#define IMXRT_USBDEV_PORTSC1_OFFSET 0x184 /* Port status/control 1 (both) */
#define IMXRT_USBDEV_USBMODE_OFFSET 0x1a8 /* USB device mode (both) */
#define IMXRT_USBHOST_USBCMD_OFFSET 0x140 /* USB command (both) */
#define IMXRT_USBHOST_USBSTS_OFFSET 0x144 /* USB status (both) */
#define IMXRT_USBHOST_USBINTR_OFFSET 0x148 /* USB interrupt enable (both) */
#define IMXRT_USBHOST_FRINDEX_OFFSET 0x14c /* USB frame index (both) */
#define IMXRT_USBHOST_PERIODICLIST_OFFSET 0x154 /* Frame list base address (host) */
#define IMXRT_USBHOST_ASYNCLISTADDR_OFFSET 0x158 /* Next asynchronous list address (host) */
#define IMXRT_USBHOST_TTCTRL_OFFSET 0x15c /* Asynchronous buffer status for embedded TT (host) */
#define IMXRT_USBHOST_BURSTSIZE_OFFSET 0x160 /* Programmable burst size (both) */
#define IMXRT_USBHOST_TXFILLTUNING_OFFSET 0x164 /* Host transmit pre-buffer packet tuning (host) */
#define IMXRT_USBHOST_BINTERVAL_OFFSET 0x174 /* Length of virtual frame (both) */
#define IMXRT_USBHOST_PORTSC1_OFFSET 0x184 /* Port status/control 1 (both) */
#define IMXRT_USBHOST_USBMODE_OFFSET 0x1a8 /* USB device mode (both) */
/* Device endpoint registers */
#define IMXRT_USBDEV_ENDPTSETUPSTAT_OFFSET 0x1ac /* Endpoint setup status */
#define IMXRT_USBDEV_ENDPTPRIME_OFFSET 0x1b0 /* Endpoint initialization */
#define IMXRT_USBDEV_ENDPTFLUSH_OFFSET 0x1b4 /* Endpoint de-initialization */
#define IMXRT_USBDEV_ENDPTSTATUS_OFFSET 0x1b8 /* Endpoint status */
#define IMXRT_USBDEV_ENDPTCOMPLETE_OFFSET 0x1bc /* Endpoint complete */
#define IMXRT_USBDEV_ENDPTCTRL_OFFSET(n) (IMXRT_USBDEV_ENDPTCTRL0_OFFSET + ((n) * 4))
#define IMXRT_USBDEV_ENDPTCTRL0_OFFSET 0x1c0 /* Endpoint control 0 */
#define IMXRT_USBDEV_ENDPTCTRL1_OFFSET 0x1c4 /* Endpoint control 1 */
#define IMXRT_USBDEV_ENDPTCTRL2_OFFSET 0x1c8 /* Endpoint control 2 */
#define IMXRT_USBDEV_ENDPTCTRL3_OFFSET 0x1cc /* Endpoint control 3 */
#define IMXRT_USBDEV_ENDPTCTRL4_OFFSET 0x1d0 /* Endpoint control 4 */
#define IMXRT_USBDEV_ENDPTCTRL5_OFFSET 0x1d4 /* Endpoint control 5 */
#define IMXRT_USBDEV_ENDPTCTRL6_OFFSET 0x1d8 /* Endpoint control 6 */
#define IMXRT_USBDEV_ENDPTCTRL7_OFFSET 0x1dc /* Endpoint control 7 */
/* USB Non-core memory map & register definition */
#define IMXRT_USBNC_USB_OTG1_CTRL_OFFSET 0x0800 /* OTG1 Control Register */
#define IMXRT_USBNC_USB_OTG2_CTRL_OFFSET 0x0800 /* OTG2 Control Register */
#define IMXRT_USBNC_USB_OTG1_PHY_CTRL_0_OFFSET 0x0818 /* OTG1 Phy Control Register */
#define IMXRT_USBNC_USB_OTG2_PHY_CTRL_0_OFFSET 0x0818 /* OTG2 Phy Control Register */
/* USBOTG register (virtual) addresses **************************************/
/* Device/host capability registers */
#define IMXRT_USBOTG_HCCR_BASE (IMXRT_USB_BASE + IMXRT_USBOTG_HCCR_OFFSET)
#define IMXRT_USBOTG_CAPLENGTH (IMXRT_USB_BASE + IMXRT_USBOTG_CAPLENGTH_OFFSET)
#define IMXRT_USBHOST_HCIVERSION (IMXRT_USB_BASE + IMXRT_USBHOST_HCIVERSION_OFFSET)
#define IMXRT_USBHOST_HCSPARAMS (IMXRT_USB_BASE + IMXRT_USBHOST_HCSPARAMS_OFFSET)
#define IMXRT_USBHOST_HCCPARAMS (IMXRT_USB_BASE + IMXRT_USBHOST_HCCPARAMS_OFFSET)
#define IMXRT_USBDEV_DCIVERSION (IMXRT_USB_BASE + IMXRT_USBDEV_DCIVERSION_OFFSET)
#define IMXRT_USBDEV_DCCPARAMS (IMXRT_USB_BASE + IMXRT_USBDEV_DCCPARAMS_OFFSET)
/* Device/host operational registers */
#define IMXRT_USBOTG_HCOR_BASE (IMXRT_USB_BASE + IMXRT_USBOTG_HCOR_OFFSET)
#define IMXRT_USBOTG_USBCMD (IMXRT_USB_BASE + IMXRT_USBOTG_USBCMD_OFFSET)
#define IMXRT_USBOTG_USBSTS (IMXRT_USB_BASE + IMXRT_USBOTG_USBSTS_OFFSET)
#define IMXRT_USBOTG_USBINTR (IMXRT_USB_BASE + IMXRT_USBOTG_USBINTR_OFFSET)
#define IMXRT_USBOTG_FRINDEX (IMXRT_USB_BASE + IMXRT_USBOTG_FRINDEX_OFFSET)
#define IMXRT_USBOTG_PERIODICLIST (IMXRT_USB_BASE + IMXRT_USBOTG_PERIODICLIST_OFFSET)
#define IMXRT_USBOTG_DEVICEADDR (IMXRT_USB_BASE + IMXRT_USBOTG_DEVICEADDR_OFFSET)
#define IMXRT_USBOTG_ASYNCLISTADDR (IMXRT_USB_BASE + IMXRT_USBOTG_ASYNCLISTADDR_OFFSET)
#define IMXRT_USBOTG_ENDPOINTLIST (IMXRT_USB_BASE + IMXRT_USBOTG_ENDPOINTLIST_OFFSET)
#define IMXRT_USBOTG_TTCTRL (IMXRT_USB_BASE + IMXRT_USBOTG_TTCTRL_OFFSET)
#define IMXRT_USBOTG_BURSTSIZE (IMXRT_USB_BASE + IMXRT_USBOTG_BURSTSIZE_OFFSET)
#define IMXRT_USBOTG_TXFILLTUNING (IMXRT_USB_BASE + IMXRT_USBOTG_TXFILLTUNING_OFFSET)
#define IMXRT_USBOTG_BINTERVAL (IMXRT_USB_BASE + IMXRT_USBOTG_BINTERVAL_OFFSET)
#define IMXRT_USBOTG_ENDPTNAK (IMXRT_USB_BASE + IMXRT_USBOTG_ENDPTNAK_OFFSET)
#define IMXRT_USBOTG_ENDPTNAKEN (IMXRT_USB_BASE + IMXRT_USBOTG_ENDPTNAKEN_OFFSET)
#define IMXRT_USBOTG_PORTSC1 (IMXRT_USB_BASE + IMXRT_USBOTG_PORTSC1_OFFSET)
#define IMXRT_USBOTG_OTGSC (IMXRT_USB_BASE + IMXRT_USBOTG_OTGSC_OFFSET)
#define IMXRT_USBOTG_USBMODE (IMXRT_USB_BASE + IMXRT_USBOTG_USBMODE_OFFSET)
#define IMXRT_USBDEV_USBCMD (IMXRT_USB_BASE + IMXRT_USBDEV_USBCMD_OFFSET)
#define IMXRT_USBDEV_USBSTS (IMXRT_USB_BASE + IMXRT_USBDEV_USBSTS_OFFSET)
#define IMXRT_USBDEV_USBINTR (IMXRT_USB_BASE + IMXRT_USBDEV_USBINTR_OFFSET)
#define IMXRT_USBDEV_FRINDEX (IMXRT_USB_BASE + IMXRT_USBDEV_FRINDEX_OFFSET)
#define IMXRT_USBDEV_DEVICEADDR (IMXRT_USB_BASE + IMXRT_USBDEV_DEVICEADDR_OFFSET)
#define IMXRT_USBDEV_ENDPOINTLIST (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPOINTLIST_OFFSET)
#define IMXRT_USBDEV_BURSTSIZE (IMXRT_USB_BASE + IMXRT_USBDEV_BURSTSIZE_OFFSET)
#define IMXRT_USBDEV_BINTERVAL (IMXRT_USB_BASE + IMXRT_USBDEV_BINTERVAL_OFFSET)
#define IMXRT_USBDEV_ENDPTNAK (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTNAK_OFFSET)
#define IMXRT_USBDEV_ENDPTNAKEN (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTNAKEN_OFFSET)
#define IMXRT_USBDEV_PORTSC1 (IMXRT_USB_BASE + IMXRT_USBDEV_PORTSC1_OFFSET)
#define IMXRT_USBDEV_USBMODE (IMXRT_USB_BASE + IMXRT_USBDEV_USBMODE_OFFSET)
#define IMXRT_USBHOST_USBCMD (IMXRT_USB_BASE + IMXRT_USBHOST_USBCMD_OFFSET)
#define IMXRT_USBHOST_USBSTS (IMXRT_USB_BASE + IMXRT_USBHOST_USBSTS_OFFSET)
#define IMXRT_USBHOST_USBINTR (IMXRT_USB_BASE + IMXRT_USBHOST_USBINTR_OFFSET)
#define IMXRT_USBHOST_FRINDEX (IMXRT_USB_BASE + IMXRT_USBHOST_FRINDEX_OFFSET)
#define IMXRT_USBHOST_PERIODICLIST (IMXRT_USB_BASE + IMXRT_USBHOST_PERIODICLIST_OFFSET)
#define IMXRT_USBHOST_ASYNCLISTADDR (IMXRT_USB_BASE + IMXRT_USBHOST_ASYNCLISTADDR_OFFSET)
#define IMXRT_USBHOST_TTCTRL (IMXRT_USB_BASE + IMXRT_USBHOST_TTCTRL_OFFSET)
#define IMXRT_USBHOST_BURSTSIZE (IMXRT_USB_BASE + IMXRT_USBHOST_BURSTSIZE_OFFSET)
#define IMXRT_USBHOST_TXFILLTUNING (IMXRT_USB_BASE + IMXRT_USBHOST_TXFILLTUNING_OFFSET)
#define IMXRT_USBHOST_BINTERVAL (IMXRT_USB_BASE + IMXRT_USBHOST_BINTERVAL_OFFSET)
#define IMXRT_USBHOST_PORTSC1 (IMXRT_USB_BASE + IMXRT_USBHOST_PORTSC1_OFFSET)
#define IMXRT_USBHOST_USBMODE (IMXRT_USB_BASE + IMXRT_USBHOST_USBMODE_OFFSET)
/* Device endpoint registers */
#define IMXRT_USBDEV_ENDPTSETUPSTAT (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTSETUPSTAT_OFFSET)
#define IMXRT_USBDEV_ENDPTPRIME (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTPRIME_OFFSET)
#define IMXRT_USBDEV_ENDPTFLUSH (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTFLUSH_OFFSET)
#define IMXRT_USBDEV_ENDPTSTATUS (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTSTATUS_OFFSET)
#define IMXRT_USBDEV_ENDPTCOMPLETE (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCOMPLETE_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL(n) (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL_OFFSET(n))
#define IMXRT_USBDEV_ENDPTCTRL0 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL0_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL1 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL1_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL2 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL2_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL3 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL3_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL4 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL4_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL5 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL5_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL6 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL6_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL7 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL7_OFFSET)
/* Device non-core registers */
#define IMXRT_USBNC_USB_OTG1_CTRL (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG1_CTRL_OFFSET)
#define IMXRT_USBNC_USB_OTG1_PHY_CTRL_0 (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG1_PHY_CTRL_0_OFFSET)
#define IMXRT_USBNC_USB_OTG2_CTRL (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG2_CTRL_OFFSET)
#define IMXRT_USBNC_USB_OTG2_PHY_CTRL_0 (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG2_PHY_CTRL_0_OFFSET)
/* USBOTG register bit definitions ******************************************/
/* Device/host capability registers */
/* CAPLENGTH */
#define USBOTG_CAPLENGTH_SHIFT (0) /* Bits 0-7: Offset from register base to operational regs */
#define USBOTG_CAPLENGTH_MASK (0xff << USBOTG_CAPLENGTH_SHIFT)
/* HCIVERSION */
#define USBHOST_HCIVERSION_SHIFT (0) /* Bits 0-15: BCD encoding of the EHCI revision number */
#define USBHOST_HCIVERSION_MASK (0xffff << USBHOST_HCIVERSION_SHIFT)
/* HCSPARAMS */
#define USBHOST_HCSPARAMS_NTT_SHIFT (24) /* Bits 24-27: Number of Transaction Translators */
#define USBHOST_HCSPARAMS_NTT_MASK (15 << USBHOST_HCSPARAMS_NTT_SHIFT)
#define USBHOST_HCSPARAMS_NPTT_SHIFT (20) /* Bits 20-23: Number of Ports per Transaction Translator */
#define USBHOST_HCSPARAMS_NPTT_MASK (15 << USBHOST_HCSPARAMS_NPTT_SHIFT)
#define USBHOST_HCSPARAMS_PI (1 >> 16) /* Bit 16: Port indicators */
#define USBHOST_HCSPARAMS_NCC_SHIFT (15) /* Bits 12-15: Number of Companion Controller */
#define USBHOST_HCSPARAMS_NCC_MASK (15 << USBHOST_HCSPARAMS_NCC_SHIFT)
#define USBHOST_HCSPARAMS_NPCC_SHIFT (8) /* Bits 8-11: Number of Ports per Companion Controller */
#define USBHOST_HCSPARAMS_NPCC_MASK (15 << USBHOST_HCSPARAMS_NPCC_SHIFT)
#define USBHOST_HCSPARAMS_PPC (1 >> 4) /* Bit 4: Port Power Control */
#define USBHOST_HCSPARAMS_NPORTS_SHIF (0) /* Bits 0-3: Number of downstream ports */
#define USBHOST_HCSPARAMS_NPORTS_MASK (15 << USBHOST_HCSPARAMS_NPORTS_SHIFT)
/* HCCPARAMS */
#define USBHOST_HCCPARAMS_EECP_SHIFT (8) /* Bits 8-15: EHCI Extended Capabilities Pointer */
#define USBHOST_HCCPARAMS_EECP_MASK (255 << USBHOST_HCCPARAMS_EECP_SHIFT)
#define USBHOST_HCCPARAMS_IST_SHIFT (4) /* Bits 4-7: Isochronous Scheduling Threshold */
#define USBHOST_HCCPARAMS_IST_MASK (15 << USBHOST_HCCPARAMS_IST_SHIFT)
#define USBHOST_HCCPARAMS_ASP (1 >> 2) /* Bit 2: Asynchronous Schedule Park Capability */
#define USBHOST_HCCPARAMS_PFL (1 >> 1) /* Bit 1: Programmable Frame List Flag */
#define USBHOST_HCCPARAMS_ADC (1 >> 0) /* Bit 0: 64-bit Addressing Capability */
/* DCIVERSION */
#define USBDEV_DCIVERSION_SHIFT (0) /* Bits 0-15: BCD encoding of the device interface */
#define USBDEV_DCIVERSION_MASK (0xffff << USBDEV_DCIVERSION_SHIFT)
/* DCCPARAMS */
#define USBDEV_DCCPARAMS_HC (1 >> 8) /* Bit 8: Host Capable */
#define USBDEV_DCCPARAMS_DC (1 >> 7) /* Bit 7: Device Capable */
#define USBDEV_DCCPARAMS_DEN_SHIFT (0) /* Bits 0-4: DEN Device Endpoint Number */
#define USBDEV_DCCPARAMS_DEN_MASK (31 << USBDEV_DCCPARAMS_DEN_SHIFT)
/* Device/host operational registers */
/* USB Command register USBCMD -- Device Mode */
#define USBDEV_USBCMD_ITC_SHIFT (16) /* Bits 16-23: Interrupt threshold control */
#define USBDEV_USBCMD_ITC_MASK (255 << USBDEV_USBCMD_ITC_SHIFT)
# define USBDEV_USBCMD_ITCIMME (0 << USBDEV_USBCMD_ITC_SHIFT) /* Immediate (no threshold) */
# define USBDEV_USBCMD_ITC1UF (1 << USBDEV_USBCMD_ITC_SHIFT) /* 1 micro frame */
# define USBDEV_USBCMD_ITC2UF (2 << USBDEV_USBCMD_ITC_SHIFT) /* 2 micro frames */
# define USBDEV_USBCMD_ITC4UF (4 << USBDEV_USBCMD_ITC_SHIFT) /* 4 micro frames */
# define USBDEV_USBCMD_ITC8UF (8 << USBDEV_USBCMD_ITC_SHIFT) /* 8 micro frames */
# define USBDEV_USBCMD_ITC16UF (16 << USBDEV_USBCMD_ITC_SHIFT) /* 16 micro frames */
# define USBDEV_USBCMD_ITC32UF (32 << USBDEV_USBCMD_ITC_SHIFT) /* 32 micro frames */
# define USBDEV_USBCMD_ITC64UF (64 << USBDEV_USBCMD_ITC_SHIFT) /* 64 micro frames */
#define USBDEV_USBCMD_ATDTW (1 << 14) /* Bit 14: Add dTD trip wire */
#define USBDEV_USBCMD_SUTW (1 << 13) /* Bit 13: Setup trip wire */
#define USBDEV_USBCMD_RST (1 << 1) /* Bit 1: 1 Controller reset */
#define USBDEV_USBCMD_RS (1 << 0) /* Bit 0: 0 Run/Stop */
/* USB Command register USBCMD -- Host Mode */
#define USBHOST_USBCMD_ITC_SHIFT (16) /* Bits 16-13: Interrupt threshold control */
#define USBHOST_USBCMD_ITC_MASK (255 << USBHOST_USBCMD_ITC_SHIFT)
# define USBHOST_USBCMD_ITCIMMED (0 << USBHOST_USBCMD_ITC_SHIFT) /* Immediate (no threshold) */
# define USBHOST_USBCMD_ITC1UF (1 << USBHOST_USBCMD_ITC_SHIFT) /* 1 micro frame */
# define USBHOST_USBCMD_ITC2UF (2 << USBHOST_USBCMD_ITC_SHIFT) /* 2 micro frames */
# define USBHOST_USBCMD_ITC4UF (4 << USBHOST_USBCMD_ITC_SHIFT) /* 4 micro frames */
# define USBHOST_USBCMD_ITC8UF (8 << USBHOST_USBCMD_ITC_SHIFT) /* 8 micro frames */
# define USBHOST_USBCMD_ITC16UF (16 << USBHOST_USBCMD_ITC_SHIFT) /* 16 micro frames */
# define USBHOST_USBCMD_ITC32UF (32 << USBHOST_USBCMD_ITC_SHIFT) /* 32 micro frames */
# define USBHOST_USBCMD_ITC64UF (64 << USBHOST_USBCMD_ITC_SHIFT) /* 64 micro frames */
#define USBHOST_USBCMD_FS2 (1 << 15) /* Bit 15: Bit 2 of the Frame List Size bits */
#define USBHOST_USBCMD_ASPE (1 << 11) /* Bit 11: Asynchronous Schedule Park Mode Enable */
#define USBHOST_USBCMD_ASP_SHIFT (8) /* Bits 8-9: Asynchronous schedule park mode */
#define USBHOST_USBCMD_ASP_MASK (3 << USBHOST_USBCMD_ASP_SHIFT)
#define USBHOST_USBCMD_IAA (1 << 6) /* Bit 6: Interrupt next asynchronous schedule */
#define USBHOST_USBCMD_ASE (1 << 5) /* Bit 5: Skips processing asynchronous schedule */
#define USBHOST_USBCMD_PSE (1 << 4) /* Bit 4: Skips processing periodic schedule */
#define USBHOST_USBCMD_FS1 (1 << 3) /* Bit 3: Bit 1 of the Frame List Size bits */
#define USBHOST_USBCMD_FS0 (1 << 2) /* Bit 2: Bit 0 of the Frame List Size bits */
#define USBHOST_USBCMD_RST (1 << 1) /* Bit 1: Controller reset */
#define USBHOST_USBCMD_RS (1 << 0) /* Bit 0: Run/Stop */
/* USB Status register USBSTS -- Device Mode */
#define USBDEV_USBSTS_NAKI (1 << 16) /* Bit 16: NAK interrupt bit */
#define USBDEV_USBSTS_SLI (1 << 8) /* Bit 8: DCSuspend */
#define USBDEV_USBSTS_SRI (1 << 7) /* Bit 7: SOF received */
#define USBDEV_USBSTS_URI (1 << 6) /* Bit 6: USB reset received */
#define USBDEV_USBSTS_PCI (1 << 2) /* Bit 2: Port change detect */
#define USBDEV_USBSTS_UEI (1 << 1) /* Bit 1: USB error interrupt */
#define USBDEV_USBSTS_UI (1 << 0) /* Bit 0: USB interrupt */
/* USB Status register USBSTS -- Host Mode */
#define USBHOST_USBSTS_UPI (1 << 19) /* Bit 19: USB host periodic interrupt */
#define USBHOST_USBSTS_UAI (1 << 18) /* Bit 18: USB host asynchronous interrupt */
#define USBHOST_USBSTS_AS (1 << 15) /* Bit 15: Asynchronous schedule status */
#define USBHOST_USBSTS_PS (1 << 14) /* Bit 14: Periodic schedule status */
#define USBHOST_USBSTS_RCL (1 << 13) /* Bit 13: Reclamation */
#define USBHOST_USBSTS_HCH (1 << 12) /* Bit 12: HCHalted */
#define USBHOST_USBSTS_SRI (1 << 7) /* Bit 7: SOF received */
#define USBHOST_USBSTS_AAI (1 << 5) /* Bit 5: Interrupt on async advance */
#define USBHOST_USBSTS_FRI (1 << 3) /* Bit 3: Frame list roll-over */
#define USBHOST_USBSTS_PCI (1 << 2) /* Bit 2: Port change detect */
#define USBHOST_USBSTS_UEI (1 << 1) /* Bit 1: USB error interrupt */
#define USBHOST_USBSTS_UI (1 << 0) /* Bit 0: USB interrupt */
/* USB interrupt register USBINTR -- Device Mode */
#define USBDEV_USBINTR_NAKE (1 << 16) /* Bit 16: NAK interrupt enable */
#define USBDEV_USBINTR_SLE (1 << 8) /* Bit 8: Sleep enable */
#define USBDEV_USBINTR_SRE (1 << 7) /* Bit 7: SOF received enable */
#define USBDEV_USBINTR_URE (1 << 6) /* Bit 6: USB reset enable */
#define USBDEV_USBINTR_PCE (1 << 2) /* Bit 2: Port change detect enable */
#define USBDEV_USBINTR_UEE (1 << 1) /* Bit 1: USB error interrupt enable */
#define USBDEV_USBINTR_UE (1 << 0) /* Bit 0: USB interrupt enable */
/* USB interrupt register USBINTR (address 0x19000148) -- Host Mode */
#define USBHOST_USBINTR_UPIA (1 << 19) /* Bit 19: USB host periodic interrupt enable */
#define USBHOST_USBINTR_UAIE (1 << 18) /* Bit 18: USB host asynchronous interrupt enable */
#define USBHOST_USBINTR_SRE (1 << 7) /* Bit 7: SOF timer interrupt enable */
#define USBHOST_USBINTR_AAE (1 << 5) /* Bit 5: Interrupt on asynchronous advance enable */
#define USBHOST_USBINTR_FRE (1 << 3) /* Bit 3: Frame list rollover enable */
#define USBHOST_USBINTR_PCE (1 << 2) /* Bit 2: Port change detect enable */
#define USBHOST_USBINTR_UEE (1 << 1) /* Bit 1: USB error interrupt enable */
#define USBHOST_USBINTR_UE (1 << 0) /* Bit 0: USB interrupt enable */
/* Frame index register FRINDEX -- Device Mode */
#define USBDEV_FRINDEX_LFN_SHIFT (3) /* Bits 3-13: Frame number of last frame transmitted */
#define USBDEV_FRINDEX_LFN_MASK (0x7ff << USBDEV_FRINDEX_LFN_SHIFT)
#define USBDEV_FRINDEX_CUFN_SHIFT (0) /* Bits 0-2: Current micro frame number */
#define USBDEV_FRINDEX_CUFN_MASK (7 << USBDEV_FRINDEX_CUFN_SHIFT)
/* Frame index register FRINDEX -- Host Mode */
#define USBHOST_FRINDEX_FLI_SHIFT (3) /* Bits 3-13: Frame list current index */
#define USBHOST_FRINDEX_FLI_MASK(n) (0x7ff << ((n) + USBHOST_FRINDEX_FLI_SHIFT - 1)
#define USBHOST_FRINDEX_CUFN_SHIFT (0) /* Bits 0-2: Current micro frame number */
#define USBHOST_FRINDEX_CUFN_MASK (7 << USBHOST_FRINDEX_CUFN_SHIFT)
/* USB Device Address register DEVICEADDR -- Device Mode */
#define USBDEV_DEVICEADDR_SHIFT (25) /* Bits 25-31: USBADR USB device address */
#define USBDEV_DEVICEADDR_MASK (0x3c << USBDEV_DEVICEADDR_SHIFT)
#define USBDEV_DEVICEADDR_USBADRA (1 << 24) /* Bit 24: Device address advance */
/* USB Periodic List Base register PERIODICLIST -- Host Mode */
#define USBHOST_PERIODICLIST_PERBASE_SHIFT (12) /* Bits 12-31: Base Address (Low) */
#define USBHOST_PERIODICLIST_PERBASE_MASK (0x000fffff << USBHOST_PERIODICLIST_PERBASE_SHIFT)
/* USB Endpoint List Address register ENDPOINTLISTADDR -- Device Mode */
#define USBDEV_ENDPOINTLIST_EPBASE_SHIFT (11) /* Bits 11-31: Endpoint list pointer (low) */
#define USBDEV_ENDPOINTLIST_EPBASE_MASK (0x001fffff << USBDEV_ENDPOINTLIST_EPBASE_SHIFT)
/* USB Asynchronous List Address register ASYNCLISTADDR -- Host Mode */
#define USBHOST_ASYNCLISTADDR_ASYBASE_SHIFT (5) /* Bits 5-31: Link pointer (Low) LPL */
#define USBHOST_ASYNCLISTADDR_ASYBASE_MASK (0x07ffffff << USBHOST_ASYNCLISTADDR_ASYBASE_SHIFT)
/* USB TT Control register TTCTRL (address 0x1900015c) -- Host Mode */
#define USBHOST_TTCTRL_TTHA_SHIFT (24) /* Bits 24-30: Hub address */
#define USBHOST_TTCTRL_TTHA_MASK (0x7f << USBHOST_TTCTRL_TTHA_SHIFT)
/* USB burst size register BURSTSIZE -- Device/Host Mode */
#define USBDEV_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX burst length */
#define USBDEV_BURSTSIZE_TXPBURST_MASK (255 << USBDEV_BURSTSIZE_TXPBURST_SHIFT)
#define USBDEV_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: RXPBURST Programmable RX burst length */
#define USBDEV_BURSTSIZE_RXPBURST_MASK (255 << USBDEV_BURSTSIZE_RXPBURST_SHIFT)
#define USBHOST_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX burst length */
#define USBHOST_BURSTSIZE_TXPBURST_MASK (255 << USBHOST_BURSTSIZE_TXPBURST_SHIFT)
#define USBHOST_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: RXPBURST Programmable RX burst length */
#define USBHOST_BURSTSIZE_RXPBURST_MASK (255 << USBHOST_BURSTSIZE_RXPBURST_SHIFT)
/* USB Transfer buffer Fill Tuning register TXFIFOFILLTUNING -- Host Mode */
#define USBHOST_TXFILLTUNING_FIFOTHRES_SHIFT (16) /* Bits 16-21: Scheduler overhead */
#define USBHOST_TXFILLTUNING_FIFOTHRES_MASK (0x3c << USBHOST_TXFILLTUNING_FIFOTHRES_SHIFT)
#define USBHOST_TXFILLTUNING_SCHEATLTH_SHIFT (8) /* Bits 8-12: Scheduler health counter */
#define USBHOST_TXFILLTUNING_SCHEATLTH_MASK (0x1f << USBHOST_TXFILLTUNING_SCHEATLTH_SHIFT)
#define USBHOST_TXFILLTUNING_SCHOH_SHIFT (0) /* Bits 0-7: FIFO burst threshold */
#define USBHOST_TXFILLTUNING_SCHOH_MASK (0xff << USBHOST_TXFILLTUNING_SCHOH_SHIFT)
/* USB BINTERVAL register BINTERVAL -- Device/Host Mode */
#define USBDEV_BINTERVAL_SHIFT (0) /* Bits 0-3: bInterval value */
#define USBDEV_BINTERVAL_MASK (15 << USBDEV_BINTERVAL_SHIFT)
#define USBHOST_BINTERVAL_SHIFT (0) /* Bits 0-3: bInterval value */
#define USBHOST_BINTERVAL_MASK (15 << USBHOST_BINTERVAL_SHIFT)
/* USB endpoint NAK register ENDPTNAK -- Device Mode */
#define USBDEV_ENDPTNAK_EPTN_SHIFT (16) /* Bits 16-19: Tx endpoint NAK */
#define USBDEV_ENDPTNAK_EPTN_MASK (15 << USBDEV_ENDPTNAK_EPTN_SHIFT)
#define USBDEV_ENDPTNAK_EPRN_SHIFT (0) /* Bits 0-3: Rx endpoint NAK */
#define USBDEV_ENDPTNAK_EPRN_MASK (15 << USBDEV_ENDPTNAK_EPRN_SHIFT)
/* USB Endpoint NAK Enable register ENDPTNAKEN -- Device Mode */
#define USBDEV_ENDPTNAK_EPTNE_SHIFT (16) /* Bits 16-19: Tx endpoint NAK enable */
#define USBDEV_ENDPTNAK_EPTNE_MASK (15 << USBDEV_ENDPTNAK_EPTNE_SHIFT)
#define USBDEV_ENDPTNAK_EPRNE_SHIFT (0) /* Bits 0-3: Rx endpoint NAK enable */
#define USBDEV_ENDPTNAK_EPRNE_MASK (15 << USBDEV_ENDPTNAK_EPRNE_SHIFT)
/* Port Status and Control register PRTSC1 -- Device Mode */
#define USBDEV_PRTSC1_PSPD_SHIFT (26) /* Bits 26-27: Port speed */
#define USBDEV_PRTSC1_PSPD_MASK (3 << USBDEV_PRTSC1_PSPD_SHIFT)
# define USBDEV_PRTSC1_PSPD_FS (0 << USBDEV_PRTSC1_PSPD_SHIFT) /* Full-speed */
# define USBDEV_PRTSC1_PSPD_LS (1 << USBDEV_PRTSC1_PSPD_SHIFT) /* Low-speed */
# define USBDEV_PRTSC1_PSPD_HS (2 << USBDEV_PRTSC1_PSPD_SHIFT) /* High-speed */
#define USBDEV_PRTSC1_PFSC (1 << 24) /* Bit 24: Port force full speed connect */
#define USBDEV_PRTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend - clock disable (PLPSCD) */
#define USBDEV_PRTSC1_PTC_SHIFT (16) /* Bits 16-19: 19: Port test control */
#define USBDEV_PRTSC1_PTC_MASK (15 << USBDEV_PRTSC1_PTC_SHIFT)
# define USBDEV_PRTSC1_PTC_DISABLE (0 << USBDEV_PRTSC1_PTC_SHIFT) /* TEST_MODE_DISABLE */
# define USBDEV_PRTSC1_PTC_JSTATE (1 << USBDEV_PRTSC1_PTC_SHIFT) /* J_STATE */
# define USBDEV_PRTSC1_PTC_KSTATE (2 << USBDEV_PRTSC1_PTC_SHIFT) /* K_STATE */
# define USBDEV_PRTSC1_PTC_SE0 (3 << USBDEV_PRTSC1_PTC_SHIFT) /* SE0 (host)/NAK (device) */
# define USBDEV_PRTSC1_PTC_PACKET (4 << USBDEV_PRTSC1_PTC_SHIFT) /* Packet */
# define USBDEV_PRTSC1_PTC_HS (5 << USBDEV_PRTSC1_PTC_SHIFT) /* FORCE_ENABLE_HS */
# define USBDEV_PRTSC1_PTC_FS (6 << USBDEV_PRTSC1_PTC_SHIFT) /* FORCE_ENABLE_FS */
#define USBDEV_PRTSC1_PIC_SHIFT (14) /* Bits 14-15: Port indicator control */
#define USBDEV_PRTSC1_PIC_MASK (3 << USBDEV_PRTSC1_PIC_SHIFT)
# define USBDEV_PRTSC1_PIC_OFF (0 << USBDEV_PRTSC1_PIC_SHIFT) /* 00 Port indicators are off */
# define USBDEV_PRTSC1_PIC_AMBER (1 << USBDEV_PRTSC1_PIC_SHIFT) /* 01 amber */
# define USBDEV_PRTSC1_PIC_GREEN (2 << USBDEV_PRTSC1_PIC_SHIFT) /* 10 green */
#define USBDEV_PRTSC1_HSP (1 << 9) /* Bit 9: High-speed status */
#define USBDEV_PRTSC1_PR (1 << 8) /* Bit 8: Port reset */
#define USBDEV_PRTSC1_SUSP (1 << 7) /* Bit 7: Suspend */
#define USBDEV_PRTSC1_FPR (1 << 6) /* Bit 6: Force port resume */
#define USBDEV_PRTSC1_PEC (1 << 3) /* Bit 3: Port enable/disable change */
#define USBDEV_PRTSC1_PE (1 << 2) /* Bit 2: Port enable */
#define USBDEV_PRTSC1_CCS (1 << 0) /* Bit 0: Current connect status */
/* Port Status and Control register PRTSC1 -- Host Mode */
#define USBHOST_PRTSC1_PSPD_SHIFT (26) /* Bits 26-27: Port speed */
#define USBHOST_PRTSC1_PSPD_MASK (3 << USBHOST_PRTSC1_PSPD_SHIFT)
# define USBHOST_PRTSC1_PSPD_FS (0 << USBHOST_PRTSC1_PSPD_SHIFT) /* Full-speed */
# define USBHOST_PRTSC1_PSPD_LS (1 << USBHOST_PRTSC1_PSPD_SHIFT) /* Low-speed */
# define USBHOST_PRTSC1_PSPD_HS (2 << USBHOST_PRTSC1_PSPD_SHIFT) /* High-speed */
#define USBHOST_PRTSC1_PFSC (1 << 24) /* Bit 24: Port force full speed connect */
#define USBHOST_PRTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend - clock disable (PLPSCD) */
#define USBHOST_PRTSC1_WKOC (1 << 22) /* Bit 22: Wake on over-current enable (WKOC_E) */
#define USBHOST_PRTSC1_WKDC (1 << 21) /* Bit 21: Wake on disconnect enable (WKDSCNNT_E) */
#define USBHOST_PRTSC1_WKCN (1 << 20) /* Bit 20: Wake on connect enable (WKCNNT_E) */
#define USBHOST_PRTSC1_PTC_SHIFT (16) /* Bits 16-19: Port test control */
#define USBHOST_PRTSC1_PTC_MASK (15 << USBHOST_PRTSC1_PTC_SHIFT)
# define USBHOST_PRTSC1_PTC_DISABLE (0 << USBHOST_PRTSC1_PTC_SHIFT) /* 0000 TEST_MODE_DISABLE */
# define USBHOST_PRTSC1_PTC_JSTATE (1 << USBHOST_PRTSC1_PTC_SHIFT) /* 0001 J_STATE */
# define USBHOST_PRTSC1_PTC_KSTATE (2 << USBHOST_PRTSC1_PTC_SHIFT) /* 0010 K_STATE */
# define USBHOST_PRTSC1_PTC_SE0 (3 << USBHOST_PRTSC1_PTC_SHIFT) /* 0011 SE0 (host)/NAK (device) */
# define USBHOST_PRTSC1_PTC_PACKET (4 << USBHOST_PRTSC1_PTC_SHIFT) /* 0100 Packet */
# define USBHOST_PRTSC1_PTC_HS (5 << USBHOST_PRTSC1_PTC_SHIFT) /* 0101 FORCE_ENABLE_HS */
# define USBHOST_PRTSC1_PTC_FS (6 << USBHOST_PRTSC1_PTC_SHIFT) /* 0110 FORCE_ENABLE_FS */
# define USBHOST_PRTSC1_PTC_LS (7 << USBHOST_PRTSC1_PTC_SHIFT) /* 0111 FORCE_ENABLE_LS */
#define USBHOST_PRTSC1_PIC_SHIFT (14) /* Bits 14-15: Port indicator control */
#define USBHOST_PRTSC1_PIC_MASK (3 << USBHOST_PRTSC1_PIC_SHIFT)
# define USBHOST_PRTSC1_PIC_OFF (0 << USBHOST_PRTSC1_PIC_SHIFT) /* 00 Port indicators are off */
# define USBHOST_PRTSC1_PIC_AMBER (1 << USBHOST_PRTSC1_PIC_SHIFT) /* 01 Amber */
# define USBHOST_PRTSC1_PIC_GREEN (2 << USBHOST_PRTSC1_PIC_SHIFT) /* 10 Green */
#define USBHOST_PRTSC1_PP (1 << 12) /* Bit 12: Port power control */
#define USBHOST_PRTSC1_LS_SHIFT (10) /* Bits 10-11: Line status */
#define USBHOST_PRTSC1_LS_MASK (3 << USBHOST_PRTSC1_LS_SHIFT)
# define USBHOST_PRTSC1_LS_SE0 (0 << USBHOST_PRTSC1_LS_SHIFT) /* SE0 (USB_DP and USB_DM LOW) */
# define USBHOST_PRTSC1_LS_JSTATE (2 << USBHOST_PRTSC1_LS_SHIFT) /* J-state (USB_DP HIGH and USB_DM LOW) */
# define USBHOST_PRTSC1_LS_KSTATE (1 << USBHOST_PRTSC1_LS_SHIFT) /* K-state (USB_DP LOW and USB_DM HIGH) */
#define USBHOST_PRTSC1_HSP (1 << 9) /* Bit 9: High-speed status */
#define USBHOST_PRTSC1_PR (1 << 8) /* Bit 8: Port reset */
#define USBHOST_PRTSC1_SUSP (1 << 7) /* Bit 7: Suspend */
#define USBHOST_PRTSC1_FPR (1 << 6) /* Bit 6: Force port resume */
#define USBHOST_PRTSC1_OCC (1 << 5) /* Bit 5: Over-current change */
#define USBHOST_PRTSC1_OCA (1 << 4) /* Bit 4: Over-current active */
#define USBHOST_PRTSC1_PEC (1 << 3) /* Bit 3: Port disable/enable change */
#define USBHOST_PRTSC1_PE (1 << 2) /* Bit 2: Port enable */
#define USBHOST_PRTSC1_CSC (1 << 1) /* Bit 1: Connect status change */
#define USBHOST_PRTSC1_CCS (1 << 0) /* Bit 0: Current connect status */
/* OTG Status and Control register (OTGSC) */
/* OTG interrupt enable */
#define USBOTG_OTGSC_DPIE (1 << 30) /* Bit 30: Data pulse interrupt enable */
#define USBOTG_OTGSC_1MSE (1 << 29) /* Bit 29: 1 millisecond timer interrupt enable */
#define USBOTG_OTGSC_BSEIE (1 << 28) /* Bit 28: B-session end interrupt enable */
#define USBOTG_OTGSC_BSVIE (1 << 27) /* Bit 27: B-session valid interrupt enable */
#define USBOTG_OTGSC_ASVIE (1 << 26) /* Bit 26: A-session valid interrupt enable */
#define USBOTG_OTGSC_AVVIE (1 << 25) /* Bit 25: A-VBUS valid interrupt enable */
#define USBOTG_OTGSC_IDIE (1 << 24) /* Bit 24: USB ID interrupt enable */
/* OTG interrupt status */
#define USBOTG_OTGSC_DPIS (1 << 22) /* Bit 22: Data pulse interrupt status */
#define USBOTG_OTGSC_1MSS (1 << 21) /* Bit 21: 1 millisecond timer interrupt status */
#define USBOTG_OTGSC_BSEIS (1 << 20) /* Bit 20: B-Session end interrupt status */
#define USBOTG_OTGSC_BSVIS (1 << 19) /* Bit 19: B-Session valid interrupt status */
#define USBOTG_OTGSC_ASVIS (1 << 18) /* Bit 18: A-Session valid interrupt status */
#define USBOTG_OTGSC_AVVIS (1 << 17) /* Bit 17: A-VBUS valid interrupt status */
#define USBOTG_OTGSC_IDIS (1 << 16) /* Bit 16: USB ID interrupt status */
/* OTG status inputs */
#define USBOTG_OTGSC_DPS (1 << 14) /* Bit 14: Data bus pulsing status */
#define USBOTG_OTGSC_1MST (1 << 13) /* Bit 13: 1 millisecond timer toggle */
#define USBOTG_OTGSC_BSE (1 << 12) /* Bit 12: B-session end */
#define USBOTG_OTGSC_BSV (1 << 11) /* Bit 11: B-session valid */
#define USBOTG_OTGSC_ASV (1 << 10) /* Bit 10: A-session valid */
#define USBOTG_OTGSC_AVV (1 << 9) /* Bit 9: A-VBUS valid */
#define USBOTG_OTGSC_ID (1 << 8) /* Bit 8: USB ID */
/* OTG controls */
#define USBOTG_OTGSC_HABA (1 << 7) /* Bit 7: Hardware assist B-disconnect to A-connect */
#define USBOTG_OTGSC_HADP (1 << 6) /* Bit 6: Hardware assist data pulse */
#define USBOTG_OTGSC_IDPU (1 << 5) /* Bit 5: ID pull-up */
#define USBOTG_OTGSC_DP (1 << 4) /* Bit 4: Data pulsing */
#define USBOTG_OTGSC_OT (1 << 3) /* Bit 3: OTG termination */
#define USBOTG_OTGSC_HAAR (1 << 2) /* Bit 2: Hardware assist auto_reset */
#define USBOTG_OTGSC_VC (1 << 1) /* Bit 1: VBUS_Charge */
#define USBOTG_OTGSC_VD (1 << 0) /* Bit 0: VBUS_Discharge */
/* USB Mode register USBMODE -- Device Mode */
#define USBDEV_USBMODE_SDIS (1 << 4) /* Bit 4: Stream disable mode */
#define USBDEV_USBMODE_SLOM (1 << 3) /* Bit 3: Setup Lockout mode */
#define USBDEV_USBMODE_ES (1 << 2) /* Bit 2: Endian select */
#define USBDEV_USBMODE_CM_SHIFT (0) /* Bits 0-1: Controller mode */
#define USBDEV_USBMODE_CM_MASK (3 << USBDEV_USBMODE_CM_SHIFT)
# define USBDEV_USBMODE_CM_IDLE (0 << USBDEV_USBMODE_CM_SHIFT) /* Idle */
# define USBDEV_USBMODE_CM_DEVICE (2 << USBDEV_USBMODE_CM_SHIFT) /* Device controller */
# define USBDEV_USBMODE_CM_HOST (3 << USBDEV_USBMODE_CM_SHIFT) /* Host controller */
/* USB Mode register USBMODE -- Device Mode */
#define USBHOST_USBMODE_VBPS (1 << 5) /* Bit 5: VBUS power select */
#define USBHOST_USBMODE_SDIS (1 << 4) /* Bit 4: Stream disable mode */
#define USBHOST_USBMODE_ES (1 << 2) /* Bit 2: Endian select */
#define USBHOST_USBMODE_CM_SHIFT (0) /* Bits 0-1: Controller mode */
#define USBHOST_USBMODE_CM_MASK (3 << USBHOST_USBMODE_CM_SHIFT)
# define USBHOST_USBMODE_CM_IDLE (0 << USBHOST_USBMODE_CM_SHIFT) /* Idle */
# define USBHOST_USBMODE_CM_DEVICE (2 << USBHOST_USBMODE_CM_SHIFT) /* Device controller */
# define USBHOST_USBMODE_CM_HOST (3 << USBHOST_USBMODE_CM_SHIFT) /* Host controller */
/* Device endpoint registers */
/* USB Endpoint Setup Status register ENDPTSETUPSTAT */
#define USBDEV_ENDPTSETSTAT_STAT15 (1 << 15) /* Bit 15: Setup EP status for logical EP 15 */
#define USBDEV_ENDPTSETSTAT_STAT14 (1 << 14) /* Bit 14: Setup EP status for logical EP 14 */
#define USBDEV_ENDPTSETSTAT_STAT13 (1 << 13) /* Bit 13: Setup EP status for logical EP 13 */
#define USBDEV_ENDPTSETSTAT_STAT12 (1 << 12) /* Bit 12: Setup EP status for logical EP 12 */
#define USBDEV_ENDPTSETSTAT_STAT11 (1 << 11) /* Bit 11: Setup EP status for logical EP 11 */
#define USBDEV_ENDPTSETSTAT_STAT10 (1 << 10) /* Bit 10: Setup EP status for logical EP 10 */
#define USBDEV_ENDPTSETSTAT_STAT9 (1 << 9) /* Bit 9: Setup EP status for logical EP 9 */
#define USBDEV_ENDPTSETSTAT_STAT8 (1 << 8) /* Bit 8: Setup EP status for logical EP 8 */
#define USBDEV_ENDPTSETSTAT_STAT7 (1 << 7) /* Bit 7: Setup EP status for logical EP 7 */
#define USBDEV_ENDPTSETSTAT_STAT6 (1 << 6) /* Bit 6: Setup EP status for logical EP 6 */
#define USBDEV_ENDPTSETSTAT_STAT5 (1 << 5) /* Bit 5: Setup EP status for logical EP 5 */
#define USBDEV_ENDPTSETSTAT_STAT4 (1 << 4) /* Bit 4: Setup EP status for logical EP 4 */
#define USBDEV_ENDPTSETSTAT_STAT3 (1 << 3) /* Bit 3: Setup EP status for logical EP 3 */
#define USBDEV_ENDPTSETSTAT_STAT2 (1 << 2) /* Bit 2: Setup EP status for logical EP 2 */
#define USBDEV_ENDPTSETSTAT_STAT1 (1 << 1) /* Bit 1: Setup EP status for logical EP 1 */
#define USBDEV_ENDPTSETSTAT_STAT0 (1 << 0) /* Bit 0: Setup EP status for logical EP 0 */
/* USB Endpoint Prime register ENDPTPRIME */
#define USBDEV_ENDPTPRIM_PETB7 (1 << 23) /* Bit 23: Prime EP xmt buffer for physical IN EP 7 */
#define USBDEV_ENDPTPRIM_PETB6 (1 << 22) /* Bit 22: Prime EP xmt buffer for physical IN EP 6 */
#define USBDEV_ENDPTPRIM_PETB5 (1 << 21) /* Bit 21: Prime EP xmt buffer for physical IN EP 5 */
#define USBDEV_ENDPTPRIM_PETB4 (1 << 20) /* Bit 20: Prime EP xmt buffer for physical IN EP 4 */
#define USBDEV_ENDPTPRIM_PETB3 (1 << 19) /* Bit 19: Prime EP xmt buffer for physical IN EP 3 */
#define USBDEV_ENDPTPRIM_PETB2 (1 << 18) /* Bit 18: Prime EP xmt buffer for physical IN EP 2 */
#define USBDEV_ENDPTPRIM_PETB1 (1 << 17) /* Bit 17: Prime EP xmt buffer for physical IN EP 1 */
#define USBDEV_ENDPTPRIM_PETB0 (1 << 16) /* Bit 16: Prime EP xmt buffer for physical IN EP 0 */
#define USBDEV_ENDPTPRIM_PERB7 (1 << 7) /* Bit 7: Prime EP recv buffer for physical OUT EP 7 */
#define USBDEV_ENDPTPRIM_PERB6 (1 << 6) /* Bit 6: Prime EP recv buffer for physical OUT EP 6 */
#define USBDEV_ENDPTPRIM_PERB5 (1 << 5) /* Bit 5: Prime EP recv buffer for physical OUT EP 5 */
#define USBDEV_ENDPTPRIM_PERB4 (1 << 4) /* Bit 4: Prime EP recv buffer for physical OUT EP 4 */
#define USBDEV_ENDPTPRIM_PERB3 (1 << 3) /* Bit 3: Prime EP recv buffer for physical OUT EP 3 */
#define USBDEV_ENDPTPRIM_PERB2 (1 << 2) /* Bit 2: Prime EP recv buffer for physical OUT EP 2 */
#define USBDEV_ENDPTPRIM_PERB1 (1 << 1) /* Bit 1: Prime EP recv buffer for physical OUT EP 1 */
#define USBDEV_ENDPTPRIM_PERB0 (1 << 0) /* Bit 0: Prime EP recv buffer for physical OUT EP 0 */
/* USB Endpoint Flush register ENDPTFLUSH */
#define USBDEV_ENDPTFLUSH_FETB7 (1 << 23) /* Bit 23: Flush EP xmt buffer for physical IN EP 7 */
#define USBDEV_ENDPTFLUSH_FETB6 (1 << 22) /* Bit 22: Flush EP xmt buffer for physical IN EP 6 */
#define USBDEV_ENDPTFLUSH_FETB5 (1 << 21) /* Bit 21: Flush EP xmt buffer for physical IN EP 5 */
#define USBDEV_ENDPTFLUSH_FETB4 (1 << 20) /* Bit 20: Flush EP xmt buffer for physical IN EP 4 */
#define USBDEV_ENDPTFLUSH_FETB3 (1 << 19) /* Bit 19: Flush EP xmt buffer for physical IN EP 3 */
#define USBDEV_ENDPTFLUSH_FETB2 (1 << 18) /* Bit 18: Flush EP xmt buffer for physical IN EP 2 */
#define USBDEV_ENDPTFLUSH_FETB1 (1 << 17) /* Bit 17: Flush EP xmt buffer for physical IN EP 1 */
#define USBDEV_ENDPTFLUSH_FETB0 (1 << 16) /* Bit 16: Flush EP xmt buffer for physical IN EP 0 */
#define USBDEV_ENDPTFLUSH_FERB7 (1 << 7) /* Bit 7: Flush EP recv buffer for physical OUT EP 7 */
#define USBDEV_ENDPTFLUSH_FERB6 (1 << 6) /* Bit 6: Flush EP recv buffer for physical OUT EP 6 */
#define USBDEV_ENDPTFLUSH_FERB5 (1 << 5) /* Bit 5: Flush EP recv buffer for physical OUT EP 5 */
#define USBDEV_ENDPTFLUSH_FERB4 (1 << 4) /* Bit 4: Flush EP recv buffer for physical OUT EP 4 */
#define USBDEV_ENDPTFLUSH_FERB3 (1 << 3) /* Bit 3: Flush EP recv buffer for physical OUT EP 3 */
#define USBDEV_ENDPTFLUSH_FERB2 (1 << 2) /* Bit 2: Flush EP recv buffer for physical OUT EP 2 */
#define USBDEV_ENDPTFLUSH_FERB1 (1 << 1) /* Bit 1: Flush EP recv buffer for physical OUT EP 1 */
#define USBDEV_ENDPTFLUSH_FERB0 (1 << 0) /* Bit 0: Flush EP recv buffer for physical OUT EP 0 */
/* USB Endpoint Status register ENDPTSTATUS */
#define USBDEV_ENDPTSTATUS_ETBR7 (1 << 23) /* Bit 23: EP xmt buffer ready for physical IN EP 7 */
#define USBDEV_ENDPTSTATUS_ETBR6 (1 << 22) /* Bit 22: EP xmt buffer ready for physical IN EP 6 */
#define USBDEV_ENDPTSTATUS_ETBR5 (1 << 21) /* Bit 21: EP xmt buffer ready for physical IN EP 5 */
#define USBDEV_ENDPTSTATUS_ETBR4 (1 << 20) /* Bit 20: EP xmt buffer ready for physical IN EP 4 */
#define USBDEV_ENDPTSTATUS_ETBR3 (1 << 19) /* Bit 19: EP xmt buffer ready for physical IN EP 3 */
#define USBDEV_ENDPTSTATUS_ETBR2 (1 << 18) /* Bit 18: EP xmt buffer ready for physical IN EP 2 */
#define USBDEV_ENDPTSTATUS_ETBR1 (1 << 17) /* Bit 17: EP xmt buffer ready for physical IN EP 1 */
#define USBDEV_ENDPTSTATUS_ETBR0 (1 << 16) /* Bit 16: EP xmt buffer ready for physical IN EP 0 */
#define USBDEV_ENDPTSTATUS_ERBR7 (1 << 7) /* Bit 7: EP recv buffer ready for physical OUT EP 7 */
#define USBDEV_ENDPTSTATUS_ERBR6 (1 << 6) /* Bit 6: EP recv buffer ready for physical OUT EP 6 */
#define USBDEV_ENDPTSTATUS_ERBR5 (1 << 5) /* Bit 5: EP recv buffer ready for physical OUT EP 5 */
#define USBDEV_ENDPTSTATUS_ERBR4 (1 << 4) /* Bit 4: EP recv buffer ready for physical OUT EP 4 */
#define USBDEV_ENDPTSTATUS_ERBR3 (1 << 3) /* Bit 3: EP recv buffer ready for physical OUT EP 3 */
#define USBDEV_ENDPTSTATUS_ERBR2 (1 << 2) /* Bit 2: EP recv buffer ready for physical OUT EP 2 */
#define USBDEV_ENDPTSTATUS_ERBR1 (1 << 1) /* Bit 1: EP recv buffer ready for physical OUT EP 1 */
#define USBDEV_ENDPTSTATUS_ERBR0 (1 << 0) /* Bit 0: EP recv buffer ready for physical OUT EP 0 */
/* USB Endpoint Complete register ENDPTCOMPLETE */
#define USBDEV_ENDPTCOMPLETE_ETCE7 (1 << 23) /* Bit 23: EP xmt complete event for physical IN EP 7 */
#define USBDEV_ENDPTCOMPLETE_ETCE6 (1 << 22) /* Bit 22: EP xmt complete event for physical IN EP 6 */
#define USBDEV_ENDPTCOMPLETE_ETCE5 (1 << 21) /* Bit 21: EP xmt complete event for physical IN EP 5 */
#define USBDEV_ENDPTCOMPLETE_ETCE4 (1 << 20) /* Bit 20: EP xmt complete event for physical IN EP 4 */
#define USBDEV_ENDPTCOMPLETE_ETCE3 (1 << 19) /* Bit 19: EP xmt complete event for physical IN EP 3 */
#define USBDEV_ENDPTCOMPLETE_ETCE2 (1 << 18) /* Bit 18: EP xmt complete event for physical IN EP 2 */
#define USBDEV_ENDPTCOMPLETE_ETCE1 (1 << 17) /* Bit 17: EP xmt complete event for physical IN EP 1 */
#define USBDEV_ENDPTCOMPLETE_ETCE0 (1 << 16) /* Bit 16: EP xmt complete event for physical IN EP 0 */
#define USBDEV_ENDPTCOMPLETE_ERCE7 (1 << 7) /* Bit 7: EP recv complete event for physical OUT EP 7 */
#define USBDEV_ENDPTCOMPLETE_ERCE6 (1 << 6) /* Bit 6: EP recv complete event for physical OUT EP 6 */
#define USBDEV_ENDPTCOMPLETE_ERCE5 (1 << 5) /* Bit 5: EP recv complete event for physical OUT EP 5 */
#define USBDEV_ENDPTCOMPLETE_ERCE4 (1 << 4) /* Bit 4: EP recv complete event for physical OUT EP 4 */
#define USBDEV_ENDPTCOMPLETE_ERCE3 (1 << 3) /* Bit 3: EP recv complete event for physical OUT EP 3 */
#define USBDEV_ENDPTCOMPLETE_ERCE2 (1 << 2) /* Bit 2: EP recv complete event for physical OUT EP 2 */
#define USBDEV_ENDPTCOMPLETE_ERCE1 (1 << 1) /* Bit 1: EP recv complete event for physical OUT EP 1 */
#define USBDEV_ENDPTCOMPLETE_ERCE0 (1 << 0) /* Bit 0: EP recv complete event for physical OUT EP 0 */
/* USB Endpoint 0 Control register ENDPTCTRL0 */
#define USBDEV_ENDPTCTRL0_TXE (1 << 23) /* Bit 23: Tx endpoint enable */
#define USBDEV_ENDPTCTRL0_TXT_SHIFT (18) /* Bits 18-19: Tx endpoint type */
#define USBDEV_ENDPTCTRL0_TXT_MASK (3 << USBDEV_ENDPTCTRL0_TXT_SHIFT)
# define USBDEV_ENDPTCTRL0_TXT_CTRL (0 << USBDEV_ENDPTCTRL0_TXT_SHIFT) /* Control */
#define USBDEV_ENDPTCTRL0_TXS (1 << 16) /* Bit 16: Tx endpoint stall */
#define USBDEV_ENDPTCTRL0_RXE (1 << 7) /* Bit 7: Rx endpoint enable */
#define USBDEV_ENDPTCTRL0_RXT_SHIFT (2) /* Bits 2-3: Endpoint type */
#define USBDEV_ENDPTCTR0L_RXT_MASK (3 << USBDEV_ENDPTCTRL0_RXT_SHIFT)
# define USBDEV_ENDPTCTRL0_RXT_CTRL (0 << USBDEV_ENDPTCTRL0_RXT_SHIFT) /* Control */
#define USBDEV_ENDPTCTRL0_RXS (1 << 0) /* Bit 0: Rx endpoint stall */
/* USB Endpoint 1-7 control registers ENDPTCTRL1-ENDPPTCTRL7 */
#define USBDEV_ENDPTCTRL_TXE (1 << 23) /* Bit 23: Tx endpoint enable */
#define USBDEV_ENDPTCTRL_TXR (1 << 22) /* Bit 22: Tx data toggle reset */
#define USBDEV_ENDPTCTRL_TXI (1 << 21) /* Bit 21: Tx data toggle inhibit */
#define USBDEV_ENDPTCTRL_TXT_SHIFT (18) /* Bits 18-19: Tx endpoint type */
#define USBDEV_ENDPTCTRL_TXT_MASK (3 << USBDEV_ENDPTCTRL_TXT_SHIFT)
# define USBDEV_ENDPTCTRL_TXT_CTRL (0 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Control */
# define USBDEV_ENDPTCTRL_TXT_ISOC (1 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Isochronous */
# define USBDEV_ENDPTCTRL_TXT_BULK (2 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Bulk */
# define USBDEV_ENDPTCTRL_TXT_INTR (3 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Interrupt */
#define USBDEV_ENDPTCTRL_TXS (1 << 16) /* Bit 16: Tx endpoint stall */
#define USBDEV_ENDPTCTRL_RXE (1 << 7) /* Bit 7: Rx endpoint enable */
#define USBDEV_ENDPTCTRL_RXR (1 << 6) /* Bit 6: Rx data toggle reset */
#define USBDEV_ENDPTCTRL_RXI (1 << 5) /* Bit 5: Rx data toggle inhibit */
#define USBDEV_ENDPTCTRL_RXT_SHIFT (2) /* Bits 2-3: Endpoint type */
#define USBDEV_ENDPTCTRL_RXT_MASK (3 << USBDEV_ENDPTCTRL_RXT_SHIFT)
# define USBDEV_ENDPTCTRL_RXT_CTRL (0 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Control */
# define USBDEV_ENDPTCTRL_RXT_ISOC (1 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Isochronous */
# define USBDEV_ENDPTCTRL_RXT_BULK (2 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Bulk */
# define USBDEV_ENDPTCTRL_RXT_INTR (3 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Interrupt */
#define USBDEV_ENDPTCTRL_RXS (1 << 0) /* Bit 0: Rx endpoint stall */
/* Device non-core registers */
/* USB OTG Control register */
/* Bits 0-6:
* Reserved
*/
#define USBNC_OVER_CUR_DIS (1 << 7) /* Bit 7: Disable Over current detection */
#define USBNC_OVER_CUR_POL (1 << 8) /* Bit 8: Polarity of over current */
#define USBNC_PWR_POL (1 << 9) /* Bit 9: Power polarity */
#define USBNC_WIE (1<< 10) /* Bit 10: Wake up interrupt enable */
/* Bit 11-13: Reserved */
#define USBNC_WKUP_SW_EN (1 << 14) /* Bit 14: Software wake up enable */
#define USBNC_WKUP_SW (1 << 15) /* Bit 15: Software wake up */
#define USBNC_WKUP_ID_EN (1 << 16) /* Bit 16: Wakeup on ID change enable */
#define USBNC_WKUP_VBUS_EN (1 << 17) /* Bit 17: Wakeup on VBUS change enable */
/* Bit 18-28: Reserved */
#define USBNC_WKUP_DPDM_EN (1 << 29) /* Bit 29: Wakeup on DPDM change enable */
/* Bit 30: Reserved */
#define USBNC_WIR (1 << 31) /* Bit 31: Wake up interrupt request */
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USBOTG_H */

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/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_usbphy.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_PHY_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_PHY_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imxrt_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IMXRT_USBPHY1_BASE_OFFSET 0x1000 /* USB PHY1 Base */
#define IMXRT_USBPHY2_BASE_OFFSET 0x2000 /* USB PHY2 Base */
#define IMXRT_USBPHY1_BASE (IMXRT_ANATOP_BASE + IMXRT_USBPHY1_BASE_OFFSET) /* USB PHY1 Base */
#define IMXRT_USBPHY2_BASE (IMXRT_ANATOP_BASE + IMXRT_USBPHY2_BASE_OFFSET) /* USB PHY2 Base */
/* Register Offsets *********************************************************/
#define IMXRT_USBPHY1_PWD_OFFSET 0x0000 /* USBPHY1 USB PHY1 Power-Down Register */
#define IMXRT_USBPHY1_PWD_CLR_OFFSET 0x0008 /* USBPHY1 USB PHY1 Power-Down Register Clear */
#define IMXRT_USBPHY1_CTRL_OFFSET 0x0030 /* USBPHY1 USB PHY1 General Control Register */
#define IMXRT_USBPHY1_CTRL_CLR_OFFSET 0x0038 /* USBPHY1 USB PHY1 General Control Register Clear */
#define IMXRT_USBPHY2_PWD_OFFSET 0x0000 /* USBPHY2 USB PHY Power-Down Register */
#define IMXRT_USBPHY2_PWD_CLR_OFFSET 0x0008 /* USBPHY2 USB PHY Power-Down Register Clear */
#define IMXRT_USBPHY2_CTRL_OFFSET 0x0030 /* USBPHY2 USB PHY General Control Register */
#define IMXRT_USBPHY2_CTRL_CLR_OFFSET 0x0038 /* USBPHY2 USB PHY General Control Register Clear */
/* Register addresses *******************************************************/
#define IMXRT_USBPHY1_PWD (IMXRT_USBPHY1_BASE + IMXRT_USBPHY1_PWD_OFFSET) /* USBPHY1 USB PHY1 Power-Down Register */
#define IMXRT_USBPHY1_PWD_CLR (IMXRT_USBPHY1_BASE + IMXRT_USBPHY1_PWD_CLR_OFFSET) /* USBPHY1 USB PHY1 Power-Down Register Clear */
#define IMXRT_USBPHY1_CTRL (IMXRT_USBPHY1_BASE + IMXRT_USBPHY1_CTRL_OFFSET) /* USBPHY1 USB PHY1 General Control Register */
#define IMXRT_USBPHY1_CTRL_CLR (IMXRT_USBPHY1_BASE + IMXRT_USBPHY1_CTRL_CLR_OFFSET) /* USBPHY1 USB PHY1 General Control Register Clear */
#define IMXRT_USBPHY2_PWD (IMXRT_USBPHY2_BASE + IMXRT_USBPHY2_PWD_OFFSET) /* USBPHY2 USB PHY2 Power-Down Register */
#define IMXRT_USBPHY2_PWD_CLR (IMXRT_USBPHY2_BASE + IMXRT_USBPHY2_PWD_CLR_OFFSET) /* USBPHY2 USB PHY2 Power-Down Register Clear */
#define IMXRT_USBPHY2_CTRL (IMXRT_USBPHY2_BASE + IMXRT_USBPHY2_CTRL_OFFSET) /* USBPHY2 USB PHY2 General Control Register */
#define IMXRT_USBPHY2_CTRL_CLR (IMXRT_USBPHY2_BASE + IMXRT_USBPHY2_CTRL_CLR_OFFSET) /* USBPHY2 USB PHY2 General Control Register Clear */
/* Register Bit Definitions *************************************************/
/* USB PHY Power-Down Register */
#define USBPHY_PWD_RXPWDRX (1 << 20) /* Bit 20: Power-down the entire USB PHY receiver block except for the full-speed differential receiver. */
#define USBPHY_PWD_RXPWDDIFF (1 << 19) /* Bit 19: Power-down the USB high-speed differential receiver. */
#define USBPHY_PWD_RXPWD1PT1 (1 << 18) /* Bit 18: Power-down the USB full-speed differential receiver. */
#define USBPHY_PWD_RXPWDENV (1 << 17) /* Bit 17: Power-down the USB high-speed receiver envelope detector (squelch signal). */
#define USBPHY_PWD_TXPWDV2I (1 << 12) /* Bit 12: Power-down the USB PHY transmit V-to-I converter and the current mirror. */
#define USBPHY_PWD_TXPWDIBIAS (1 << 11) /* Bit 11: Power-down the USB PHY current bias block for the transmitter. */
#define USBPHY_PWD_TXPWDFS (1 << 10) /* Bit 10: Power-down the USB full-speed drivers. */
/* USB PHY General Control Register */
#define USBPHY_CTRL_SFTRST (1 << 31) /* Bit 31: Soft-reset */
#define USBPHY_CTRL_CLKGATE (1 << 30) /* Bit 30: Gate UTMI clocks */
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_PHY_H */

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/****************************************************************************
* arch/arm/src/imxrt/hardware/rt105x/imxrt105x_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* System memory map */
#define IMXRT_ITCM_BASE 0x00000000 /* 512KB ITCM */
/* 0x00080000 512KB ITCM Reserved */
/* 0x00100000 1MB ITCM Reserved */
#define IMXRT_ROMCP_BASE 0x00200000 /* 96KB ROMCP */
/* 0x00218000 416KB ROMCP Reserved */
/* 0x00280000 1536KB Reserved */
/* 0x00400000 124MB Reserved */
#define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */
#define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */
#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */
/* 0x20080000 512KB DTCM Reserved */
/* 0x20100000 1MB Reserved */
#define IMXRT_OCRAM_BASE 0x20200000 /* 512KB OCRAM */
/* 0x20280000 1536KB OCRAM Reserved */
/* 0x20400000 252MB Reserved */
/* 0x30000000 256MB Reserved */
#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */
#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */
#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */
#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */
/* 40400000 12MB Reserved */
#define IMXRT_MAINCNF_BASE 0x41000000 /* 1MB "main" configuration port */
#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */
/* 41200000 1MB Reserved for "per" GPV */
/* 41300000 1MB Reserved for "ems" GPV */
#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */
/* 0x41500000 1MB GPV Reserved */
/* 0x41600000 1MB GPV Reserved */
/* 0x41700000 1MB GPV Reserved */
/* 0x41800000 8MB Reserved */
/* 0x42000000 32MB Reserved */
/* 0x44000000 64MB Reserved */
/* 0x48000000 384MB Reserved */
#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 504MB FlexSPI/ FlexSPI ciphertext */
#define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */
#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */
#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */
#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */
/* 0xe0100000 511MB Reserved */
/* AIPS-1 memory map */
/* 0x40000000 256KB Reserved */
/* 0x40040000 240KB Reserved */
#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 6KB AIPS-1 Configuration */
#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */
#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */
/* 0x40088000 16KB Reserved */
/* 0x4008c000 16KB Reserved */
#define IMXRT_MTR_BASE 0x40090000 /* 16KB MTR */
#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */
/* 0x40098000 16KB Reserved */
/* 0x4009c000 16KB Reserved */
/* 0x400a0000 16KB Reserved */
#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */
#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */
#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */
#define IMXRT_FLEXRAM_BASE 0x400b0000 /* 16KB CM7_MX6RT(FLEXRAM) */
#define IMXRT_EWM_BASE 0x400b4000 /* 16KB EWM */
#define IMXRT_WDOG1_BASE 0x400b8000 /* 16KB WDOG1 */
#define IMXRT_WDOG3_BASE 0x400bc000 /* 16KB WDOG3 */
#define IMXRT_GPIO5_BASE 0x400c0000 /* 16KB GPIO5 */
#define IMXRT_ADC1_BASE 0x400c4000 /* 16KB ADC1 */
#define IMXRT_ADC2_BASE 0x400c8000 /* 16KB ADC2 */
#define IMXRT_TRNG_BASE 0x400cc000 /* 16KB TRNG */
#define IMXRT_WDOG2_BASE 0x400d0000 /* 16KB WDOG2 */
#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */
#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */
#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */
/* 0x400e0000 16KB Reserved */
/* 0x400e4000 16KB Reserved */
#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */
#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */
/* 400f0000 16KB Reserved */
#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */
#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */
#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */
/* AIPS-2 memory map */
/* 0x40100000 256KB Reserved */
/* 0x40140000 240KB Reserved */
#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */
#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/
#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */
#define IMXRT_LPUART2_BASE 0x40188000 /* 16KB LPUART2 */
#define IMXRT_LPUART3_BASE 0x4018c000 /* 16KB LPUART3 */
#define IMXRT_LPUART4_BASE 0x40190000 /* 16KB LPUART4 */
#define IMXRT_LPUART5_BASE 0x40194000 /* 16KB LPUART5 */
#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */
#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */
#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */
/* 0x401a4000 16KB Reserved */
/* 0x401a8000 16KB Reserved */
#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */
#define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */
/* 0x401b4000 16KB Reserved */
#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */
#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */
#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */
#define IMXRT_GPIO4_BASE 0x401c4000 /* 16KB GPIO4 */
/* 0x401c8000 16KB Reserved */
/* 0x401cc000 16KB Reserved */
#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */
#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */
/* 0x401d8000 16KB Reserved */
#define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */
#define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */
#define IMXRT_QTIMER3_BASE 0x401e4000 /* 16KB QTimer3 */
#define IMXRT_QTIMER4_BASE 0x401e8000 /* 16KB QTimer4 */
#define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */
#define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */
#define IMXRT_OCOTP_BASE 0x401f4000 /* 16KB OCOTP */
#define IMXRT_IOMUXC_BASE 0x401f8000 /* 16KB IOMUXC */
#define IMXRT_KPP_BASE 0x401fc000 /* 16KB KPP */
/* AIPS-3 memory map */
/* 0x40200000 256KB Reserved */
/* 0x40240000 240KB Reserved */
#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */
/* 0x40280000 16KB Reserved */
/* 0x40284000 16KB Reserved */
/* 0x40288000 16KB Reserved */
/* 0x4028c000 16KB Reserved */
/* 0x40290000 16KB Reserved */
/* 0x40294000 16KB Reserved */
/* 0x40298000 16KB Reserved */
/* 0x4029c000 16KB Reserved */
/* 0x402a0000 16KB Reserved */
/* 0x402a4000 16KB Reserved */
#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI controller */
/* 0x402ac000 16KB Reserved */
/* 0x402b0000 16KB Reserved */
#define IMXRT_PXP_BASE 0x402b4000 /* 16KB PXP */
#define IMXRT_LCDIF_BASE 0x402b8000 /* 16KB LCDIF */
#define IMXRT_CSI_BASE 0x402bc000 /* 16KB CSI */
#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */
#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */
/* 0x402c8000 16KB Reserved */
/* 0x402cc000 16KB Reserved */
/* 0x402d0000 16KB Reserved */
/* 0x402d4000 16KB Reserved */
#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */
#define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */
#define IMXRT_USB_BASE 0x402e0200 /* 16KB USB(USB) */
/* 0x402e4000 16KB Reserved */
/* 0x402e8000 16KB Reserved */
/* 0x402ec000 16KB Reserved */
#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */
/* 0x402f4000 16KB Reserved */
/* 0x402f8000 16KB Reserved */
#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */
/* AIPS-4 memory map */
/* 0x40300000 256KB Reserved */
/* 0x40340000 240KB Reserved */
#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */
#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */
#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */
#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */
#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */
/* 0x40390000 16KB Reserved */
#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */
#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */
#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */
#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */
/* 0x403a4000 16KB Reserved */
/* 0x403a8000 16KB Reserved */
/* 0x403ac000 16KB Reserved */
#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */
#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */
#define IMXRT_AOI2_BASE 0x403b8000 /* 16KB AOI2 */
#define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */
#define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */
#define IMXRT_XBAR3_BASE 0x403c4000 /* 16KB XBAR3 */
#define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */
#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */
#define IMXRT_ENC3_BASE 0x403d0000 /* 16KB ENC3 */
#define IMXRT_ENC4_BASE 0x403d4000 /* 16KB ENC4 */
/* 0x403d8000 16KB Reserved */
#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */
#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */
#define IMXRT_FLEXPWM3_BASE 0x403e4000 /* 16KB FLEXPWM3 */
#define IMXRT_FLEXPWM4_BASE 0x403e8000 /* 16KB FLEXPWM4 */
#define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */
#define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */
#define IMXRT_LPI2C2_BASE 0x403f4000 /* 16KB LPI2C2 */
#define IMXRT_LPI2C3_BASE 0x403f8000 /* 16KB LPI2C3 */
#define IMXRT_LPI2C4_BASE 0x403fc000 /* 16KB LPI2C4 */
/* PPB memory map */
#define IMXRT_TPIU_BASE 0xe0040000 /* 4KB TPIU */
#define IMXRT_ETM_BASE 0xe0041000 /* 4KB ETM */
#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */
#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */
#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */
/* 0xe0045000 236KB PPB Reserved */
#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */
/* 0xe0081000 444KB PPB Reserved */
/* 0xe00f0000 52KB PPB Reserved */
#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */
#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */
#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H */

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/****************************************************************************
* arch/arm/src/imxrt/imxrt_clockconfig.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_arch.h"
#include <arch/board/board.h>
#include "hardware/imxrt_ccm.h"
#include "hardware/imxrt_dcdc.h"
#include "imxrt_clockconfig.h"
#include "imxrt_lcd.h"
#include "hardware/imxrt_memorymap.h"
#include "hardware/imxrt_iomuxc.h"
#include <stdlib.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define VIDEO_PLL_MIN_FREQ 650000000
#define OSC24_FREQ 24000000
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_lcd_clockconfig
****************************************************************************/
#ifdef CONFIG_IMXRT_LCD
static void imxrt_lcd_clockconfig(void)
{
uint32_t reg;
uint32_t reg2;
int post;
int pre;
uint32_t numerator;
uint32_t denominator;
uint32_t post_divider;
uint32_t pre_divider;
uint32_t loop_divider;
uint32_t target_freq;
uint32_t freq_error;
target_freq = (CONFIG_IMXRT_LCD_HWIDTH +
CONFIG_IMXRT_LCD_HPULSE +
CONFIG_IMXRT_LCD_HFRONTPORCH +
CONFIG_IMXRT_LCD_HBACKPORCH) *
(CONFIG_IMXRT_LCD_VHEIGHT +
CONFIG_IMXRT_LCD_VPULSE +
CONFIG_IMXRT_LCD_VFRONTPORCH +
CONFIG_IMXRT_LCD_VBACKPORCH) *
CONFIG_IMXRT_LCD_REFRESH_FREQ;
for (post_divider = 1; post_divider < 16; post_divider <<= 1)
{
if (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider >= VIDEO_PLL_MIN_FREQ)
{
break;
}
}
loop_divider = (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider) / OSC24_FREQ;
numerator = (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider) -
(loop_divider * OSC24_FREQ);
denominator = OSC24_FREQ;
/* Bypass PLL first */
modifyreg32(IMXRT_CCM_ANALOG_PLL_VIDEO,
CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK,
CCM_ANALOG_PLL_VIDEO_BYPASS |
CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M);
putreg32(CCM_ANALOG_PLL_VIDEO_NUM_A(numerator),
IMXRT_CCM_ANALOG_PLL_VIDEO_NUM);
putreg32(CCM_ANALOG_PLL_VIDEO_DENOM_B(denominator),
IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM);
/* Set post divider:
*
* ------------------------------------------------------------------------
* | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] |
* ------------------------------------------------------------------------
* | 1 | 2 | 0 |
* ------------------------------------------------------------------------
* | 2 | 1 | 0 |
* ------------------------------------------------------------------------
* | 4 | 2 | 3 |
* ------------------------------------------------------------------------
* | 8 | 1 | 3 |
* ------------------------------------------------------------------------
* | 16 | 0 | 3 |
* ------------------------------------------------------------------------
*/
reg = getreg32(IMXRT_CCM_ANALOG_PLL_VIDEO);
reg &= ~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK |
CCM_ANALOG_PLL_VIDEO_POWERDOWN);
reg |= CCM_ANALOG_PLL_VIDEO_ENABLE |
CCM_ANALOG_PLL_VIDEO_DIV_SELECT(loop_divider);
reg2 = getreg32(IMXRT_CCM_ANALOG_MISC2);
reg2 &= ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK;
switch (post_divider)
{
case 16:
reg |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4;
reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3);
break;
case 8:
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2;
reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3);
break;
case 4:
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1;
reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3);
break;
case 2:
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2;
reg2 |= 0;
break;
default:
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1;
reg2 |= 0;
break;
}
putreg32(reg, IMXRT_CCM_ANALOG_PLL_VIDEO);
putreg32(reg2, IMXRT_CCM_ANALOG_MISC2);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_VIDEO) &
CCM_ANALOG_PLL_VIDEO_LOCK) == 0)
{
}
/* Disable Bypass */
modifyreg32(IMXRT_CCM_ANALOG_PLL_VIDEO,
CCM_ANALOG_PLL_VIDEO_BYPASS,
0);
freq_error = IMXRT_LCD_VIDEO_PLL_FREQ;
pre_divider = 0;
post_divider = 0;
for (post = 0; post < 8; post++)
{
for (pre = 0; pre < 8; pre++)
{
int32_t temp_error;
temp_error = labs((post + 1) * (pre + 1) * target_freq -
IMXRT_LCD_VIDEO_PLL_FREQ);
if (temp_error < freq_error)
{
pre_divider = pre;
post_divider = post;
freq_error = temp_error;
}
}
}
/* Select PLL5 as LCD Clock and set Pre divider. */
modifyreg32(IMXRT_CCM_CSCDR2,
CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK |
CCM_CSCDR2_LCDIF_PRED_MASK,
CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL5 |
CCM_CSCDR2_LCDIF_PRED(pre_divider));
/* Set Post divider. */
modifyreg32(IMXRT_CCM_CBCMR, CCM_CBCMR_LCDIF_PODF_MASK,
CCM_CBCMR_LCDIF_PODF(post_divider));
}
#endif
/****************************************************************************
* Name: imxrt_pllsetup
****************************************************************************/
static void imxrt_pllsetup(void)
{
#ifdef CONFIG_ARCH_FAMILY_IMXRT102x
uint32_t pll2reg;
#endif
uint32_t pll3reg;
uint32_t reg;
#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined (CONFIG_ARCH_FAMILY_IMXRT106x))
/* Init Arm PLL1 */
reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_DIV_SELECT) |
CCM_ANALOG_PLL_ARM_ENABLE;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_ARM);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_ARM) & CCM_ANALOG_PLL_ARM_LOCK) == 0)
{
}
/* Init Sys PLL2 */
reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) |
CCM_ANALOG_PLL_SYS_ENABLE;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0)
{
}
/* Init USB PLL3 */
/* capture it's original value */
pll3reg = getreg32(IMXRT_CCM_ANALOG_PFD_480);
putreg32(pll3reg |
CCM_ANALOG_PFD_480_PFD0_CLKGATE |
CCM_ANALOG_PFD_480_PFD1_CLKGATE |
CCM_ANALOG_PFD_480_PFD2_CLKGATE |
CCM_ANALOG_PFD_480_PFD3_CLKGATE,
IMXRT_CCM_ANALOG_PFD_480);
reg = IMXRT_USB2_PLL_DIV_SELECT |
CCM_ANALOG_PLL_USB2_ENABLE |
CCM_ANALOG_PLL_USB2_EN_USB_CLKS |
CCM_ANALOG_PLL_USB2_POWER;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB2);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB2) &
CCM_ANALOG_PLL_USB2_LOCK) == 0)
{
}
putreg32(pll3reg, IMXRT_CCM_ANALOG_PFD_480);
#ifdef CONFIG_IMXRT_LCD
/* Init Video PLL5 */
imxrt_lcd_clockconfig();
#endif
/* Init ENET PLL6 */
reg = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ |
CCM_ANALOG_PLL_ENET_ENET1_125M_EN |
CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN |
CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN |
CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_ENET);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) &
CCM_ANALOG_PLL_ENET_LOCK) == 0)
{
}
#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x)
/* Init Sys PLL2 */
/* First reset its fractional dividers */
pll2reg = getreg32(IMXRT_CCM_ANALOG_PFD_528);
putreg32(pll2reg |
CCM_ANALOG_PFD_528_PFD0_CLKGATE |
CCM_ANALOG_PFD_528_PFD1_CLKGATE |
CCM_ANALOG_PFD_528_PFD2_CLKGATE |
CCM_ANALOG_PFD_528_PFD3_CLKGATE,
IMXRT_CCM_ANALOG_PFD_528);
reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_DIV_SELECT) |
CCM_ANALOG_PLL_SYS_ENABLE;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) &
CCM_ANALOG_PLL_SYS_LOCK) == 0)
{
}
putreg32(pll2reg, IMXRT_CCM_ANALOG_PFD_528);
/* Init USB PLL3 */
/* capture it's original value */
pll3reg = getreg32(IMXRT_CCM_ANALOG_PFD_480);
putreg32(pll3reg |
CCM_ANALOG_PFD_480_PFD0_CLKGATE |
CCM_ANALOG_PFD_480_PFD1_CLKGATE |
CCM_ANALOG_PFD_480_PFD2_CLKGATE |
CCM_ANALOG_PFD_480_PFD3_CLKGATE,
IMXRT_CCM_ANALOG_PFD_480);
reg = CCM_ANALOG_PLL_USB2_DIV_SELECT(IMXRT_USB2_PLL_DIV_SELECT) |
CCM_ANALOG_PLL_USB2_ENABLE | CCM_ANALOG_PLL_USB2_EN_USB_CLKS |
CCM_ANALOG_PLL_USB2_POWER;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB2);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB2) &
CCM_ANALOG_PLL_USB2_LOCK) == 0)
{
}
putreg32(pll3reg, IMXRT_CCM_ANALOG_PFD_480);
/* Init Audio PLL4 */
reg = CCM_ANALOG_PLL_AUDIO_DIV_SELECT(IMXRT_AUDIO_PLL_DIV_SELECT) |
CCM_ANALOG_PLL_AUDIO_ENABLE;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_AUDIO);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_AUDIO) &
CCM_ANALOG_PLL_AUDIO_LOCK) == 0)
{
}
/* Init ENET PLL6 */
reg = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ |
CCM_ANALOG_PLL_ENET_ENET1_125M_EN |
CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN |
CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_ENET);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) &
CCM_ANALOG_PLL_ENET_LOCK) == 0)
{
}
#else
# error Unrecognised IMXRT family member for clock config
#endif
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_clockconfig
*
* Description:
* Called to initialize the i.MXRT. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void imxrt_clockconfig(void)
{
/* Don't change the current basic clock configuration if we are running
* from SDRAM. In this case, some bootloader logic has already configured
* clocking and SDRAM. We are pretty much committed to using things the
* way that the bootloader has left them.
*
* Note that although this is safe at boot while nothing is using
* the clocks additional caution is required if at some later date
* we want to manipulate the PODFs while the system is running
* (for power minimisation) because changing those is not glitch free.
*/
#ifndef CONFIG_IMXRT_BOOT_SDRAM
uint32_t reg;
/* Set clock mux and dividers */
/* Set PERIPH_CLK2 MUX to OSC */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
reg |= CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK;
putreg32(reg, IMXRT_CCM_CBCMR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) != 0)
{
}
/* Set PERIPH_CLK MUX to PERIPH_CLK2 */
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_PERIPH_CLK_SEL_MASK;
reg |= CCM_CBCDR_PERIPH_CLK_SEL(CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2);
putreg32(reg, IMXRT_CCM_CBCDR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0)
{
}
/* Set Soc VDD and wait for it to stablise */
reg = getreg32(IMXRT_DCDC_REG3);
reg &= ~(DCDC_REG3_TRG_MASK);
reg |= DCDC_REG3_TRG(IMXRT_VDD_SOC);
putreg32(reg, IMXRT_DCDC_REG3);
while ((getreg32(IMXRT_DCDC_REG0) & DCDC_REG0_STS_DC_OK) == 0)
{
}
/* OK, now nothing is depending on us, configure the PLLs */
imxrt_pllsetup();
/* Set Dividers */
reg = getreg32(IMXRT_CCM_CACRR);
reg &= ~CCM_CACRR_ARM_PODF_MASK;
reg |= CCM_CACRR_ARM_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_ARM_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CACRR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_ARM_PODF_BUSY) != 0)
{
}
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_AHB_PODF_MASK;
reg |= CCM_CBCDR_AHB_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_AHB_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CBCDR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_AHB_PODF_BUSY) != 0)
{
}
/* Adjust IPG and PERCLK PODFs. Consumers of these clocks will need to
* be gated if there are any (there aren't at boot).
*/
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_IPG_PODF_MASK;
reg |= CCM_CBCDR_IPG_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_IPG_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CBCDR);
reg = getreg32(IMXRT_CCM_CSCMR1);
reg &= ~CCM_CSCMR1_PERCLK_PODF_MASK;
reg |= CCM_CSCMR1_PERCLK_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_PERCLK_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CSCMR1);
#ifndef CONFIG_IMXRT_SEMC_INIT_DONE
/* Configure SEMC Clock only if not already done by DCD SDR */
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_SEMC_PODF_MASK;
reg |= CCM_CBCDR_SEMC_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_SEMC_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CBCDR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_SEMC_PODF_BUSY) != 0)
{
}
#endif
/* Set PRE_PERIPH_CLK to Board Selection */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
reg |= CCM_CBCMR_PRE_PERIPH_CLK_SEL(IMXRT_PRE_PERIPH_CLK_SEL);
putreg32(reg, IMXRT_CCM_CBCMR);
/* Set PERIPH_CLK MUX to Board Selection */
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_PERIPH_CLK_SEL_MASK;
reg |= CCM_CBCDR_PERIPH_CLK_SEL(IMXRT_PERIPH_CLK_SEL);
putreg32(reg, IMXRT_CCM_CBCDR);
/* Wait handshake */
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0)
{
}
/* Set PERCLK_CLK_SEL to Board Selection */
reg = getreg32(IMXRT_CCM_CSCMR1);
reg &= ~CCM_CSCMR1_PERCLK_CLK_SEL_MASK;
reg |= CCM_CSCMR1_PERCLK_CLK_SEL(IMXRT_PERCLK_CLK_SEL);
putreg32(reg, IMXRT_CCM_CSCMR1);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0)
{
}
/* Setup perhiperals. At this point these are not activated so don't
* need to worry too much about switching off the clock feeds.
*/
/* Set UART source to PLL3 80M */
reg = getreg32(IMXRT_CCM_CSCDR1);
reg &= ~CCM_CSCDR1_UART_CLK_SEL;
reg |= CCM_CSCDR1_UART_CLK_SEL_PLL3_80;
putreg32(reg, IMXRT_CCM_CSCDR1);
/* Set UART divider to 1 */
reg = getreg32(IMXRT_CCM_CSCDR1);
reg &= ~CCM_CSCDR1_UART_CLK_PODF_MASK;
reg |= CCM_CSCDR1_UART_CLK_PODF(CCM_PODF_FROM_DIVISOR(1));
putreg32(reg, IMXRT_CCM_CSCDR1);
#ifdef CONFIG_IMXRT_FLEXIO1
#ifdef CONFIG_ARCH_FAMILY_IMXRT102x
/* Set FlEXIO1 source */
reg = getreg32(IMXRT_CCM_CSCMR2);
reg &= ~CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK;
reg |= CCM_CSCMR2_FLEXIO1_CLK_SEL(CONFIG_FLEXIO1_CLK);
putreg32(reg, IMXRT_CCM_CSCMR2);
/* Set FlEXIO1 divider */
reg = getreg32(IMXRT_CCM_CS1CDR);
reg &= ~(CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK | \
CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK);
reg |= CCM_CS1CDR_FLEXIO1_CLK_PODF
(CCM_PODF_FROM_DIVISOR(CONFIG_FLEXIO1_PODF_DIVIDER));
reg |= CCM_CS1CDR_FLEXIO1_CLK_PRED
(CCM_PRED_FROM_DIVISOR(CONFIG_FLEXIO1_PRED_DIVIDER));
putreg32(reg, IMXRT_CCM_CS1CDR);
#elif (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
/* Set FlEXIO1 source & divider */
reg = getreg32(IMXRT_CCM_CDCDR);
reg &= ~(CCM_CDCDR_FLEXIO1_CLK_SEL_MASK |
CCM_CDCDR_FLEXIO1_CLK_PODF_MASK |
CCM_CDCDR_FLEXIO1_CLK_PRED_MASK);
reg |= CCM_CDCDR_FLEXIO1_CLK_SEL(CONFIG_FLEXIO1_CLK);
reg |= CCM_CDCDR_FLEXIO1_CLK_PODF
(CCM_PODF_FROM_DIVISOR(CONFIG_FLEXIO1_PODF_DIVIDER));
reg |= CCM_CDCDR_FLEXIO1_CLK_PRED
(CCM_PRED_FROM_DIVISOR(CONFIG_FLEXIO1_PRED_DIVIDER));
putreg32(reg, IMXRT_CCM_CDCDR);
#endif /* CONFIG_ARCH_FAMILY_IMXRT102x */
#endif /* CONFIG_IMXRT_FLEXIO1 */
#if (defined(CONFIG_IMXRT_FLEXIO2) || defined(CONFIG_IMXRT_FLEXIO3))
/* Set FlEXIO2 source */
reg = getreg32(IMXRT_CCM_CSCMR2);
reg &= ~CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK;
reg |= CCM_CSCMR2_FLEXIO2_CLK_SEL(CONFIG_FLEXIO2_CLK);
putreg32(reg, IMXRT_CCM_CSCMR2);
/* Set FlEXIO2 divider */
reg = getreg32(IMXRT_CCM_CS1CDR);
reg &= ~(CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK | \
CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK);
reg |= CCM_CS1CDR_FLEXIO2_CLK_PODF
(CCM_PODF_FROM_DIVISOR(CONFIG_FLEXIO2_PODF_DIVIDER));
reg |= CCM_CS1CDR_FLEXIO2_CLK_PRED
(CCM_PRED_FROM_DIVISOR(CONFIG_FLEXIO2_PRED_DIVIDER));
putreg32(reg, IMXRT_CCM_CS1CDR);
#endif /* CONFIG_IMXRT_FLEXIO2 */
#ifdef CONFIG_IMXRT_LPI2C
/* Set LPI2C source to PLL3 60M */
reg = getreg32(IMXRT_CCM_CSCDR2);
reg &= ~CCM_CSCDR2_LPI2C_CLK_SEL;
reg |= IMXRT_LPI2C_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CSCDR2);
/* Set LPI2C divider to 5 for 12 MHz */
reg = getreg32(IMXRT_CCM_CSCDR2);
reg &= ~CCM_CSCDR2_LPI2C_CLK_PODF_MASK;
reg |= CCM_CSCDR2_LPI2C_CLK_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_LSI2C_PODF_DIVIDER)
);
putreg32(reg, IMXRT_CCM_CSCDR2);
#endif
#ifdef CONFIG_IMXRT_FLEXCAN
/* Set FlexCAN clock source to PLL3 80M */
reg = getreg32(IMXRT_CCM_CSCMR2);
reg &= ~CCM_CSCMR2_CAN_CLK_SEL_MASK;
reg |= IMXRT_CAN_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CSCMR2);
/* Set FlexCAN dividet to 1 for 80 MHz */
reg = getreg32(IMXRT_CCM_CSCMR2);
reg &= ~CCM_CSCMR2_CAN_CLK_PODF_MASK;
reg |= CCM_CSCMR2_CAN_CLK_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_CAN_PODF_DIVIDER)
);
putreg32(reg, IMXRT_CCM_CSCMR2);
#endif
#ifdef CONFIG_IMXRT_LPSPI
/* Set LPSPI clock source to PLL3 PFD0 */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_LPSPI_CLK_SEL_MASK;
reg |= IMXRT_LPSPI_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CBCMR);
/* Set LPSPI divider to IMXRT_LSPI_PODF_DIVIDER */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_LPSPI_PODF_MASK;
reg |= CCM_CBCMR_LPSPI_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_LSPI_PODF_DIVIDER)
);
putreg32(reg, IMXRT_CCM_CBCMR);
#endif
#ifdef IMXRT_TRACE_PODF_DIVIDER
/* Set TRACE clock source and speed */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_TRACE_CLK_SEL_MASK;
reg |= IMXRT_TRACE_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CBCMR);
reg = getreg32(IMXRT_CCM_CSCDR1);
reg &= ~CCM_CSCDR1_TRACE_PODF_MASK;
reg |= CCM_CSCDR1_TRACE_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_TRACE_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CSCDR1);
#endif
#ifdef CONFIG_IMXRT_USDHC
/* Optionally set USDHC1 & 2 to generate clocks
* from IMXRT_USDHC1_CLK_SELECT
*/
reg = getreg32(IMXRT_CCM_CSCMR1);
reg &= ~(CCM_CSCMR1_USDHC1_CLK_SEL | CCM_CSCMR1_USDHC2_CLK_SEL);
#if defined(IMXRT_USDHC1_CLK_SELECT)
reg |= IMXRT_USDHC1_CLK_SELECT;
#endif
#if defined(IMXRT_USDHC2_CLK_SELECT)
reg |= IMXRT_USDHC2_CLK_SELECT;
#endif
putreg32(reg, IMXRT_CCM_CSCMR1);
/* Now divide down clocks by IMXRT_USDHC[1|2]_PODF_DIVIDER */
reg = getreg32(IMXRT_CCM_CSCDR1);
reg &= ~(CCM_CSCDR1_USDHC1_PODF_MASK | CCM_CSCDR1_USDHC2_PODF_MASK);
#if defined(IMXRT_USDHC1_PODF_DIVIDER)
reg |= CCM_CSCDR1_USDHC1_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_USDHC1_PODF_DIVIDER));
#endif
#if defined(IMXRT_USDHC2_PODF_DIVIDER)
reg |= CCM_CSCDR1_USDHC2_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_USDHC2_PODF_DIVIDER));
#endif
putreg32(reg, IMXRT_CCM_CSCDR1);
#endif
/* Ensure platform memory clocks remain enabled in WFI */
reg = getreg32(IMXRT_CCM_CGPR);
reg |= CCM_CGPR_INT_MEM_CLK_LPM;
putreg32(reg, IMXRT_CCM_CGPR);
/* Remain in run mode */
modifyreg32(IMXRT_CCM_CLPCR,
CCM_CLPCR_LPM_MASK,
CCM_CLPCR_LPM_RUN);
#endif
}

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/****************************************************************************
* arch/arm/src/imxrt/imxrt_lowputc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <fixedmath.h>
#include <assert.h>
#include "arm_arch.h"
#include "hardware/imxrt_iomuxc.h"
#include "hardware/imxrt_pinmux.h"
#include "hardware/imxrt_ccm.h"
#include "hardware/imxrt_lpuart.h"
#include "imxrt_config.h"
#include "imxrt_periphclks.h"
#include "imxrt_iomuxc.h"
#include "imxrt_gpio.h"
#include "imxrt_lowputc.h"
#include "arm_internal.h"
#include <arch/board/board.h> /* Include last: has dependencies */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifdef HAVE_LPUART_CONSOLE
# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART1_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART1_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART1_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART1_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART1_2STOP
# elif defined(CONFIG_LPUART2_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART2_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART2_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART2_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART2_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART2_2STOP
# elif defined(CONFIG_LPUART3_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART3_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART3_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART3_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART3_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART3_2STOP
# elif defined(CONFIG_LPUART4_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART4_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART4_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART4_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART4_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART4_2STOP
# elif defined(CONFIG_LPUART5_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART5_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART5_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART5_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART5_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART5_2STOP
# elif defined(CONFIG_LPUART6_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART6_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART6_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART6_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART6_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART6_2STOP
# elif defined(CONFIG_LPUART7_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART7_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART7_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART7_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART7_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART7_2STOP
# elif defined(CONFIG_LPUART8_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART8_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART8_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART8_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART8_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART8_2STOP
# endif
#endif
/* Clocking *****************************************************************/
/* The UART module receives two clocks, a peripheral_clock (ipg_clk) and the
* module_clock (ipg_perclk). The peripheral_clock is used as write clock
* of the TxFIFO, read clock of the RxFIFO and synchronization of the modem
* control input pins. It must always be running when UART is enabled.
*
* The default lpuart1 ipg_clk is 66MHz (max 66.5MHz). ipg_clk is shared
* among many modules and should not be controlled by the UART logic.
*
* The module_clock is for all the state machines, writing RxFIFO, reading
* TxFIFO, etc. It must always be running when UART is sending or receiving
* characters. This clock is used in order to allow frequency scaling on
* peripheral_clock without changing configuration of baud rate.
*
* The default ipg_perclk is 80MHz (max 80MHz). ipg_perclk is gated by
* CCGR5[CG12], lpuart1_clk_enable. The clock generation sequence is:
*
* pll3_sw_clk (480M) -> CCGR5[CG12] -> 3 bit divider cg podf=6 ->
* PLL3_80M (80Mhz) -> CDCDR1: lpuart1_clk_podf ->
* 6 bit divider default=1 -> LPUART1_CLK_ROOT
*
* REVISIT: This logic assumes that all dividers are at the default value
* and that the value of the ipg_perclk is 80MHz.
*/
#define IPG_PERCLK_FREQUENCY 80000000
/* The BRM sub-block receives ref_clk (module_clock clock after divider).
* From this clock, and with integer and non-integer division, BRM generates
* a 16x baud rate clock.
*/
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef HAVE_LPUART_CONSOLE
static const struct uart_config_s g_console_config =
{
.baud = IMXRT_CONSOLE_BAUD, /* Configured baud */
.parity = IMXRT_CONSOLE_PARITY, /* 0=none, 1=odd, 2=even */
.bits = IMXRT_CONSOLE_BITS, /* Number of bits (5-9) */
.stopbits2 = IMXRT_CONSOLE_2STOP, /* true: Configure with 2 stop bits instead of 1 */
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
void imxrt_lpuart_clock_enable (uint32_t base)
{
if (base == IMXRT_LPUART1_BASE)
{
imxrt_clockall_lpuart1();
}
else if (base == IMXRT_LPUART2_BASE)
{
imxrt_clockall_lpuart2();
}
else if (base == IMXRT_LPUART3_BASE)
{
imxrt_clockall_lpuart3();
}
else if (base == IMXRT_LPUART4_BASE)
{
imxrt_clockall_lpuart4();
}
else if (base == IMXRT_LPUART5_BASE)
{
imxrt_clockall_lpuart5();
}
else if (base == IMXRT_LPUART6_BASE)
{
imxrt_clockall_lpuart6();
}
else if (base == IMXRT_LPUART7_BASE)
{
imxrt_clockall_lpuart7();
}
else if (base == IMXRT_LPUART8_BASE)
{
imxrt_clockall_lpuart8();
}
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization including setup of the console UART. This UART done
* early so that the serial console is available for debugging very early
* in the boot sequence.
*
****************************************************************************/
void imxrt_lowsetup(void)
{
#ifndef CONFIG_SUPPRESS_LPUART_CONFIG
#ifdef HAVE_LPUART_DEVICE
#ifdef CONFIG_IMXRT_LPUART1
/* Configure LPUART1 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART1_RX);
imxrt_config_gpio(GPIO_LPUART1_TX);
#ifdef CONFIG_LPUART1_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART1_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART1_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART2
/* Configure LPUART2 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART2_RX);
imxrt_config_gpio(GPIO_LPUART2_TX);
#ifdef CONFIG_LPUART2_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART2_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART2_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART3
/* Configure LPUART3 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART3_RX);
imxrt_config_gpio(GPIO_LPUART3_TX);
#ifdef CONFIG_LPUART3_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART3_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART3_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART4
/* Configure LPUART4 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART4_RX);
imxrt_config_gpio(GPIO_LPUART4_TX);
#ifdef CONFIG_LPUART4_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART4_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART4_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART5
/* Configure LPUART5 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART5_RX);
imxrt_config_gpio(GPIO_LPUART5_TX);
#ifdef CONFIG_LPUART5_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART5_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART5_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART6
/* Configure LPUART6 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART6_RX);
imxrt_config_gpio(GPIO_LPUART6_TX);
#ifdef CONFIG_LPUART6_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART6_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART6_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART7
/* Configure LPUART7 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART7_RX);
imxrt_config_gpio(GPIO_LPUART7_TX);
#ifdef CONFIG_LPUART7_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART7_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART7_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART8
/* Configure LPUART8 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART8_RX);
imxrt_config_gpio(GPIO_LPUART8_TX);
#ifdef CONFIG_LPUART8_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART8_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART8_RTS);
#endif
#endif
#ifdef HAVE_LPUART_CONSOLE
/* Configure the serial console for initial, non-interrupt driver mode */
imxrt_lpuart_configure(IMXRT_CONSOLE_BASE, &g_console_config);
#endif
#endif /* HAVE_LPUART_DEVICE */
#endif /* CONFIG_SUPPRESS_LPUART_CONFIG */
}
/****************************************************************************
* Name: imxrt_lpuart_configure
*
* Description:
* Configure a UART for non-interrupt driven operation
*
****************************************************************************/
#ifdef HAVE_LPUART_DEVICE
int imxrt_lpuart_configure(uint32_t base,
FAR const struct uart_config_s *config)
{
uint32_t src_freq = 0;
uint32_t pll3_div = 0;
uint32_t uart_div = 0;
uint32_t lpuart_freq = 0;
uint16_t sbr;
uint16_t temp_sbr;
uint32_t osr;
uint32_t temp_osr;
uint32_t temp_diff;
uint32_t calculated_baud;
uint32_t baud_diff;
uint32_t regval;
uint32_t regval2;
if ((getreg32(IMXRT_CCM_CSCDR1) & CCM_CSCDR1_UART_CLK_SEL) != 0)
{
src_freq = BOARD_XTAL_FREQUENCY;
}
else
{
if ((getreg32(IMXRT_CCM_ANALOG_PLL_USB2) &
CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) != 0)
{
pll3_div = 22;
}
else
{
pll3_div = 20;
}
src_freq = (BOARD_XTAL_FREQUENCY * pll3_div) / 6;
}
uart_div = (getreg32(IMXRT_CCM_CSCDR1) &
CCM_CSCDR1_UART_CLK_PODF_MASK) + 1;
lpuart_freq = src_freq / uart_div;
/* This LPUART instantiation uses a slightly different baud rate
* calculation. The idea is to use the best OSR (over-sampling rate)
* possible.
*
* NOTE: OSR is typically hard-set to 16 in other LPUART instantiations
* loop to find the best OSR value possible, one that generates minimum
* baud_diff iterate through the rest of the supported values of OSR
*/
baud_diff = config->baud;
osr = 0;
sbr = 0;
for (temp_osr = 4; temp_osr <= 32; temp_osr++)
{
/* Calculate the temporary sbr value */
temp_sbr = (lpuart_freq / (config->baud * temp_osr));
/* Set temp_sbr to 1 if the sourceClockInHz can not satisfy the
* desired baud rate.
*/
if (temp_sbr == 0)
{
temp_sbr = 1;
}
/* Calculate the baud rate based on the temporary OSR and SBR values */
calculated_baud = (lpuart_freq / (temp_osr * temp_sbr));
temp_diff = calculated_baud - config->baud;
/* Select the better value between srb and (sbr + 1) */
if (temp_diff > (config->baud -
(lpuart_freq / (temp_osr * (temp_sbr + 1)))))
{
temp_diff = config->baud -
(lpuart_freq / (temp_osr * (temp_sbr + 1)));
temp_sbr++;
}
if (temp_diff <= baud_diff)
{
baud_diff = temp_diff;
osr = temp_osr;
sbr = temp_sbr;
}
}
if (baud_diff > ((config->baud / 100) * 3))
{
/* Unacceptable baud rate difference of more than 3% */
return ERROR;
}
/* Enable lpuart clock */
imxrt_lpuart_clock_enable(base);
/* Reset all internal logic and registers, except the Global Register */
regval = getreg32(base + IMXRT_LPUART_GLOBAL_OFFSET);
regval |= LPUART_GLOBAL_RST;
putreg32(regval, base + IMXRT_LPUART_GLOBAL_OFFSET);
regval &= ~LPUART_GLOBAL_RST;
putreg32(regval, base + IMXRT_LPUART_GLOBAL_OFFSET);
/* Construct MODIR register */
regval = 0;
if (config->userts)
{
regval |= LPUART_MODIR_RXRTSE;
}
else if (config->users485)
{
/* Both TX and RX side can't control RTS, so this gives
* the RX side precedence. This should have been filtered
* in layers above anyway, but it's just a precaution.
*/
regval |= LPUART_MODIR_TXRTSE;
}
if (config->usects)
{
regval |= LPUART_MODIR_TXCTSE;
}
if (config->invrts)
{
regval |= LPUART_MODIR_TXRTSPOL;
}
putreg32(regval, base + IMXRT_LPUART_MODIR_OFFSET);
regval = 0;
if ((osr > 3) && (osr < 8))
{
regval |= LPUART_BAUD_BOTHEDGE;
}
if (config->stopbits2)
{
regval |= LPUART_BAUD_SBNS;
}
regval |= LPUART_BAUD_OSR(osr) | LPUART_BAUD_SBR(sbr);
putreg32(regval, base + IMXRT_LPUART_BAUD_OFFSET);
regval = 0;
if (config->parity == 1)
{
regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_ODD;
}
else if (config->parity == 2)
{
regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_EVEN;
}
if (config->bits == 9 || (config->bits == 8 && config->parity != 0))
{
regval |= LPUART_CTRL_M;
}
else if ((config->bits == 8))
{
regval &= ~LPUART_CTRL_M;
}
else
{
/* Here should be added support of other bit modes. */
#warning missing logic
return ERROR;
}
regval2 = getreg32(base + IMXRT_LPUART_FIFO_OFFSET);
regval2 |= LPUART_FIFO_RXFLUSH | LPUART_FIFO_TXFLUSH |
LPUART_FIFO_RXFE | LPUART_FIFO_RXIDEN_1 | LPUART_FIFO_TXFE;
putreg32(regval2 , base + IMXRT_LPUART_FIFO_OFFSET);
regval |= LPUART_CTRL_RE | LPUART_CTRL_TE;
putreg32(regval, base + IMXRT_LPUART_CTRL_OFFSET);
return OK;
}
#endif /* HAVE_LPUART_DEVICE */
/****************************************************************************
* Name: imxrt_lowputc
*
* Description:
* Output a byte with as few system dependencies as possible. This will
* even work BEFORE the console is initialized if we are booting from U-
* Boot (and the same UART is used for the console, of course.)
*
****************************************************************************/
#if defined(HAVE_LPUART_DEVICE) && defined(CONFIG_DEBUG_FEATURES)
void imxrt_lowputc(int ch)
{
while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) == 0)
{
}
/* If the character to output is a newline, then pre-pend a carriage
* return
*/
if (ch == '\n')
{
/* Send the carriage return by writing it into the UART_TXD register. */
putreg32((uint32_t)'\r', IMXRT_CONSOLE_BASE +
IMXRT_LPUART_DATA_OFFSET);
/* Wait for the transmit register to be emptied. When the TXFE bit is
* non-zero, the TX Buffer FIFO is empty.
*/
while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) == 0)
{
}
}
/* Send the character by writing it into the UART_TXD register. */
putreg32((uint32_t)ch, IMXRT_CONSOLE_BASE + IMXRT_LPUART_DATA_OFFSET);
}
#endif

1997
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13
Ubiquitous/Nuttx_Fusion_XiUOS/readme.md
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@ -266,23 +266,22 @@ git clone https://git.trustie.net/xuos/kconfig-frontends.git
#### 在Nuttx\app_match_nuttx目录下执行
```shell
chmod +x build.sh
source build.sh
```
#### 执行完毕会跳转到Nuttx\nuttx目录，执行
```shell
sudo ./tools/configure.sh stm32f4discovery:nsh (应用内核一起编译)
./tools/configure.sh stm32f4discovery:nsh (应用内核一起编译)
sudo ./tools/configure.sh stm32f4discovery:kostest (应用内核分开编译)
./tools/configure.sh stm32f4discovery:kostest (应用内核分开编译)
视情况而定，如果需要前面加sudo
```
#### 然后执行
```shell
sudo make menuconfig
make menuconfig
```
##### 开启Nuttx Support CLOCK_MONOTONIC
@ -328,7 +327,9 @@ sudo make menuconfig
#### 在当前目录执行编译
```shell
sudo make -j8
make
或
make -j8
```
make时加上V=1参数可以看到较为详细的编译信息，但是编译过程会比较慢。最后在nuttx下会编译出一个nuttx.bin文件(应用内核一起编译)

380
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/.config Normal file
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@ -0,0 +1,380 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
CONFIG_ROOT_DIR="../../../.."
CONFIG_BSP_DIR="."
CONFIG_RT_Thread_DIR="../.."
CONFIG_RTT_DIR="../../rt-thread"
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_BIG_ENDIAN is not set
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M4=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
CONFIG_RT_USING_DFS_ROMFS=y
# CONFIG_RT_USING_DFS_RAMFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
CONFIG_RT_USING_CAN=y
# CONFIG_RT_CAN_USING_HDR is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
CONFIG_RT_USING_I2C=y
# CONFIG_RT_I2C_DEBUG is not set
CONFIG_RT_USING_I2C_BITOPS=y
# CONFIG_RT_I2C_BITOPS_DEBUG is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
CONFIG_RT_USING_SPI_MSD=y
CONFIG_RT_USING_SFUD=y
CONFIG_RT_SFUD_USING_SFDP=y
CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
# CONFIG_RT_SFUD_USING_QSPI is not set
CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
# CONFIG_RT_DEBUG_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
CONFIG_RT_USING_PTHREADS=y
CONFIG_PTHREAD_NUM_MAX=8
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F4=y
#
# Hardware Drivers Config
#
CONFIG_SOC_STM32F407ZG=y
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_CH438 is not set
CONFIG_BSP_USING_USB=y
CONFIG_BSP_USING_STM32_USBH=y
CONFIG_USB_BUS_NAME="usb"
CONFIG_USB_DRIVER_NAME="usb_drv"
CONFIG_USB_DEVICE_NAME="usb_dev"
# CONFIG_BSP_USING_RNG is not set
# CONFIG_BSP_USING_UDID is not set
#
# MicroPython
#
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# More Drivers
#
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_DRV_USING_OV2640 is not set
#
# APP_Framework
#
#
# Framework
#
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
CONFIG_ADD_XIZI_FETURES=y
# CONFIG_ADD_NUTTX_FETURES is not set
# CONFIG_ADD_RTTHREAD_FETURES is not set
# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
# CONFIG_SUPPORT_KNOWING_FRAMEWORK is not set
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
#
# Security
#
# CONFIG_CRYPTO is not set
#
# Applications
#
#
# config stack size and priority of main task
#
CONFIG_MAIN_KTASK_STACK_SIZE=1024
#
# ota app
#
# CONFIG_APPLICATION_OTA is not set
#
# test app
#
# CONFIG_USER_TEST is not set
#
# connection app
#
# CONFIG_APPLICATION_CONNECTION is not set
#
# control app
#
#
# knowing app
#
# CONFIG_APPLICATION_KNOWING is not set
#
# sensor app
#
# CONFIG_APPLICATION_SENSOR is not set
# CONFIG_USING_EMBEDDED_DATABASE_APP is not set
#
# lib
#
CONFIG_APP_SELECT_NEWLIB=y
# CONFIG_APP_SELECT_OTHER_LIB is not set
# CONFIG_LIB_USING_CJSON is not set
# CONFIG_LIB_USING_QUEUE is not set
# CONFIG_LIB_LV is not set
# CONFIG_USING_EMBEDDED_DATABASE is not set

243
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/.gitignore vendored Normal file
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@ -0,0 +1,243 @@
# this
*.map
*.dblite
*.bin
*.axf
*.old
*~
*.o
*.bak
*.dep
*.i
*.d
*.uimg
GPATH
GRTAGS
GTAGS
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h
# General
.DS_Store
.AppleDouble
.LSOverride
# Icon must end with two \r
Icon
# Thumbnails
._*
# Files that might appear in the root of a volume
.DocumentRevisions-V100
.fseventsd
.Spotlight-V100
.TemporaryItems
.Trashes
.VolumeIcon.icns
.com.apple.timemachine.donotpresent
# Directories potentially created on remote AFP share
.AppleDB
.AppleDesktop
Network Trash Folder
Temporary Items
.apdisk
# Byte-compiled / optimized / DLL files
__pycache__/
*.py[cod]
*$py.class
# C extensions
*.so
# Distribution / packaging
.Python
build/
develop-eggs/
dist/
downloads/
eggs/
.eggs/
lib/
lib64/
parts/
sdist/
var/
wheels/
share/python-wheels/
*.egg-info/
.installed.cfg
*.egg
MANIFEST
# PyInstaller
# Usually these files are written by a python script from a template
# before PyInstaller builds the exe, so as to inject date/other infos into it.
*.manifest
*.spec
# Installer logs
pip-log.txt
pip-delete-this-directory.txt
# Unit test / coverage reports
htmlcov/
.tox/
.nox/
.coverage
.coverage.*
.cache
nosetests.xml
coverage.xml
*.cover
*.py,cover
.hypothesis/
.pytest_cache/
cover/
# Translations
*.mo
*.pot
# Django stuff:
*.log
local_settings.py
db.sqlite3
db.sqlite3-journal
# Flask stuff:
instance/
.webassets-cache
# Scrapy stuff:
.scrapy
# Sphinx documentation
docs/_build/
# PyBuilder
.pybuilder/
target/
# Jupyter Notebook
.ipynb_checkpoints
# IPython
profile_default/
ipython_config.py
# pyenv
# For a library or package, you might want to ignore these files since the code is
# intended to run in multiple environments; otherwise, check them in:
# .python-version
# pipenv
# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
# However, in case of collaboration, if having platform-specific dependencies or dependencies
# having no cross-platform support, pipenv may install dependencies that don't work, or not
# install all needed dependencies.
#Pipfile.lock
# PEP 582; used by e.g. github.com/David-OConnor/pyflow
__pypackages__/
# Celery stuff
celerybeat-schedule
celerybeat.pid
# SageMath parsed files
*.sage.py
# Environments
.env
.venv
env/
venv/
ENV/
env.bak/
venv.bak/
# Spyder project settings
.spyderproject
.spyproject
# Rope project settings
.ropeproject
# mkdocs documentation
/site
# mypy
.mypy_cache/
.dmypy.json
dmypy.json
# Pyre type checker
.pyre/
# pytype static type analyzer
.pytype/
# Cython debug symbols
cython_debug/
# Prerequisites
*.d
# Object files
*.o
*.ko
*.obj
*.elf
# Linker output
*.ilk
*.map
*.exp
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
# Debug files
*.dSYM/
*.su
*.idb
*.pdb
# Kernel Module Compile Results
*.mod*
*.cmd
.tmp_versions/
modules.order
Module.symvers
Mkfile.old
dkms.con

29
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mainmenu "RT-Thread Configuration"
config ROOT_DIR
string
default "../../../.."
config BSP_DIR
string
default "."
config RT_Thread_DIR
string
default "../.."
config RTT_DIR
string
default "../../rt-thread"
config APP_DIR
string
default "../../../../APP_Framework"
source "$RTT_DIR/Kconfig"
source "$RTT_DIR/bsp/stm32/libraries/Kconfig"
source "board/Kconfig"
source "$RT_Thread_DIR/micropython/Kconfig"
source "$RT_Thread_DIR/app_match_rt-thread/Kconfig"
source "$ROOT_DIR/APP_Framework/Kconfig"

91
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# STM32F407最小系统板说明
采用ST公司的32位ARM-Cortex M4内核的STM32F407
## 以下为引脚硬件的连接表
## **W25q16(SPI1 )**
| 引脚 | 作用 | 引脚序号 | W25q16 |
| ---- | --------- | -------- | --------|
| PA5 | SPI1_SCK | 41 | CLK |
| PA6 | SPI1_MISO | 42 | DO |
| PA7 | SPI1_MOSI | 43 | DI |
| PB0 | SpiFlash_nCS | 46 | nCS |
## **CRF1278-L3(SPI2 )**
| 引脚 | 作用 | 引脚序号 | CRF1278 |
| ---- | --------- | -------- | --------|
| PB13 | SPI2_SCK | 74 | SCK |
| PC2 | SPI2_MISO | 28 | MISO |
| PC3 | SPI2_MOSI | 29 | MOSI |
| PC6 | LORA_nCS | 96 | NSS |
## **XPT2046(SPI3)**
| 引脚 | 作用 | 引脚序号 | XPT2046 |
| ---- | --------- | -------- | --------|
| PB3 | SPI3_SCK | 133 | DCLK |
| PB4 | SPI3_MISO | 134 | DOUT |
| PB5 | SPI3_MOSI | 135 | DIN |
| PG13 | T_nCS | 128 | CS |
## **sensor(I2C1)**
| PB6 | I2C_SCL |
| ---- | ---------- |
| PB7 | I2C_SDA |
## **TTL_debug(uart1)**
| 引脚 | 作用 | 引脚序号 | TTL_debug |
| ---- | ----------|------------ |--------- |
| PA9 | USART1_TX | 101 |USART1_RX |
| PA10 | USART1_RX | 102 |USART1_TX |
## **NB/4G(uart2)**
| 引脚 | 作用 | 引脚序号 | NB/4G |
| ---- | ----------|------------ |--------- |
| PA2 | USART2_TX | 36 |USART2_RX |
| PA3 | USART2_RX | 37 |USART2_TX |
## **Ethernet/WIFI(uart3)**
| 引脚 | 作用 | 引脚序号 | Ethernet/WIFI |
| ---- | ----------|------------ |------------- |
| PB10 | USART3_TX | 69 |UART0_RXD |
| PB11 | USART3_RX | 70 |UART0_TXD |
## **BT-HC08(uart4)**
| 引脚 | 作用 | 引脚序号 | BT-HC08 |
| -----------| ---------|------------ |--------- |
| PA0_WAKEUP | UART4_TX | 34 | RXD |
| PA1 | UART4_RX | 35 | TXD |
## **SD**
| 引脚 | 作用 | 引脚序号 | TF-01A |
| ---- | --------- | -------- | ---------|
| PC10 | SDIO_D2 | 114 | DATA2 |
| PC11 | SDIO_D3 | 115 | DATA3 |
| PD2 | SDIO_CMD | 116 | CMD |
| PC12 | SDIO_CK | 113 | CLK |
| PC8 | SDIO_D0 | 98 | DATA0 |
| PC9 | SDIO_D1 | 99 | DATA1 |
## **USB-HOST**
| 引脚 | 作用 | 引脚序号 | USB-S |
| -----------| --------- |------------ |------------|
| PA12 | USB_OTG_DP | 104 | USB_OTG_DP |
| PA11 | USB_OTG_DM | 103 | USB_OTG_DM |
## **CAN**
| 引脚 | 作用 | 引脚序号 | USB-S |
| -----------| --------- |------------ |---------|
| PB8 | CAN1_RX | 139 | CAN1_TX |
| PB9 | CAN1_TX | 140 | CAN1_RX |

15
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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

92
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import os
import sys
import rtconfig
import SCons
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../rt-thread')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
AddOption('--compiledb',
dest = 'compiledb',
action = 'store_true',
default = False,
help = 'generate compile_commands.json')
if GetOption('compiledb'):
if int(SCons.__version__.split('.')[0]) >= 4:
env['COMPILATIONDB_USE_ABSPATH'] = True
env.Tool('compilation_db')
env.CompilationDatabase('compile_commands.json')
else:
print('Warning: --compiledb only support on SCons 4.0+')
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
#if os.path.exists(SDK_ROOT + '/libraries'):
# libraries_path_prefix = SDK_ROOT + '/libraries'
#else:
# libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
libraries_path_prefix = RTT_ROOT + '/bsp/stm32/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
stm32_library = 'STM32F4xx_HAL'
rtconfig.BSP_LIBRARY_TYPE = stm32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
# include more drivers
objs.extend(SConscript(os.getcwd() + '/../../app_match_rt-thread/SConscript'))
# include APP_Framework/Framework
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Framework/SConscript'))
# include APP_Framework/Applications
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SConscript'))
# include APP_Framework/lib
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript'))
# include Ubiquitous/RT-Thread/micropython
objs.extend(SConscript(os.getcwd() + '/../../micropython/SConscript'))
# make a building
DoBuilding(TARGET, objs)

12
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/applications/SConscript Normal file
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import rtconfig
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd]
src = Split("""
main.c
""")
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

51
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/applications/main.c Normal file
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/*
* @Author: chunyexixiaoyu
* @Date: 2021-09-24 16:33:15
* @LastEditTime: 2021-09-24 15:48:30
* @LastEditors: Please set LastEditors
* @Description: In User Settings Edit
* @FilePath: \xiuos\Ubiquitous\RT_Thread\bsp\stm32f407-atk-coreboard\applications\main.c
*/
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#include <board.h>
#include <stdio.h>
#include <string.h>
#ifdef RT_USING_POSIX
#include <pthread.h>
#include <unistd.h>
#include <stdio.h>
#include <dfs_poll.h>
#include <dfs_posix.h>
#include <dfs.h>
#ifdef RT_USING_POSIX_TERMIOS
#include <posix_termios.h>
#endif
#endif
#define LED0_PIN GET_PIN(G, 15)
extern int FrameworkInit();
int main(void)
{
int count = 1;
rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
rt_thread_mdelay(100);
FrameworkInit();
printf("XIUOS stm32f4 build %s %s\n",__DATE__,__TIME__);
while (count++)
{
rt_pin_write(LED0_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED0_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}

43
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/applications/uart_test.c Normal file
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/*
* @Author: yongliang
* @Date: 2022-03-31 16:00:00
* @Description: uart_test code
* @FilePath: \xiuos\Ubiquitous\RT_Thread\aiit_board\stm32f407_mini_board\applications\uart_test.c
*/
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#include <board.h>
#include <stdio.h>
#include <string.h>
int main (void)
{
/*1.设置系统中断优先组*/
/*2.串口初始化*/
while(1)
{
if(USART_RX_STA&0X8000)
{
len =USART_RX_STA&0X3fff;
printf("发送的消息为:\r\n");
for(t=0;t<len;t++)
{
USART_SendData(USART1,USART_RX_BUF[T]);
}

17
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/CubeMX_Config/.mxproject Normal file
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441
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/CubeMX_Config/CubeMX_Config.ioc Normal file
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#MicroXplorer Configuration settings - do not modify
CAN1.CalculateTimeQuantum=380.95238095238096
CAN1.IPParameters=CalculateTimeQuantum
FSMC.IPParameters=WriteOperation1
FSMC.WriteOperation1=FSMC_WRITE_OPERATION_ENABLE
File.Version=6
GPIO.groupedBy=Group By Peripherals
KeepUserPlacement=false
Mcu.Family=STM32F4
Mcu.IP0=CAN1
Mcu.IP1=FSMC
Mcu.IP10=SPI3
Mcu.IP11=SYS
Mcu.IP12=TIM2
Mcu.IP13=TIM11
Mcu.IP14=TIM13
Mcu.IP15=TIM14
Mcu.IP16=UART4
Mcu.IP17=USART1
Mcu.IP18=USART2
Mcu.IP19=USART3
Mcu.IP2=I2C1
Mcu.IP3=IWDG
Mcu.IP4=NVIC
Mcu.IP5=RCC
Mcu.IP6=RTC
Mcu.IP7=SDIO
Mcu.IP8=SPI1
Mcu.IP9=SPI2
Mcu.IPNb=20
Mcu.Name=STM32F407Z(E-G)Tx
Mcu.Package=LQFP144
Mcu.Pin0=PC14-OSC32_IN
Mcu.Pin1=PC15-OSC32_OUT
Mcu.Pin10=PC2
Mcu.Pin11=PC3
Mcu.Pin12=PA0-WKUP
Mcu.Pin13=PA1
Mcu.Pin14=PA2
Mcu.Pin15=PA3
Mcu.Pin16=PA5
Mcu.Pin17=PA6
Mcu.Pin18=PA7
Mcu.Pin19=PF12
Mcu.Pin2=PF0
Mcu.Pin20=PF13
Mcu.Pin21=PF14
Mcu.Pin22=PF15
Mcu.Pin23=PG0
Mcu.Pin24=PG1
Mcu.Pin25=PE7
Mcu.Pin26=PE8
Mcu.Pin27=PE9
Mcu.Pin28=PE10
Mcu.Pin29=PE11
Mcu.Pin3=PF1
Mcu.Pin30=PE12
Mcu.Pin31=PE13
Mcu.Pin32=PE14
Mcu.Pin33=PE15
Mcu.Pin34=PB10
Mcu.Pin35=PB11
Mcu.Pin36=PB13
Mcu.Pin37=PD8
Mcu.Pin38=PD9
Mcu.Pin39=PD10
Mcu.Pin4=PF2
Mcu.Pin40=PD11
Mcu.Pin41=PD12
Mcu.Pin42=PD13
Mcu.Pin43=PD14
Mcu.Pin44=PD15
Mcu.Pin45=PG2
Mcu.Pin46=PG3
Mcu.Pin47=PG4
Mcu.Pin48=PG5
Mcu.Pin49=PC8
Mcu.Pin5=PF3
Mcu.Pin50=PC9
Mcu.Pin51=PA9
Mcu.Pin52=PA10
Mcu.Pin53=PA13
Mcu.Pin54=PA14
Mcu.Pin55=PC10
Mcu.Pin56=PC11
Mcu.Pin57=PC12
Mcu.Pin58=PD0
Mcu.Pin59=PD1
Mcu.Pin6=PF4
Mcu.Pin60=PD2
Mcu.Pin61=PD4
Mcu.Pin62=PD5
Mcu.Pin63=PG10
Mcu.Pin64=PG11
Mcu.Pin65=PG12
Mcu.Pin66=PG13
Mcu.Pin67=PG14
Mcu.Pin68=PB3
Mcu.Pin69=PB4
Mcu.Pin7=PF5
Mcu.Pin70=PB5
Mcu.Pin71=PB6
Mcu.Pin72=PB7
Mcu.Pin73=PB8
Mcu.Pin74=PB9
Mcu.Pin75=PE0
Mcu.Pin76=PE1
Mcu.Pin77=VP_IWDG_VS_IWDG
Mcu.Pin78=VP_RTC_VS_RTC_Activate
Mcu.Pin79=VP_SYS_VS_Systick
Mcu.Pin8=PH0-OSC_IN
Mcu.Pin80=VP_TIM2_VS_ClockSourceINT
Mcu.Pin81=VP_TIM11_VS_ClockSourceINT
Mcu.Pin82=VP_TIM13_VS_ClockSourceINT
Mcu.Pin83=VP_TIM14_VS_ClockSourceINT
Mcu.Pin9=PH1-OSC_OUT
Mcu.PinsNb=84
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F407ZGTx
MxCube.Version=5.6.0
MxDb.Version=DB.5.0.60
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
PA0-WKUP.Locked=true
PA0-WKUP.Mode=Asynchronous
PA0-WKUP.Signal=UART4_TX
PA1.Locked=true
PA1.Mode=Asynchronous
PA1.Signal=UART4_RX
PA10.Mode=Asynchronous
PA10.Signal=USART1_RX
PA13.Mode=Serial_Wire
PA13.Signal=SYS_JTMS-SWDIO
PA14.Mode=Serial_Wire
PA14.Signal=SYS_JTCK-SWCLK
PA2.Locked=true
PA2.Mode=Asynchronous
PA2.Signal=USART2_TX
PA3.Locked=true
PA3.Mode=Asynchronous
PA3.Signal=USART2_RX
PA5.Locked=true
PA5.Mode=Full_Duplex_Master
PA5.Signal=SPI1_SCK
PA6.Locked=true
PA6.Mode=Full_Duplex_Master
PA6.Signal=SPI1_MISO
PA7.Locked=true
PA7.Mode=Full_Duplex_Master
PA7.Signal=SPI1_MOSI
PA9.Mode=Asynchronous
PA9.Signal=USART1_TX
PB10.Mode=Asynchronous
PB10.Signal=USART3_TX
PB11.Mode=Asynchronous
PB11.Signal=USART3_RX
PB13.Mode=Full_Duplex_Master
PB13.Signal=SPI2_SCK
PB3.Locked=true
PB3.Mode=Full_Duplex_Master
PB3.Signal=SPI3_SCK
PB4.Locked=true
PB4.Mode=Full_Duplex_Master
PB4.Signal=SPI3_MISO
PB5.Locked=true
PB5.Mode=Full_Duplex_Master
PB5.Signal=SPI3_MOSI
PB6.Locked=true
PB6.Mode=I2C
PB6.Signal=I2C1_SCL
PB7.Locked=true
PB7.Mode=I2C
PB7.Signal=I2C1_SDA
PB8.Mode=Master
PB8.Signal=CAN1_RX
PB9.Locked=true
PB9.Mode=Master
PB9.Signal=CAN1_TX
PC10.Mode=SD_4_bits_Wide_bus
PC10.Signal=SDIO_D2
PC11.Mode=SD_4_bits_Wide_bus
PC11.Signal=SDIO_D3
PC12.Mode=SD_4_bits_Wide_bus
PC12.Signal=SDIO_CK
PC14-OSC32_IN.Mode=LSE-External-Oscillator
PC14-OSC32_IN.Signal=RCC_OSC32_IN
PC15-OSC32_OUT.Mode=LSE-External-Oscillator
PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
PC2.Mode=Full_Duplex_Master
PC2.Signal=SPI2_MISO
PC3.Mode=Full_Duplex_Master
PC3.Signal=SPI2_MOSI
PC8.Mode=SD_4_bits_Wide_bus
PC8.Signal=SDIO_D0
PC9.Mode=SD_4_bits_Wide_bus
PC9.Signal=SDIO_D1
PD0.Signal=FSMC_D2_DA2
PD1.Signal=FSMC_D3_DA3
PD10.Signal=FSMC_D15_DA15
PD11.Signal=FSMC_A16_CLE
PD12.Signal=FSMC_A17_ALE
PD13.Signal=FSMC_A18
PD14.Signal=FSMC_D0_DA0
PD15.Signal=FSMC_D1_DA1
PD2.Mode=SD_4_bits_Wide_bus
PD2.Signal=SDIO_CMD
PD4.Signal=FSMC_NOE
PD5.Signal=FSMC_NWE
PD8.Signal=FSMC_D13_DA13
PD9.Signal=FSMC_D14_DA14
PE0.Signal=FSMC_NBL0
PE1.Signal=FSMC_NBL1
PE10.Signal=FSMC_D7_DA7
PE11.Signal=FSMC_D8_DA8
PE12.Signal=FSMC_D9_DA9
PE13.Signal=FSMC_D10_DA10
PE14.Signal=FSMC_D11_DA11
PE15.Signal=FSMC_D12_DA12
PE7.Signal=FSMC_D4_DA4
PE8.Signal=FSMC_D5_DA5
PE9.Signal=FSMC_D6_DA6
PF0.Signal=FSMC_A0
PF1.Signal=FSMC_A1
PF12.Signal=FSMC_A6
PF13.Signal=FSMC_A7
PF14.Signal=FSMC_A8
PF15.Signal=FSMC_A9
PF2.Signal=FSMC_A2
PF3.Signal=FSMC_A3
PF4.Signal=FSMC_A4
PF5.Signal=FSMC_A5
PG0.Signal=FSMC_A10
PG1.Signal=FSMC_A11
PG10.Mode=NorPsramChipSelect3_1
PG10.Signal=FSMC_NE3
PG11.Locked=true
PG11.Signal=GPIO_Output
PG12.Locked=true
PG12.Signal=FSMC_NE4
PG13.Locked=true
PG13.Signal=ETH_TXD0
PG14.Locked=true
PG14.Signal=GPIO_Output
PG2.Signal=FSMC_A12
PG3.Signal=FSMC_A13
PG4.Signal=FSMC_A14
PG5.Signal=FSMC_A15
PH0-OSC_IN.Mode=HSE-External-Oscillator
PH0-OSC_IN.Signal=RCC_OSC_IN
PH1-OSC_OUT.Mode=HSE-External-Oscillator
PH1-OSC_OUT.Signal=RCC_OSC_OUT
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32F407ZGTx
ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=0
ProjectManager.MainLocation=Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=CubeMX_Config.ioc
ProjectManager.ProjectName=CubeMX_Config
ProjectManager.RegisterCallBack=
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_RTC_Init-RTC-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_TIM14_Init-TIM14-false-HAL-true,8-MX_TIM13_Init-TIM13-false-HAL-true,9-MX_TIM11_Init-TIM11-false-HAL-true,10-MX_SDIO_SD_Init-SDIO-false-HAL-true,11-MX_TIM2_Init-TIM2-false-HAL-true,12-MX_SPI2_Init-SPI2-false-HAL-true,13-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,14-MX_FSMC_Init-FSMC-false-HAL-true,15-MX_UART4_Init-UART4-false-HAL-true,16-MX_USART2_UART_Init-USART2-false-HAL-true,17-MX_CAN1_Init-CAN1-false-HAL-true
RCC.48MHZClocksFreq_Value=48000000
RCC.AHBFreq_Value=168000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
RCC.APB1Freq_Value=42000000
RCC.APB1TimFreq_Value=84000000
RCC.APB2CLKDivider=RCC_HCLK_DIV2
RCC.APB2Freq_Value=84000000
RCC.APB2TimFreq_Value=168000000
RCC.CortexFreq_Value=168000000
RCC.EthernetFreq_Value=168000000
RCC.FCLKCortexFreq_Value=168000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=168000000
RCC.HSE_VALUE=8000000
RCC.HSI_VALUE=16000000
RCC.I2SClocksFreq_Value=192000000
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
RCC.LSI_VALUE=32000
RCC.MCO2PinFreq_Value=168000000
RCC.PLLCLKFreq_Value=168000000
RCC.PLLM=4
RCC.PLLN=168
RCC.PLLQ=7
RCC.PLLQCLKFreq_Value=48000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE
RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE
RCC.RTCFreq_Value=32768
RCC.RTCHSEDivFreq_Value=4000000
RCC.SYSCLKFreq_VALUE=168000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.VCOI2SOutputFreq_Value=384000000
RCC.VCOInputFreq_Value=2000000
RCC.VCOOutputFreq_Value=336000000
RCC.VcooutputI2S=192000000
SH.FSMC_A0.0=FSMC_A0,19b-a1
SH.FSMC_A0.ConfNb=1
SH.FSMC_A1.0=FSMC_A1,19b-a1
SH.FSMC_A1.ConfNb=1
SH.FSMC_A10.0=FSMC_A10,19b-a1
SH.FSMC_A10.ConfNb=1
SH.FSMC_A11.0=FSMC_A11,19b-a1
SH.FSMC_A11.ConfNb=1
SH.FSMC_A12.0=FSMC_A12,19b-a1
SH.FSMC_A12.ConfNb=1
SH.FSMC_A13.0=FSMC_A13,19b-a1
SH.FSMC_A13.ConfNb=1
SH.FSMC_A14.0=FSMC_A14,19b-a1
SH.FSMC_A14.ConfNb=1
SH.FSMC_A15.0=FSMC_A15,19b-a1
SH.FSMC_A15.ConfNb=1
SH.FSMC_A16_CLE.0=FSMC_A16,19b-a1
SH.FSMC_A16_CLE.ConfNb=1
SH.FSMC_A17_ALE.0=FSMC_A17,19b-a1
SH.FSMC_A17_ALE.ConfNb=1
SH.FSMC_A18.0=FSMC_A18,19b-a1
SH.FSMC_A18.ConfNb=1
SH.FSMC_A2.0=FSMC_A2,19b-a1
SH.FSMC_A2.ConfNb=1
SH.FSMC_A3.0=FSMC_A3,19b-a1
SH.FSMC_A3.ConfNb=1
SH.FSMC_A4.0=FSMC_A4,19b-a1
SH.FSMC_A4.ConfNb=1
SH.FSMC_A5.0=FSMC_A5,19b-a1
SH.FSMC_A5.ConfNb=1
SH.FSMC_A6.0=FSMC_A6,19b-a1
SH.FSMC_A6.ConfNb=1
SH.FSMC_A7.0=FSMC_A7,19b-a1
SH.FSMC_A7.ConfNb=1
SH.FSMC_A8.0=FSMC_A8,19b-a1
SH.FSMC_A8.ConfNb=1
SH.FSMC_A9.0=FSMC_A9,19b-a1
SH.FSMC_A9.ConfNb=1
SH.FSMC_D0_DA0.0=FSMC_D0,16b-d1
SH.FSMC_D0_DA0.ConfNb=1
SH.FSMC_D10_DA10.0=FSMC_D10,16b-d1
SH.FSMC_D10_DA10.ConfNb=1
SH.FSMC_D11_DA11.0=FSMC_D11,16b-d1
SH.FSMC_D11_DA11.ConfNb=1
SH.FSMC_D12_DA12.0=FSMC_D12,16b-d1
SH.FSMC_D12_DA12.ConfNb=1
SH.FSMC_D13_DA13.0=FSMC_D13,16b-d1
SH.FSMC_D13_DA13.ConfNb=1
SH.FSMC_D14_DA14.0=FSMC_D14,16b-d1
SH.FSMC_D14_DA14.ConfNb=1
SH.FSMC_D15_DA15.0=FSMC_D15,16b-d1
SH.FSMC_D15_DA15.ConfNb=1
SH.FSMC_D1_DA1.0=FSMC_D1,16b-d1
SH.FSMC_D1_DA1.ConfNb=1
SH.FSMC_D2_DA2.0=FSMC_D2,16b-d1
SH.FSMC_D2_DA2.ConfNb=1
SH.FSMC_D3_DA3.0=FSMC_D3,16b-d1
SH.FSMC_D3_DA3.ConfNb=1
SH.FSMC_D4_DA4.0=FSMC_D4,16b-d1
SH.FSMC_D4_DA4.ConfNb=1
SH.FSMC_D5_DA5.0=FSMC_D5,16b-d1
SH.FSMC_D5_DA5.ConfNb=1
SH.FSMC_D6_DA6.0=FSMC_D6,16b-d1
SH.FSMC_D6_DA6.ConfNb=1
SH.FSMC_D7_DA7.0=FSMC_D7,16b-d1
SH.FSMC_D7_DA7.ConfNb=1
SH.FSMC_D8_DA8.0=FSMC_D8,16b-d1
SH.FSMC_D8_DA8.ConfNb=1
SH.FSMC_D9_DA9.0=FSMC_D9,16b-d1
SH.FSMC_D9_DA9.ConfNb=1
SH.FSMC_NBL0.0=FSMC_NBL0,2ByteEnable1
SH.FSMC_NBL0.ConfNb=1
SH.FSMC_NBL1.0=FSMC_NBL1,2ByteEnable1
SH.FSMC_NBL1.ConfNb=1
SH.FSMC_NOE.0=FSMC_NOE,Sram1
SH.FSMC_NOE.ConfNb=1
SH.FSMC_NWE.0=FSMC_NWE,Sram1
SH.FSMC_NWE.ConfNb=1
SPI1.CalculateBaudRate=42.0 MBits/s
SPI1.Direction=SPI_DIRECTION_2LINES
SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
SPI1.Mode=SPI_MODE_MASTER
SPI1.VirtualType=VM_MASTER
SPI2.CalculateBaudRate=21.0 MBits/s
SPI2.Direction=SPI_DIRECTION_2LINES
SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
SPI2.Mode=SPI_MODE_MASTER
SPI2.VirtualType=VM_MASTER
SPI3.CalculateBaudRate=21.0 MBits/s
SPI3.Direction=SPI_DIRECTION_2LINES
SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
SPI3.Mode=SPI_MODE_MASTER
SPI3.VirtualType=VM_MASTER
UART4.IPParameters=VirtualMode
UART4.VirtualMode=Asynchronous
USART1.IPParameters=VirtualMode
USART1.VirtualMode=VM_ASYNC
USART2.IPParameters=VirtualMode
USART2.VirtualMode=VM_ASYNC
USART3.IPParameters=VirtualMode
USART3.VirtualMode=VM_ASYNC
VP_IWDG_VS_IWDG.Mode=IWDG_Activate
VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
VP_TIM11_VS_ClockSourceINT.Mode=Enable_Timer
VP_TIM11_VS_ClockSourceINT.Signal=TIM11_VS_ClockSourceINT
VP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer
VP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT
VP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer
VP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT
VP_TIM2_VS_ClockSourceINT.Mode=Internal
VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT
board=custom

91
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
** This notice applies to any and all portions of this file
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include <rtthread.h>
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

442
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/**
******************************************************************************
* @file stm32f4xx_hal_conf_template.h
* @author MCD Application Team
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f4xx_hal_conf.h.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */
#define HAL_CAN_MODULE_ENABLED
/* #define HAL_CRC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_DAC_MODULE_ENABLED */
/* #define HAL_DCMI_MODULE_ENABLED */
/* #define HAL_DMA2D_MODULE_ENABLED */
/* #define HAL_ETH_MODULE_ENABLED */
/* #define HAL_NAND_MODULE_ENABLED */
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_PCCARD_MODULE_ENABLED */
#define HAL_SRAM_MODULE_ENABLED
/* #define HAL_SDRAM_MODULE_ENABLED */
/* #define HAL_HASH_MODULE_ENABLED */
#define HAL_I2C_MODULE_ENABLED
/* #define HAL_I2S_MODULE_ENABLED */
#define HAL_IWDG_MODULE_ENABLED
/* #define HAL_LTDC_MODULE_ENABLED */
/* #define HAL_RNG_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
#define HAL_SD_MODULE_ENABLED
/* #define HAL_MMC_MODULE_ENABLED */
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
/* #define HAL_USART_MODULE_ENABLED */
/* #define HAL_IRDA_MODULE_ENABLED */
/* #define HAL_SMARTCARD_MODULE_ENABLED */
/* #define HAL_SMBUS_MODULE_ENABLED */
/* #define HAL_WWDG_MODULE_ENABLED */
/* #define HAL_PCD_MODULE_ENABLED */
/* #define HAL_HCD_MODULE_ENABLED */
/* #define HAL_DSI_MODULE_ENABLED */
/* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_FMPI2C_MODULE_ENABLED */
/* #define HAL_SPDIFRX_MODULE_ENABLED */
/* #define HAL_DFSDM_MODULE_ENABLED */
/* #define HAL_LPTIM_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2U
#define MAC_ADDR1 0U
#define MAC_ADDR2 0U
#define MAC_ADDR3 0U
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848_PHY_ADDRESS Address*/
#define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32f4xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32f4xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f4xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32f4xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32f4xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32f4xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f4xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_FMPI2C_MODULE_ENABLED
#include "stm32f4xx_hal_fmpi2c.h"
#endif /* HAL_FMPI2C_MODULE_ENABLED */
#ifdef HAL_SPDIFRX_MODULE_ENABLED
#include "stm32f4xx_hal_spdifrx.h"
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32f4xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32f4xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f4xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_IT_H
#define __STM32F4xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
** This notice applies to any and all portions of this file
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
CAN_HandleTypeDef hcan1;
I2C_HandleTypeDef hi2c1;
IWDG_HandleTypeDef hiwdg;
RTC_HandleTypeDef hrtc;
SD_HandleTypeDef hsd;
SPI_HandleTypeDef hspi1;
SPI_HandleTypeDef hspi2;
SPI_HandleTypeDef hspi3;
TIM_HandleTypeDef htim2;
TIM_HandleTypeDef htim11;
TIM_HandleTypeDef htim13;
TIM_HandleTypeDef htim14;
UART_HandleTypeDef huart4;
UART_HandleTypeDef huart1;
UART_HandleTypeDef huart2;
UART_HandleTypeDef huart3;
SRAM_HandleTypeDef hsram1;
/* USER CODE BEGIN PV */
/* Private variables ---------------------------------------------------------*/
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_USART1_UART_Init(void);
static void MX_USART3_UART_Init(void);
static void MX_RTC_Init(void);
static void MX_IWDG_Init(void);
static void MX_TIM14_Init(void);
static void MX_TIM13_Init(void);
static void MX_TIM11_Init(void);
static void MX_SDIO_SD_Init(void);
static void MX_TIM2_Init(void);
static void MX_SPI2_Init(void);
static void MX_FSMC_Init(void);
static void MX_UART4_Init(void);
static void MX_USART2_UART_Init(void);
static void MX_CAN1_Init(void);
static void MX_I2C1_Init(void);
static void MX_SPI1_Init(void);
static void MX_SPI3_Init(void);
/* USER CODE BEGIN PFP */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_USART1_UART_Init();
MX_USART3_UART_Init();
MX_RTC_Init();
MX_IWDG_Init();
MX_TIM14_Init();
MX_TIM13_Init();
MX_TIM11_Init();
MX_SDIO_SD_Init();
MX_TIM2_Init();
MX_SPI2_Init();
MX_FSMC_Init();
MX_UART4_Init();
MX_USART2_UART_Init();
MX_CAN1_Init();
MX_I2C1_Init();
MX_SPI1_Init();
MX_SPI3_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
|RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 4;
RCC_OscInitStruct.PLL.PLLN = 168;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 7;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
{
Error_Handler();
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief CAN1 Initialization Function
* @param None
* @retval None
*/
static void MX_CAN1_Init(void)
{
/* USER CODE BEGIN CAN1_Init 0 */
/* USER CODE END CAN1_Init 0 */
/* USER CODE BEGIN CAN1_Init 1 */
/* USER CODE END CAN1_Init 1 */
hcan1.Instance = CAN1;
hcan1.Init.Prescaler = 16;
hcan1.Init.Mode = CAN_MODE_NORMAL;
hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ;
hcan1.Init.TimeSeg1 = CAN_BS1_1TQ;
hcan1.Init.TimeSeg2 = CAN_BS2_1TQ;
hcan1.Init.TimeTriggeredMode = DISABLE;
hcan1.Init.AutoBusOff = DISABLE;
hcan1.Init.AutoWakeUp = DISABLE;
hcan1.Init.AutoRetransmission = DISABLE;
hcan1.Init.ReceiveFifoLocked = DISABLE;
hcan1.Init.TransmitFifoPriority = DISABLE;
if (HAL_CAN_Init(&hcan1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN CAN1_Init 2 */
/* USER CODE END CAN1_Init 2 */
}
/**
* @brief I2C1 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C1_Init(void)
{
/* USER CODE BEGIN I2C1_Init 0 */
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
hi2c1.Init.ClockSpeed = 100000;
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
hi2c1.Init.OwnAddress1 = 0;
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
hi2c1.Init.OwnAddress2 = 0;
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
/**
* @brief IWDG Initialization Function
* @param None
* @retval None
*/
static void MX_IWDG_Init(void)
{
/* USER CODE BEGIN IWDG_Init 0 */
/* USER CODE END IWDG_Init 0 */
/* USER CODE BEGIN IWDG_Init 1 */
/* USER CODE END IWDG_Init 1 */
hiwdg.Instance = IWDG;
hiwdg.Init.Prescaler = IWDG_PRESCALER_4;
hiwdg.Init.Reload = 4095;
if (HAL_IWDG_Init(&hiwdg) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN IWDG_Init 2 */
/* USER CODE END IWDG_Init 2 */
}
/**
* @brief RTC Initialization Function
* @param None
* @retval None
*/
static void MX_RTC_Init(void)
{
/* USER CODE BEGIN RTC_Init 0 */
/* USER CODE END RTC_Init 0 */
/* USER CODE BEGIN RTC_Init 1 */
/* USER CODE END RTC_Init 1 */
/** Initialize RTC Only
*/
hrtc.Instance = RTC;
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
hrtc.Init.AsynchPrediv = 127;
hrtc.Init.SynchPrediv = 255;
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
if (HAL_RTC_Init(&hrtc) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN RTC_Init 2 */
/* USER CODE END RTC_Init 2 */
}
/**
* @brief SDIO Initialization Function
* @param None
* @retval None
*/
static void MX_SDIO_SD_Init(void)
{
/* USER CODE BEGIN SDIO_Init 0 */
/* USER CODE END SDIO_Init 0 */
/* USER CODE BEGIN SDIO_Init 1 */
/* USER CODE END SDIO_Init 1 */
hsd.Instance = SDIO;
hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
hsd.Init.BusWide = SDIO_BUS_WIDE_1B;
hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
hsd.Init.ClockDiv = 0;
if (HAL_SD_Init(&hsd) != HAL_OK)
{
Error_Handler();
}
if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SDIO_Init 2 */
/* USER CODE END SDIO_Init 2 */
}
/**
* @brief SPI1 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI1_Init(void)
{
/* USER CODE BEGIN SPI1_Init 0 */
/* USER CODE END SPI1_Init 0 */
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
hspi1.Init.Mode = SPI_MODE_MASTER;
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi1.Init.NSS = SPI_NSS_SOFT;
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi1.Init.CRCPolynomial = 10;
if (HAL_SPI_Init(&hspi1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
/**
* @brief SPI2 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI2_Init(void)
{
/* USER CODE BEGIN SPI2_Init 0 */
/* USER CODE END SPI2_Init 0 */
/* USER CODE BEGIN SPI2_Init 1 */
/* USER CODE END SPI2_Init 1 */
/* SPI2 parameter configuration*/
hspi2.Instance = SPI2;
hspi2.Init.Mode = SPI_MODE_MASTER;
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi2.Init.NSS = SPI_NSS_SOFT;
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi2.Init.CRCPolynomial = 10;
if (HAL_SPI_Init(&hspi2) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SPI2_Init 2 */
/* USER CODE END SPI2_Init 2 */
}
/**
* @brief SPI3 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI3_Init(void)
{
/* USER CODE BEGIN SPI3_Init 0 */
/* USER CODE END SPI3_Init 0 */
/* USER CODE BEGIN SPI3_Init 1 */
/* USER CODE END SPI3_Init 1 */
/* SPI3 parameter configuration*/
hspi3.Instance = SPI3;
hspi3.Init.Mode = SPI_MODE_MASTER;
hspi3.Init.Direction = SPI_DIRECTION_2LINES;
hspi3.Init.DataSize = SPI_DATASIZE_8BIT;
hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi3.Init.NSS = SPI_NSS_SOFT;
hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi3.Init.TIMode = SPI_TIMODE_DISABLE;
hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi3.Init.CRCPolynomial = 10;
if (HAL_SPI_Init(&hspi3) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SPI3_Init 2 */
/* USER CODE END SPI3_Init 2 */
}
/**
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
TIM_MasterConfigTypeDef sMasterConfig = {0};
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
htim2.Init.Prescaler = 0;
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
htim2.Init.Period = 0;
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
{
Error_Handler();
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
}
/**
* @brief TIM11 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM11_Init(void)
{
/* USER CODE BEGIN TIM11_Init 0 */
/* USER CODE END TIM11_Init 0 */
/* USER CODE BEGIN TIM11_Init 1 */
/* USER CODE END TIM11_Init 1 */
htim11.Instance = TIM11;
htim11.Init.Prescaler = 0;
htim11.Init.CounterMode = TIM_COUNTERMODE_UP;
htim11.Init.Period = 0;
htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim11) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM11_Init 2 */
/* USER CODE END TIM11_Init 2 */
}
/**
* @brief TIM13 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM13_Init(void)
{
/* USER CODE BEGIN TIM13_Init 0 */
/* USER CODE END TIM13_Init 0 */
/* USER CODE BEGIN TIM13_Init 1 */
/* USER CODE END TIM13_Init 1 */
htim13.Instance = TIM13;
htim13.Init.Prescaler = 0;
htim13.Init.CounterMode = TIM_COUNTERMODE_UP;
htim13.Init.Period = 0;
htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim13.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim13) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM13_Init 2 */
/* USER CODE END TIM13_Init 2 */
}
/**
* @brief TIM14 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM14_Init(void)
{
/* USER CODE BEGIN TIM14_Init 0 */
/* USER CODE END TIM14_Init 0 */
/* USER CODE BEGIN TIM14_Init 1 */
/* USER CODE END TIM14_Init 1 */
htim14.Instance = TIM14;
htim14.Init.Prescaler = 0;
htim14.Init.CounterMode = TIM_COUNTERMODE_UP;
htim14.Init.Period = 0;
htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim14) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM14_Init 2 */
/* USER CODE END TIM14_Init 2 */
}
/**
* @brief UART4 Initialization Function
* @param None
* @retval None
*/
static void MX_UART4_Init(void)
{
/* USER CODE BEGIN UART4_Init 0 */
/* USER CODE END UART4_Init 0 */
/* USER CODE BEGIN UART4_Init 1 */
/* USER CODE END UART4_Init 1 */
huart4.Instance = UART4;
huart4.Init.BaudRate = 115200;
huart4.Init.WordLength = UART_WORDLENGTH_8B;
huart4.Init.StopBits = UART_STOPBITS_1;
huart4.Init.Parity = UART_PARITY_NONE;
huart4.Init.Mode = UART_MODE_TX_RX;
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
if (HAL_UART_Init(&huart4) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN UART4_Init 2 */
/* USER CODE END UART4_Init 2 */
}
/**
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
/* USER CODE BEGIN USART1_Init 0 */
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
huart1.Init.BaudRate = 115200;
huart1.Init.WordLength = UART_WORDLENGTH_8B;
huart1.Init.StopBits = UART_STOPBITS_1;
huart1.Init.Parity = UART_PARITY_NONE;
huart1.Init.Mode = UART_MODE_TX_RX;
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
if (HAL_UART_Init(&huart1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
/**
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
/* USER CODE BEGIN USART2_Init 0 */
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
huart2.Init.BaudRate = 115200;
huart2.Init.WordLength = UART_WORDLENGTH_8B;
huart2.Init.StopBits = UART_STOPBITS_1;
huart2.Init.Parity = UART_PARITY_NONE;
huart2.Init.Mode = UART_MODE_TX_RX;
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
if (HAL_UART_Init(&huart2) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
/**
* @brief USART3 Initialization Function
* @param None
* @retval None
*/
static void MX_USART3_UART_Init(void)
{
/* USER CODE BEGIN USART3_Init 0 */
/* USER CODE END USART3_Init 0 */
/* USER CODE BEGIN USART3_Init 1 */
/* USER CODE END USART3_Init 1 */
huart3.Instance = USART3;
huart3.Init.BaudRate = 115200;
huart3.Init.WordLength = UART_WORDLENGTH_8B;
huart3.Init.StopBits = UART_STOPBITS_1;
huart3.Init.Parity = UART_PARITY_NONE;
huart3.Init.Mode = UART_MODE_TX_RX;
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
if (HAL_UART_Init(&huart3) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USART3_Init 2 */
/* USER CODE END USART3_Init 2 */
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOG, GPIO_PIN_11|GPIO_PIN_14, GPIO_PIN_RESET);
/*Configure GPIO pins : PG11 PG14 */
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_14;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
/*Configure GPIO pin : PG13 */
GPIO_InitStruct.Pin = GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
}
/* FSMC initialization function */
static void MX_FSMC_Init(void)
{
/* USER CODE BEGIN FSMC_Init 0 */
/* USER CODE END FSMC_Init 0 */
FSMC_NORSRAM_TimingTypeDef Timing = {0};
/* USER CODE BEGIN FSMC_Init 1 */
/* USER CODE END FSMC_Init 1 */
/** Perform the SRAM1 memory initialization sequence
*/
hsram1.Instance = FSMC_NORSRAM_DEVICE;
hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
/* hsram1.Init */
hsram1.Init.NSBank = FSMC_NORSRAM_BANK3;
hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
hsram1.Init.PageSize = FSMC_PAGE_SIZE_NONE;
/* Timing */
Timing.AddressSetupTime = 15;
Timing.AddressHoldTime = 15;
Timing.DataSetupTime = 255;
Timing.BusTurnAroundDuration = 15;
Timing.CLKDivision = 16;
Timing.DataLatency = 17;
Timing.AccessMode = FSMC_ACCESS_MODE_A;
/* ExtTiming */
if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
{
Error_Handler( );
}
/* USER CODE BEGIN FSMC_Init 2 */
/* USER CODE END FSMC_Init 2 */
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
while(1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f4xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32f4xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex-M4 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32F4xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32f4xx.s). */
/******************************************************************************/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#include "stm32f4xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
STM32F412Zx || STM32F412Vx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* #define DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
STM32F479xx */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
RCC->AHB1ENR |= 0x000001F8;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000;
/*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank5_6->SDCR[0] = 0x000019E4;
FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x00000073;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001091;
FMC_Bank1->BTCR[3] = 0x00110212;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F469xx || STM32F479xx */
(void)(tmp);
}
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#if defined (DATA_IN_ExtSDRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
#if defined(STM32F446xx)
/* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
clock */
RCC->AHB1ENR |= 0x0000007D;
#else
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */
RCC->AHB1ENR |= 0x000001F8;
#endif /* STM32F446xx */
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
#if defined(STM32F446xx)
/* Connect PAx pins to FMC Alternate function */
GPIOA->AFR[0] |= 0xC0000000;
GPIOA->AFR[1] |= 0x00000000;
/* Configure PDx pins in Alternate function mode */
GPIOA->MODER |= 0x00008000;
/* Configure PDx pins speed to 50 MHz */
GPIOA->OSPEEDR |= 0x00008000;
/* Configure PDx pins Output type to push-pull */
GPIOA->OTYPER |= 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOA->PUPDR |= 0x00000000;
/* Connect PCx pins to FMC Alternate function */
GPIOC->AFR[0] |= 0x00CC0000;
GPIOC->AFR[1] |= 0x00000000;
/* Configure PDx pins in Alternate function mode */
GPIOC->MODER |= 0x00000A00;
/* Configure PDx pins speed to 50 MHz */
GPIOC->OSPEEDR |= 0x00000A00;
/* Configure PDx pins Output type to push-pull */
GPIOC->OTYPER |= 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOC->PUPDR |= 0x00000000;
#endif /* STM32F446xx */
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xA02A000A;
/* Configure PDx pins speed to 50 MHz */
GPIOD->OSPEEDR = 0xA02A000A;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 50 MHz */
GPIOE->OSPEEDR = 0xAAAA800A;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable SDRAM bank1 */
#if defined(STM32F446xx)
FMC_Bank5_6->SDCR[0] = 0x00001954;
#else
FMC_Bank5_6->SDCR[0] = 0x000019E4;
#endif /* STM32F446xx */
FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x000000F3;
#else
FMC_Bank5_6->SDCMR = 0x00000073;
#endif /* STM32F446xx */
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x00044014;
#else
FMC_Bank5_6->SDCMR = 0x00046014;
#endif /* STM32F446xx */
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
#if defined(STM32F446xx)
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
#else
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
#endif /* STM32F446xx */
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif /* DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
#if defined(DATA_IN_ExtSRAM)
/*-- GPIOs Configuration -----------------------------------------------------*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR |= 0x00000078;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00085AAA;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000CAFFF;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FMC/FSMC Configuration --------------------------------------------------*/
/* Enable the FMC/FSMC interface clock */
RCC->AHB3ENR |= 0x00000001;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001091;
FMC_Bank1->BTCR[3] = 0x00110212;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
|| defined(STM32F412Zx) || defined(STM32F412Vx)
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
(void)(tmp);
}
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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menu"Hardware Drivers Config"
menuconfig SOC_STM32F407ZG
bool
select SOC_SERIES_STM32F4
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Using UART device"
default y
select RT_USING_SERIAL
if BSP_USING_UART
source "$BSP_DIR/board/ports/uart/Kconfig"
endif
menuconfig BSP_USING_I2C1
bool "Using I2C device"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C1
source "$BSP_DIR/board/ports/I2c/Kconfig"
endif
menuconfig BSP_USING_SPI
bool "Using SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
source "$BSP_DIR/board/ports/spi/Kconfig"
endif
menuconfig BSP_USING_CH438
bool "Using CH438 device"
default y
if BSP_USING_CH438
source "$BSP_DIR/board/ports/ch438/Kconfig"
endif
menuconfig BSP_USING_USB
bool "Using USB device"
default n
select BSP_USING_STM32_USBH
select RESOURCES_USB
select RESOURCES_USB_HOST
select USBH_MSTORAGE
select RESOURCES_USB_DEVICE
if BSP_USING_USB
source "$BSP_DIR/board/ports/usb/Kconfig"
endif
source "$RTT_DIR/bsp/stm32/libraries/HAL_Drivers/Kconfig"
endmenu

31
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/SConscript Normal file
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import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
CubeMX_Config/Src/stm32f4xx_hal_msp.c
''')
path = [cwd]
path += [cwd + '/CubeMX_Config/Inc']
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB
if rtconfig.CROSS_TOOL == 'gcc':
src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f407xx.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s']
CPPDEFINES = ['STM32F407xx']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

59
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/board.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift first version
*/
#include "board.h"
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/**Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
|RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 4;
RCC_OscInitStruct.PLL.PLLN = 168;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 7;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
{
Error_Handler();
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
}

50
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/board.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-5 SummerGift first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rtthread.h>
#include <stm32f4xx.h>
#include "drv_common.h"
#include "drv_gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM32_SRAM_SIZE (128)
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (1024 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END STM32_SRAM_END
void SystemClock_Config(void);
#ifdef __cplusplus
}
#endif
#endif

243
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/drv_dcmi.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-27 thread-liu the first version
*/
#include "board.h"
#ifdef BSP_USING_DCMI
#include <drv_dcmi.h>
#ifdef RT_USING_POSIX
#include <dfs_posix.h>
#include <dfs_poll.h>
#ifdef RT_USING_POSIX_TERMIOS
#include <posix_termios.h>
#endif
#endif
#define DRV_DEBUG
#define LOG_TAG "drv.dcmi"
#include <drv_log.h>
static void (*dcmi_irq_callback)(void) = NULL;
static struct stm32_dcmi rt_dcmi = {0};
DMA_HandleTypeDef hdma_dcmi;
static void rt_hw_dcmi_dma_init(void)
{
__HAL_RCC_DMA2_CLK_ENABLE();
hdma_dcmi.Instance = DMA2_Stream1;
hdma_dcmi.Init.Channel = DMA_CHANNEL_1;
hdma_dcmi.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_dcmi.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_dcmi.Init.MemInc = DMA_MINC_ENABLE;
hdma_dcmi.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
hdma_dcmi.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
hdma_dcmi.Init.Mode = DMA_NORMAL;
hdma_dcmi.Init.Priority = DMA_PRIORITY_HIGH;
hdma_dcmi.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
hdma_dcmi.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
hdma_dcmi.Init.MemBurst = DMA_MBURST_SINGLE;
hdma_dcmi.Init.PeriphBurst = DMA_PBURST_SINGLE;
HAL_DMA_Init(&hdma_dcmi);
__HAL_LINKDMA(&rt_dcmi.DCMI_Handle, DMA_Handle, hdma_dcmi);
__HAL_DMA_ENABLE_IT(&hdma_dcmi,DMA_IT_TC);
HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 0x00, 0x00);
HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);;
}
/*
DMA multi_buffer DMA Transfer.
*/
void rt_hw_dcmi_dma_config(rt_uint32_t dst_addr1, rt_uint32_t dst_addr2, rt_uint32_t len)
{
HAL_DMAEx_MultiBufferStart(&hdma_dcmi, (rt_uint32_t)&DCMI->DR, dst_addr1, dst_addr2, len);
__HAL_DMA_ENABLE_IT(&hdma_dcmi, DMA_IT_TC);
}
static rt_err_t rt_hw_dcmi_init(DCMI_HandleTypeDef *device)
{
RT_ASSERT(device != RT_NULL);
device->Instance = DCMI;
device->Init.SynchroMode = DCMI_SYNCHRO_HARDWARE;
device->Init.PCKPolarity = DCMI_PCKPOLARITY_RISING;
device->Init.VSPolarity = DCMI_VSPOLARITY_LOW;
device->Init.HSPolarity = DCMI_HSPOLARITY_LOW;
device->Init.CaptureRate = DCMI_CR_ALL_FRAME;
device->Init.ExtendedDataMode = DCMI_EXTEND_DATA_8B;
device->Init.JPEGMode = DCMI_JPEG_ENABLE;
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
device->Init.ByteSelectMode = DCMI_BSM_ALL;
device->Init.ByteSelectStart = DCMI_OEBS_ODD;
device->Init.LineSelectMode = DCMI_LSM_ALL;
device->Init.LineSelectStart = DCMI_OELS_ODD;
#endif
if(HAL_DCMI_Init(device) != HAL_OK)
{
LOG_E("dcmi init error!");
return RT_ERROR;
}
else
{
LOG_I("dcmi HAL_DCMI_Init success");
}
DCMI->IER = 0x0;
__HAL_DCMI_ENABLE_IT(device, DCMI_IT_FRAME);
__HAL_DCMI_ENABLE(device);
return RT_EOK;
}
void DCMI_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DCMI_IRQHandler(&rt_dcmi.DCMI_Handle);
/* leave interrupt */
rt_interrupt_leave();
}
/*
the camera starts transfering photos
*/
void rt_dcmi_start(uint32_t pData, uint32_t Length)
{
HAL_DCMI_Start_DMA(&rt_dcmi.DCMI_Handle,DCMI_MODE_SNAPSHOT,pData, Length);
}
/*
the camera stops transfering photos
*/
void rt_dcmi_stop(void)
{
HAL_DCMI_Stop(&rt_dcmi.DCMI_Handle);//
}
/* Capture a frame of the image */
void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
{
rt_interrupt_enter();
__HAL_DCMI_ENABLE_IT(&rt_dcmi.DCMI_Handle, DCMI_IT_FRAME);
rt_dcmi_stop();
if(NULL != dcmi_irq_callback)
{
(*dcmi_irq_callback)();
}
rt_interrupt_leave();
}
void DMA2_Stream1_IRQHandler(void)
{
extern void camera_dma_data_process(void);
/* enter interrupt */
rt_interrupt_enter();
if (__HAL_DMA_GET_FLAG(&hdma_dcmi, DMA_FLAG_TCIF1_5) != RESET)
{
__HAL_DMA_CLEAR_FLAG(&hdma_dcmi, DMA_FLAG_TCIF1_5);
}
/* leave interrupt */
rt_interrupt_leave();
}
static rt_err_t rt_dcmi_init(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
rt_err_t result = RT_EOK;
result = rt_hw_dcmi_init(&rt_dcmi.DCMI_Handle);
if (result != RT_EOK)
{
return result;
}
rt_hw_dcmi_dma_init();
return result;
}
static rt_err_t rt_dcmi_open(rt_device_t dev, rt_uint16_t oflag)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_dcmi_close(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_dcmi_control(rt_device_t dev, int cmd, void *args)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_size_t rt_dcmi_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_size_t rt_dcmi_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
rt_err_t rt_set_irq_dcmi_callback_hander(void (*p)(void))
{
if(NULL == p)
{
LOG_E("set irq dcmi callback hander is NULL");
return RT_ERROR;
}
dcmi_irq_callback = p;
return RT_EOK;
}
int dcmi_init(void)
{
int ret = 0;
rt_device_t dcmi_dev = RT_NULL;
rt_dcmi.dev.parent.type = RT_Device_Class_Miscellaneous;
rt_dcmi.dev.parent.init = rt_dcmi_init;
rt_dcmi.dev.parent.open = rt_dcmi_open;
rt_dcmi.dev.parent.close = rt_dcmi_close;
rt_dcmi.dev.parent.read = rt_dcmi_read;
rt_dcmi.dev.parent.write = rt_dcmi_write;
rt_dcmi.dev.parent.control = rt_dcmi_control;
rt_dcmi.dev.parent.user_data = RT_NULL;
ret = rt_device_register(&rt_dcmi.dev.parent, "dcmi", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
if(ret != RT_EOK)
{
LOG_E("dcmi registered fail!!\n\r");
return -RT_ERROR;
}
LOG_I("dcmi registered successfully!");
dcmi_dev = rt_device_find("dcmi");
if (dcmi_dev == RT_NULL)
{
LOG_E("can't find dcmi device!");
return RT_ERROR;
}
ret = rt_device_open(dcmi_dev, RT_DEVICE_FLAG_RDWR);
if(ret != RT_EOK)
{
LOG_E("can't open dcmi device!");
return RT_ERROR;
}
LOG_I("dcmi open successfully");
return RT_EOK;
}
INIT_BOARD_EXPORT(dcmi_init);
#endif

37
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/drv_dcmi.h Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-27 thread-liu the first version
*/
#ifndef __DRV_DCMI_H__
#define __DRV_DCMI_H__
#include "board.h"
#ifdef __cplusplus
extern "C" {
#endif
struct rt_dcmi_device
{
struct rt_device parent;
};
struct stm32_dcmi
{
DCMI_HandleTypeDef DCMI_Handle;
struct rt_dcmi_device dev;
};
extern DMA_HandleTypeDef hdma_dcmi;
extern void DCMI_IRQHandler(void);
extern void rt_hw_dcmi_dma_config(rt_uint32_t dst_addr1, rt_uint32_t dst_addr2, rt_uint32_t len);
extern void rt_dcmi_start(uint32_t pData, uint32_t Length);
extern void rt_dcmi_stop(void);
extern rt_err_t rt_set_irq_dcmi_callback_hander(void (*p)(void));
#ifdef __cplusplus
}
#endif
#endif

159
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/linker_scripts/link.lds Normal file
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/*
* linker script for STM32F4xx with GNU ld
* bernard.xiong 2009-10-14
* flybreak 2018-11-19 Add support for RAM2
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */
RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */
RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x200;
SECTIONS
{
.text :
{
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
_etext = .;
} > CODE = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM1
.stack :
{
. = ALIGN(4);
_sstack = .;
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >RAM1
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > RAM1
__bss_end = .;
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

13
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/ports/I2c/Kconfig Normal file
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config BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default y
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
int "I2C scl pin number"
range 0 143
default 24
config BSP_I2C1_SDA_PIN
int "I2C sda pin number"
range 0 143
default 25
endif

11
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/ports/can/Kconfig Normal file
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config CAN_BUS_NAME_1
string "can bus name"
default "can1"
config CAN_DRIVER_NAME
string "can driver name"
default "can1_drv"
config CAN_1_DEVICE_NAME_1
string "can bus 1 device 1 name"
default "can1_dev1"

39
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/ports/ch438/Kconfig Normal file
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config CH438_BUS_NAME
string
default "extuart"
config CH438_DRIVER_NAME
string
default "extuart_drv"
config CH438_DEVICE_NAME_0
string
default "extuart_dev0"
config CH438_DEVICE_NAME_1
string
default "extuart_dev1"
config CH438_DEVICE_NAME_2
string
default "extuart_dev2"
config CH438_DEVICE_NAME_3
string
default "extuart_dev3"
config CH438_DEVICE_NAME_4
string
default "extuart_dev4"
config CH438_DEVICE_NAME_5
string
default "extuart_dev5"
config CH438_DEVICE_NAME_6
string
default "extuart_dev6"
config CH438_DEVICE_NAME_7
string
default "extuart_dev7"

4
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/ports/gpio/Kconfig Normal file
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config BSP_USING_GPIO
bool "Enable GPIO"
default y

46
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/ports/spi/Kconfig Normal file
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config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
config BSP_USING_SPI2
bool "Enable SPI2 BUS"
default n
config BSP_SPI2_TX_USING_DMA
bool "Enable SPI2 TX DMA"
depends on BSP_USING_SPI2
default n
config BSP_SPI2_RX_USING_DMA
bool "Enable SPI2 RX DMA"
depends on BSP_USING_SPI2
select BSP_SPI2_TX_USING_DMA
default n
config BSP_USING_SPI3
bool "Enable SPI3 BUS"
default n
config BSP_SPI3_TX_USING_DMA
bool "Enable SPI3 TX DMA"
depends on BSP_USING_SPI3
default n
config BSP_SPI3_RX_USING_DMA
bool "Enable SPI3 RX DMA"
depends on BSP_USING_SPI3
select BSP_SPI3_TX_USING_DMA
default n

21
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/ports/uart/Kconfig Normal file
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config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_USING_UART3
bool "Enable UART3"
default n
config BSP_USING_UART4
bool "Enable UART4"
default n

15
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/board/ports/usb/Kconfig Normal file
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config BSP_USING_STM32_USBH
bool "Using usb host"
default y
if BSP_USING_STM32_USBH
config USB_BUS_NAME
string "usb bus name"
default "usb"
config USB_DRIVER_NAME
string "usb bus driver name"
default "usb_drv"
config USB_DEVICE_NAME
string "usb bus device name"
default "usb_dev"
endif

226
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/rtconfig.h Normal file
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
#define ROOT_DIR "../../../.."
#define BSP_DIR "."
#define RT_Thread_DIR "../.."
#define RTT_DIR "../../rt-thread"
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_USING_MEMHEAP_AUTO_BINDING
#define RT_USING_MEMHEAP_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40004
#define ARCH_ARM
#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M4
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define RT_USING_MSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_ROMFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_PIN
#define RT_USING_RTC
#define RT_USING_SPI
#define RT_USING_SPI_MSD
#define RT_USING_SFUD
#define RT_SFUD_USING_SFDP
#define RT_SFUD_USING_FLASH_INFO_TABLE
#define RT_SFUD_SPI_MAX_HZ 50000000
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_PTHREADS
#define PTHREAD_NUM_MAX 8
#define RT_USING_POSIX
#define RT_LIBC_USING_TIME
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread Utestcases */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32F4
/* Hardware Drivers Config */
#define SOC_STM32F407ZG
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
#define BSP_USING_USB
#define BSP_USING_STM32_USBH
#define USB_BUS_NAME "usb"
#define USB_DRIVER_NAME "usb_drv"
#define USB_DEVICE_NAME "usb_dev"
/* MicroPython */
/* More Drivers */
/* APP_Framework */
/* Framework */
#define TRANSFORM_LAYER_ATTRIUBUTE
#define ADD_XIZI_FETURES
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 1024
/* ota app */
/* test app */
/* connection app */
/* control app */
/* knowing app */
/* sensor app */
/* lib */
#define APP_SELECT_NEWLIB
#endif

151
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-arm32-board/rtconfig.py Normal file
View File

@ -0,0 +1,151 @@
import os
SRC_APP_DIR = '../../../../APP_Framework'
# toolchains options
ARCH='arm'
CPU='cortex-m4'
CROSS_TOOL='gcc'
# bsp lib config
BSP_LIBRARY_TYPE = None
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'/opt/gcc-arm-none-eabi-7-2018-q2-update/bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
CXX = PREFIX + 'g++'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 -g'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CXXFLAGS += ' -std=gnu++11'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
CXX = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M4.fp '
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
CFLAGS += ' -D__MICROLIB '
AFLAGS += ' --pd "__MICROLIB SETA 1" '
LFLAGS += ' --library_type=microlib '
EXEC_PATH += '/ARM/ARMCC/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = '-Dewarm'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M4'
CFLAGS += ' -e'
CFLAGS += ' --fpu=VFPv4_sp'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M4'
AFLAGS += ' --fpu VFPv4_sp'
AFLAGS += ' -S'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = ' --config "board/linker_scripts/link.icf"'
LFLAGS += ' --entry __iar_program_start'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

155
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32h743_openmv_h7plus/.config
View File

@ -11,7 +11,6 @@ CONFIG_RTT_DIR="../../rt-thread"
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_BIG_ENDIAN is not set
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
@ -22,6 +21,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
@ -32,7 +32,8 @@ CONFIG_IDLE_THREAD_STACK_SIZE=256
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
@ -60,14 +61,19 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BSET_MODE is not set
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
#
@ -79,8 +85,7 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_RT_VER_NUM=0x40100
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
@ -94,18 +99,9 @@ CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
CONFIG_RT_USING_CPLUSPLUS=y
# CONFIG_RT_USING_CPLUSPLUS11 is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
# CONFIG_RT_USING_LEGACY is not set
CONFIG_RT_USING_MSH=y
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
@ -119,11 +115,8 @@ CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_POSIX=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
@ -153,14 +146,15 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
CONFIG_RT_USING_DFS_ROMFS=y
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_FAL is not set
# CONFIG_RT_USING_LWP is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
@ -179,9 +173,28 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
CONFIG_RT_USING_SDIO=y
CONFIG_RT_SDIO_STACK_SIZE=512
CONFIG_RT_SDIO_THREAD_PRIORITY=15
CONFIG_RT_MMCSD_STACK_SIZE=1024
CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_SPI_BITOPS is not set
CONFIG_RT_USING_QSPI=y
# CONFIG_RT_USING_SPI_MSD is not set
CONFIG_RT_USING_SFUD=y
CONFIG_RT_SFUD_USING_SFDP=y
CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
CONFIG_RT_SFUD_USING_QSPI=y
CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
# CONFIG_RT_DEBUG_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
@ -194,53 +207,64 @@ CONFIG_RT_USING_PIN=y
#
# Using USB
#
CONFIG_RT_USING_USB=y
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
CONFIG_RT_USING_USB_DEVICE=y
CONFIG_RT_USBD_THREAD_STACK_SZ=4096
CONFIG_USB_VENDOR_ID=0x0FFE
CONFIG_USB_PRODUCT_ID=0x0001
# CONFIG_RT_USB_DEVICE_COMPOSITE is not set
# CONFIG__RT_USB_DEVICE_NONE is not set
CONFIG__RT_USB_DEVICE_CDC=y
# CONFIG__RT_USB_DEVICE_MSTORAGE is not set
# CONFIG__RT_USB_DEVICE_HID is not set
# CONFIG__RT_USB_DEVICE_WINUSB is not set
# CONFIG__RT_USB_DEVICE_AUDIO is not set
CONFIG_RT_USB_DEVICE_CDC=y
CONFIG_RT_VCOM_TASK_STK_SIZE=512
CONFIG_RT_CDC_RX_BUFSIZE=128
# CONFIG_RT_VCOM_TX_USE_DMA is not set
CONFIG_RT_VCOM_SERNO="32021919830108"
CONFIG_RT_VCOM_SER_LEN=14
CONFIG_RT_VCOM_TX_TIMEOUT=1000
#
# POSIX layer and C standard library
# C/C++ and POSIX layer
#
CONFIG_RT_USING_LIBC=y
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
CONFIG_RT_USING_POSIX_DELAY=y
CONFIG_RT_USING_POSIX_CLOCK=y
# CONFIG_RT_USING_POSIX_TIMER is not set
CONFIG_RT_USING_PTHREADS=y
CONFIG_PTHREAD_NUM_MAX=8
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Interprocess Communication (IPC)
#
# CONFIG_RT_USING_POSIX_PIPE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
#
# Socket is in the 'Network' category
#
CONFIG_RT_USING_CPLUSPLUS=y
# CONFIG_RT_USING_CPLUSPLUS11 is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
@ -249,7 +273,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_LWP is not set
# CONFIG_RT_USING_VBUS is not set
#
# RT-Thread Utestcases
@ -272,11 +296,20 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_LPUART1 is not set
CONFIG_BSP_USING_SDRAM=y
CONFIG_BSP_USING_QSPI=y
CONFIG_BSP_USING_ONCHIP_RTC=y
# CONFIG_BSP_USING_CRC is not set
# CONFIG_BSP_USING_RNG is not set
# CONFIG_BSP_USING_UDID is not set
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_SDRAM=y
# CONFIG_BSP_USING_QSPI_FLASH is not set
CONFIG_BSP_USING_SDMMC=y
CONFIG_BSP_USING_USBD=y
#
# More Drivers
#

29
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32h743_openmv_h7plus/README.md
View File

@ -83,3 +83,32 @@
| PG8 | FMC_SDCLK |
| PG15 | FMC_SDNCAS |
| PF11 | FMC_SDNRAS |
### QSPI FLASH W25Q256JV
| 引脚 | 作用 |
| ---- | --------------- |
| PF6 | QUADSPI_BK1_IO3 |
| PF7 | QUADSPI_BK1_IO2 |
| PF8 | QUADSPI_BK1_IO0 |
| PF9 | QUADSPI_BK1_IO1 |
| PF10 | QUADSPI_CLK |
| PG6 | QUADSPI_BK1_NCS |
### SDIO USD-1040310811
| 引脚 | 作用 |
| ---- | ---------- |
| PC8 | SDMMC1_D0 |
| PC9 | SDMMC1_D1 |
| PC10 | SDMMC1_D2 |
| PC11 | SDMMC1_D3 |
| PC12 | SDMMC1_CK |
| PD2 | SDMMC1_CMD |
### USBCDC
| 引脚 | 作用 |
| ---- | ------------- |
| PA11 | USB_OTG_FS_DM |
| PA12 | USB_OTG_FS_DP |

4
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32h743_openmv_h7plus/applications/main.c
View File

@ -31,9 +31,11 @@ extern int FrameworkInit();
int main(void)
{
rt_pin_mode(LEDR_PIN, PIN_MODE_OUTPUT);
rt_thread_mdelay(100);
FrameworkInit();
printf("XIUOS stm32h7 build %s %s\n",__DATE__,__TIME__);
#ifdef BSP_USING_USBD
//rt_console_set_device("vcom");
#endif
while (1)
{
rt_pin_write(LEDR_PIN, PIN_HIGH);

4
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32h743_openmv_h7plus/board/CubeMX_Config/.mxproject
View File

File diff suppressed because one or more lines are too long

6
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32h743_openmv_h7plus/board/CubeMX_Config/Core/Inc/main.h
View File

@ -49,6 +49,8 @@ extern "C" {
/* USER CODE END EM */
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
@ -59,10 +61,6 @@ void Error_Handler(void);
/* Private defines -----------------------------------------------------------*/
#define LED_RED_Pin GPIO_PIN_0
#define LED_RED_GPIO_Port GPIOC
#define LED_GREEN_Pin GPIO_PIN_1
#define LED_GREEN_GPIO_Port GPIOC
#define LED_BLUE_Pin GPIO_PIN_2
#define LED_BLUE_GPIO_Port GPIOC
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */

14
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32h743_openmv_h7plus/board/CubeMX_Config/Core/Inc/stm32h7xx_hal_conf.h
View File

@ -43,7 +43,7 @@
/* #define HAL_CRC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_DAC_MODULE_ENABLED */
/* #define HAL_DCMI_MODULE_ENABLED */
#define HAL_DCMI_MODULE_ENABLED
/* #define HAL_DMA2D_MODULE_ENABLED */
/* #define HAL_ETH_MODULE_ENABLED */
/* #define HAL_NAND_MODULE_ENABLED */
@ -64,23 +64,23 @@
/* #define HAL_IWDG_MODULE_ENABLED */
/* #define HAL_LPTIM_MODULE_ENABLED */
/* #define HAL_LTDC_MODULE_ENABLED */
/* #define HAL_QSPI_MODULE_ENABLED */
#define HAL_QSPI_MODULE_ENABLED
/* #define HAL_RAMECC_MODULE_ENABLED */
/* #define HAL_RNG_MODULE_ENABLED */
/* #define HAL_RTC_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
/* #define HAL_SD_MODULE_ENABLED */
#define HAL_SD_MODULE_ENABLED
/* #define HAL_MMC_MODULE_ENABLED */
/* #define HAL_SPDIFRX_MODULE_ENABLED */
/* #define HAL_SPI_MODULE_ENABLED */
/* #define HAL_SWPMI_MODULE_ENABLED */
/* #define HAL_TIM_MODULE_ENABLED */
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
/* #define HAL_USART_MODULE_ENABLED */
/* #define HAL_IRDA_MODULE_ENABLED */
/* #define HAL_SMARTCARD_MODULE_ENABLED */
/* #define HAL_WWDG_MODULE_ENABLED */
/* #define HAL_PCD_MODULE_ENABLED */
#define HAL_PCD_MODULE_ENABLED
/* #define HAL_HCD_MODULE_ENABLED */
/* #define HAL_DFSDM_MODULE_ENABLED */
/* #define HAL_DSI_MODULE_ENABLED */
@ -168,7 +168,7 @@
#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */
#define USE_RTOS 0
#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
#define USE_SPI_CRC 0U /*!< use CRC in SPI */
#define USE_SPI_CRC 0U /*!< use CRC in SPI */
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */

5
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32h743_openmv_h7plus/board/CubeMX_Config/Core/Inc/stm32h7xx_it.h
View File

@ -55,6 +55,11 @@ void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void DMA1_Stream3_IRQHandler(void);
void SDMMC1_IRQHandler(void);
void DCMI_IRQHandler(void);
void OTG_FS_EP1_OUT_IRQHandler(void);
void OTG_FS_EP1_IN_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */

346
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32h743_openmv_h7plus/board/CubeMX_Config/Core/Src/main.c
View File

@ -40,8 +40,21 @@
/* Private variables ---------------------------------------------------------*/
DCMI_HandleTypeDef hdcmi;
DMA_HandleTypeDef hdma_dcmi;
QSPI_HandleTypeDef hqspi;
RTC_HandleTypeDef hrtc;
SD_HandleTypeDef hsd1;
TIM_HandleTypeDef htim1;
UART_HandleTypeDef huart1;
PCD_HandleTypeDef hpcd_USB_OTG_FS;
SDRAM_HandleTypeDef hsdram1;
/* USER CODE BEGIN PV */
@ -53,6 +66,13 @@ void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_USART1_UART_Init(void);
static void MX_FMC_Init(void);
static void MX_QUADSPI_Init(void);
static void MX_SDMMC1_SD_Init(void);
static void MX_DMA_Init(void);
static void MX_RTC_Init(void);
static void MX_DCMI_Init(void);
static void MX_USB_OTG_FS_PCD_Init(void);
static void MX_TIM1_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
@ -72,6 +92,12 @@ int main(void)
/* USER CODE END 1 */
/* Enable I-Cache---------------------------------------------------------*/
SCB_EnableICache();
/* Enable D-Cache---------------------------------------------------------*/
SCB_EnableDCache();
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
@ -92,6 +118,13 @@ int main(void)
MX_GPIO_Init();
MX_USART1_UART_Init();
MX_FMC_Init();
MX_QUADSPI_Init();
MX_SDMMC1_SD_Init();
MX_DMA_Init();
MX_RTC_Init();
MX_DCMI_Init();
MX_USB_OTG_FS_PCD_Init();
MX_TIM1_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
@ -119,24 +152,25 @@ void SystemClock_Config(void)
/** Supply configuration update enable
*/
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_LSI
|RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 3;
RCC_OscInitStruct.PLL.PLLN = 200;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
@ -145,7 +179,6 @@ void SystemClock_Config(void)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
@ -165,6 +198,242 @@ void SystemClock_Config(void)
}
}
/**
* @brief DCMI Initialization Function
* @param None
* @retval None
*/
static void MX_DCMI_Init(void)
{
/* USER CODE BEGIN DCMI_Init 0 */
/* USER CODE END DCMI_Init 0 */
/* USER CODE BEGIN DCMI_Init 1 */
/* USER CODE END DCMI_Init 1 */
hdcmi.Instance = DCMI;
hdcmi.Init.SynchroMode = DCMI_SYNCHRO_HARDWARE;
hdcmi.Init.PCKPolarity = DCMI_PCKPOLARITY_FALLING;
hdcmi.Init.VSPolarity = DCMI_VSPOLARITY_LOW;
hdcmi.Init.HSPolarity = DCMI_HSPOLARITY_LOW;
hdcmi.Init.CaptureRate = DCMI_CR_ALL_FRAME;
hdcmi.Init.ExtendedDataMode = DCMI_EXTEND_DATA_8B;
hdcmi.Init.JPEGMode = DCMI_JPEG_ENABLE;
hdcmi.Init.ByteSelectMode = DCMI_BSM_ALL;
hdcmi.Init.ByteSelectStart = DCMI_OEBS_ODD;
hdcmi.Init.LineSelectMode = DCMI_LSM_ALL;
hdcmi.Init.LineSelectStart = DCMI_OELS_ODD;
if (HAL_DCMI_Init(&hdcmi) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN DCMI_Init 2 */
/* USER CODE END DCMI_Init 2 */
}
/**
* @brief QUADSPI Initialization Function
* @param None
* @retval None
*/
static void MX_QUADSPI_Init(void)
{
/* USER CODE BEGIN QUADSPI_Init 0 */
/* USER CODE END QUADSPI_Init 0 */
/* USER CODE BEGIN QUADSPI_Init 1 */
/* USER CODE END QUADSPI_Init 1 */
/* QUADSPI parameter configuration*/
hqspi.Instance = QUADSPI;
hqspi.Init.ClockPrescaler = 1;
hqspi.Init.FifoThreshold = 3;
hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
hqspi.Init.FlashSize = 24;
hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_2_CYCLE;
hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
hqspi.Init.FlashID = QSPI_FLASH_ID_1;
hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
if (HAL_QSPI_Init(&hqspi) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN QUADSPI_Init 2 */
/* USER CODE END QUADSPI_Init 2 */
}
/**
* @brief RTC Initialization Function
* @param None
* @retval None
*/
static void MX_RTC_Init(void)
{
/* USER CODE BEGIN RTC_Init 0 */
/* USER CODE END RTC_Init 0 */
RTC_TimeTypeDef sTime = {0};
RTC_DateTypeDef sDate = {0};
/* USER CODE BEGIN RTC_Init 1 */
/* USER CODE END RTC_Init 1 */
/** Initialize RTC Only
*/
hrtc.Instance = RTC;
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
hrtc.Init.AsynchPrediv = 127;
hrtc.Init.SynchPrediv = 255;
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE;
if (HAL_RTC_Init(&hrtc) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN Check_RTC_BKUP */
/* USER CODE END Check_RTC_BKUP */
/** Initialize RTC and set the Time and Date
*/
sTime.Hours = 0x0;
sTime.Minutes = 0x0;
sTime.Seconds = 0x0;
sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
sTime.StoreOperation = RTC_STOREOPERATION_RESET;
if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK)
{
Error_Handler();
}
sDate.WeekDay = RTC_WEEKDAY_MONDAY;
sDate.Month = RTC_MONTH_JANUARY;
sDate.Date = 0x1;
sDate.Year = 0x0;
if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN RTC_Init 2 */
/* USER CODE END RTC_Init 2 */
}
/**
* @brief SDMMC1 Initialization Function
* @param None
* @retval None
*/
static void MX_SDMMC1_SD_Init(void)
{
/* USER CODE BEGIN SDMMC1_Init 0 */
/* USER CODE END SDMMC1_Init 0 */
/* USER CODE BEGIN SDMMC1_Init 1 */
/* USER CODE END SDMMC1_Init 1 */
hsd1.Instance = SDMMC1;
hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B;
hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
hsd1.Init.ClockDiv = 4;
if (HAL_SD_Init(&hsd1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SDMMC1_Init 2 */
/* USER CODE END SDMMC1_Init 2 */
}
/**
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
TIM_OC_InitTypeDef sConfigOC = {0};
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
htim1.Init.Prescaler = 0;
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
htim1.Init.Period = 7;
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim1.Init.RepetitionCounter = 0;
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
{
Error_Handler();
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
sConfigOC.Pulse = 3;
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
{
Error_Handler();
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
sBreakDeadTimeConfig.DeadTime = 0;
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
sBreakDeadTimeConfig.BreakFilter = 0;
sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
sBreakDeadTimeConfig.Break2Filter = 0;
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
HAL_TIM_MspPostInit(&htim1);
}
/**
* @brief USART1 Initialization Function
* @param None
@ -213,6 +482,58 @@ static void MX_USART1_UART_Init(void)
}
/**
* @brief USB_OTG_FS Initialization Function
* @param None
* @retval None
*/
static void MX_USB_OTG_FS_PCD_Init(void)
{
/* USER CODE BEGIN USB_OTG_FS_Init 0 */
/* USER CODE END USB_OTG_FS_Init 0 */
/* USER CODE BEGIN USB_OTG_FS_Init 1 */
/* USER CODE END USB_OTG_FS_Init 1 */
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
hpcd_USB_OTG_FS.Init.dev_endpoints = 9;
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USB_OTG_FS_Init 2 */
/* USER CODE END USB_OTG_FS_Init 2 */
}
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
/* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
/* DMA interrupt init */
/* DMA1_Stream3_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);
}
/* FMC initialization function */
static void MX_FMC_Init(void)
{
@ -271,24 +592,24 @@ static void MX_GPIO_Init(void)
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, LED_RED_Pin|LED_GREEN_Pin|LED_BLUE_Pin, GPIO_PIN_RESET);
HAL_GPIO_WritePin(LED_RED_GPIO_Port, LED_RED_Pin, GPIO_PIN_RESET);
/*Configure GPIO pins : LED_RED_Pin LED_GREEN_Pin LED_BLUE_Pin */
GPIO_InitStruct.Pin = LED_RED_Pin|LED_GREEN_Pin|LED_BLUE_Pin;
/*Configure GPIO pin : LED_RED_Pin */
GPIO_InitStruct.Pin = LED_RED_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
HAL_GPIO_Init(LED_RED_GPIO_Port, &GPIO_InitStruct);
}
@ -327,3 +648,4 @@ void assert_failed(uint8_t *file, uint32_t line)
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

570
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32h743_openmv_h7plus/board/CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c
View File

@ -25,6 +25,7 @@
#include "drv_common.h"
#endif
/* USER CODE END Includes */
extern DMA_HandleTypeDef hdma_dcmi;
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
@ -59,7 +60,9 @@
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
@ -77,6 +80,484 @@ void HAL_MspInit(void)
/* USER CODE END MspInit 1 */
}
/**
* @brief DCMI MSP Initialization
* This function configures the hardware resources used in this example
* @param hdcmi: DCMI handle pointer
* @retval None
*/
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hdcmi->Instance==DCMI)
{
/* USER CODE BEGIN DCMI_MspInit 0 */
/* USER CODE END DCMI_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DCMI_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**DCMI GPIO Configuration
PE4 ------> DCMI_D4
PE5 ------> DCMI_D6
PE6 ------> DCMI_D7
PB7 ------> DCMI_VSYNC
PB6 ------> DCMI_D5
PG11 ------> DCMI_D3
PG10 ------> DCMI_D2
PC7 ------> DCMI_D1
PC6 ------> DCMI_D0
PA4 ------> DCMI_HSYNC
PA6 ------> DCMI_PIXCLK
*/
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF13_DCMI;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF13_DCMI;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF13_DCMI;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF13_DCMI;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF13_DCMI;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* DCMI DMA Init */
/* DCMI Init */
hdma_dcmi.Instance = DMA1_Stream3;
hdma_dcmi.Init.Request = DMA_REQUEST_DCMI;
hdma_dcmi.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_dcmi.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_dcmi.Init.MemInc = DMA_MINC_ENABLE;
hdma_dcmi.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
hdma_dcmi.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
hdma_dcmi.Init.Mode = DMA_CIRCULAR;
hdma_dcmi.Init.Priority = DMA_PRIORITY_HIGH;
hdma_dcmi.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
hdma_dcmi.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
hdma_dcmi.Init.MemBurst = DMA_MBURST_SINGLE;
hdma_dcmi.Init.PeriphBurst = DMA_PBURST_SINGLE;
if (HAL_DMA_Init(&hdma_dcmi) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(hdcmi,DMA_Handle,hdma_dcmi);
/* DCMI interrupt Init */
HAL_NVIC_SetPriority(DCMI_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DCMI_IRQn);
/* USER CODE BEGIN DCMI_MspInit 1 */
/* USER CODE END DCMI_MspInit 1 */
}
}
/**
* @brief DCMI MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hdcmi: DCMI handle pointer
* @retval None
*/
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
{
if(hdcmi->Instance==DCMI)
{
/* USER CODE BEGIN DCMI_MspDeInit 0 */
/* USER CODE END DCMI_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_DCMI_CLK_DISABLE();
/**DCMI GPIO Configuration
PE4 ------> DCMI_D4
PE5 ------> DCMI_D6
PE6 ------> DCMI_D7
PB7 ------> DCMI_VSYNC
PB6 ------> DCMI_D5
PG11 ------> DCMI_D3
PG10 ------> DCMI_D2
PC7 ------> DCMI_D1
PC6 ------> DCMI_D0
PA4 ------> DCMI_HSYNC
PA6 ------> DCMI_PIXCLK
*/
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7|GPIO_PIN_6);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11|GPIO_PIN_10);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7|GPIO_PIN_6);
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_6);
/* DCMI DMA DeInit */
HAL_DMA_DeInit(hdcmi->DMA_Handle);
/* DCMI interrupt DeInit */
HAL_NVIC_DisableIRQ(DCMI_IRQn);
/* USER CODE BEGIN DCMI_MspDeInit 1 */
/* USER CODE END DCMI_MspDeInit 1 */
}
}
/**
* @brief QSPI MSP Initialization
* This function configures the hardware resources used in this example
* @param hqspi: QSPI handle pointer
* @retval None
*/
void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hqspi->Instance==QUADSPI)
{
/* USER CODE BEGIN QUADSPI_MspInit 0 */
/* USER CODE END QUADSPI_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_QSPI;
PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_QSPI_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
/**QUADSPI GPIO Configuration
PG6 ------> QUADSPI_BK1_NCS
PF7 ------> QUADSPI_BK1_IO2
PF6 ------> QUADSPI_BK1_IO3
PF10 ------> QUADSPI_CLK
PF9 ------> QUADSPI_BK1_IO1
PF8 ------> QUADSPI_BK1_IO0
*/
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
/* USER CODE BEGIN QUADSPI_MspInit 1 */
/* USER CODE END QUADSPI_MspInit 1 */
}
}
/**
* @brief QSPI MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hqspi: QSPI handle pointer
* @retval None
*/
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi)
{
if(hqspi->Instance==QUADSPI)
{
/* USER CODE BEGIN QUADSPI_MspDeInit 0 */
/* USER CODE END QUADSPI_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_QSPI_CLK_DISABLE();
/**QUADSPI GPIO Configuration
PG6 ------> QUADSPI_BK1_NCS
PF7 ------> QUADSPI_BK1_IO2
PF6 ------> QUADSPI_BK1_IO3
PF10 ------> QUADSPI_CLK
PF9 ------> QUADSPI_BK1_IO1
PF8 ------> QUADSPI_BK1_IO0
*/
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6);
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_10|GPIO_PIN_9
|GPIO_PIN_8);
/* USER CODE BEGIN QUADSPI_MspDeInit 1 */
/* USER CODE END QUADSPI_MspDeInit 1 */
}
}
/**
* @brief RTC MSP Initialization
* This function configures the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hrtc->Instance==RTC)
{
/* USER CODE BEGIN RTC_MspInit 0 */
/* USER CODE END RTC_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_RTC_ENABLE();
/* USER CODE BEGIN RTC_MspInit 1 */
/* USER CODE END RTC_MspInit 1 */
}
}
/**
* @brief RTC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
{
if(hrtc->Instance==RTC)
{
/* USER CODE BEGIN RTC_MspDeInit 0 */
/* USER CODE END RTC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_RTC_DISABLE();
/* USER CODE BEGIN RTC_MspDeInit 1 */
/* USER CODE END RTC_MspDeInit 1 */
}
}
/**
* @brief SD MSP Initialization
* This function configures the hardware resources used in this example
* @param hsd: SD handle pointer
* @retval None
*/
void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hsd->Instance==SDMMC1)
{
/* USER CODE BEGIN SDMMC1_MspInit 0 */
/* USER CODE END SDMMC1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC;
PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_SDMMC1_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/**SDMMC1 GPIO Configuration
PC12 ------> SDMMC1_CK
PC11 ------> SDMMC1_D3
PC10 ------> SDMMC1_D2
PD2 ------> SDMMC1_CMD
PC9 ------> SDMMC1_D1
PC8 ------> SDMMC1_D0
*/
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9
|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* SDMMC1 interrupt Init */
HAL_NVIC_SetPriority(SDMMC1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
/* USER CODE BEGIN SDMMC1_MspInit 1 */
/* USER CODE END SDMMC1_MspInit 1 */
}
}
/**
* @brief SD MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hsd: SD handle pointer
* @retval None
*/
void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
{
if(hsd->Instance==SDMMC1)
{
/* USER CODE BEGIN SDMMC1_MspDeInit 0 */
/* USER CODE END SDMMC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SDMMC1_CLK_DISABLE();
/**SDMMC1 GPIO Configuration
PC12 ------> SDMMC1_CK
PC11 ------> SDMMC1_D3
PC10 ------> SDMMC1_D2
PD2 ------> SDMMC1_CMD
PC9 ------> SDMMC1_D1
PC8 ------> SDMMC1_D0
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9
|GPIO_PIN_8);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
/* SDMMC1 interrupt DeInit */
HAL_NVIC_DisableIRQ(SDMMC1_IRQn);
/* USER CODE BEGIN SDMMC1_MspDeInit 1 */
/* USER CODE END SDMMC1_MspDeInit 1 */
}
}
/**
* @brief TIM_PWM MSP Initialization
* This function configures the hardware resources used in this example
* @param htim_pwm: TIM_PWM handle pointer
* @retval None
*/
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
{
if(htim_pwm->Instance==TIM1)
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
/* USER CODE BEGIN TIM1_MspInit 1 */
/* USER CODE END TIM1_MspInit 1 */
}
}
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(htim->Instance==TIM1)
{
/* USER CODE BEGIN TIM1_MspPostInit 0 */
/* USER CODE END TIM1_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
/**TIM1 GPIO Configuration
PA8 ------> TIM1_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN TIM1_MspPostInit 1 */
/* USER CODE END TIM1_MspPostInit 1 */
}
}
/**
* @brief TIM_PWM MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param htim_pwm: TIM_PWM handle pointer
* @retval None
*/
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm)
{
if(htim_pwm->Instance==TIM1)
{
/* USER CODE BEGIN TIM1_MspDeInit 0 */
/* USER CODE END TIM1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_TIM1_CLK_DISABLE();
/* USER CODE BEGIN TIM1_MspDeInit 1 */
/* USER CODE END TIM1_MspDeInit 1 */
}
}
/**
* @brief UART MSP Initialization
* This function configures the hardware resources used in this example
@ -92,7 +573,6 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
@ -153,6 +633,91 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
}
/**
* @brief PCD MSP Initialization
* This function configures the hardware resources used in this example
* @param hpcd: PCD handle pointer
* @retval None
*/
void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hpcd->Instance==USB_OTG_FS)
{
/* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
/* USER CODE END USB_OTG_FS_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Enable USB Voltage detector
*/
HAL_PWREx_EnableUSBVoltageDetector();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**USB_OTG_FS GPIO Configuration
PA12 ------> USB_OTG_FS_DP
PA11 ------> USB_OTG_FS_DM
*/
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* Peripheral clock enable */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
/* USB_OTG_FS interrupt Init */
HAL_NVIC_SetPriority(OTG_FS_EP1_OUT_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(OTG_FS_EP1_OUT_IRQn);
HAL_NVIC_SetPriority(OTG_FS_EP1_IN_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(OTG_FS_EP1_IN_IRQn);
/* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
/* USER CODE END USB_OTG_FS_MspInit 1 */
}
}
/**
* @brief PCD MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hpcd: PCD handle pointer
* @retval None
*/
void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd)
{
if(hpcd->Instance==USB_OTG_FS)
{
/* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */
/* USER CODE END USB_OTG_FS_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USB_OTG_FS_CLK_DISABLE();
/**USB_OTG_FS GPIO Configuration
PA12 ------> USB_OTG_FS_DP
PA11 ------> USB_OTG_FS_DM
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12|GPIO_PIN_11);
/* USB_OTG_FS interrupt DeInit */
HAL_NVIC_DisableIRQ(OTG_FS_EP1_OUT_IRQn);
HAL_NVIC_DisableIRQ(OTG_FS_EP1_IN_IRQn);
/* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */
/* USER CODE END USB_OTG_FS_MspDeInit 1 */
}
}
static uint32_t FMC_Initialized = 0;
static void HAL_FMC_MspInit(void){
@ -430,3 +995,4 @@ void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

387
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32h743_openmv_h7plus/board/CubeMX_Config/CubeMX_Config.ioc
View File

@ -1,4 +1,32 @@
#MicroXplorer Configuration settings - do not modify
CORTEX_M7.CPU_DCache=Enabled
CORTEX_M7.CPU_ICache=Enabled
CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache
DCMI.IPParameters=JPEGMode
DCMI.JPEGMode=DCMI_JPEG_ENABLE
Dma.DCMI.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.DCMI.0.EventEnable=DISABLE
Dma.DCMI.0.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.DCMI.0.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.DCMI.0.Instance=DMA1_Stream3
Dma.DCMI.0.MemBurst=DMA_MBURST_SINGLE
Dma.DCMI.0.MemDataAlignment=DMA_MDATAALIGN_WORD
Dma.DCMI.0.MemInc=DMA_MINC_ENABLE
Dma.DCMI.0.Mode=DMA_CIRCULAR
Dma.DCMI.0.PeriphBurst=DMA_PBURST_SINGLE
Dma.DCMI.0.PeriphDataAlignment=DMA_PDATAALIGN_WORD
Dma.DCMI.0.PeriphInc=DMA_PINC_DISABLE
Dma.DCMI.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.DCMI.0.Priority=DMA_PRIORITY_HIGH
Dma.DCMI.0.RequestNumber=1
Dma.DCMI.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.DCMI.0.SignalID=NONE
Dma.DCMI.0.SyncEnable=DISABLE
Dma.DCMI.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.DCMI.0.SyncRequestNumber=1
Dma.DCMI.0.SyncSignalID=NONE
Dma.Request0=DCMI
Dma.RequestsNb=1
FMC.BankMapConfig=FMC_SWAPBMAP_DISABLE
FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_2
FMC.ColumnBitsNumber1=FMC_SDRAM_COLUMN_BITS_NUM_9
@ -18,117 +46,189 @@ KeepUserPlacement=false
Mcu.CPN=STM32H743IIK6
Mcu.Family=STM32H7
Mcu.IP0=CORTEX_M7
Mcu.IP1=FMC
Mcu.IP2=NVIC
Mcu.IP3=RCC
Mcu.IP4=SYS
Mcu.IP5=USART1
Mcu.IPNb=6
Mcu.IP1=DCMI
Mcu.IP10=TIM1
Mcu.IP11=USART1
Mcu.IP12=USB_OTG_FS
Mcu.IP2=DMA
Mcu.IP3=FMC
Mcu.IP4=NVIC
Mcu.IP5=QUADSPI
Mcu.IP6=RCC
Mcu.IP7=RTC
Mcu.IP8=SDMMC1
Mcu.IP9=SYS
Mcu.IPNb=13
Mcu.Name=STM32H743IIKx
Mcu.Package=UFBGA176
Mcu.Pin0=PE1
Mcu.Pin1=PE0
Mcu.Pin10=PI9
Mcu.Pin11=PI4
Mcu.Pin12=PH15
Mcu.Pin13=PI1
Mcu.Pin14=PF0
Mcu.Pin15=PI10
Mcu.Pin16=PH13
Mcu.Pin17=PH14
Mcu.Pin18=PI0
Mcu.Pin19=PH0-OSC_IN (PH0)
Mcu.Pin2=PG15
Mcu.Pin20=PH1-OSC_OUT (PH1)
Mcu.Pin21=PF2
Mcu.Pin22=PF1
Mcu.Pin23=PG8
Mcu.Pin24=PF3
Mcu.Pin25=PF4
Mcu.Pin26=PF5
Mcu.Pin27=PH12
Mcu.Pin28=PG5
Mcu.Pin29=PG4
Mcu.Pin3=PD0
Mcu.Pin30=PH11
Mcu.Pin31=PH10
Mcu.Pin32=PD15
Mcu.Pin33=PC0
Mcu.Pin34=PC1
Mcu.Pin35=PC2_C
Mcu.Pin36=PG1
Mcu.Pin37=PH8
Mcu.Pin38=PH9
Mcu.Pin39=PD14
Mcu.Pin4=PI7
Mcu.Pin40=PC4
Mcu.Pin41=PF13
Mcu.Pin42=PG0
Mcu.Pin43=PE13
Mcu.Pin44=PD10
Mcu.Pin45=PC5
Mcu.Pin46=PF12
Mcu.Pin47=PF15
Mcu.Pin48=PE8
Mcu.Pin49=PE9
Mcu.Pin5=PI6
Mcu.Pin50=PE11
Mcu.Pin51=PE14
Mcu.Pin52=PD9
Mcu.Pin53=PD8
Mcu.Pin54=PA7
Mcu.Pin55=PF11
Mcu.Pin56=PF14
Mcu.Pin57=PE7
Mcu.Pin58=PE10
Mcu.Pin59=PE12
Mcu.Pin6=PI5
Mcu.Pin60=PE15
Mcu.Pin61=PB14
Mcu.Pin62=PB15
Mcu.Pin63=VP_SYS_VS_Systick
Mcu.Pin7=PD1
Mcu.Pin8=PI3
Mcu.Pin9=PI2
Mcu.PinsNb=64
Mcu.Pin10=PG10
Mcu.Pin11=PD0
Mcu.Pin12=PC11
Mcu.Pin13=PC10
Mcu.Pin14=PA12
Mcu.Pin15=PI7
Mcu.Pin16=PI6
Mcu.Pin17=PI5
Mcu.Pin18=PD1
Mcu.Pin19=PI3
Mcu.Pin2=PC12
Mcu.Pin20=PI2
Mcu.Pin21=PA11
Mcu.Pin22=PI9
Mcu.Pin23=PI4
Mcu.Pin24=PD2
Mcu.Pin25=PH15
Mcu.Pin26=PI1
Mcu.Pin27=PF0
Mcu.Pin28=PI10
Mcu.Pin29=PH13
Mcu.Pin3=PE4
Mcu.Pin30=PH14
Mcu.Pin31=PI0
Mcu.Pin32=PC9
Mcu.Pin33=PA8
Mcu.Pin34=PH0-OSC_IN (PH0)
Mcu.Pin35=PC8
Mcu.Pin36=PC7
Mcu.Pin37=PH1-OSC_OUT (PH1)
Mcu.Pin38=PF2
Mcu.Pin39=PF1
Mcu.Pin4=PE5
Mcu.Pin40=PG8
Mcu.Pin41=PC6
Mcu.Pin42=PF3
Mcu.Pin43=PF4
Mcu.Pin44=PG6
Mcu.Pin45=PF7
Mcu.Pin46=PF6
Mcu.Pin47=PF5
Mcu.Pin48=PH12
Mcu.Pin49=PG5
Mcu.Pin5=PE6
Mcu.Pin50=PG4
Mcu.Pin51=PF10
Mcu.Pin52=PF9
Mcu.Pin53=PF8
Mcu.Pin54=PH11
Mcu.Pin55=PH10
Mcu.Pin56=PD15
Mcu.Pin57=PC0
Mcu.Pin58=PG1
Mcu.Pin59=PH8
Mcu.Pin6=PB7
Mcu.Pin60=PH9
Mcu.Pin61=PD14
Mcu.Pin62=PA4
Mcu.Pin63=PC4
Mcu.Pin64=PF13
Mcu.Pin65=PG0
Mcu.Pin66=PE13
Mcu.Pin67=PD10
Mcu.Pin68=PA6
Mcu.Pin69=PC5
Mcu.Pin7=PB6
Mcu.Pin70=PF12
Mcu.Pin71=PF15
Mcu.Pin72=PE8
Mcu.Pin73=PE9
Mcu.Pin74=PE11
Mcu.Pin75=PE14
Mcu.Pin76=PD9
Mcu.Pin77=PD8
Mcu.Pin78=PA7
Mcu.Pin79=PF11
Mcu.Pin8=PG15
Mcu.Pin80=PF14
Mcu.Pin81=PE7
Mcu.Pin82=PE10
Mcu.Pin83=PE12
Mcu.Pin84=PE15
Mcu.Pin85=PB14
Mcu.Pin86=PB15
Mcu.Pin87=VP_RTC_VS_RTC_Activate
Mcu.Pin88=VP_RTC_VS_RTC_Calendar
Mcu.Pin89=VP_SYS_VS_Systick
Mcu.Pin9=PG11
Mcu.PinsNb=90
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32H743IIKx
MxCube.Version=6.5.0
MxDb.Version=DB.6.0.50
MxCube.Version=6.4.0
MxDb.Version=DB.6.0.40
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.DCMI_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.DMA1_Stream3_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.OTG_FS_EP1_IN_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.OTG_FS_EP1_OUT_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SDMMC1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
PA11.GPIOParameters=GPIO_Speed
PA11.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PA11.Mode=Device_Only
PA11.Signal=USB_OTG_FS_DM
PA12.GPIOParameters=GPIO_Speed
PA12.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PA12.Mode=Device_Only
PA12.Signal=USB_OTG_FS_DP
PA4.GPIOParameters=GPIO_Speed,GPIO_PuPd
PA4.GPIO_PuPd=GPIO_PULLUP
PA4.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PA4.Locked=true
PA4.Mode=Slave_8_bits_External_Synchro
PA4.Signal=DCMI_HSYNC
PA6.GPIOParameters=GPIO_Speed,GPIO_PuPd
PA6.GPIO_PuPd=GPIO_PULLUP
PA6.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PA6.Locked=true
PA6.Mode=Slave_8_bits_External_Synchro
PA6.Signal=DCMI_PIXCLK
PA7.GPIOParameters=GPIO_PuPd
PA7.GPIO_PuPd=GPIO_PULLUP
PA7.Locked=true
PA7.Signal=FMC_SDNWE
PA8.GPIOParameters=GPIO_Speed,GPIO_PuPd
PA8.GPIO_PuPd=GPIO_PULLUP
PA8.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PA8.Signal=S_TIM1_CH1
PB14.Locked=true
PB14.Mode=Asynchronous
PB14.Signal=USART1_TX
PB15.Locked=true
PB15.Mode=Asynchronous
PB15.Signal=USART1_RX
PB6.GPIOParameters=GPIO_Speed,GPIO_PuPd
PB6.GPIO_PuPd=GPIO_PULLUP
PB6.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PB6.Locked=true
PB6.Mode=Slave_8_bits_External_Synchro
PB6.Signal=DCMI_D5
PB7.GPIOParameters=GPIO_Speed,GPIO_PuPd
PB7.GPIO_PuPd=GPIO_PULLUP
PB7.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PB7.Locked=true
PB7.Mode=Slave_8_bits_External_Synchro
PB7.Signal=DCMI_VSYNC
PC0.GPIOParameters=GPIO_Label
PC0.GPIO_Label=LED_RED
PC0.Locked=true
PC0.Signal=GPIO_Output
PC1.GPIOParameters=GPIO_Label
PC1.GPIO_Label=LED_GREEN
PC1.Locked=true
PC1.Signal=GPIO_Output
PC2_C.GPIOParameters=GPIO_Label
PC2_C.GPIO_Label=LED_BLUE
PC2_C.Locked=true
PC2_C.Signal=GPIO_Output
PC10.Mode=SD_4_bits_Wide_bus
PC10.Signal=SDMMC1_D2
PC11.Mode=SD_4_bits_Wide_bus
PC11.Signal=SDMMC1_D3
PC12.Mode=SD_4_bits_Wide_bus
PC12.Signal=SDMMC1_CK
PC4.GPIOParameters=GPIO_PuPd
PC4.GPIO_PuPd=GPIO_PULLUP
PC4.Locked=true
@ -139,6 +239,22 @@ PC5.GPIO_PuPd=GPIO_PULLUP
PC5.Locked=true
PC5.Mode=SdramChipSelect1_1
PC5.Signal=FMC_SDCKE0
PC6.GPIOParameters=GPIO_Speed,GPIO_PuPd
PC6.GPIO_PuPd=GPIO_PULLUP
PC6.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PC6.Locked=true
PC6.Mode=Slave_8_bits_External_Synchro
PC6.Signal=DCMI_D0
PC7.GPIOParameters=GPIO_Speed,GPIO_PuPd
PC7.GPIO_PuPd=GPIO_PULLUP
PC7.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PC7.Locked=true
PC7.Mode=Slave_8_bits_External_Synchro
PC7.Signal=DCMI_D1
PC8.Mode=SD_4_bits_Wide_bus
PC8.Signal=SDMMC1_D0
PC9.Mode=SD_4_bits_Wide_bus
PC9.Signal=SDMMC1_D1
PD0.GPIOParameters=GPIO_PuPd
PD0.GPIO_PuPd=GPIO_PULLUP
PD0.Signal=FMC_D2_DA2
@ -154,6 +270,8 @@ PD14.Signal=FMC_D0_DA0
PD15.GPIOParameters=GPIO_PuPd
PD15.GPIO_PuPd=GPIO_PULLUP
PD15.Signal=FMC_D1_DA1
PD2.Mode=SD_4_bits_Wide_bus
PD2.Signal=SDMMC1_CMD
PD8.GPIOParameters=GPIO_PuPd
PD8.GPIO_PuPd=GPIO_PULLUP
PD8.Signal=FMC_D13_DA13
@ -184,6 +302,24 @@ PE14.Signal=FMC_D11_DA11
PE15.GPIOParameters=GPIO_PuPd
PE15.GPIO_PuPd=GPIO_PULLUP
PE15.Signal=FMC_D12_DA12
PE4.GPIOParameters=GPIO_Speed,GPIO_PuPd
PE4.GPIO_PuPd=GPIO_PULLUP
PE4.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PE4.Locked=true
PE4.Mode=Slave_8_bits_External_Synchro
PE4.Signal=DCMI_D4
PE5.GPIOParameters=GPIO_Speed,GPIO_PuPd
PE5.GPIO_PuPd=GPIO_PULLUP
PE5.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PE5.Locked=true
PE5.Mode=Slave_8_bits_External_Synchro
PE5.Signal=DCMI_D6
PE6.GPIOParameters=GPIO_Speed,GPIO_PuPd
PE6.GPIO_PuPd=GPIO_PULLUP
PE6.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PE6.Locked=true
PE6.Mode=Slave_8_bits_External_Synchro
PE6.Signal=DCMI_D7
PE7.GPIOParameters=GPIO_PuPd
PE7.GPIO_PuPd=GPIO_PULLUP
PE7.Signal=FMC_D4_DA4
@ -199,6 +335,11 @@ PF0.Signal=FMC_A0
PF1.GPIOParameters=GPIO_PuPd
PF1.GPIO_PuPd=GPIO_PULLUP
PF1.Signal=FMC_A1
PF10.GPIOParameters=GPIO_Speed
PF10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PF10.Locked=true
PF10.Mode=Single Bank 1
PF10.Signal=QUADSPI_CLK
PF11.GPIOParameters=GPIO_PuPd
PF11.GPIO_PuPd=GPIO_PULLUP
PF11.Signal=FMC_SDNRAS
@ -226,12 +367,44 @@ PF4.Signal=FMC_A4
PF5.GPIOParameters=GPIO_PuPd
PF5.GPIO_PuPd=GPIO_PULLUP
PF5.Signal=FMC_A5
PF6.GPIOParameters=GPIO_Speed
PF6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PF6.Locked=true
PF6.Mode=Single Bank 1
PF6.Signal=QUADSPI_BK1_IO3
PF7.GPIOParameters=GPIO_Speed
PF7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PF7.Locked=true
PF7.Mode=Single Bank 1
PF7.Signal=QUADSPI_BK1_IO2
PF8.GPIOParameters=GPIO_Speed
PF8.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PF8.Locked=true
PF8.Mode=Single Bank 1
PF8.Signal=QUADSPI_BK1_IO0
PF9.GPIOParameters=GPIO_Speed
PF9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PF9.Locked=true
PF9.Mode=Single Bank 1
PF9.Signal=QUADSPI_BK1_IO1
PG0.GPIOParameters=GPIO_PuPd
PG0.GPIO_PuPd=GPIO_PULLUP
PG0.Signal=FMC_A10
PG1.GPIOParameters=GPIO_PuPd
PG1.GPIO_PuPd=GPIO_PULLUP
PG1.Signal=FMC_A11
PG10.GPIOParameters=GPIO_Speed,GPIO_PuPd
PG10.GPIO_PuPd=GPIO_PULLUP
PG10.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PG10.Locked=true
PG10.Mode=Slave_8_bits_External_Synchro
PG10.Signal=DCMI_D2
PG11.GPIOParameters=GPIO_Speed,GPIO_PuPd
PG11.GPIO_PuPd=GPIO_PULLUP
PG11.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PG11.Locked=true
PG11.Mode=Slave_8_bits_External_Synchro
PG11.Signal=DCMI_D3
PG15.GPIOParameters=GPIO_PuPd
PG15.GPIO_PuPd=GPIO_PULLUP
PG15.Signal=FMC_SDNCAS
@ -241,6 +414,11 @@ PG4.Signal=FMC_A14_BA0
PG5.GPIOParameters=GPIO_PuPd
PG5.GPIO_PuPd=GPIO_PULLUP
PG5.Signal=FMC_A15_BA1
PG6.GPIOParameters=GPIO_PuPd
PG6.GPIO_PuPd=GPIO_PULLUP
PG6.Locked=true
PG6.Mode=Single Bank 1
PG6.Signal=QUADSPI_BK1_NCS
PG8.GPIOParameters=GPIO_PuPd
PG8.GPIO_PuPd=GPIO_PULLUP
PG8.Signal=FMC_SDCLK
@ -313,7 +491,7 @@ ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32H743IIKx
ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.10.0
ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.9.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
@ -331,7 +509,13 @@ ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5.32
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_FMC_Init-FMC-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_FMC_Init-FMC-false-HAL-true,5-MX_QUADSPI_Init-QUADSPI-false-HAL-true,6-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,7-MX_DMA_Init-DMA-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_DCMI_Init-DCMI-false-HAL-true,10-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
QUADSPI.ChipSelectHighTime=QSPI_CS_HIGH_TIME_2_CYCLE
QUADSPI.ClockPrescaler=1
QUADSPI.FifoThreshold=3
QUADSPI.FlashSize=24
QUADSPI.IPParameters=ClockPrescaler,FifoThreshold,SampleShifting,FlashSize,ChipSelectHighTime
QUADSPI.SampleShifting=QSPI_SAMPLE_SHIFTING_HALFCYCLE
RCC.ADCFreq_Value=24187500
RCC.AHB12Freq_Value=200000000
RCC.AHB4Freq_Value=200000000
@ -349,20 +533,21 @@ RCC.D1PPRE=RCC_APB3_DIV2
RCC.D2PPRE1=RCC_APB1_DIV2
RCC.D2PPRE2=RCC_APB2_DIV2
RCC.D3PPRE=RCC_APB4_DIV2
RCC.DFSDMACLkFreq_Value=400000000
RCC.DFSDMACLkFreq_Value=200000000
RCC.DFSDMFreq_Value=100000000
RCC.DIVM1=3
RCC.DIVN1=200
RCC.DIVP1Freq_Value=400000000
RCC.DIVP2Freq_Value=24187500
RCC.DIVP3Freq_Value=24187500
RCC.DIVQ1Freq_Value=400000000
RCC.DIVQ1=4
RCC.DIVQ1Freq_Value=200000000
RCC.DIVQ2Freq_Value=24187500
RCC.DIVQ3Freq_Value=24187500
RCC.DIVR1Freq_Value=400000000
RCC.DIVR2Freq_Value=24187500
RCC.DIVR3Freq_Value=24187500
RCC.FDCANFreq_Value=400000000
RCC.FDCANFreq_Value=200000000
RCC.FMCFreq_Value=200000000
RCC.FamilyName=M
RCC.HCLK3ClockFreq_Value=200000000
@ -372,7 +557,7 @@ RCC.HRTIMFreq_Value=200000000
RCC.HSE_VALUE=12000000
RCC.I2C123Freq_Value=100000000
RCC.I2C4Freq_Value=100000000
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
RCC.LPTIM1Freq_Value=100000000
RCC.LPTIM2Freq_Value=100000000
RCC.LPTIM345Freq_Value=100000000
@ -387,13 +572,13 @@ RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.QSPIFreq_Value=200000000
RCC.RNGFreq_Value=48000000
RCC.RTCFreq_Value=32000
RCC.SAI1Freq_Value=400000000
RCC.SAI23Freq_Value=400000000
RCC.SAI4AFreq_Value=400000000
RCC.SAI4BFreq_Value=400000000
RCC.SDMMCFreq_Value=400000000
RCC.SPDIFRXFreq_Value=400000000
RCC.SPI123Freq_Value=400000000
RCC.SAI1Freq_Value=200000000
RCC.SAI23Freq_Value=200000000
RCC.SAI4AFreq_Value=200000000
RCC.SAI4BFreq_Value=200000000
RCC.SDMMCFreq_Value=200000000
RCC.SPDIFRXFreq_Value=200000000
RCC.SPI123Freq_Value=200000000
RCC.SPI45Freq_Value=100000000
RCC.SPI6Freq_Value=100000000
RCC.SWPMI1Freq_Value=100000000
@ -404,13 +589,16 @@ RCC.Tim2OutputFreq_Value=200000000
RCC.TraceFreq_Value=64000000
RCC.USART16Freq_Value=100000000
RCC.USART234578Freq_Value=100000000
RCC.USBFreq_Value=400000000
RCC.USBCLockSelection=RCC_USBCLKSOURCE_HSI48
RCC.USBFreq_Value=48000000
RCC.VCO1OutputFreq_Value=800000000
RCC.VCO2OutputFreq_Value=48375000
RCC.VCO3OutputFreq_Value=48375000
RCC.VCOInput1Freq_Value=4000000
RCC.VCOInput2Freq_Value=375000
RCC.VCOInput3Freq_Value=375000
SDMMC1.ClockDiv=4
SDMMC1.IPParameters=ClockDiv
SH.FMC_A0.0=FMC_A0,12b-sda1
SH.FMC_A0.ConfNb=1
SH.FMC_A1.0=FMC_A1,12b-sda1
@ -519,8 +707,21 @@ SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda1
SH.FMC_SDNRAS.ConfNb=1
SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda1
SH.FMC_SDNWE.ConfNb=1
SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1
SH.S_TIM1_CH1.ConfNb=1
TIM1.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE
TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
TIM1.IPParameters=Channel-PWM Generation1 CH1,Period,AutoReloadPreload,Pulse-PWM Generation1 CH1
TIM1.Period=7
TIM1.Pulse-PWM\ Generation1\ CH1=3
USART1.IPParameters=VirtualMode-Asynchronous
USART1.VirtualMode-Asynchronous=VM_ASYNC
USB_OTG_FS.IPParameters=VirtualMode
USB_OTG_FS.VirtualMode=Device_Only
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar
VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom

44
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32h743_openmv_h7plus/board/Kconfig
View File

@ -38,7 +38,7 @@ menu "On-chip Peripheral Drivers"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_USING_LPUART1
config BSP_USING_LPUART1
bool "Enable LPUART1"
default n
@ -48,12 +48,46 @@ menu "On-chip Peripheral Drivers"
default n
endif
config BSP_USING_SDRAM
bool "Enable SDRAM"
default n
config BSP_USING_QSPI
bool "Enable QSPI BUS"
select RT_USING_QSPI
select RT_USING_SPI
default n
config BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
source "$RTT_DIR/bsp/stm32/libraries/HAL_Drivers/Kconfig"
endmenu
endmenu
menu "Onboard Peripheral Drivers"
config BSP_USING_SDRAM
bool "Enable SDRAM"
default n
config BSP_USING_QSPI_FLASH
bool "Enable QSPI FLASH (W25Q256 qspi)"
select BSP_USING_QSPI
select RT_USING_SFUD
select RT_SFUD_USING_QSPI
default n
config BSP_USING_SDMMC
bool "Enable SDMMC (SD card)"
select RT_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
config BSP_USING_USBD
bool "Enable OTGFS as USB device"
select RT_USING_USB_DEVICE
default n
endmenu
endmenu

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