From 56fbb14dad408a2d5d959fa7d54c585d532ac027 Mon Sep 17 00:00:00 2001 From: Wang_Weigen Date: Thu, 24 Mar 2022 17:21:14 +0800 Subject: [PATCH] replace file 'fsl_phy.c' to support LAN8720a --- .../third_party_driver/ethernet/Makefile | 2 +- .../ethernet/{ksz8081 => lan8720}/Makefile | 0 .../ethernet/{ksz8081 => lan8720}/fsl_phy.c | 96 +++++++++---------- .../ethernet/{ksz8081 => lan8720}/fsl_phy.h | 74 ++++++++------ Ubiquitous/XiZi/path_kernel.mk | 2 +- 5 files changed, 95 insertions(+), 79 deletions(-) rename Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/{ksz8081 => lan8720}/Makefile (100%) rename Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/{ksz8081 => lan8720}/fsl_phy.c (71%) mode change 100755 => 100644 rename Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/{ksz8081 => lan8720}/fsl_phy.h (72%) mode change 100755 => 100644 diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/Makefile index 14be72829..65f5adc78 100755 --- a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/Makefile +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/Makefile @@ -1,3 +1,3 @@ SRC_FILES := enet_ethernetif.c enet_ethernetif_kinetis.c fsl_enet.c -SRC_DIR := ksz8081 +SRC_DIR := lan8720 include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/ksz8081/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/Makefile similarity index 100% rename from Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/ksz8081/Makefile rename to Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/Makefile diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/ksz8081/fsl_phy.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.c old mode 100755 new mode 100644 similarity index 71% rename from Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/ksz8081/fsl_phy.c rename to Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.c index 7f99f8216..1017aa038 --- a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/ksz8081/fsl_phy.c +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.c @@ -1,28 +1,44 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2017 NXP * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * - * SPDX-License-Identifier: BSD-3-Clause + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/** - * @file fsl_phy.c - * @brief phy drivers for ksz8081 - * @version 1.0 - * @author AIIT XUOS Lab - * @date 2021.11.11 - */ - -#include "lwipopts.h" #include "fsl_phy.h" - /******************************************************************************* * Definitions ******************************************************************************/ /*! @brief Defines the timeout macro. */ -#define PHY_TIMEOUT_COUNT 100000 +#define PHY_TIMEOUT_COUNT 0x3FFFFFFU /******************************************************************************* * Prototypes @@ -52,12 +68,11 @@ extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) { uint32_t bssReg; - uint32_t counter = PHY_TIMEOUT_COUNT; - uint32_t idReg = 0; - status_t result = kStatus_Success; + uint32_t counter = PHY_TIMEOUT_COUNT; + uint32_t idReg = 0; + status_t result = kStatus_Success; uint32_t instance = ENET_GetInstance(base); uint32_t timeDelay; - uint32_t ctlReg = 0; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Set SMI first. */ @@ -69,7 +84,7 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) while ((idReg != PHY_CONTROL_ID1) && (counter != 0)) { PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); - counter--; + counter --; } if (!counter) @@ -79,44 +94,30 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) /* Reset PHY. */ counter = PHY_TIMEOUT_COUNT; - result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); if (result == kStatus_Success) - { -#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE) - uint32_t data = 0; - result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); - if (result != kStatus_Success) - { - return result; - } - result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK)); - if (result != kStatus_Success) - { - return result; - } -#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */ - + { + /* Set the negotiation. */ result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); if (result == kStatus_Success) { - result = - PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, + (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); if (result == kStatus_Success) { /* Check auto negotiation complete. */ - while (counter--) + while (counter --) { result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); - if (result == kStatus_Success) + if ( result == kStatus_Success) { - PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); - if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK)) + if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) { /* Wait a moment for Phy status stable. */ - for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay++) + for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++) { __ASM("nop"); } @@ -219,17 +220,17 @@ status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, } else { - data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; } - return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data); + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data); } else { /* First read the current status in control register. */ - result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &data); if (result == kStatus_Success) { - return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); + return PHY_Write(base, phyAddr, PHY_CONTROL1_REG, (data | PHY_CTL1_REMOTELOOP_MASK)); } } } @@ -249,10 +250,10 @@ status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, else { /* First read the current status in control one register. */ - result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &data); if (result == kStatus_Success) { - return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); + return PHY_Write(base, phyAddr, PHY_CONTROL1_REG, (data & ~PHY_CTL1_REMOTELOOP_MASK)); } } } @@ -291,7 +292,6 @@ status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t * status_t result = kStatus_Success; uint32_t data, ctlReg; - /* Read the control two register. */ result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); if (result == kStatus_Success) diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/ksz8081/fsl_phy.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.h old mode 100755 new mode 100644 similarity index 72% rename from Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/ksz8081/fsl_phy.h rename to Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.h index 3f0e905fa..3e2a93cb1 --- a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/ksz8081/fsl_phy.h +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.h @@ -1,19 +1,36 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * - * SPDX-License-Identifier: BSD-3-Clause + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - -/** - * @file fsl_phy.h - * @brief phy drivers for ksz8081 - * @version 1.0 - * @author AIIT XUOS Lab - * @date 2021.11.11 - */ - #ifndef _FSL_PHY_H_ #define _FSL_PHY_H_ @@ -37,10 +54,9 @@ #define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ #define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ #define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ -#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ -#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ +#define PHY_CONTROL1_REG 0x1FU /*!< The PHY control one register. */ -#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ +#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/ /*! @brief Defines the mask flag in basic control register. */ #define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ @@ -49,20 +65,20 @@ #define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ #define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ #define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ -#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */ +#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */ /*!@brief Defines the mask flag of operation mode in control two register*/ -#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ -#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ -#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ -#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ -#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ -#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ -#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ +#define PHY_CTL1_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ +//#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ +#define PHY_CTL1_10HALFDUPLEX_MASK 0x0004U /*!< The PHY 10M half duplex mask. */ +#define PHY_CTL1_100HALFDUPLEX_MASK 0x0008U /*!< The PHY 100M half duplex mask. */ +#define PHY_CTL1_10FULLDUPLEX_MASK 0x0014U /*!< The PHY 10M full duplex mask. */ +#define PHY_CTL1_100FULLDUPLEX_MASK 0x0018U /*!< The PHY 100M full duplex mask. */ +#define PHY_CTL1_SPEEDUPLX_MASK 0x001CU /*!< The PHY speed and duplex mask. */ #define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */ -#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ +#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ #define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) - + /*! @brief Defines the mask flag in basic status register. */ #define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ #define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ @@ -78,8 +94,8 @@ /*! @brief Defines the PHY status. */ enum _phy_status { - kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ - kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ + kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ + kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ }; /*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ @@ -112,16 +128,16 @@ extern "C" { #endif /*! - * @name PHY Driver - * @{ - */ + * @name PHY Driver + * @{ + */ /*! * @brief Initializes PHY. * * This function initialize the SMI interface and initialize PHY. * The SMI is the MII management interface between PHY and MAC, which should be - * firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. + * firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. * * @param base ENET peripheral base address. * @param phyAddr The PHY address. diff --git a/Ubiquitous/XiZi/path_kernel.mk b/Ubiquitous/XiZi/path_kernel.mk index 3696e2a4b..3b6f53047 100755 --- a/Ubiquitous/XiZi/path_kernel.mk +++ b/Ubiquitous/XiZi/path_kernel.mk @@ -14,7 +14,7 @@ KERNELPATHS :=-I$(BSP_ROOT) \ -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/osa \ -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/phy \ -I$(BSP_ROOT)/third_party_driver/ethernet \ - -I$(BSP_ROOT)/third_party_driver/ethernet/ksz8081 \ + -I$(BSP_ROOT)/third_party_driver/ethernet/lan8720 \ -I$(BSP_ROOT)/third_party_driver/MIMXRT1052 \ -I$(BSP_ROOT)/third_party_driver/MIMXRT1052/drivers \ -I$(BSP_ROOT)/third_party_driver/CMSIS/Include \