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Change some compile flags.

This commit is contained in:
TXuian 2024-05-15 17:59:38 +08:00
parent 48abec8a00
commit 52387d47a7
36 changed files with 7264 additions and 7175 deletions
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3
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/config.mk
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@ -1,6 +1,7 @@
export CROSS_COMPILE ?= arm-none-eabi-
export DEVICE = -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=softfp
export CFLAGS := $(DEVICE) -Wall -O2 -g -gdwarf-2 -Wnull-dereference -Waddress -Warray-bounds -Wchar-subscripts -Wimplicit-int -Wimplicit-function-declaration -Wcomment -Wformat -Wmissing-braces -Wnonnull -Wparentheses -Wpointer-sign -Wreturn-type -Wsequence-point -Wstrict-aliasing -Wstrict-overflow=1 -Wswitch -Wtrigraphs -Wuninitialized -Wunknown-pragmas -Wunused-function -Wunused-label -Wunused-value -Wunused-variable -Wunused-function
# export CFLAGS := $(DEVICE) -std=c11 -Wall -O2 -g -gdwarf-2 -Wnull-dereference -Waddress -Warray-bounds -Wchar-subscripts -Wimplicit-int -Wimplicit-function-declaration -Wcomment -Wformat -Wmissing-braces -Wnonnull -Wparentheses -Wpointer-sign -Wreturn-type -Wsequence-point -Wstrict-aliasing -Wstrict-overflow=1 -Wswitch -Wtrigraphs -Wuninitialized -Wunknown-pragmas -Wunused-function -Wunused-label -Wunused-value -Wunused-variable -Wunused-function
export CFLAGS := $(DEVICE) -std=c11 -Wall -O2 -g -gdwarf-2 -Waddress -Warray-bounds -Wchar-subscripts -Wimplicit-int -Wimplicit-function-declaration -Wcomment -Wformat -Wmissing-braces -Wnonnull -Wparentheses -Wpointer-sign -Wreturn-type -Wsequence-point -Wstrict-aliasing -Wstrict-overflow=1 -Wswitch -Wtrigraphs -Wuninitialized -Wunknown-pragmas -Wunused-function -Wunused-label -Wunused-value -Wunused-variable -Wunused-function
export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
# export LFLAGS := $(DEVICE) -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/nxp_imx6q_sabrelite.lds
export LFLAGS := $(DEVICE) --specs=nosys.specs -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/nxp_imx6q_sabrelite.lds

4
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/include/cortex_a9.h
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@ -70,10 +70,10 @@ Modification:
#define ISB() __asm__ volatile("isb\n\t")
#define _ARM_MRC(coproc, opcode1, Rt, CRn, CRm, opcode2) \
asm volatile("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r"(Rt))
__asm__ volatile("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r"(Rt))
#define _ARM_MCR(coproc, opcode1, Rt, CRn, CRm, opcode2) \
asm volatile("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" ::[input] "r"(Rt))
__asm__ volatile("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" ::[input] "r"(Rt))
#define WriteReg(value, address) (*(volatile unsigned int*)(address) = (value))
#define ReadReg(address) (*(volatile unsigned int*)(address))

2
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/include/regs.h
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@ -56,7 +56,7 @@ typedef unsigned int reg32_t;
#endif
//
// Typecast macro for C or asm. In C, the cast is applied, while in asm it is excluded. This is
// Typecast macro for C or __asm__. In C, the cast is applied, while in __asm__ it is excluded. This is
// used to simplify macro definitions in the module register headers.
//
#ifndef __REG_VALUE_TYPE

4
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/include/soc_memory_map.h
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@ -18,14 +18,14 @@
/**
* @file soc_memory_map.h
* @brief support imx6q soc memory map define, reference from u-boot-2009-08/include/asm-arm/arch-mx6/mx6.h
* @brief support imx6q soc memory map define, reference from u-boot-2009-08/include/__asm__-arm/arch-mx6/mx6.h
* @version 3.0
* @author AIIT XUOS Lab
* @date 2023.09.08
*/
/*************************************************
File name: soc_memory_map.h
Description: support imx6q soc memory map define, reference from u-boot-2009-08/include/asm-arm/arch-mx6/mx6.h
Description: support imx6q soc memory map define, reference from u-boot-2009-08/include/__asm__-arm/arch-mx6/mx6.h
Others:
History:
1. Date: 2023-08-28

4
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/nxp_imx6q_sabrelite.lds
View File

@ -85,7 +85,7 @@ MEMORY
{
ocram (rwx) : ORIGIN = 0x00900000, LENGTH = 256K
ddr3 (rwx) : ORIGIN = 0x10000000, LENGTH = 1024M
virt_ddr3 (WRX) : ORIGIN = 0x90011000, LENGTH = 1024M
virt_ddr3 (WRX) : ORIGIN = 0x90014000, LENGTH = 1024M
}
SECTIONS
@ -159,7 +159,7 @@ SECTIONS
} > ddr3
/* Other Kernel code is placed over 0x10011000(phy) and 0x90011000(virt). */
.text : AT(0x10011000) {
.text : AT(0x10014000) {
*(.vectors)
. = ALIGN(0x1000);
*(.text .text.* .gnu.linkonce.t.*)

15
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/pagetable_attr.c
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@ -56,10 +56,9 @@ void GetUsrDevPteAttr(uintptr_t* attr)
usr_pte_attr.entry = 0;
usr_pte_attr.desc_type = PAGE_4K;
usr_pte_attr.C = 0;
usr_pte_attr.B = 0;
usr_pte_attr.TEX = 2;
usr_pte_attr.S = 0;
// usr_pte_attr.B = 1;
usr_pte_attr.S = 1;
usr_pte_attr.AP1_0 = AccessPermission_KernelUser;
}
*attr = usr_pte_attr.entry;
@ -99,5 +98,13 @@ void GetKernPteAttr(uintptr_t* attr)
void GetPdeAttr(uintptr_t* attr)
{
*attr = PAGE_DIR_COARSE;
static char init = 0;
static PageDirEntry pde_attr;
if (init == 0) {
init = 1;
pde_attr.entry = 0;
pde_attr.desc_type = PAGE_DIR_COARSE;
}
*attr = pde_attr.entry;
}

4
Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/include/iomux_v3.h
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@ -21,14 +21,14 @@
/**
* @file iomux_v3.h
* @brief support imx6q iomux function define, reference from u-boot-2009-08/include/asm-arm/arch-mx6/iomux_v3.h
* @brief support imx6q iomux function define, reference from u-boot-2009-08/include/__asm__-arm/arch-mx6/iomux_v3.h
* @version 3.0
* @author AIIT XUOS Lab
* @date 2023.09.08
*/
/*************************************************
File name: iomux_v3.h
Description: support imx6q iomux function define, reference from u-boot-2009-08/include/asm-arm/arch-mx6/iomux_v3.h
Description: support imx6q iomux function define, reference from u-boot-2009-08/include/__asm__-arm/arch-mx6/iomux_v3.h
Others:
History:
1. Date: 2023-09-08

4
Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/include/regs_pins.h
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@ -21,14 +21,14 @@
/**
* @file regs_pins.h
* @brief support imx6q pin map define, reference from u-boot-2009-08/include/asm-arm/arch-mx6/mx6_pins.h
* @brief support imx6q pin map define, reference from u-boot-2009-08/include/__asm__-arm/arch-mx6/mx6_pins.h
* @version 3.0
* @author AIIT XUOS Lab
* @date 2023.09.08
*/
/*************************************************
File name: regs_pins.h
Description: support imx6q pin map define, reference from u-boot-2009-08/include/asm-arm/arch-mx6/mx6_pins.h
Description: support imx6q pin map define, reference from u-boot-2009-08/include/__asm__-arm/arch-mx6/mx6_pins.h
Others:
History:
1. Date: 2023-09-08

4
Ubiquitous/XiZi_AIoT/services/app/Makefile
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@ -1,7 +1,7 @@
ifeq ($(BOARD), imx6q-sabrelite)
toolchain ?= arm-none-eabi-
user_ldflags = --specs=nosys.specs -Wl,-Map=user.map,-cref -N
cflags = -std=c11 -O2 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
cflags = -std=c11 -O2 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
ifeq ($(BOARD), zynq7000-zc702)
toolchain ?= arm-xilinx-eabi-
@ -14,7 +14,7 @@ endif
cc = ${toolchain}gcc
ld = ${toolchain}g++
objdump = ${toolchain}objdump
c_useropts = -O0
c_useropts = -O2
INC_DIR = -I$(KERNEL_ROOT)/services/shell/letter-shell \
-I$(KERNEL_ROOT)/services/lib/ipc \

4
Ubiquitous/XiZi_AIoT/services/app/test_irq_block.c
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@ -13,7 +13,7 @@
#include "test_irq.h"
IPC_INTERFACE(Ipc_wait_intr_3, 1, ignore, 0);
int wait_intr(struct Session* session, void* ignore_param)
int wait_intr(struct Session* session)
{
return IPC_CALL(Ipc_wait_intr_3)(session, NULL);
}
@ -28,7 +28,7 @@ int main(int argc, char* argv[])
}
printf("%s start waiting for IRQ.\n", prog_name);
wait_intr(&session, NULL);
wait_intr(&session);
printf("%s return from waiting for IRQ.\n", prog_name);
exit();

4
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile
View File

@ -9,8 +9,8 @@ ld = ${toolchain}g++
objdump = ${toolchain}objdump
user_ldflags = -N -Ttext 0
cflags = -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
c_useropts = -O0
cflags = -march=armv7-a -std=c11 -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
c_useropts = -O2
INC_DIR = -I$(KERNEL_ROOT)/services/fs/libfs \
-I$(KERNEL_ROOT)/services/lib/ipc \

2
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/clock/Makefile
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@ -10,7 +10,7 @@ objdump = ${toolchain}objdump
user_ldflags = -N -Ttext 0
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
c_useropts = -O0
c_useropts = -O2
INC_DIR = -I$(KERNEL_ROOT)/services/app \
-I$(KERNEL_ROOT)/services/boards/$(BOARD) \

34
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/clock/timer.c
View File

@ -109,20 +109,20 @@ void system_time_init(void)
int IPC_DO_SERVE_FUNC(Ipc_delay_us)(uint32_t* usecs)
{
uint32_t instance = g_system_timer_port;
if (*usecs == 0) {
return 0;
}
// uint32_t instance = g_system_timer_port;
// if (*usecs == 0) {
// return 0;
// }
/* enable the counter first */
epit_counter_enable(instance, *usecs, POLLING_MODE);
// /* enable the counter first */
// epit_counter_enable(instance, *usecs, POLLING_MODE);
/* wait for the compare event */
while (!epit_get_compare_event(instance))
;
// /* wait for the compare event */
// while (!epit_get_compare_event(instance))
// ;
/* disable the counter to save power */
epit_counter_disable(instance);
// /* disable the counter to save power */
// epit_counter_disable(instance);
return 0;
}
@ -159,19 +159,19 @@ IPC_SERVER_REGISTER_INTERFACES(IpcSabreliteTimer, 2, Ipc_delay_us, Ipc_get_micro
int main(int argc, char** argv)
{
printf("TIMER: Mapping %x(size: %x) to %x\n", AIPS1_ARB_PHY_BASE_ADDR, AIPS1_ARB_END_ADDR - AIPS1_ARB_BASE_ADDR, AIPS1_ARB_BASE_ADDR);
printf("TIMER: Mapping %08x(size: %x) to %08x\n", AIPS1_ARB_PHY_BASE_ADDR, AIPS1_ARB_END_ADDR - AIPS1_ARB_BASE_ADDR, AIPS1_ARB_BASE_ADDR);
if (!mmap(AIPS1_ARB_BASE_ADDR, AIPS1_ARB_PHY_BASE_ADDR, AIPS1_ARB_END_ADDR - AIPS1_ARB_BASE_ADDR, true)) {
printf("TIMER : mmap AIPS1 ARB(%x) failed\n", AIPS1_ARB_PHY_BASE_ADDR);
printf("TIMER : mmap AIPS1 ARB(%-08x) failed\n", AIPS1_ARB_PHY_BASE_ADDR);
}
printf("TIMER: Mapping %x(size: %x) to %x\n", AIPS2_ARB_PHY_BASE_ADDR, AIPS2_ARB_END_ADDR - AIPS2_ARB_BASE_ADDR, AIPS2_ARB_BASE_ADDR);
printf("TIMER: Mapping %08x(size: %x) to %08x\n", AIPS2_ARB_PHY_BASE_ADDR, AIPS2_ARB_END_ADDR - AIPS2_ARB_BASE_ADDR, AIPS2_ARB_BASE_ADDR);
if (!mmap(AIPS2_ARB_BASE_ADDR, AIPS2_ARB_PHY_BASE_ADDR, AIPS2_ARB_END_ADDR - AIPS2_ARB_BASE_ADDR, true)) {
printf("TIMER : mmap AIPS1 ARB(%x) failed\n", AIPS2_ARB_PHY_BASE_ADDR);
printf("TIMER : mmap AIPS1 ARB(%-08x) failed\n", AIPS2_ARB_PHY_BASE_ADDR);
}
printf("TIMER: Mapping %x(size: %x) to %x\n", REGS_ARMGLOBALTIMER_BASE, 0x1000, 0x00a00000);
printf("TIMER: Mapping %08x(size: %x) to %08x\n", REGS_ARMGLOBALTIMER_BASE, 0x1000, 0x00a00000);
if (!mmap(REGS_ARMGLOBALTIMER_BASE, 0x00a00000, 0x1000, true)) {
printf("TIMER : mmap GLOBAL TIMER(%x) failed\n", 0x00a00000);
printf("TIMER : mmap GLOBAL TIMER(%-08x) failed\n", 0x00a00000);
}
static char server_name[] = "TimerServer";

12
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/enet/Makefile
View File

@ -9,8 +9,16 @@ ld = ${toolchain}g++
objdump = ${toolchain}objdump
user_ldflags = -N -Ttext 0
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
c_useropts = -O0
cflags = -std=c11 -march=armv7-a -mcpu=cortex-a9 -mtune=cortex-a9 -g \
-Wno-unused -Wno-format -fno-common -ffreestanding -fno-builtin -static \
-Wno-unaligned-access -fdce -Wall -Werror -Wno-uninitialized -Wno-strict-aliasing -fdiagnostics-show-option \
-mapcs -marm -mfpu=neon -ftree-vectorize -fno-math-errno -funsafe-math-optimizations -fno-signed-zeros -mfloat-abi=softfp \
-fno-omit-frame-pointer -fno-stack-protector -fno-pie
# cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic \
# -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
c_useropts = -O2
INC_DIR = -I$(KERNEL_ROOT)/services/app \
-I$(KERNEL_ROOT)/services/boards/$(BOARD) \

9
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/enet/board_network.c
View File

@ -110,15 +110,6 @@ void imx_enet_iomux(void)
gpio_set_direction(GPIO_PORT6, 24, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT6, 24, GPIO_HIGH_LEVEL);
#endif
#ifdef BOARD_SABRE_AI
/* Select ENET, ENET_CAN1_STEER(PORT_EXP_B3) */
max7310_set_gpio_output(1, 2, GPIO_LOW_LEVEL);
/* Select ALT5 mode of GPIO_19 for GPIO4_5 - PGMIT_INT_B */
/* active low input */
gpio_set_gpio(GPIO_PORT4, 5);
gpio_set_direction(GPIO_PORT4, 5, GPIO_GDIR_INPUT);
#endif
}
#ifdef BOARD_SABRE_LITE

27
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/enet/enet_drv.c
View File

@ -63,15 +63,17 @@ int imx_enet_mii_read(volatile hw_enet_t* enet_reg, unsigned char phy_addr,
while (1) {
if (enet_reg->EIR.U & ENET_EVENT_MII) {
printf("[%s %d], EIR: %08x\n", __func__, __LINE__, enet_reg->EIR.U);
enet_reg->EIR.U = ENET_EVENT_MII;
break;
}
if ((--waiting) == 0)
return -1;
hal_delay_us(ENET_MII_TICK);
hal_delay_us(0);
}
printf("[%s %d], EIR: %08x\n", __func__, __LINE__, enet_reg->EIR.U);
*value = ENET_MII_GET_DATA(enet_reg->MMFR.U);
return 0;
}
@ -89,6 +91,7 @@ int imx_enet_mii_write(volatile hw_enet_t* enet_reg, unsigned char phy_addr,
}
enet_reg->MMFR.U = ENET_MII_WRITE(phy_addr, reg_addr, value); /* Write CMD */
printf("MMFR.U: %08x value: %08x\n", enet_reg->MMFR.U, value);
while (1) {
if (enet_reg->EIR.U & ENET_EVENT_MII) {
@ -112,18 +115,16 @@ static void imx_enet_bd_init(imx_enet_priv_t* dev, int dev_idx)
{
int i;
imx_enet_bd_t* p;
imx_enet_bd_t *rx_bd_base = (imx_enet_bd_t*)malloc(sizeof(imx_enet_bd_t)), //
*tx_bd_base = (imx_enet_bd_t*)malloc(sizeof(imx_enet_bd_t));
rx_bd_base += (dev_idx * ENET_BD_RX_NUM);
tx_bd_base += (dev_idx * ENET_BD_TX_NUM);
imx_enet_bd_t *rx_bd_base = (imx_enet_bd_t*)malloc(sizeof(imx_enet_bd_t) * (ENET_BD_RX_NUM * NUM_OF_ETH_DEVS)), //
*tx_bd_base = (imx_enet_bd_t*)malloc(sizeof(imx_enet_bd_t) * (ENET_BD_TX_NUM * NUM_OF_ETH_DEVS));
#define _SABRELITE_ENET_BUFFER_SIZE 2048
p = dev->rx_bd = (imx_enet_bd_t*)rx_bd_base;
for (i = 0; i < ENET_BD_RX_NUM; i++, p++) {
p->status = BD_RX_ST_EMPTY;
p->length = 0;
p->data = (unsigned char*)malloc(2048);
p->data = (unsigned char*)malloc(_SABRELITE_ENET_BUFFER_SIZE);
// printf("rx bd %x, buffer is %x\n", (unsigned int)p, (unsigned int)p->data);
}
@ -135,7 +136,7 @@ static void imx_enet_bd_init(imx_enet_priv_t* dev, int dev_idx)
for (i = 0; i < ENET_BD_TX_NUM; i++, p++) {
p->status = 0;
p->length = 0;
p->data = (unsigned char*)malloc(2048);
p->data = (unsigned char*)malloc(_SABRELITE_ENET_BUFFER_SIZE);
// printf("tx bd %x, buffer is %x\n", (unsigned int)p, (unsigned int)p->data);
}
@ -156,7 +157,7 @@ static void imx_enet_chip_init(imx_enet_priv_t* dev)
enet_reg->ECR.U = ENET_RESET;
while (enet_reg->ECR.U & ENET_RESET) {
yield(SYS_TASK_YIELD_NO_REASON);
hal_delay_us(ENET_COMMON_TICK);
}
enet_reg->EIMR.U = 0x00000000;
@ -471,13 +472,15 @@ int imx_enet_send(imx_enet_priv_t* dev, unsigned char* buf, int length, unsigned
if (p->status & BD_TX_ST_WRAP) {
p = dev->tx_bd;
} else
} else {
p++;
}
dev->tx_cur = p;
dev->tx_busy = 1;
dev->tx_key = key;
enet_reg->TDAR.U = ENET_RX_TX_ACTIVE;
printf("EIR: %08x, ECR: %08x, TDAR.U: %08x, RDAR.U: %08x (%08x)\n", dev->enet_reg->EIR.U, dev->enet_reg->ECR.U, dev->enet_reg->TDAR.U, dev->enet_reg->RDAR.U, ENET_RX_TX_ACTIVE);
return 0;
}
@ -552,6 +555,9 @@ void imx_enet_start(imx_enet_priv_t* dev, unsigned char* enaddr)
dev->tx_busy = 0;
dev->enet_reg->ECR.U |= ENET_ETHER_EN | ENET_ETHER_SPEED_1000M | ENET_ETHER_LITTLE_ENDIAN;
dev->enet_reg->RDAR.U |= ENET_RX_TX_ACTIVE;
HW_ENET_RDAR_WR(ENET_RX_TX_ACTIVE);
printf("addr1: %x, addr2: %x\n", &dev->enet_reg->RDAR.U, HW_ENET_RDAR_ADDR);
printf("EIR: %08x, ECR: %08x, TDAR.U: %08x, RDAR.U: %08x (%08x)\n", dev->enet_reg->EIR.U, dev->enet_reg->ECR.U, dev->enet_reg->TDAR.U, dev->enet_reg->RDAR.U, ENET_RX_TX_ACTIVE);
}
void imx_enet_stop(imx_enet_priv_t* dev)
@ -609,5 +615,6 @@ int imx_enet_mii_type(imx_enet_priv_t* dev, enum imx_mii_type mii_type)
printf("BUG:unknow MII type=%x\n", mii_type);
break;
}
printf("RCR: %08x, TFWR: %08x\n", enet_reg->RCR.U, enet_reg->TFWR.U);
return 0;
}

74
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/enet/enet_test.c
View File

@ -38,21 +38,12 @@
#include <string.h>
#include "enet.h"
#include "sdk_types.h"
#include "soc_memory_map.h"
#include "libserial.h"
#include "usyscall.h"
typedef enum _test_return {
TEST_NOT_STARTED = -3, // present in the menu, but not run
TEST_NOT_IMPLEMENTED = -2, // present in the menu, but not functional
TEST_FAILED = -1,
TEST_PASSED = 0,
TEST_BYPASSED = 2, // user elected to exit the test before it was run
TEST_NOT_PRESENT = 3, // not present in the menu.
TEST_CONTINUE = 4 // proceed with the test. opposite of TEST_BYPASSED
} test_return_t;
#define ENET_PHY_ADDR 6
static imx_enet_priv_t enet0;
@ -99,6 +90,53 @@ static int pkt_compare(unsigned char* packet1, unsigned char* packet2, int lengt
return 0;
}
//////////////////////////////////////////
void print_hw_enet(const hw_enet_t* enet)
{
printf("********************************\n");
printf("EIR: %08x\n", enet->EIR.U);
printf("EIMR: %08x\n", enet->EIMR.U);
printf("RDAR: %08x\n", enet->RDAR.U);
printf("TDAR: %08x\n", enet->TDAR.U);
printf("ECR: %08x\n", enet->ECR.U);
printf("MMFR: %08x\n", enet->MMFR.U);
printf("MSCR: %08x\n", enet->MSCR.U);
printf("MIBC: %08x\n", enet->MIBC.U);
printf("RCR: %08x\n", enet->RCR.U);
printf("TCR: %08x\n", enet->TCR.U);
printf("PALR: %08x\n", enet->PALR.U);
printf("PAUR: %08x\n", enet->PAUR.U);
printf("OPD: %08x\n", enet->OPD.U);
printf("IAUR: %08x\n", enet->IAUR.U);
printf("IALR: %08x\n", enet->IALR.U);
printf("GAUR: %08x\n", enet->GAUR.U);
printf("GALR: %08x\n", enet->GALR.U);
printf("TFWR: %08x\n", enet->TFWR.U);
printf("RDSR: %08x\n", enet->RDSR.U);
printf("TDSR: %08x\n", enet->TDSR.U);
printf("MRBR: %08x\n", enet->MRBR.U);
printf("RSFL: %08x\n", enet->RSFL.U);
printf("RSEM: %08x\n", enet->RSEM.U);
printf("RAEM: %08x\n", enet->RAEM.U);
printf("RAFL: %08x\n", enet->RAFL.U);
printf("TSEM: %08x\n", enet->TSEM.U);
printf("TAEM: %08x\n", enet->TAEM.U);
printf("TAFL: %08x\n", enet->TAFL.U);
printf("TIPG: %08x\n", enet->TIPG.U);
printf("FTRL: %08x\n", enet->FTRL.U);
printf("TACC: %08x\n", enet->TACC.U);
printf("RACC: %08x\n", enet->RACC.U);
printf("ATCR: %08x\n", enet->ATCR.U);
printf("ATVR: %08x\n", enet->ATVR.U);
printf("ATOFF: %08x\n", enet->ATOFF.U);
printf("ATPER: %08x\n", enet->ATPER.U);
printf("ATCOR: %08x\n", enet->ATCOR.U);
printf("ATINC: %08x\n", enet->ATINC.U);
printf("ATSTMP: %08x\n", enet->ATSTMP.U);
printf("********************************\n");
}
//////////////////////////////////////////
/*!
* This test performs a loopback transfer on the RGMII interface through
* an external AR8031 giga ethernet PHY.
@ -136,10 +174,10 @@ int enet_test()
printf("Ethernet link is up!\n");
break;
}
yield(SYS_TASK_YIELD_NO_REASON);
hal_delay_us(100000); // 100 ms
}
imx_enet_phy_enable_external_loopback(dev0);
// imx_enet_phy_enable_external_loopback(dev0);
printf("ENET %0d: [ %s ] [ %s ] [ %s ]:\n", dev0->phy_addr,
(dev0->status & ENET_STATUS_FULL_DPLX) ? "FULL_DUPLEX" : "HALF_DUPLEX",
@ -152,7 +190,6 @@ int enet_test()
printf("ENET link status check fail\n");
return TEST_FAILED;
}
imx_enet_start(dev0, mac_addr0);
// send packet
@ -174,7 +211,7 @@ int enet_test()
}
if (!(ENET_EVENT_TX & enet_events)) {
printf("ENET tx fail\n");
printf("ENET tx fail event: %08x\n", enet_events);
return TEST_FAILED;
}
@ -217,19 +254,20 @@ int main(int argc, char** argv)
exit();
}
printf("%s: Mapping %x(size: %x) to %x\n", enet_server_name, AIPS1_ARB_PHY_BASE_ADDR, AIPS1_ARB_END_ADDR - AIPS1_ARB_BASE_ADDR, AIPS1_ARB_BASE_ADDR);
printf("%s: Mapping %08x(size: %x) to %08x\n", enet_server_name, AIPS1_ARB_PHY_BASE_ADDR, AIPS1_ARB_END_ADDR - AIPS1_ARB_BASE_ADDR, AIPS1_ARB_BASE_ADDR);
if (!mmap(AIPS1_ARB_BASE_ADDR, AIPS1_ARB_PHY_BASE_ADDR, AIPS1_ARB_END_ADDR - AIPS1_ARB_BASE_ADDR, true)) {
printf("%s: mmap AIPS1 ARB(%x) failed\n", enet_server_name, AIPS1_ARB_PHY_BASE_ADDR);
printf("%s: mmap AIPS1 ARB(%8x) failed\n", enet_server_name, AIPS1_ARB_PHY_BASE_ADDR);
exit();
}
printf("%s: Mapping %x(size: %x) to %x\n", enet_server_name, AIPS2_ARB_PHY_BASE_ADDR, AIPS2_ARB_END_ADDR - AIPS2_ARB_BASE_ADDR, AIPS2_ARB_BASE_ADDR);
printf("%s: Mapping %08x(size: %x) to %8x\n", enet_server_name, AIPS2_ARB_PHY_BASE_ADDR, AIPS2_ARB_END_ADDR - AIPS2_ARB_BASE_ADDR, AIPS2_ARB_BASE_ADDR);
if (!mmap(AIPS2_ARB_BASE_ADDR, AIPS2_ARB_PHY_BASE_ADDR, AIPS2_ARB_END_ADDR - AIPS2_ARB_BASE_ADDR, true)) {
printf("%s: mmap AIPS1 ARB(%x) failed\n", enet_server_name, AIPS2_ARB_PHY_BASE_ADDR);
printf("%s: mmap AIPS1 ARB(%08x) failed\n", enet_server_name, AIPS2_ARB_PHY_BASE_ADDR);
exit();
}
enet_test();
exit();
return 0;
}

4
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/enet/regsenet.h
View File

@ -23,6 +23,8 @@
#include "regs.h"
#include "soc_memory_map.h"
/*
* i.MX6DQ ENET
*
@ -76,7 +78,7 @@
//@{
#ifndef REGS_ENET_BASE
#define HW_ENET_INSTANCE_COUNT (1) //!< Number of instances of the ENET module.
#define REGS_ENET_BASE (0x02188000) //!< Base address for ENET.
#define REGS_ENET_BASE USERLAND_MMIO_P2V(0x02188000) //!< Base address for ENET.
#endif
//@}

2
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/gpio/Makefile
View File

@ -10,7 +10,7 @@ objdump = ${toolchain}objdump
user_ldflags = -N -Ttext 0
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
c_useropts = -O0
c_useropts = -O2
INC_DIR = -I$(KERNEL_ROOT)/services/app \
-I$(KERNEL_ROOT)/services/boards/$(BOARD) \

9
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/include/regs.h
View File

@ -33,9 +33,12 @@
//
#ifndef __LANGUAGE_ASM__
typedef unsigned char reg8_t;
typedef unsigned short reg16_t;
typedef unsigned int reg32_t;
#include <stddef.h>
#include <stdint.h>
typedef uint8_t reg8_t;
typedef uint16_t reg16_t;
typedef uint32_t reg32_t;
#endif
//

13841
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/include/regsccm.h
View File

File diff suppressed because it is too large Load Diff

3
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/include/regsgpio.h
View File

@ -22,11 +22,10 @@
#define __HW_GPIO_REGISTERS_H__
#include "regs.h"
#include "soc_memory_map.h"
/*
* i.MX6SL GPIO
* i.MX6DQ GPIO
*
* GPIO
*

3
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/include/regsiomuxc.h
View File

@ -24,7 +24,6 @@
#include "regs.h"
#include "soc_memory_map.h"
// clang-format off
/*
* i.MX6DQ IOMUXC
*
@ -110468,8 +110467,6 @@ typedef struct _hw_iomuxc
#define HW_IOMUXC (*(hw_iomuxc_t *) REGS_IOMUXC_BASE)
#endif
//clang-format on
#endif // __HW_IOMUXC_REGISTERS_H__
// v18/121106/1.2.2
// EOF

5
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/include/sdk_types.h
View File

@ -27,9 +27,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SDK_TYPES_H__
#define __SDK_TYPES_H__
#pragma once
//! @addtogroup sdk_common
//! @{
@ -117,7 +115,6 @@ enum display_type {
//! @}
#endif // __SDK_TYPES_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

324
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/include/soc_memory_map.h
View File

@ -31,44 +31,52 @@
#ifndef _SOC_MEMORY_MAP_H
#define _SOC_MEMORY_MAP_H
// NOTE: THIS FILE IS GOING AWAY.
//
// DEVELOPERS - PLEASE USE register/*.h MACROS TO ACCESS REGSITERS.
//
// clang-format off
#define BOARD_SABRE_LITE
#define CHIP_MX6DQ 1
#define BOARD_REV_A
#define DRIVER_MAPPING_OFFSET 0x50000000
#define USERLAND_MMIO_P2V(a) (DRIVER_MAPPING_OFFSET + a)
#define USERLAND_MMIO_P2V(a) ((uintptr_t)DRIVER_MAPPING_OFFSET + (uintptr_t)a)
#define BAAD_STATUS 0xbaadbaad
#define GOOD_STATUS 0x900d900d
#define BAAD_STATUS 0xbaadbaad
#define GOOD_STATUS 0x900d900d
// CPU Memory Map
#define MMDC0_ARB_BASE_ADDR 0x80000000
#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
#define MMDC1_ARB_BASE_ADDR 0xC0000000
#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
#define OCRAM_ARB_BASE_ADDR 0x00900000
#define OCRAM_ARB_END_ADDR 0x0091FFFF
#define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR
//#define MMDC1_BASE_ADDR 0x10000000
//#define MMDC1_END_ADDR 0x7FFFFFFF
//#define MMDC0_BASE_ADDR 0x80000000
//#define MMDC0_END_ADDR 0xFFFFFFFF
#define OCRAM_BASE_ADDR 0x00900000
#define OCRAM_END_ADDR 0x009FFFFF
#define IRAM_BASE_ADDR OCRAM_BASE_ADDR
#define PCIE_BASE_ADDR 0x01000000
#define PCIE_END_ADDR 0x01FFFFFF
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
#define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR
#define CAAM_SEC_RAM_START_ADDR 0x00100000
#define CAAM_SEC_RAM_END_ADDR 0x00103FFF
#define GPMI_BASE_ADDR 0x00112000
#define APBH_DMA_BASE_ADDR 0x00110000
#define APBH_DMA_END_ADDR 0x00117FFF
#define HDMI_BASE_ADDR 0x00120000
#define HDMI_END_ADDR 0x00128FFF
#define GPU_3D_BASE_ADDR 0x00130000
#define GPU_3D_END_ADDR 0x00133FFF
#define GPU_2D_BASE_ADDR 0x00134000
#define GPU_2D_END_ADDR 0x00137FFF
#define DTCP_BASE_ADDR 0x00138000
#define DTCP_END_ADDR 0x0013BFFF
#define GPU_MEM_BASE_ADDR GPU_3D_BASE_ADDR
#define GPV0_BASE_ADDR 0x00B00000
#define GPV1_BASE_ADDR 0x00C00000
#define GPV2_BASE_ADDR 0x00200000
#define GPV3_BASE_ADDR 0x00300000
#define GPV4_BASE_ADDR 0x00800000
// Blocks connected via pl301periph
// s_e_N ports
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x00017FFF
#define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR
#define GPU_2D_ARB_BASE_ADDR 0x02200000
#define GPU_2D_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000
#define OPENVG_ARB_END_ADDR 0x02207FFF
// GPV - PL301 configuration ports
#define GPV0_BASE_ADDR 0x00B00000
#define GPV1_BASE_ADDR 0x00C00000
#define GPV2_BASE_ADDR 0x00D00000
// s_g_N ports
#define AIPS1_ARB_PHY_BASE_ADDR 0x02000000
#define AIPS1_ARB_PHY_END_ADDR 0x020FFFFF
#define AIPS2_ARB_PHY_BASE_ADDR 0x02100000
@ -79,142 +87,150 @@
#define AIPS2_ARB_BASE_ADDR USERLAND_MMIO_P2V(AIPS2_ARB_PHY_BASE_ADDR)
#define AIPS2_ARB_END_ADDR USERLAND_MMIO_P2V(AIPS2_ARB_PHY_END_ADDR)
// #define SATA_ARB_BASE_ADDR 0x02200000
// #define SATA_ARB_END_ADDR 0x02203FFF
// #define OPENVG_ARB_BASE_ADDR 0x02204000
// #define OPENVG_ARB_END_ADDR 0x02207FFF
#define WEIM_ARB_BASE_ADDR 0x08000000
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
#define SATA_BASE_ADDR 0x02200000
#define SATA_END_ADDR 0x02203FFF
#define OPENVG_BASE_ADDR 0x02204000
#define OPENVG_END_ADDR 0x02207FFF
#define HSI_BASE_ADDR 0x02208000
#define HSI_END_ADDR 0x0220BFFF
#define IPU1_BASE_ADDR 0x02400000
#define IPU1_END_ADDR 0x027FFFFF
#define IPU2_BASE_ADDR 0x02800000
#define IPU2_END_ADDR 0x02BFFFFF
#define WEIM_CS_BASE_ADDR 0x08000000
#define WEIM_CS_END_ADDR 0x0FFFFFFF
// CoreSight (ARM Debug)
// ***** TO UPDATE *****
#define DEBUG_ROM_BASE_ADDR 0x02140000
#define ETB_BASE_ADDR 0x02141000
#define EXT_CTI_BASE_ADDR 0x02142000
#define TPIU_BASE_ADDR 0x02143000
#define FUNNEL_BASE_ADDR 0x02144000
#define CORTEX_ROM_TABLE 0x0214F000
#define CORTEX_DEBUG_UNIT 0x02150000
#define CORE0_DEBUG_UNIT 0x02150000
#define PMU0_BASE_ADDR 0x02151000
#define CORE1_DEBUG_UNIT 0x02152000
#define PMU1_BASE_ADDR 0x02153000
#define CORE2_DEBUG_UNIT 0x02154000
#define PMU2_BASE_ADDR 0x02155000
#define CORE3_DEBUG_UNIT 0x02156000
#define PMU3_BASE_ADDR 0x02157000
#define CTI0_BASE_ADDR 0x02158000
#define CTI1_BASE_ADDR 0x02159000
#define CTI2_BASE_ADDR 0x0215A000
#define CTI3_BASE_ADDR 0x0215B000
#define PTM0_BASE_ADDR 0x0215C000
#define PTM_BASE_ADDR 0x0215C000
#define PTM1_BASE_ADDR 0x0215D000
#define PTM2_BASE_ADDR 0x0215E000
#define PTM3_BASE_ADDR 0x0215F000
// *********************
#define DEBUG_ROM_BASE_ADDR 0x02140000
#define ETB_BASE_ADDR 0x02141000
#define EXT_CTI_BASE_ADDR 0x02142000
#define TPIU_BASE_ADDR 0x02143000
#define FUNNEL_BASE_ADDR 0x02144000
#define CORTEX_ROM_TABLE 0x0214F000
#define CORTEX_DEBUG_UNIT 0x02150000
#define CORE0_DEBUG_UNIT 0x02150000
#define PMU0_BASE_ADDR 0x02151000
#define CORE1_DEBUG_UNIT 0x02152000
#define PMU1_BASE_ADDR 0x02153000
#define CORE2_DEBUG_UNIT 0x02154000
#define PMU2_BASE_ADDR 0x02155000
#define CORE3_DEBUG_UNIT 0x02156000
#define PMU3_BASE_ADDR 0x02157000
#define CTI0_BASE_ADDR 0x02158000
#define CTI1_BASE_ADDR 0x02159000
#define CTI2_BASE_ADDR 0x0215A000
#define CTI3_BASE_ADDR 0x0215B000
#define PTM0_BASE_ADDR 0x0215C000
#define PTM_BASE_ADDR 0x0215C000
#define PTM1_BASE_ADDR 0x0215D000
#define PTM2_BASE_ADDR 0x0215E000
#define PTM3_BASE_ADDR 0x0215F000
// Legacy Defines
#define CSD0_DDR_BASE_ADDR MMDC0_ARB_BASE_ADDR
#define CSD1_DDR_BASE_ADDR 0xC0000000
#define CS0_BASE_ADDR WEIM_ARB_BASE_ADDR
// Defines for Blocks connected via AIPS (SkyBlue)
#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
#define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
#define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
//slots 0,7 of SDMA reserved, therefore left unused in IPMUX3
#define SPDIF_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00004000) // 0x02004000
#define ECSPI1_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00008000) // 0x02008000
#define ECSPI2_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x0000C000) // 0x0200C000
#define ECSPI3_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00010000) // 0x02010000
#define ECSPI4_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00014000) // 0x02014000
#define UART5_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00018000) //slot 6
#define UART1_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00020000) // 0x02020000
#define UART2_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00024000) //slot 9
#define SSI1_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00028000) // 0x02028000
#define SSI2_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x0002C000) // 0x0202C000
#define SSI3_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00030000) // 0x02030000
#define UART3_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00034000) //slot 13
#define UART4_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00038000) //slot 14
#define SPBA_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x0003C000) // 0x0203C000 haku
#define VPU_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00040000) //slot 33, global en[1], til 0x7BFFF
#define SPDIF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x04000) //slot 1
#define ECSPI1_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x08000) //slot 2
#define ECSPI2_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x0C000) //slot 3
#define ECSPI3_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x10000) //slot 4
#define ECSPI4_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x14000) //slot 5
#define ECSPI5_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x18000) //slot 6
#define UART1_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x20000) //slot 8
#define ESAI1_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x24000) //slot 9
#define SSI1_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x28000) //slot 10
#define SSI2_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x2C000) //slot 11
#define SSI3_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x30000) //slot 12
#define ASRC_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x34000) //slot 13
#define SPBA_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x3C000) //slot 15
#define VPU_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x40000) //slot 33, global en[1], til 0x7BFFF
// AIPS_TZ#1- On Platform
#define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x0007C000) // 0x0207C000
#define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x7C000)
#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x80000)
// AIPS_TZ#1- Off Platform
#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00080000) // 0x02080000
//#define USBOH3_BASE_ADDR AIPS1_BASE_ADDR
#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x0000)
#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x4000)
#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x8000)
#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC000)
#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000)
#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x14000)
#define GPT_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x18000)
#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C000)
#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000)
#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x24000)
#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x28000)
#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x2C000)
#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000)
#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x34000)
#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x38000)
#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x3C000)
#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000)
#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x44000)
#define IP2APB_USBPHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x49000)
#define IP2APB_USBPHY2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x4A000)
#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x4C000)
#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000)
#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x54000)
#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x58000)
#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x5C000)
#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000)
#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x64000)
#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x68000)
#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x6C000)
#define SDMA_IPS_HOST_BASE_ADDR SDMA_BASE_ADDR
#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00000000) // 0x02080000
#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00004000) // 0x02084000
#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00008000) // 0x02088000
#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000C000) // 0x0208C000
#define DBGMON_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00010000) // 0x02090000
#define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00014000) // 0x02094000
#define GPT_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00018000) // 0x02098000
#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0001C000) // 0x0209C000
#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00020000) // 0x020A0000
#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00024000) // 0x020A4000
#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00028000) // 0x020A8000
#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0002C000) // 0x020AC000
#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00030000)
#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00034000)
#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00038000) // 0x020B8000
#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0003C000) // 0x020BC000
#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00040000) // 0x020C0000
#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00044000) // 0x020C4000
#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00048000) // 0x020C8000 same as CCM_ANALOG above
#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0004C000) // 0x020CC000
#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00050000) // 0x020D0000
#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00054000) // 0x020D4000
#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00058000) // 0x020D8000
#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0005C000) // 0x020DC000 same as DVFS below
#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00060000) // 0x020E0000
#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00064000) // 0x020E4000 (was DCIC1)
#define SPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00068000) // 0x020E8000 (was DCIC2)
#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0006C000) // 0x020EC000
#define EPXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00070000) // 0x020F0000
#define SDMA_IPS_HOST_BASE_ADDR SDMA_BASE_ADDR
#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00074000) // 0x020F4000
#define ELCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00078000) // 0x020F8000
#define DCP_BASE_ADDRESS (AIPS1_OFF_BASE_ADDR + 0x0007C000) // 0x020FC000
// AIPS_TZ#2- On Platform
#define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x0007C000) // 0x0217C000
// AIPS_TZ#2- Off Platform
#define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x00080000) // 0x02180000
#define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x7C000)
#define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x80000)
#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
#define USBO2H_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00000000)
#define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00004000)
#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00008000) // 0x02188000
#define MSHC_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000C000)
//For ESDHC became Usdhc, temporarily allowing both new and old names
#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00010000) // 0x02190000
#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00014000) // 0x02194000
#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00018000) // 0x02198000
#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0001C000) // 0x0219C000
#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00020000) // 0x021A0000
#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00024000) // 0x021A4000
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00028000) // 0x021A8000
#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00078000)
//AIPS2_OFF_BASE_ADDR
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0002C000) // 0x021AC000
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00030000) // 0x021B0000
#define RNGB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00034000) // 0x021B4000
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00038000) // 0x021B8000
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0003C000) // 0x021BC000
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00040000) // 0x021C0000
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00044000) // 0x021C4000
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00048000) // 0x021C8000
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00050000) // 0x021D0000
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00058000) // 0x021D8000
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00078000)
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0007C000)
#define CAAM_BASE_ADDR AIPS_TZ2_BASE_ADDR
#define ARM_IPS_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x40000)
#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x0000)
#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x4000)
#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x8000)
#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC000)
#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000)
#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x14000)
#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x18000)
#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C000)
#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000)
#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x24000)
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x28000)
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x2C000)
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000)
#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x34000)
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x38000)
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x3C000)
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000)
#define PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x44000)
#define PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x48000)
#define PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x4C000)
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000)
#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x54000)
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x58000)
#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x5C000)
#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000)
#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x64000)
#define UART2_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x68000)
#define UART3_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x6C000)
#define UART4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000)
#define UART5_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x74000)
// Cortex-A9 MPCore private memory region
#define ARM_PERIPHBASE 0x00A00000
#define SCU_BASE_ADDR ARM_PERIPHBASE
#define IC_INTERFACES_BASE_ADDR (ARM_PERIPHBASE+0x0100)
#define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE+0x0200)
#define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE+0x0600)
#define IC_DISTRIBUTOR_BASE_ADDR (ARM_PERIPHBASE+0x1000)
//Add from mx53 for ds90ur124.c
#define GPR_BASE_ADDR (IOMUXC_BASE_ADDR + 0x0)
#define OBSRV_BASE_ADDR (GPR_BASE_ADDR + 0x38)
#define SW_MUX_BASE_ADDR (OBSRV_BASE_ADDR + 0x14)
// clang-format
#endif //_SOC_MEMORY_MAP_H

2
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/lib/Makefile
View File

@ -10,7 +10,7 @@ objdump = ${toolchain}objdump
user_ldflags = -N -Ttext 0
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
c_useropts = -O0
c_useropts = -O2
INC_DIR = -I$(KERNEL_ROOT)/services/app \
-I$(KERNEL_ROOT)/services/boards/$(BOARD) \

4
Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile
View File

@ -1,7 +1,7 @@
ifeq ($(BOARD), imx6q-sabrelite)
toolchain ?= arm-none-eabi-
user_ldflags = -N -Ttext 0
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
ifeq ($(BOARD), zynq7000-zc702)
toolchain ?= arm-xilinx-eabi-
@ -13,7 +13,7 @@ cc = ${toolchain}gcc
ld = ${toolchain}g++
objdump = ${toolchain}objdump
c_useropts = -O0
c_useropts = -O2
INC_DIR = -I$(KERNEL_ROOT)/services/fs/libfs \
-I$(KERNEL_ROOT)/services/fs/fs_server/include \

2
Ubiquitous/XiZi_AIoT/services/fs/fs_server/fs_server.c
View File

@ -357,7 +357,7 @@ int main(int argc, char* argv[])
MemFsInit((uintptr_t)FS_IMG_ADDR, (uint32_t)len);
if (register_server("MemFS") < 0) {
printf("register server name: %s failed.\n", "SimpleServer");
printf("register server name: %s failed.\n", "MemFs");
exit();
}
ipc_server_loop(&IpcFsServer);

4
Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile
View File

@ -1,7 +1,7 @@
ifeq ($(BOARD), imx6q-sabrelite)
toolchain ?= arm-none-eabi-
user_ldflags = -N -Ttext 0
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
ifeq ($(BOARD), zynq7000-zc702)
toolchain ?= arm-xilinx-eabi-
@ -13,7 +13,7 @@ cc = ${toolchain}gcc
ld = ${toolchain}g++
objdump = ${toolchain}objdump
c_useropts = -O0
c_useropts = -O2
INC_DIR = -I$(KERNEL_ROOT)/services/fs/libfs \
-I$(KERNEL_ROOT)/services/lib/ipc \

4
Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile
View File

@ -1,7 +1,7 @@
ifeq ($(BOARD), imx6q-sabrelite)
toolchain ?= arm-none-eabi-
user_ldflags = -N -Ttext 0
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
ifeq ($(BOARD), zynq7000-zc702)
toolchain ?= arm-xilinx-eabi-
@ -13,7 +13,7 @@ cc = ${toolchain}gcc
ld = ${toolchain}g++
objdump = ${toolchain}objdump
c_useropts = -O0
c_useropts = -O2
INC_DIR = -I$(KERNEL_ROOT)/services/lib/ipc \
-I$(KERNEL_ROOT)/services/lib/memory \

6
Ubiquitous/XiZi_AIoT/services/lib/ipc/libipc.h
View File

@ -60,13 +60,13 @@ typedef struct {
struct IpcArgInfo {
uint16_t offset;
uint16_t len;
};
} __attribute__((packed));
/* [header, ipc_arg_buffer_len[], ipc_arg_buffer[]] */
struct IpcMsg {
ipc_msg_header header;
uintptr_t buf[];
};
} __attribute__((packed));
enum {
IPC_ARG_INFO_BASE_OFFSET = sizeof(ipc_msg_header),
};
@ -76,7 +76,7 @@ typedef int (*IpcInterface)(struct IpcMsg* msg);
struct IpcNode {
char* name;
IpcInterface interfaces[UINT8_MAX];
};
} __attribute__((packed));
#define IPC_SERVER_LOOP(ipc_node_name) rpc_server_loop_##rpc_node_name
#define IPC_SERVICES(ipc_node_name, ...) \

2
Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile
View File

@ -10,7 +10,7 @@ objdump = ${toolchain}objdump
user_ldflags = -N -Ttext 0
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
c_useropts = -O0
c_useropts = -O2
INC_DIR = -I$(KERNEL_ROOT)/services/app \
-I$(KERNEL_ROOT)/services/fs/libfs \

2
Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile
View File

@ -10,7 +10,7 @@ objdump = ${toolchain}objdump
user_ldflags = -N -Ttext 0
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
c_useropts = -O0
c_useropts = -O2
INC_DIR = -I$(KERNEL_ROOT)/services/app \
-I$(KERNEL_ROOT)/services/fs/libfs \

2
Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile
View File

@ -10,7 +10,7 @@ objdump = ${toolchain}objdump
user_ldflags = -N -Ttext 0
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
c_useropts = -O0
c_useropts = -O2
INC_DIR = -I$(KERNEL_ROOT)/services/app \
-I$(KERNEL_ROOT)/services/fs/libfs \

2
Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile
View File

@ -13,7 +13,7 @@ cc = ${toolchain}gcc
ld = ${toolchain}g++
objdump = ${toolchain}objdump
c_useropts = -O0
c_useropts = -O2
INC_DIR = -I$(KERNEL_ROOT)/services/app \
-I$(KERNEL_ROOT)/services/fs/libfs \

8
Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c
View File

@ -109,10 +109,10 @@ void show_mem(void)
user_dynamic_free += user_phy_freemem_buddy.free_list[j].n_free_pages * (1 << j) * PAGE_SIZE;
kernel_free += kern_virtmem_buddy.free_list[j].n_free_pages * (1 << j) * PAGE_SIZE;
}
LOG_PRINTF("%-16s 0x%064lx\n", "TOTAL(B)", total);
LOG_PRINTF("%-16s 0x%064lx\n", "KERNEL USED(B)", (kern_virtmem_buddy.mem_end - kern_virtmem_buddy.mem_start - kernel_free));
LOG_PRINTF("%-16s 0x%064lx\n", "LIBMEM USED(B)", (user_phy_freemem_buddy.mem_end - user_phy_freemem_buddy.mem_start - user_dynamic_free));
LOG_PRINTF("%-16s 0x%064lx\n", "FREE(B)", user_dynamic_free + kernel_free);
LOG_PRINTF("%-16s 0x%016lx\n", "TOTAL(B)", total);
LOG_PRINTF("%-16s 0x%016lx\n", "KERNEL USED(B)", (kern_virtmem_buddy.mem_end - kern_virtmem_buddy.mem_start - kernel_free));
LOG_PRINTF("%-16s 0x%016lx\n", "LIBMEM USED(B)", (user_phy_freemem_buddy.mem_end - user_phy_freemem_buddy.mem_start - user_dynamic_free));
LOG_PRINTF("%-16s 0x%016lx\n", "FREE(B)", user_dynamic_free + kernel_free);
SHOWINFO_BORDER_LINE();
return;